JP2018058737A - Group iii nitride semiconductor substrate and method for manufacturing the same - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 195
- 239000000758 substrate Substances 0.000 title claims abstract description 110
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
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- 238000002360 preparation method Methods 0.000 claims description 11
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- 238000010586 diagram Methods 0.000 description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 14
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- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 10
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- 238000001451 molecular beam epitaxy Methods 0.000 description 2
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- XOYLJNJLGBYDTH-UHFFFAOYSA-M chlorogallium Chemical compound [Ga]Cl XOYLJNJLGBYDTH-UHFFFAOYSA-M 0.000 description 1
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Abstract
Description
本発明は、III族窒化物半導体基板、及び、III族窒化物半導体基板の製造方法に関する。 The present invention relates to a group III nitride semiconductor substrate and a method for manufacturing a group III nitride semiconductor substrate.
関連する技術が特許文献１に開示されている。特許文献１には、III族窒化物バルク結晶から切り出された複数の小片基板を互いに隣接させて配置した後、当該小片基板上にIII族窒化物結晶を成長させるIII族窒化物結晶の製造方法が開示されている。なお、複数の小片基板の主面（露出面）の面方位は均一にすることが開示されている。 A related technique is disclosed in Patent Document 1. Patent Document 1 discloses a method of manufacturing a group III nitride crystal in which a plurality of small piece substrates cut out from a group III nitride bulk crystal are arranged adjacent to each other and then a group III nitride crystal is grown on the small piece substrate. Is disclosed. It is disclosed that the surface orientations of the main surfaces (exposed surfaces) of the plurality of small piece substrates are made uniform.
１つのIII族窒化物半導体基板の上に、互いに性質が異なる複数種類のデバイス（光デバイス、電子デバイス等）を形成するための技術が望まれている。 A technique for forming a plurality of types of devices (optical devices, electronic devices, etc.) having different properties from each other on one group III nitride semiconductor substrate is desired.
III族窒化物半導体基板の上に形成されるデバイスの性質は、当該III族窒化物半導体基板の成長面の面方位に依存する場合がある。 The property of the device formed on the group III nitride semiconductor substrate may depend on the plane orientation of the growth surface of the group III nitride semiconductor substrate.
従来のIII族窒化物半導体基板は、結晶方位が揃ったバルク結晶により構成される。このようなIII族窒化物半導体基板の場合、成長面内での面方位のばらつきはなく、均一となる。このため、このようなIII族窒化物半導体基板の場合、同様な性質のデバイスを多数形成することはできるが、互いに性質が異なる複数種類のデバイスを形成するのは容易でない。 A conventional group III nitride semiconductor substrate is composed of a bulk crystal having a uniform crystal orientation. In the case of such a group III nitride semiconductor substrate, there is no variation in the plane orientation within the growth plane, and it becomes uniform. Therefore, in the case of such a group III nitride semiconductor substrate, a large number of devices having similar properties can be formed, but it is not easy to form a plurality of types of devices having different properties.
本発明は、１つのIII族窒化物半導体基板の上に、互いに性質が異なる複数種類のデバイスを形成するための技術を提供することを課題とする。 An object of the present invention is to provide a technique for forming a plurality of types of devices having different properties on one group III nitride semiconductor substrate.
本発明によれば、
III族窒化物半導体で構成された第１乃至第Ｎ（Ｎは２以上の整数）の結晶部分を含むIII族窒化物半導体層を有し、
前記第１乃至第Ｎの結晶部分は、前記III族窒化物半導体層の表面における面方位が互いに異なるIII族窒化物半導体基板が提供される。
According to the present invention,
A group III nitride semiconductor layer including first to N-th (N is an integer of 2 or more) crystal parts composed of a group III nitride semiconductor;
The first to Nth crystal parts provide a group III nitride semiconductor substrate having different plane orientations on the surface of the group III nitride semiconductor layer.
また、本発明によれば、
露出面の面方位が互いに異なる第１乃至第Ｎ（Ｎは２以上の整数）のIII族窒化物半導体の複数の結晶片を、前記露出面が同一方向を向くように並べる下地層準備工程と、
前記下地層準備工程の後、前記露出面上にIII族窒化物半導体をエピタキシャル成長させ、前記結晶片各々から成長したIII族窒化物半導体同志を接合させるIII族窒化物半導体層形成工程と、
を有するIII族窒化物半導体基板の製造方法が提供される。
Moreover, according to the present invention,
A base layer preparation step of arranging a plurality of crystal pieces of first to Nth (N is an integer of 2 or more) Group III nitride semiconductors having different surface orientations of the exposed surfaces so that the exposed surfaces are directed in the same direction; ,
After the underlayer preparation step, a group III nitride semiconductor layer is formed on the exposed surface by epitaxial growth of a group III nitride semiconductor, and a group III nitride semiconductor layer grown from each of the crystal pieces is joined.
There is provided a method for producing a group III nitride semiconductor substrate having:
本発明によれば、１つのIII族窒化物半導体基板の上に、互いに性質が異なる複数種類のデバイスを形成するための技術が実現される。 According to the present invention, a technique for forming a plurality of types of devices having different properties on one group III nitride semiconductor substrate is realized.
以下、本願発明の基板及びその製造方法の実施形態について図面を用いて説明する。なお、図はあくまで発明の構成を説明するための概略図であり、各部材の大きさ、形状、数、異なる部材の大きさの比率などは図示するものに限定されない。 Hereinafter, embodiments of the substrate of the present invention and the manufacturing method thereof will be described with reference to the drawings. The drawings are only schematic diagrams for explaining the configuration of the invention, and the size, shape, number, and ratio of different member sizes are not limited to those shown in the drawings.
まず、本実施形態の概要について説明する。本実施形態のIII族窒化物半導体基板は、III族窒化物半導体層を有する。III族窒化物半導体層は、III族窒化物半導体で構成された第１乃至第Ｎ（Ｎは２以上の整数）の結晶部分を含む。すなわち、第１乃至第Ｎの結晶部分が互いに接合し、III族窒化物半導体層を構成している。第１乃至第Ｎの結晶部分は、III族窒化物半導体層の表面における面方位が互いに異なる。 First, an outline of the present embodiment will be described. The group III nitride semiconductor substrate of this embodiment has a group III nitride semiconductor layer. The group III nitride semiconductor layer includes first to Nth (N is an integer of 2 or more) crystal parts made of a group III nitride semiconductor. That is, the first to Nth crystal portions are joined together to form a group III nitride semiconductor layer. The first to Nth crystal parts have different plane orientations on the surface of the group III nitride semiconductor layer.
このような本実施形態のIII族窒化物半導体基板の場合、成長面（III族窒化物半導体層の表面）内に、表面の面方位が互いに異なる複数のエリアが形成される。そして、各エリア内に、各面方位に応じた性質を有するデバイス（光デバイス、電子デバイス等）を形成することができる。このように、本実施形態によれば、１つのIII族窒化物半導体基板の上に、互いに性質が異なる複数種類のデバイスを形成することが可能となる。 In the case of such a group III nitride semiconductor substrate of this embodiment, a plurality of areas having different surface orientations are formed in the growth surface (the surface of the group III nitride semiconductor layer). In each area, a device (an optical device, an electronic device, etc.) having a property corresponding to each plane orientation can be formed. Thus, according to this embodiment, it is possible to form a plurality of types of devices having different properties from each other on one group III nitride semiconductor substrate.
次に、本実施形態の構成について詳細に説明する。まず、本実施形態のIII族窒化物半導体基板の製造方法について説明する。図１のフローチャートに示すように、本実施形態のIII族窒化物半導体基板の製造方法は、下地層準備工程Ｓ１と、III族窒化物半導体層形成工程Ｓ２とを有する。図２のフローチャートに示すように、本実施形態のIII族窒化物半導体基板の製造方法は、さらに、除去工程Ｓ３を有してもよい。 Next, the configuration of the present embodiment will be described in detail. First, the manufacturing method of the group III nitride semiconductor substrate of this embodiment is demonstrated. As shown in the flowchart of FIG. 1, the method for manufacturing a group III nitride semiconductor substrate of this embodiment includes an underlayer preparation step S1 and a group III nitride semiconductor layer formation step S2. As shown in the flowchart of FIG. 2, the method for manufacturing a group III nitride semiconductor substrate of the present embodiment may further include a removal step S3.
下地層準備工程Ｓ１は、複数の結晶片を、所定の露出面が同一方向を向くように並べる。なお、「同一方向を向く」とは、所定の露出面の法線方向が同一（互いに平行）である状態のみならず、法線方向が互いに±５°以内の範囲でずれた状態を含んでもよい。このように並べられた複数の結晶片により、下地層が構成される。 In the underlayer preparation step S1, a plurality of crystal pieces are arranged such that predetermined exposed surfaces face the same direction. Note that “facing in the same direction” includes not only a state in which normal directions of predetermined exposure surfaces are the same (parallel to each other) but also a state in which normal directions are deviated within a range of ± 5 ° from each other. Good. A plurality of crystal pieces arranged in this way constitute an underlayer.
複数の結晶片の中には、同一方向を向いて並べられる所定の露出面の面方位が互いに異なる第１乃至第Ｎ（Ｎは２以上の整数）の結晶片が含まれる。なお、複数の結晶片の中には、同一方向を向いて並べられる所定の露出面の面方位が互いに同じものが含まれてもよい。露出面の面方位が同じである複数の結晶片は、ひとまとまりになるように並べられてもよいし、ばらばらに散在してもよい。すなわち、第１乃至第Ｎの結晶片の中の少なくとも１つは複数の結晶片を有し、当該複数の結晶片は下地層においてひとまとまりとなって並んでいてもよい。 The plurality of crystal pieces include first to Nth (N is an integer of 2 or more) crystal pieces having different plane orientations of predetermined exposed surfaces arranged in the same direction. Note that the plurality of crystal pieces may include those having the same plane orientation of the predetermined exposed surfaces arranged in the same direction. A plurality of crystal pieces having the same surface orientation of the exposed surface may be arranged in a group or may be scattered. That is, at least one of the first to Nth crystal pieces may have a plurality of crystal pieces, and the plurality of crystal pieces may be arranged in a group in the underlayer.
第１乃至第Ｎの結晶片の所定の露出面の面方位は特段制限されない。例えば、第１乃至第Ｎの結晶片の所定の露出面の面方位の組み合わせは、＋ｃ面、ｍ面、ａ面、｛１１−２２｝面、｛１１−２２｝面を所定角度（例：±１０°以内）傾けた面、｛１１−２４｝面、｛１１−２４｝面を所定角度（例：±１０°以内）傾けた面、｛１０−１２｝面、｛１０−１２｝面を所定角度（例：±１０°以内）傾けた面、｛１０−１１｝面、｛１０−１１｝面を所定角度（例：±１０°以内）傾けた面、｛２０−２１｝面、｛２０−２１｝面を所定角度（例：±１０°以内）傾けた面、｛２０−２３｝面、及び、｛２０−２３｝面を所定角度（例：±１０°以内）傾けた面の中のいずれかを任意に組み合わせたものであってもよい。 The plane orientation of the predetermined exposed surface of the first to Nth crystal pieces is not particularly limited. For example, the combination of the plane orientations of the predetermined exposed surfaces of the first to Nth crystal pieces is the + c plane, the m plane, the a plane, the {11-22} plane, and the {11-22} plane with a predetermined angle (example: Within ± 10 °) inclined surface, {11-24} surface, {11-24} surface inclined by a predetermined angle (eg, within ± 10 °), {10-12} surface, {10-12} surface , A surface tilted by a predetermined angle (eg, within ± 10 °), a {10-11} plane, a surface tilted by a {10-11} plane by a predetermined angle (eg, within ± 10 °), a {20-21} plane, {20-21} plane tilted by a predetermined angle (example: within ± 10 °), {20-23} plane, and {20-23} plane tilted by a predetermined angle (eg: within ± 10 °) Any of these may be combined arbitrarily.
ここで、複数の結晶片を準備する処理について説明する。複数の結晶片は、露出面が所定の面方位となっていればよく、その形状及び大きさは特段制限されない。例えば、互いに形状及び大きさが異なる結晶片が含まれてもよい。また、複数の結晶片の中には、厚さが互いに異なるものが含まれてもよい。結晶片の露出面の面方位を制御することで、下地層の上に形成されるIII族窒化物半導体層の露出面（成長面）に現れる面方位を制御することができる。 Here, a process for preparing a plurality of crystal pieces will be described. The plurality of crystal pieces only have to have a predetermined plane orientation on the exposed surface, and the shape and size are not particularly limited. For example, crystal pieces having different shapes and sizes may be included. In addition, the plurality of crystal pieces may include those having different thicknesses. By controlling the surface orientation of the exposed surface of the crystal piece, the surface orientation appearing on the exposed surface (growth surface) of the group III nitride semiconductor layer formed on the base layer can be controlled.
結晶片は、例えば、露出面が所定の面方位となっているIII族窒化物半導体基板（バルク結晶）から切り出すことで形成されてもよい。切り出す方法は特段制限されず、バンドソー、内周刃、外周刃などを用いて結晶片を切出してもよいし、劈開面で劈開することで結晶片を切出してもよい。その他、露出面が所定の面方位となっているIII族窒化物半導体基板（バルク結晶）の破片を加工し、所定の面方位の面を露出させたり、所定の形状にしたりすることで、結晶片が形成されてもよい。 The crystal piece may be formed by, for example, cutting out from a group III nitride semiconductor substrate (bulk crystal) whose exposed surface has a predetermined plane orientation. The cutting method is not particularly limited, and the crystal piece may be cut out using a band saw, an inner peripheral blade, an outer peripheral blade, or the like, or may be cut out by cleaving on a cleavage plane. In addition, by processing a fragment of a group III nitride semiconductor substrate (bulk crystal) whose exposed surface has a predetermined plane orientation, the surface of the predetermined plane orientation is exposed or formed into a predetermined shape, so that the crystal A piece may be formed.
ここで、図３（平面図）及び図４（側面図）を用いて、第１の面方位の露出面を有する結晶片を形成する処理の一例を説明する。当該例では、第１の面方位の露出面を有する第１のIII族窒化物半導体基板１０１を２つに分割することで、第１の面方位の露出面を有する２つの結晶片２１−１及び２１−２を形成している。 Here, an example of a process for forming a crystal piece having an exposed surface in the first plane orientation will be described with reference to FIG. 3 (plan view) and FIG. 4 (side view). In this example, the first group III nitride semiconductor substrate 101 having the exposed surface having the first surface orientation is divided into two, thereby two crystal pieces 21-1 having the exposed surface having the first surface orientation. And 21-2.
次に、図５（平面図）及び図６（側面図）を用いて、第１の面方位と異なる第２の面方位の露出面を有する結晶片を形成する処理の一例を説明する。当該例では、第２の面方位の露出面を有する第２のIII族窒化物半導体基板１０２を２つに分割することで、第２の面方位の露出面を有する２つの結晶片２２−１及び２２−２を形成している。 Next, an example of a process for forming a crystal piece having an exposed surface having a second surface orientation different from the first surface orientation will be described with reference to FIGS. 5 (plan view) and FIG. 6 (side view). In this example, the second group III nitride semiconductor substrate 102 having the exposed surface of the second plane orientation is divided into two, so that two crystal pieces 22-1 having the exposed surface of the second plane orientation are divided. And 22-2.
次に、図７（平面図）及び図８（側面図）を用いて、第１の面方位と異なる第２の面方位の露出面を有する結晶片を形成する処理の一例を説明する。当該例では、第１の面方位の露出面を有する第１のIII族窒化物半導体基板１０１から、短冊状に複数の小片を切り出すことで、複数の結晶片２２−１乃至２２−３を形成している。そして、図８に示すように、小片を切り出す際の切断面の傾きを制御することで、切断面の面方位を第２の面方位にしている。 Next, an example of a process for forming a crystal piece having an exposed surface having a second surface orientation different from the first surface orientation will be described with reference to FIGS. 7 (plan view) and FIG. 8 (side view). In this example, a plurality of crystal pieces 22-1 to 22-3 are formed by cutting a plurality of small pieces into a strip shape from the first group III nitride semiconductor substrate 101 having an exposed surface in the first plane orientation. doing. And as shown in FIG. 8, the surface orientation of a cut surface is made into the 2nd surface orientation by controlling the inclination of the cut surface at the time of cutting out a small piece.
例えば、上述のような方法を用いることで、所定の面方位の露出面を有する結晶片を作り分けることができる。なお、図３乃至図８を用いて説明した例はあくまで一例であり、１つのIII族窒化物半導体基板から切り出す結晶片の数、大きさ及びその形状等は、図示した例に限定されない。 For example, by using the method as described above, crystal pieces having an exposed surface with a predetermined plane orientation can be made separately. Note that the examples described with reference to FIGS. 3 to 8 are merely examples, and the number, size, shape, and the like of crystal pieces cut out from one group III nitride semiconductor substrate are not limited to the illustrated examples.
下地層準備工程Ｓ１では、このような複数の結晶片を、所定の面方位の露出面が同一方向を向くように並べる。 In the underlayer preparation step S1, such a plurality of crystal pieces are arranged so that the exposed surfaces of a predetermined plane orientation face the same direction.
図９の平面図は、基板ホルダ２００上に２つの結晶片（第１の結晶片２１及び第２の結晶片２２）を並べた状態の一例を示す。図９では、第１の面方位の露出面を有する第１の結晶片２１と、第１の面方位と異なる第２の面方位の露出面を有する第２の結晶片２２とが、当該露出面が同一方向（図中、紙面に対して垂直かつ手前側に向かう方向）を向くように並べられている。なお、第１の結晶片２１と第２の結晶片２２とは、互いに接していてもよいし、互いの間にわずかな隙間が存在してもよい。また、第１の結晶片２１と第２の結晶片２２とは、例えば接着剤などにより、互いに接着していてもよい。 The plan view of FIG. 9 shows an example of a state in which two crystal pieces (the first crystal piece 21 and the second crystal piece 22) are arranged on the substrate holder 200. In FIG. 9, a first crystal piece 21 having an exposed surface with a first surface orientation and a second crystal piece 22 having an exposed surface with a second surface orientation different from the first surface orientation are exposed. The planes are arranged so as to face the same direction (in the figure, the direction perpendicular to the plane of the drawing and toward the front side). The first crystal piece 21 and the second crystal piece 22 may be in contact with each other, or a slight gap may exist between them. Further, the first crystal piece 21 and the second crystal piece 22 may be bonded to each other by, for example, an adhesive.
図１０の平面図は、基板ホルダ２００上に結晶片を並べた状態の他の一例を示す。図１０では、第１の面方位の露出面を有する第１の結晶片２１−１乃至２１−４と、第１の面方位と異なる第２の面方位の露出面を有する第２の結晶片２２−１乃至２２−４とが、当該露出面が同一方向（図中、紙面に対して垂直かつ手前側に向かう方向）を向くように並べられている。なお、隣接する結晶片は、互いに接していてもよいし、互いの間にわずかな隙間が存在してもよい。また、隣接する結晶片は、例えば接着剤などにより、互いに接着していてもよい。 The plan view of FIG. 10 shows another example of a state in which crystal pieces are arranged on the substrate holder 200. In FIG. 10, first crystal pieces 21-1 to 21-4 having an exposed surface with a first surface orientation and a second crystal piece having an exposed surface with a second surface orientation different from the first surface orientation. 22-1 to 22-4 are arranged so that the exposed surfaces face the same direction (in the drawing, the direction perpendicular to the paper surface and toward the front side). Adjacent crystal pieces may be in contact with each other, or a slight gap may exist between them. Adjacent crystal pieces may be bonded to each other by, for example, an adhesive.
ここでは、２種類の結晶片を並べる例を説明したが、３種類以上の結晶片が並べられてもよい。また、複数の結晶片の並べ方は、図示する例に限定されない。 Here, an example in which two types of crystal pieces are arranged has been described, but three or more types of crystal pieces may be arranged. Further, the way of arranging the plurality of crystal pieces is not limited to the example illustrated.
図１及び図２に戻り、III族窒化物半導体層形成工程Ｓ２は、下地層準備工程Ｓ１の後に行われる。III族窒化物半導体層形成工程Ｓ２では、結晶片の露出面上にIII族窒化物半導体をエピタキシャル成長させ、結晶片各々から成長したIII族窒化物半導体同志を接合させる。結晶片から成長し、互いに接合したIII族窒化物半導体により、III族窒化物半導体層が構成される。 Returning to FIG. 1 and FIG. 2, the group III nitride semiconductor layer forming step S2 is performed after the base layer preparing step S1. In the group III nitride semiconductor layer forming step S2, a group III nitride semiconductor is epitaxially grown on the exposed surface of the crystal piece, and the group III nitride semiconductors grown from each crystal piece are joined. A group III nitride semiconductor layer is composed of group III nitride semiconductors grown from crystal pieces and bonded to each other.
III族窒化物半導体のエピタキシャル成長の具体例は特段制限されず、ＭＯＶＰＥ（Metal Organic Vapor Phase Epitaxy）、ＨＶＰＥ（Hydride Vapor Phase Epitaxy）、ＭＢＥ（Molecular Beam Epitaxy）、ＬＰＥ（Liquid Phase Epitaxy）等を利用できる。 Specific examples of epitaxial growth of group III nitride semiconductors are not particularly limited, and MOVPE (Metal Organic Vapor Phase Epitaxy), HVPE (Hydride Vapor Phase Epitaxy), MBE (Molecular Beam Epitaxy), LPE (Liquid Phase Epitaxy), etc. can be used. .
例えば、図１１に示すようなハイドライド気相成長（ＨＶＰＥ）装置１００を用いて実現してもよい。 For example, it may be realized by using a hydride vapor phase epitaxy (HVPE) apparatus 100 as shown in FIG.
図示するＨＶＰＥ装置１００は、反応管１２１と、反応管１２１内に設けられている基板ホルダ２００とを備える。また、ＨＶＰＥ装置１００は、III族原料ガスを反応管１２１内に供給するIII族原料ガス供給部１３９と、窒素原料ガスを反応管１２１内に供給する窒素原料ガス供給部１３７とを備える。さらに、ＨＶＰＥ装置１００は、ガス排出管１３５と、ヒータ１２９、１３０とを備える。 The illustrated HVPE apparatus 100 includes a reaction tube 121 and a substrate holder 200 provided in the reaction tube 121. The HVPE apparatus 100 includes a group III source gas supply unit 139 that supplies a group III source gas into the reaction tube 121 and a nitrogen source gas supply unit 137 that supplies a nitrogen source gas into the reaction tube 121. Further, the HVPE apparatus 100 includes a gas exhaust pipe 135 and heaters 129 and 130.
基板ホルダ２００は、反応管１２１の下流側に回転軸１３２により回転自在に設けられている。ガス排出管１３５は、反応管１２１のうち基板ホルダ２００の下流側に設けられている。 The substrate holder 200 is rotatably provided by a rotating shaft 132 on the downstream side of the reaction tube 121. The gas discharge pipe 135 is provided on the downstream side of the substrate holder 200 in the reaction pipe 121.
III族原料ガス供給部１３９は、ガス供給管１２６とソースボート１２８とIII族（Ｇａ）原料１２７と反応管１２１のうち遮蔽板１３６の下の層とを含む。 The group III source gas supply unit 139 includes a gas supply pipe 126, a source boat 128, a group III (Ga) source 127, and a layer below the shielding plate 136 among the reaction tubes 121.
窒素原料ガス供給部１３７は、ガス供給管１２４と反応管１２１のうち遮蔽板１３６の上の層とを含む。 The nitrogen source gas supply unit 137 includes a gas supply pipe 124 and a layer on the shielding plate 136 in the reaction pipe 121.
III族原料ガス供給部１３９は、III族原子のハロゲン化物（たとえば、ＧａＣｌ）を生成し、これを基板ホルダ２００に保持された下地層２０の表面に供給する。 The group III source gas supply unit 139 generates a halide of group III atoms (for example, GaCl) and supplies it to the surface of the underlayer 20 held by the substrate holder 200.
ガス供給管１２６の供給口は、III族原料ガス供給部１３９内の上流側に配置されている。このため、供給されたハロゲン化水素ガス（たとえば、ＨＣｌガス）は、III族原料ガス供給部１３９内でソースボート１２８中のIII族原料１２７と接触するようになっている。 The supply port of the gas supply pipe 126 is arranged on the upstream side in the group III source gas supply unit 139. For this reason, the supplied hydrogen halide gas (for example, HCl gas) comes into contact with the group III source material 127 in the source boat 128 in the group III source gas supply unit 139.
これにより、ガス供給管１２６から供給されるハロゲン含有ガスは、ソースボート１２８中のIII族原料１２７の表面または揮発したIII族分子と接触し、III族分子をハロゲン化してIII族のハロゲン化物を含むIII族原料ガスを生成する。なお、このIII族原料ガス供給部１３９の周囲にはヒータ１２９が配置され、III族原料ガス供給部１３９内は、たとえば８００〜９００℃程度の温度に維持される。 Thereby, the halogen-containing gas supplied from the gas supply pipe 126 comes into contact with the surface of the group III raw material 127 in the source boat 128 or the volatilized group III molecule, and the group III molecule is halogenated to form a group III halide. A Group III source gas is produced. A heater 129 is disposed around the group III source gas supply unit 139, and the inside of the group III source gas supply unit 139 is maintained at a temperature of about 800 to 900 ° C., for example.
反応管１２１の上流側は、遮蔽板１３６により２つの層に区画されている。図中の遮蔽板１３６の上側に位置する窒素原料ガス供給部１３７中を、ガス供給管１２４から供給されたアンモニアが通過し、熱により分解が促進される。なお、この窒素原料ガス供給部１３７の周囲にはヒータ１２９が配置され、窒素原料ガス供給部１３７内は、たとえば８００〜９００℃程度の温度に維持される。 The upstream side of the reaction tube 121 is divided into two layers by a shielding plate 136. Ammonia supplied from the gas supply pipe 124 passes through the nitrogen source gas supply unit 137 located on the upper side of the shielding plate 136 in the drawing, and decomposition is accelerated by heat. A heater 129 is disposed around the nitrogen source gas supply unit 137, and the nitrogen source gas supply unit 137 is maintained at a temperature of about 800 to 900 ° C., for example.
図中の右側に位置する成長領域１２２には、基板ホルダ２００が配置され、この成長領域１２２内でＧａＮ等のIII族窒化物半導体の成長が行われる。この成長領域１２２の周囲にはヒータ１３０が配置され、成長領域１２２内は、たとえば１０００℃〜１０５０℃程度の温度に維持される。 In the growth region 122 located on the right side in the drawing, the substrate holder 200 is disposed, and a group III nitride semiconductor such as GaN is grown in the growth region 122. A heater 130 is disposed around the growth region 122, and the inside of the growth region 122 is maintained at a temperature of about 1000 ° C. to 1050 ° C., for example.
III族窒化物半導体の成長条件は、従来のものと同様とすることができる。すなわち、従来と同様の成長条件で、下地層２０の上にIII族窒化物半導体を成長させると、成長過程において、各結晶片から成長したIII族窒化物半導体同志が互いに接し、そして、互いに接合する。 The growth conditions of the group III nitride semiconductor can be the same as the conventional one. That is, when a group III nitride semiconductor is grown on the underlayer 20 under the same growth conditions as in the prior art, the group III nitride semiconductors grown from each crystal piece are in contact with each other in the growth process, and are joined together. To do.
図１２に、III族窒化物半導体層形成工程Ｓ２の後のIII族窒化物半導体基板１の側面図の一例を示す。また、図１３に、図１２のIII族窒化物半導体基板１を図中上から見た平面図を示す。 FIG. 12 shows an example of a side view of the group III nitride semiconductor substrate 1 after the group III nitride semiconductor layer forming step S2. FIG. 13 is a plan view of the group III nitride semiconductor substrate 1 of FIG. 12 as viewed from above.
図示するIII族窒化物半導体層１０は、第１の結晶片２１から成長した第１の結晶部分１１と、第２の結晶片２２から成長した第２の結晶部分１２とを有する。第１の結晶部分１１と第２の結晶部分１２とは互いに接合しているが、III族窒化物半導体基板１の厚さ方向に垂直な面の面方位は互いに異なる。このため、蛍光顕微鏡像等で観察することで、第１の結晶部分１１及び第２の結晶部分１２の界面を特定することができる。 The group III nitride semiconductor layer 10 shown in the figure has a first crystal portion 11 grown from a first crystal piece 21 and a second crystal portion 12 grown from a second crystal piece 22. The first crystal portion 11 and the second crystal portion 12 are bonded to each other, but the plane orientations of the surfaces perpendicular to the thickness direction of the group III nitride semiconductor substrate 1 are different from each other. For this reason, the interface of the 1st crystal part 11 and the 2nd crystal part 12 can be specified by observing with a fluorescence microscope image etc.
第１の結晶部分１１の露出面の面方位は、第１の結晶片２１の露出面の面方位と同様、第１の面方位である。そして、第２の結晶部分１２の露出面の面方位は、第２の結晶片２２の露出面の面方位と同様、第２の面方位である。 The surface orientation of the exposed surface of the first crystal portion 11 is the first surface orientation similar to the surface orientation of the exposed surface of the first crystal piece 21. The surface orientation of the exposed surface of the second crystal portion 12 is the second surface orientation, similar to the surface orientation of the exposed surface of the second crystal piece 22.
図１４に、III族窒化物半導体層形成工程Ｓ２の後のIII族窒化物半導体基板１の側面図の他の一例を示す。当該例の場合、２つの第１の結晶片２１−１及び２１−２と、２つの第２の結晶片２２−１及び２２−２とにより、下地層２０が形成されている。図１４のIII族窒化物半導体基板１を図中上から見た平面図も、上記例と同様、図１３で示される。 FIG. 14 shows another example of a side view of the group III nitride semiconductor substrate 1 after the group III nitride semiconductor layer forming step S2. In the case of the example, the base layer 20 is formed by the two first crystal pieces 21-1 and 21-2 and the two second crystal pieces 22-1 and 22-2. A plan view of the group III nitride semiconductor substrate 1 of FIG. 14 as viewed from above is also shown in FIG.
なお、下地層２０の構成を制御することで、図１５及び図１６に示すようなIII族窒化物半導体基板１を形成することもできる。図１５及び図１６に示すIII族窒化物半導体基板１は、第１の結晶部分１１、第２の結晶部分１２及び第３の結晶部分１３により、III族窒化物半導体層１０が構成されている。図１５及び図１６に示すIII族窒化物半導体基板１を比べると、第１の結晶部分１１、第２の結晶部分１２及び第３の結晶部分１３の形状及び並び方が互いに異なる。 Note that the group III nitride semiconductor substrate 1 as shown in FIGS. 15 and 16 can also be formed by controlling the configuration of the underlayer 20. In the group III nitride semiconductor substrate 1 shown in FIGS. 15 and 16, the group III nitride semiconductor layer 10 is constituted by the first crystal portion 11, the second crystal portion 12, and the third crystal portion 13. . Comparing the group III nitride semiconductor substrate 1 shown in FIGS. 15 and 16, the shape and arrangement of the first crystal portion 11, the second crystal portion 12, and the third crystal portion 13 are different from each other.
図１５及び図１６に示す例において、第１の結晶部分１１、第２の結晶部分１２及び第３の結晶部分１３の露出面の面方位は、互いに異なってもよいし、一部の組み合わせ同志が同一であってもよい。例えば、図１５に示す例において、第１の結晶部分１１及び第３の結晶部分１３の面方位は同じであってもよい。そして、第１の結晶部分１１及び第３の結晶部分１３と、第２の結晶部分１２とは、面方位が互いに異なってもよい。この場合、第１の面方位の露出面を有する第１の結晶部分１１及び第３の結晶部分１３により、第１の面方位と異なる第２の面方位の露出面を有する第２の結晶部分１２が挟まれた状態となる。 In the examples shown in FIGS. 15 and 16, the surface orientations of the exposed surfaces of the first crystal portion 11, the second crystal portion 12, and the third crystal portion 13 may be different from each other. May be the same. For example, in the example shown in FIG. 15, the first crystal portion 11 and the third crystal portion 13 may have the same plane orientation. The first crystal portion 11 and the third crystal portion 13 and the second crystal portion 12 may have different plane orientations. In this case, the first crystal portion 11 and the third crystal portion 13 having the exposed surface of the first surface orientation have the second crystal portion having the exposed surface of the second surface orientation different from the first surface orientation. 12 is sandwiched.
III族窒化物半導体層形成工程Ｓ２の後、図２に示すように、除去工程Ｓ３を行ってもよい。 After the group III nitride semiconductor layer formation step S2, a removal step S3 may be performed as shown in FIG.
除去工程Ｓ３では、複数の結晶片で構成された下地層２０を除去する。例えば、図１２及び図１４に示すように、III族窒化物半導体層１０及び下地層２０の積層体となっているIII族窒化物半導体基板１から、下地層２０を除去する。例えば、研磨により下地層２０を削り落としてもよいし、又は、バンドソー、内周刃、外周刃などを用いてIII族窒化物半導体層１０から下地層２０を切り離してもよい。図１７に、図１２及び図１４に示すIII族窒化物半導体基板１から下地層２０を除去した状態の一例を示す。 In the removal step S3, the underlayer 20 composed of a plurality of crystal pieces is removed. For example, as shown in FIGS. 12 and 14, the underlayer 20 is removed from the group III nitride semiconductor substrate 1 that is a stacked body of the group III nitride semiconductor layer 10 and the underlayer 20. For example, the underlayer 20 may be scraped off by polishing, or the underlayer 20 may be separated from the group III nitride semiconductor layer 10 using a band saw, an inner peripheral blade, an outer peripheral blade, or the like. FIG. 17 shows an example of a state in which the underlayer 20 is removed from the group III nitride semiconductor substrate 1 shown in FIGS. 12 and 14.
次に、例えば上述のような製造方法で製造される本実施形態のIII族窒化物半導体基板１の構成について説明する。本実施形態のIII族窒化物半導体基板１は、下地層準備工程Ｓ１及びIII族窒化物半導体層形成工程Ｓ２を実行することで得られるIII族窒化物半導体層１０と下地層２０との積層体、又は、さらに除去工程Ｓ３を実行することで積層体から下地層２０を除去したものである。 Next, the structure of the group III nitride semiconductor substrate 1 of this embodiment manufactured by the manufacturing method as described above will be described. The group III nitride semiconductor substrate 1 of the present embodiment is a laminate of the group III nitride semiconductor layer 10 and the base layer 20 obtained by executing the base layer preparation step S1 and the group III nitride semiconductor layer formation step S2. Alternatively, the underlayer 20 is removed from the laminate by further executing the removing step S3.
図１３に、本実施形態のIII族窒化物半導体基板１の平面模式図の一例を示す。そして、図１７に、本実施形態のIII族窒化物半導体基板１の側面模式図の一例を示す。 FIG. 13 shows an example of a schematic plan view of the group III nitride semiconductor substrate 1 of the present embodiment. FIG. 17 shows an example of a schematic side view of the group III nitride semiconductor substrate 1 of the present embodiment.
図１３及び図１７に示すように、本実施形態のIII族窒化物半導体基板１は、III族窒化物半導体で構成されたIII族窒化物半導体層１０を有する。III族窒化物半導体層１０は、III族窒化物半導体で構成された第１乃至第Ｎ（Ｎは２以上の整数）の結晶部分を含む。図１３及び図１７の例の場合、III族窒化物半導体層１０は、２つの結晶部分（第１の結晶部分１１及び第２の結晶部分１２）を含む。そして、第１乃至第Ｎの結晶部分（図１３及び図１７の例の場合、第１の結晶部分１１及び第２の結晶部分１２）は、III族窒化物半導体層１０の表面（図１３で示される表面）における面方位が互いに異なる。なお、第１乃至第Ｎの結晶部分（図１３及び図１７の例の場合、第１の結晶部分１１及び第２の結晶部分１２）は、互いに接合している。 As shown in FIGS. 13 and 17, the group III nitride semiconductor substrate 1 of this embodiment includes a group III nitride semiconductor layer 10 made of a group III nitride semiconductor. The group III nitride semiconductor layer 10 includes first to Nth (N is an integer of 2 or more) crystal portions made of a group III nitride semiconductor. 13 and 17, the group III nitride semiconductor layer 10 includes two crystal parts (first crystal part 11 and second crystal part 12). The first to Nth crystal parts (the first crystal part 11 and the second crystal part 12 in the case of the examples of FIGS. 13 and 17) are the surfaces of the group III nitride semiconductor layer 10 (in FIG. 13). The surface orientations on the surface shown are different from each other. Note that the first to Nth crystal parts (the first crystal part 11 and the second crystal part 12 in the example of FIGS. 13 and 17) are joined to each other.
ところで、第１の結晶部分１１及び第２の結晶部分１２は、III族窒化物半導体の成長段階で意図せず局所的に形成されたような欠陥でない。すなわち、本実施形態のIII族窒化物半導体層１０は、第１の面方位の露出面（成長面）を有する結晶において、局所的に、第１の面方位と異なる第２の面方位が露出したようなものとは異なる。本実施形態のIII族窒化物半導体層１０は、第１の面方位の露出面（成長面）を有する第１の結晶部分１１及び第２の面方位露出面（成長面）を有する第２の結晶部分１２を意図的に形成したものである。 Incidentally, the first crystal portion 11 and the second crystal portion 12 are not defects that are not intentionally formed locally in the growth stage of the group III nitride semiconductor. That is, in the group III nitride semiconductor layer 10 of the present embodiment, the second surface orientation different from the first surface orientation is locally exposed in the crystal having the exposed surface (growth surface) of the first surface orientation. It is different from what you did. The group III nitride semiconductor layer 10 of the present embodiment includes a first crystal portion 11 having a first surface orientation exposed surface (growth surface) and a second surface orientation exposed surface (growth surface). The crystal portion 12 is intentionally formed.
意図せず第２の結晶部分１２が形成された場合、露出面（成長面）におけるその面積がデバイスを形成するためには小さすぎる恐れがある。また、その発生位置が不規則であるという問題もある。また、そのような欠陥がばらついて存在するため、露出面（成長面）における総面積はデバイスを形成する上で十分であるが、各々では不十分という問題も発生し得る。さらに、そのような結晶部分を探し出すのに労力を費やさなければならないという問題もある。 If the second crystal portion 12 is formed unintentionally, the area of the exposed surface (growth surface) may be too small to form a device. There is also a problem that the occurrence position is irregular. In addition, since such defects are scattered, the total area on the exposed surface (growth surface) is sufficient for forming a device, but there may be a problem that each of them is insufficient. Furthermore, there is a problem that labor must be expended to find such a crystal part.
本実施形態によれば、下地層準備工程Ｓ１における結晶片の種類及びその配置方法を制御することで、III族窒化物半導体層１０における各結晶部分の占有率、発生位置等を制御することができる。例えば、III族窒化物半導体層１０の露出面における占有面積が１５％以上である結晶部分を少なくとも２つ形成することができる。III族窒化物半導体層１０の露出面の面積は、例えば、３００μｍ２以上である。露出面（成長面）における各結晶部分の占有面積をこの程度大きくすれば、各結晶部分の露出面（成長面）上に、所定のデバイスを十分に形成することができる。すなわち、III族窒化物半導体層１０の露出面（成長面）上に、少なくとも２種類のデバイスを形成することができる。 According to the present embodiment, by controlling the type of crystal pieces and the arrangement method thereof in the underlayer preparation step S1, the occupation ratio, generation position, and the like of each crystal portion in the group III nitride semiconductor layer 10 can be controlled. it can. For example, at least two crystal parts having an occupied area of 15% or more on the exposed surface of the group III nitride semiconductor layer 10 can be formed. The area of the exposed surface of group III nitride semiconductor layer 10 is, for example, 300 μm 2 or more. If the area occupied by each crystal portion on the exposed surface (growth surface) is increased to this extent, a predetermined device can be sufficiently formed on the exposed surface (growth surface) of each crystal portion. That is, at least two types of devices can be formed on the exposed surface (growth surface) of the group III nitride semiconductor layer 10.
また、本実施形態によれば、III族窒化物半導体層１０において、第１乃至第Ｎ（Ｎは２以上の整数）の結晶部分各々をひとまとまりとすることができる（図１３、図１５及び図１６参照）。かかる場合、III族窒化物半導体層１０の露出面（成長面）において、各結晶部分の露出面がひとまとまりとなる。結果、ひとまとまりとなり、十分な面積を稼いだ各結晶部分の露出面上に、所定のデバイスを形成することが可能となる。 Further, according to the present embodiment, in the group III nitride semiconductor layer 10, the first to Nth (N is an integer of 2 or more) crystal portions can be grouped together (FIGS. 13, 15 and 15). (See FIG. 16). In such a case, the exposed surface of each crystal portion is a group on the exposed surface (growth surface) of the group III nitride semiconductor layer 10. As a result, it is possible to form a predetermined device on the exposed surface of each crystal portion that has gathered together and gained a sufficient area.
なお、第１乃至第Ｎ（Ｎは２以上の整数）の結晶部分の露出面の面方位は特段制限されない。例えば、第１乃至第Ｎの結晶部分の露出面の面方位の組み合わせは、＋ｃ面、ｍ面、ａ面、｛１１−２２｝面、｛１１−２２｝面を所定角度（例：±１０°以内）傾けた面、｛１１−２４｝面、｛１１−２４｝面を所定角度（例：±１０°以内）傾けた面、｛１０−１２｝面、｛１０−１２｝面を所定角度（例：±１０°以内）傾けた面、｛１０−１１｝面、｛１０−１１｝面を所定角度（例：±１０°以内）傾けた面、｛２０−２１｝面、｛２０−２１｝面を所定角度（例：±１０°以内）傾けた面、｛２０−２３｝面、及び、｛２０−２３｝面を所定角度（例：±１０°以内）傾けた面の中のいずれかを任意に組み合わせたものであってもよい。例えば、第１乃至第Ｎの結晶部分の中には、面方位が互いに５°より大きくずれているペアが含まれてもよい。本実施形態によれば、このような結晶部分同士が互いに接合したIII族窒化物半導体層１０を実現することができる。 In addition, the surface orientation of the exposed surface of the first to Nth (N is an integer of 2 or more) crystal portions is not particularly limited. For example, the combinations of the plane orientations of the exposed surfaces of the first to Nth crystal portions are a predetermined angle (eg, ± 10) with respect to the + c plane, m plane, a plane, {11-22} plane, and {11-22} plane. Within [deg.] Tilted surface, {11-24} plane, {11-24} plane tilted at a predetermined angle (eg, within ± 10 [deg.]), {10-12} plane, {10-12} plane specified Angled surface (eg, within ± 10 °), {10-11} surface, {10-11} surface inclined at a predetermined angle (eg, within ± 10 °), {20-21} surface, {20 -21} surface inclined by a predetermined angle (eg, within ± 10 °), {20-23} surface, and {20-23} surface inclined by a predetermined angle (eg, within ± 10 °) Any of these may be combined arbitrarily. For example, the first to Nth crystal portions may include pairs whose plane orientations are shifted from each other by more than 5 °. According to this embodiment, the group III nitride semiconductor layer 10 in which such crystal parts are bonded to each other can be realized.
次に、図１３に、本実施形態のIII族窒化物半導体基板１の平面模式図の一例を示す。そして、図１２及び図１４に、本実施形態のIII族窒化物半導体基板１の側面模式図の他の一例を示す。 Next, FIG. 13 shows an example of a schematic plan view of the group III nitride semiconductor substrate 1 of the present embodiment. FIG. 12 and FIG. 14 show another example of a schematic side view of the group III nitride semiconductor substrate 1 of the present embodiment.
図１２及び図１４に示すように、当該例の場合、III族窒化物半導体基板１は、III族窒化物半導体層１０に加えて下地層２０を有する。 As shown in FIGS. 12 and 14, in the case of this example, the group III nitride semiconductor substrate 1 has a base layer 20 in addition to the group III nitride semiconductor layer 10.
下地層２０は、III族窒化物半導体の複数の結晶片（第１の結晶片２１、第２の結晶片２２等）が並んで構成される。複数の結晶片は、上記本実施形態のIII族窒化物半導体基板１の製造方法で説明した通り、露出面の面方位が互いに異なる第１乃至第Ｎの結晶片に分かれ、当該露出面が同一方向を向くように並んでいる。III族窒化物半導体層１０は、下地層２０の露出面（結晶片の露出面）の上にIII族窒化物半導体をエピタキシャル成長させることで形成されている。下地層２０において、第１乃至第Ｎの結晶片各々がひとまとまりとなって並んでいてもよい。 The underlayer 20 is composed of a plurality of group III nitride semiconductor crystal pieces (a first crystal piece 21, a second crystal piece 22, and the like). The plurality of crystal pieces are divided into first to Nth crystal pieces having different plane orientations of the exposed surfaces, as described in the method of manufacturing the group III nitride semiconductor substrate 1 of the present embodiment, and the exposed surfaces are the same. They are lined up to face the direction. The group III nitride semiconductor layer 10 is formed by epitaxially growing a group III nitride semiconductor on the exposed surface of the underlayer 20 (exposed surface of the crystal piece). In the underlayer 20, each of the first to Nth crystal pieces may be arranged together.
次に、本実施形態の作用効果について説明する。 Next, the effect of this embodiment is demonstrated.
本実施形態によれば、III族窒化物半導体で構成された第１乃至第Ｎ（Ｎは２以上の整数）の結晶部分を含むIII族窒化物半導体層１０を有し、第１乃至第Ｎの結晶部分は、III族窒化物半導体層の表面における面方位が互いに異なるIII族窒化物半導体基板１が実現される。 According to this embodiment, the group III nitride semiconductor layer 10 including the first to Nth (N is an integer of 2 or more) crystal parts composed of a group III nitride semiconductor is provided, and the first to Nth layers are included. In the crystal part, the group III nitride semiconductor substrate 1 having different plane orientations on the surface of the group III nitride semiconductor layer is realized.
このようなIII族窒化物半導体基板１の場合、成長面（III族窒化物半導体層１０の表面）において、互いに面方位が異なる複数のエリアが現れる。各エリアに各面方位に応じた性質のデバイスを形成することで、互いに性質が異なる複数種類のデバイスを形成することができる。 In the case of such a group III nitride semiconductor substrate 1, a plurality of areas having different plane orientations appear on the growth surface (the surface of the group III nitride semiconductor layer 10). By forming a device having a property corresponding to each plane orientation in each area, a plurality of types of devices having different properties can be formed.
また、本実施形態によれば、第１の面方位の露出面を有する結晶部分により、第１の面方位と異なる第２の面方位の露出面を有する結晶部分を挟み込んだ状態となるIII族窒化物半導体層１０を形成することもできる。例えば、図１５に示す例において、第１の結晶部分１１及び第３の結晶部分１３の面方位を同じとし（第１の面方位）、第２の結晶部分１２の面方位を異なるものとした場合（第２の面方位）、第１の面方位の露出面を有する第１の結晶部分１１及び第３の結晶部分１３により、第１の面方位と異なる第２の面方位の露出面を有する第２の結晶部分１２が挟まれた状態となる。このように、露出面が所定の面方位となっている結晶部分に、露出面が他の所定の面方位となっている結晶部分を挟み込むことで、応力緩和等の効果が期待される。 In addition, according to the present embodiment, a group III in which a crystal portion having an exposed surface having a second surface orientation different from the first surface orientation is sandwiched between crystal portions having an exposed surface having a first surface orientation. The nitride semiconductor layer 10 can also be formed. For example, in the example shown in FIG. 15, the first crystal portion 11 and the third crystal portion 13 have the same plane orientation (first plane orientation), and the second crystal portion 12 has a different plane orientation. In the case (second plane orientation), an exposed surface having a second plane orientation different from the first plane orientation is formed by the first crystal portion 11 and the third crystal portion 13 having the exposed surface having the first plane orientation. It will be in the state where the 2nd crystal part 12 to have was pinched. In this way, an effect such as stress relaxation is expected by sandwiching a crystal part having an exposed surface in another predetermined plane orientation in a crystal part in which the exposed surface has a predetermined plane orientation.
＜＜実施例＞＞
露出面の面方位が互いに大きく異なる２つの結晶片を、当該露出面が同一方向を向くように並べて形成した下地層２０の上にIII族窒化物半導体を成長させた場合、各結晶片から成長したIII族窒化物半導体結晶同志が接合することを確認した。
<< Example >>
When a group III nitride semiconductor is grown on an underlayer 20 formed by arranging two crystal pieces whose exposed surface orientations are greatly different from each other so that the exposed surfaces are oriented in the same direction, the crystal grows from each crystal piece. It was confirmed that the group III nitride semiconductor crystals joined together.
まず、露出面の面方位が互いに大きく異なる２つの結晶片を準備した。極点図測定で２つの結晶片の露出面を評価したところ、一方（第１の結晶片）は、露出面の面方位が＋Ｃ面であった。他方（第２の結晶片）は、＋Ｃ面が露出面から５０°程度傾いていた。 First, two crystal pieces having different plane orientations of the exposed surfaces were prepared. When the exposed surfaces of two crystal pieces were evaluated by pole figure measurement, the surface orientation of the exposed surface of one (first crystal piece) was the + C plane. The other (second crystal piece) had a + C plane inclined about 50 ° from the exposed surface.
この２つの結晶片を、露出面が同一方向を向くように、互いの側面で互いに接する状態で基板ホルダ上に配置して下地層２０を形成した。そして、当該下地層２０の上に、以下の条件でIII族窒化物半導体を成長させた。 The underlayer 20 was formed by placing the two crystal pieces on the substrate holder so that the exposed surfaces faced in the same direction and in contact with each other. Then, a group III nitride semiconductor was grown on the underlayer 20 under the following conditions.
装置：ＨＶＰＥ装置
成長温度：１０４０℃
V／III比：１０
成長時間：２７０分
Equipment: HVPE equipment Growth temperature: 1040 ° C
V / III ratio: 10
Growth time: 270 minutes
図１８に、III族窒化物半導体を成長させた後のIII族窒化物半導体基板１の平面を蛍光顕微鏡で観察した画像を示す。特に、第１の結晶片から成長した第１の結晶部分と、第２の結晶片から成長した第２の結晶部分との境界部分を示している。図示するように、第１の結晶部分と第２の結晶部分とが互いに結合したことを確認した。これにより、露出面の面方位が互いに異なる複数の結晶片を並べて下地層２０を形成後、当該下地層２０の上にIII族窒化物半導体を成長させると、各結晶片から成長したIII族窒化物半導体結晶が互いに接合して、III族窒化物半導体層１０を形成することが確認できた。 FIG. 18 shows an image obtained by observing the plane of the group III nitride semiconductor substrate 1 after growing the group III nitride semiconductor with a fluorescence microscope. In particular, a boundary portion between a first crystal portion grown from the first crystal piece and a second crystal portion grown from the second crystal piece is shown. As shown in the figure, it was confirmed that the first crystal portion and the second crystal portion were bonded to each other. Thus, after forming a base layer 20 by arranging a plurality of crystal pieces having different plane orientations of the exposed surface, a group III nitride semiconductor is grown on the base layer 20, and the group III nitride grown from each crystal piece is formed. It was confirmed that the compound semiconductor crystals were bonded to each other to form the group III nitride semiconductor layer 10.
以下、参考形態の例を付記する。
１． III族窒化物半導体で構成された第１乃至第Ｎ（Ｎは２以上の整数）の結晶部分を含むIII族窒化物半導体層を有し、
前記第１乃至第Ｎの結晶部分は、前記III族窒化物半導体層の表面における面方位が互いに異なるIII族窒化物半導体基板。
２． １に記載のIII族窒化物半導体基板において、
前記第１乃至第Ｎの結晶部分は互いに接合しているIII族窒化物半導体基板。
３． １又は２に記載のIII族窒化物半導体基板において、
前記III族窒化物半導体層の前記表面における占有面積が１５％以上である前記結晶部分を少なくとも２つ有するIII族窒化物半導体基板。
４． １から３のいずれかに記載のIII族窒化物半導体基板において、
前記III族窒化物半導体層において、前記第１乃至第Ｎの結晶部分各々がひとまとまりとなっているIII族窒化物半導体基板。
５． １から４のいずれかに記載のIII族窒化物半導体基板において、
前記第１乃至第Ｎの結晶部分の中には、前記面方位が互いに５°より大きくずれているペアが含まれるIII族窒化物半導体基板。
６． １から５のいずれかに記載のIII族窒化物半導体基板において、
III族窒化物半導体の複数の結晶片が並んで構成された下地層をさらに有し、
前記下地層は、露出面の面方位が互いに異なる第１乃至第Ｎの結晶片を含むIII族窒化物半導体基板。
７． ６に記載のIII族窒化物半導体基板において、
前記III族窒化物半導体層は、前記下地層の前記露出面の上にIII族窒化物半導体をエピタキシャル成長させることで形成されているIII族窒化物半導体基板。
８． ６又は７に記載のIII族窒化物半導体基板において、
前記第１乃至第Ｎの結晶片の中の少なくとも１つは複数の結晶片を有し、当該複数の結晶片は前記下地層においてひとまとまりとなって並んでいるIII族窒化物半導体基板。
９． 露出面の面方位が互いに異なる第１乃至第Ｎ（Ｎは２以上の整数）のIII族窒化物半導体の複数の結晶片を、前記露出面が同一方向を向くように並べる下地層準備工程と、
前記下地層準備工程の後、前記露出面上にIII族窒化物半導体をエピタキシャル成長させ、前記結晶片各々から成長したIII族窒化物半導体同志を接合させるIII族窒化物半導体層形成工程と、
を有するIII族窒化物半導体基板の製造方法。
１０． ９に記載のIII族窒化物半導体基板の製造方法において、
前記III族窒化物半導体層形成工程の後、複数の前記結晶片で構成された下地層を除去する除去工程をさらに有するIII族窒化物半導体基板の製造方法。
Hereinafter, examples of the reference form will be added.
1. A group III nitride semiconductor layer including first to N-th (N is an integer of 2 or more) crystal parts composed of a group III nitride semiconductor;
The first to Nth crystal parts are group III nitride semiconductor substrates having different plane orientations on the surface of the group III nitride semiconductor layer.
2. In the group III nitride semiconductor substrate according to 1,
A group III nitride semiconductor substrate in which the first to Nth crystal portions are bonded to each other.
3. In the group III nitride semiconductor substrate according to 1 or 2,
A group III nitride semiconductor substrate having at least two crystal portions each having an occupied area of 15% or more on the surface of the group III nitride semiconductor layer.
4). In the group III nitride semiconductor substrate according to any one of 1 to 3,
A group III nitride semiconductor substrate, wherein each of the first to Nth crystal portions is a group in the group III nitride semiconductor layer.
5. In the group III nitride semiconductor substrate according to any one of 1 to 4,
A group III nitride semiconductor substrate in which the first to Nth crystal portions include pairs whose plane orientations are shifted from each other by more than 5 °.
6). In the group III nitride semiconductor substrate according to any one of 1 to 5,
It further has an underlayer configured by arranging a plurality of crystal pieces of a group III nitride semiconductor,
The underlayer is a group III nitride semiconductor substrate including first to Nth crystal pieces having different exposed surface orientations.
7). In the group III nitride semiconductor substrate according to 6,
The group III nitride semiconductor layer is a group III nitride semiconductor substrate formed by epitaxially growing a group III nitride semiconductor on the exposed surface of the base layer.
8). In the group III nitride semiconductor substrate according to 6 or 7,
At least one of the first to Nth crystal pieces has a plurality of crystal pieces, and the plurality of crystal pieces are arranged in a group in the underlayer.
9. A base layer preparation step of arranging a plurality of crystal pieces of first to Nth (N is an integer of 2 or more) Group III nitride semiconductors having different surface orientations of the exposed surfaces so that the exposed surfaces are directed in the same direction; ,
After the underlayer preparation step, a group III nitride semiconductor layer is formed on the exposed surface by epitaxial growth of a group III nitride semiconductor, and a group III nitride semiconductor layer grown from each of the crystal pieces is joined.
A method for producing a group III nitride semiconductor substrate having:
10. In the method for producing a group III nitride semiconductor substrate according to 9,
A method for manufacturing a group III nitride semiconductor substrate, further comprising a removal step of removing the underlayer composed of the plurality of crystal pieces after the step of forming the group III nitride semiconductor layer.
１ III族窒化物半導体基板
１０ III族窒化物半導体層
１１ 第１の結晶部分
１２ 第２の結晶部分
１３ 第３の結晶部分
２０ 下地層
２１ 第１の結晶片
２１−１ 第１の結晶片
２１−２ 第１の結晶片
２１−３ 第１の結晶片
２１−４ 第１の結晶片
２２ 第２の結晶片
２２−１ 第２の結晶片
２２−２ 第２の結晶片
２２−３ 第２の結晶片
２２−４ 第２の結晶片
１０１ 第１のIII族窒化物半導体基板
１０２ 第２のIII族窒化物半導体基板
１００ ＨＶＰＥ装置
１２１ 反応管
１２２ 成長領域
１２４ ガス供給管
１２５ 配管
１２６ ガス供給管
１２７ III族原料
１２８ ソースボート
１２９ ヒータ
１３０ ヒータ
１３２ 回転軸
１３５ ガス排出管
１３６ 遮蔽板
１３７ 窒素原料ガス供給部
１３９ III族原料ガス供給部
２００ 基板ホルダ
1 Group III Nitride Semiconductor Substrate 10 Group III Nitride Semiconductor Layer 11 First Crystal Part 12 Second Crystal Part 13 Third Crystal Part 20 Underlayer 21 First Crystal Piece 21-1 First Crystal Piece 21 -2 1st crystal piece 21-3 1st crystal piece 21-4 1st crystal piece 22 2nd crystal piece 22-1 2nd crystal piece 22-2 2nd crystal piece 22-3 2nd Crystal piece 22-4 second crystal piece 101 first group III nitride semiconductor substrate 102 second group III nitride semiconductor substrate 100 HVPE apparatus 121 reaction tube 122 growth region 124 gas supply tube 125 piping 126 gas supply tube 127 Group III material 128 Source boat 129 Heater 130 Heater 132 Rotating shaft 135 Gas discharge pipe 136 Shielding plate 137 Nitrogen material gas supply unit 139 Group III material gas supply unit 200 Substrate holder
Claims (10)
前記第１乃至第Ｎの結晶部分は、前記III族窒化物半導体層の表面における面方位が互いに異なるIII族窒化物半導体基板。 A group III nitride semiconductor layer including first to N-th (N is an integer of 2 or more) crystal parts composed of a group III nitride semiconductor;
The first to Nth crystal parts are group III nitride semiconductor substrates having different plane orientations on the surface of the group III nitride semiconductor layer.
前記第１乃至第Ｎの結晶部分は互いに接合しているIII族窒化物半導体基板。 In the group III nitride semiconductor substrate according to claim 1,
A group III nitride semiconductor substrate in which the first to Nth crystal portions are bonded to each other.
前記III族窒化物半導体層の前記表面における占有面積が１５％以上である前記結晶部分を少なくとも２つ有するIII族窒化物半導体基板。 In the group III nitride semiconductor substrate according to claim 1 or 2,
A group III nitride semiconductor substrate having at least two crystal portions each having an occupied area of 15% or more on the surface of the group III nitride semiconductor layer.
前記III族窒化物半導体層において、前記第１乃至第Ｎの結晶部分各々がひとまとまりとなっているIII族窒化物半導体基板。 In the group III nitride semiconductor substrate according to any one of claims 1 to 3,
A group III nitride semiconductor substrate, wherein each of the first to Nth crystal portions is a group in the group III nitride semiconductor layer.
前記第１乃至第Ｎの結晶部分の中には、前記面方位が互いに５°より大きくずれているペアが含まれるIII族窒化物半導体基板。 In the group III nitride semiconductor substrate according to any one of claims 1 to 4,
A group III nitride semiconductor substrate in which the first to Nth crystal portions include pairs whose plane orientations are shifted from each other by more than 5 °.
III族窒化物半導体の複数の結晶片が並んで構成された下地層をさらに有し、
前記下地層は、露出面の面方位が互いに異なる第１乃至第Ｎの結晶片を含むIII族窒化物半導体基板。 In the group III nitride semiconductor substrate according to any one of claims 1 to 5,
It further has an underlayer configured by arranging a plurality of crystal pieces of a group III nitride semiconductor,
The underlayer is a group III nitride semiconductor substrate including first to Nth crystal pieces having different exposed surface orientations.
前記III族窒化物半導体層は、前記下地層の前記露出面の上にIII族窒化物半導体をエピタキシャル成長させることで形成されているIII族窒化物半導体基板。 In the group III nitride semiconductor substrate according to claim 6,
The group III nitride semiconductor layer is a group III nitride semiconductor substrate formed by epitaxially growing a group III nitride semiconductor on the exposed surface of the base layer.
前記第１乃至第Ｎの結晶片の中の少なくとも１つは複数の結晶片を有し、当該複数の結晶片は前記下地層においてひとまとまりとなって並んでいるIII族窒化物半導体基板。 In the group III nitride semiconductor substrate according to claim 6 or 7,
At least one of the first to Nth crystal pieces has a plurality of crystal pieces, and the plurality of crystal pieces are arranged in a group in the underlayer.
前記下地層準備工程の後、前記露出面上にIII族窒化物半導体をエピタキシャル成長させ、前記結晶片各々から成長したIII族窒化物半導体同志を接合させるIII族窒化物半導体層形成工程と、
を有するIII族窒化物半導体基板の製造方法。 A base layer preparation step of arranging a plurality of crystal pieces of first to Nth (N is an integer of 2 or more) Group III nitride semiconductors having different surface orientations of the exposed surfaces so that the exposed surfaces are directed in the same direction; ,
After the underlayer preparation step, a group III nitride semiconductor layer is formed on the exposed surface by epitaxial growth of a group III nitride semiconductor, and a group III nitride semiconductor layer grown from each of the crystal pieces is joined.
A method for producing a group III nitride semiconductor substrate having:
前記III族窒化物半導体層形成工程の後、複数の前記結晶片で構成された下地層を除去する除去工程をさらに有するIII族窒化物半導体基板の製造方法。 In the manufacturing method of the group III nitride semiconductor substrate according to claim 9,
A method for manufacturing a group III nitride semiconductor substrate, further comprising a removal step of removing the underlayer composed of the plurality of crystal pieces after the step of forming the group III nitride semiconductor layer.
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