JP2018056760A - Differential amplifier and voltage follower circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an input offset voltage of a differential amplifier.SOLUTION: An input differential pair 102 generates a differential current according to each voltage of an inverted input terminal (IN-) and a non-inverted input terminal (IN;). A tail current source 104 supplies a tail current I to the input differential pair 102. A first resistance Ris provided between a first terminal of a first input transistor Mand the tail current source 104. A second resistance Ris provided between a first terminal of a second input transistor Mand the tail current source 104. A constant current circuit 106 is connected to the respective second terminals of the first input transistor Mand the second input transistor Mand generates constant currents Iand I. A correction circuit 120 is connected to the respective second terminals of the first input transistor Mand the second input transistor Mand generates correction currents I,Iaccording to an electric potential difference between the respective first terminals of the first input transistor Mand the second input transistor M.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a differential amplifier.

In many electronic circuits, differential amplifiers (operational amplifiers) are used. The differential amplifier is a circuit that amplifies a difference between two input voltages. FIG. 1A is a circuit diagram of a buffer circuit (voltage follower, voltage tracker) which is one of applications of a differential amplifier. The voltage follower circuit 200 includes a differential amplifier 100R in which an output and an inverting input are connected. An input voltage _VIN from the voltage source 204 is input to the input of the voltage follower circuit 200 (the non-inverting input of the differential amplifier 100R), and a smoothing capacitor 202 is connected to the output thereof. Is done.

  FIG. 1B is a circuit diagram illustrating a configuration example of the differential amplifier. The differential amplifier 100R mainly includes an input differential pair 102, a tail current source 104, a constant current circuit 106, and an output stage 110.

Input differential pair 102 includes a first input transistor _{M 1} and the second input transistor _{M 2.} A first input transistor _{M 1} gate is connected to the inverting input of the differential amplifier 100R (IN-), the second input transistor _{M 2} gate is connected to the non-inverting input of the differential amplifier 100R (IN +).

The tail current source 104 supplies a tail current I to the input differential pair 102. Tail current source 104 includes a P-channel MOS transistor _{M 3} in which the first bias terminal (bias1) terminal is connected to the gate, in accordance with the voltage of the bias1 terminal, tail current I is defined.

The constant current circuit 106 is a so-called active load connected to the input differential pair 102 and includes a transistor M ₄ connected to the transistor M ₁ and a transistor M ₅ connected to the transistor M ₂ . The transistors M ₄ and M ₅ generate a constant current corresponding to the voltage at the bias1 terminal.

The output stage 110 converts the difference between the currents I _M1 and I _M2 flowing through the transistors M ₁ and M ₂ constituting the input differential pair 102 into an output voltage _VOUT and outputs the output voltage from the OUT terminal.

When a large-capacity capacitor (capacitive load) is connected to the output terminal OUT of the differential amplifier 100R as in the voltage follower circuit 200 of FIG. 1A, phase compensation is performed on the drain side of the input differential pair 102. Therefore, resistors R ₁ and R ₂ and a capacitor C ₃ are inserted.

Japanese Patent Application No. 2015-024291

  As a result of studying the differential amplifier 100R in FIG. 1B, the present inventors have recognized the following problems.

The phase compensation resistors R ₁ and R ₂ are designed to have the same resistance value R, and the input offset voltage V _OS of the differential amplifier 100R is zero in an ideal state. However, in reality, a mismatch occurs in the resistance values R of the resistors R ₁ and R ₂ , which causes the input offset voltage V _OS .

Consider the effects of resistance mismatch. For simplicity, not mismatch occurs in the transistor, the resistance value of the resistor R ₂ is to be increased ΔR than the design value R. Due to the increased resistance component ΔR, the source voltage V _S2 of the second input transistor M ₂ becomes lower than the source voltage V _{S1 of} the first input transistor M ₁ . This potential difference V _S2 −V _S1 becomes the input offset voltage V _OS . In the voltage follower circuit 200, the offset voltage V _OS appears as a difference between the input voltage V _IN and the output voltage V _OUT and can be defined by Expression (1).
V _IN −V _OUT = V _OS (1)

The relational expression between the source voltages V _S1 and V _{S2 of the} differential pair transistors M ₁ and M ₂ , the input voltage V _IN , and the output voltage V _OUT is as follows.
V _IN + V _GS2 = V _S2
V _OUT + V _GS1 = V _S1
Here, when the expression is arranged as V _GS1 = V _GS2 , Expression (2) is obtained.
V _IN −V _OUT = V _OS = V _S2 −V _S1 (2)
Next, the relationship between voltage _{V C} and the source voltage _{V S1, V S2} common terminal VC of the formula (3) is expressed by (4).
V _C −V _S2 = (I / 2 + ΔI) × (R + ΔR) (3)
V _C −V _S1 = (I / 2−ΔI) × R (4)
By arranging the equations (2) to (4), the input offset voltage V _OS generated by the resistance mismatch is obtained as the equation (5).
V _OS = V _S2 −V _S1 = (I / 2 + ΔI) × (R + ΔR) − (I / 2−ΔI) × R
= 2ΔI · R + 1/2 · ΔR + ΔI · ΔR (5)

As is apparent from the equation (5), the input offset voltage V _OS is generated according to the resistance mismatch amount ΔR.

In general, the resistances R ₁ and R ₂ for phase compensation are arranged close to each other on a semiconductor chip (die) so as to have a pair property. Accordingly, consideration is given to reducing the mismatch ΔR of the resistance values of the resistors R ₁ and R ₂ with respect to process variations and temperature variations. However, it is difficult to make the mismatch ΔR completely zero.

Conventionally, resistors R _1, trimming the resistance value of R ₂ (adjusted) capable constitute, in an inspection process before shipment of the semiconductor chip, the input offset voltage V _OS is the resistor R _1, R ₂ as close to zero The resistance value is adjusted.

However, after the trimming is completed, when the semiconductor chip of the differential amplifier 100 is accommodated in the package or when the package is mounted on the printed board, stress is generated in the semiconductor chip, and the resistance values of the resistors R ₁ and R ₂ In some cases, a later mismatch may occur.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and one of exemplary objects of an embodiment thereof is to provide a differential amplifier having an improved input offset voltage.

  One embodiment of the present invention relates to a differential amplifier. The differential amplifier includes a first input transistor and a second input transistor. The differential amplifier generates a differential current corresponding to the voltage of each of the inverting input terminal and the non-inverting input terminal, and a tail current in the input differential pair. , A first resistor provided between the first terminal of the first input transistor and the tail current source, and a second resistor provided between the first terminal of the second input transistor and the tail current source. A constant current circuit for generating a constant current connected to the second terminal of the first input transistor and the second terminal of the second input transistor; the second terminal of the first input transistor; and the second terminal of the second input transistor Connected to the output stage for generating the output voltage, the second terminal of the first input transistor and the second terminal of the second input transistor, and the first terminal of the first input transistor, And a correction circuit for generating a correction current differential in accordance with the potential difference between the first terminal of the second input transistor.

  According to this aspect, the mismatch between the first resistor and the second resistor can be corrected.

  The correction circuit includes a first correction transistor and a second correction transistor, and generates a correction current that generates a differential correction current according to the voltages of the first terminal of the first input transistor and the first terminal of the second input transistor. And a correction current source for supplying a current to the correction differential pair.

  The first correction transistor and the second correction transistor may have the same polarity as the first input transistor and the second input transistor. The same polarity includes not only the case where the transistors are the same type and the same polarity (conductivity type) but also the case where the transistors are different types and the same polarity (conductivity type).

  The first correction transistor and the second correction transistor have opposite polarities (different polarities) to the first input transistor and the second input transistor, and the correction circuit loops back the current flowing through the first correction transistor and the second correction transistor. A current mirror circuit for generating a dynamic correction current may be further included. The reverse polarity includes not only the case where the transistors are of the same type and different polarities (conductivity types) but also the case where the transistors are different types and have different polarities (conductivity types).

  The input differential pair is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the first correction transistor and the second correction transistor may be PNP-type bipolar transistors.

  The input differential pair is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the first correction transistor and the second correction transistor may be NPN bipolar transistors.

  The input differential pair is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the first correction transistor and the second correction transistor may be NPN bipolar transistors.

  The input differential pair is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the first correction transistor and the second correction transistor may be PNP bipolar transistors.

  Another aspect of the present invention is also a differential amplifier. The differential amplifier includes an inverting input terminal and a non-inverting input terminal, a first input transistor having a control terminal connected to the inverting input terminal, a second input transistor having a control terminal connected to the non-inverting input terminal, a tail, A tail current source for supplying current, a first resistor provided between the tail current source and the first terminal of the first input transistor, and a second resistor provided between the tail current source and the first terminal of the second input transistor. The resistor, the control terminal are connected to the first terminal of the first input transistor, the first correction transistor having the same polarity as the first input transistor, the control terminal is connected to the first terminal of the second input transistor, and the second input A second correction transistor having the same polarity as the transistor; a correction current source connected to the first terminal of the first correction transistor and the first terminal of the second correction transistor; A first current source connected to the second terminal of the transistor and the second terminal of the first correction transistor; a second current source connected to the second terminal of the second input transistor and the second terminal of the second correction transistor; And an output stage connected to the second terminal of the first input transistor and the second terminal of the second input transistor to generate an output voltage.

  Yet another embodiment of the present invention is also a differential amplifier. The differential amplifier includes an inverting input terminal and a non-inverting input terminal, a first input transistor having a control terminal connected to the inverting input terminal, a second input transistor having a control terminal connected to the non-inverting input terminal, a tail, A tail current source for supplying current, a first resistor provided between the tail current source and the first terminal of the first input transistor, and a second resistor provided between the tail current source and the first terminal of the second input transistor. The resistor, the control terminal are connected to the first terminal of the first input transistor, the first correction transistor having the opposite polarity to the first input transistor, the control terminal is connected to the first terminal of the second input transistor, and the second input A second correction transistor having a polarity opposite to that of the transistor; a correction current source connected to the first terminal of the first correction transistor and the first terminal of the second correction transistor; Connected to the first current mirror circuit for folding the current flowing through the transistor, the second current mirror circuit for folding the current flowing through the second correction transistor, the second terminal of the first input transistor, and the output terminal of the first current mirror circuit. A first current source; a second current source connected to a second terminal of the second input transistor and an output terminal of the second current mirror circuit; a second terminal of the first input transistor; and a second terminal of the second input transistor. And an output stage for generating an output voltage.

  The differential amplifier may be integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, the characteristics of the differential amplifier can be improved.

FIG. 1A is a circuit diagram of a buffer circuit which is one application of a differential amplifier, and FIG. 1B is a circuit diagram showing a configuration example of the differential amplifier. 1 is a circuit diagram of a differential amplifier according to an embodiment. FIG. It is a circuit diagram of the structural example of a differential amplifier. 4A and 4B are diagrams showing the correction effect of the input offset voltage V _OS in the differential amplifier of FIG. It is a circuit diagram which shows another structural example of a differential amplifier. FIG. 10 is a circuit diagram of a differential amplifier according to a second modification.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through other members that do not affect the state or inhibit the function is also included.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. This includes cases where the connection is indirectly made through other members that do not affect the connection state or inhibit the function.

FIG. 2 is a circuit diagram of the differential amplifier 100 according to the embodiment. The differential amplifier 100 mainly includes an input differential pair 102, a tail current source 104, a constant current circuit 106, a phase compensation circuit 108, an output stage 110, and a correction circuit 120, and is integrated on a single semiconductor substrate. Differential amplifier 100 amplifies a potential difference between the inverting input terminal (IN-) and the non-inverting input terminal (IN +), and outputs an output voltage _{V OUT} from the output terminal OUT.

The input differential pair 102 includes a first input transistor M ₁ and a second input transistor M ₂ that are P-channel MOSFETs. First input transistor M ₁ of the control terminal (gate) is connected to the inverting input terminal IN-, the control terminal of the second input transistor M ₂ is connected to the non-inverting input terminal IN +. The input differential pair 102 generates differential currents I _M1 and I _M2 corresponding to the voltages V _{IN +} and V _IN− of the inverting input terminal IN− and the non-inverting input terminal IN +, respectively.

The tail current source 104 supplies a tail current I to the input differential pair 102. For example the tail current source 104 includes a transistor _{M 3} is a P-channel MOSFET in which a control terminal (gate) is connected to the bias terminal bias1.

The phase compensation circuit 108 is inserted between the input differential pair 102 and the tail current source 104. The phase compensation circuit 108 includes a first resistor R ₁ , a second resistor R ₂ and a capacitor C ₁ . The first resistor R ₁ is provided between the first terminal (source) of the first input transistor M ₁ and the tail current source 104, and the second resistor R ₂ is the first terminal (source) of the second input transistor M ₂ . And the tail current source 104. Capacitor C ₁ is connected between a first source of input transistor M ₁ second source of input transistor M _2.

The constant current circuit 106 is connected to the second terminal of the first input transistor _{M 1} (drain) and a second input second terminal of the transistor _{M 2} (drain), for generating a constant current _{I M4, I M5.} For example, the constant current circuit 106 includes transistors M ₄ and M ₅ that are N-channel MOSFETs whose control terminals (gates) are commonly connected. The transistors M ₄ and M ₅ are biased by a voltage corresponding to the voltage V _{bias1 of the} bias1 terminal so that currents I _M4 and I _M5 proportional to the tail current I generated by the tail current source 104 flow. Transistor _{M 11} More specifically forms a current mirror circuit together with the transistor _M 4, _{M 5.} The gate of the transistor _{M 12} is connected to the bias1 terminal, the transistor _{M 12,} the current _{I M12} proportional to the tail current I flows, thus proportional to the current _{I M4, I M5} and the current I generated by the constant current circuit 106 There is a relationship.

Output stage 110 is connected to the second terminal of the first input transistor _{M 1} (drain) and a second input second terminal of the transistor _{M 2} (drain), and generates an output voltage _{V OUT.} For example, the output stage 110 includes transistors M ₆ , M ₇ , M ₈ , and M ₉ . The transistors M ₆ and M ₇ are N-channel MOSFETs, and their control terminals (gates) are connected to the bias2 terminal and supplied with a predetermined bias voltage. Transistors M ₈ and M _{9 form} a current mirror circuit. The drain of the transistor M ₆ is connected to the output terminal OUT.

  The circuit configurations of the constant current circuit 106 and the output stage 110 are not particularly limited, and various known circuit formats can be adopted. For example, a cascode type may be used as the current mirror circuit.

Correction circuit 120 receives a first input transistor _{M 1} of the voltage of the first terminal (the source _{voltage) V S1} and the second input first terminal (the source _{voltage) V S2} of the transistor _{M 2.} The two outputs of the correction circuit 120 is connected to the second terminal of the first input transistor M ₁ (drain) and a second input second terminal of the transistor M ₂ (drain), the source of the first input transistor I _M1 generating a differential correction current _{I CMP1, I CMP2} that the voltage _{V S1} according to the potential difference of the second input transistor _{M 2} of the source voltage _{V S2.}

  The present invention is understood as the block diagram and circuit diagram of FIG. 2 or extends to various devices and circuits derived from the above description, and is not limited to a specific configuration. In the following, more specific configuration examples and examples will be described in order not to narrow the scope of the present invention but to help understanding and clarify the essence and circuit operation of the present invention.

FIG. 3 is a circuit diagram of a configuration example of the differential amplifier 100. In FIG. 3, a differential amplifier 100 is used. The correction circuit 120 includes a correction differential pair 122 and a correction current source 124. The correction differential pair 122 is a differential correction current according to the voltage V _S1 of the first terminal (source) of the first input transistor M ₁ and the voltage V _S2 of the first terminal (source) of the second input transistor M ₂ . I _CMP1 and I _CMP2 are generated. The correction current source 124 supplies a constant current I ₂ to the correction differential pair 122.

More specifically correction differential pair 122 includes a first correction transistor _{Q 1} and the second correction transistor _{Q 2} of PNP type. The PNP-type bipolar transistor has the same polarity as the P-channel MOSFET constituting the input differential pair 102. Voltages V _S1 and V _S2 of the sources of the first input transistor M ₁ and the second input transistor M ₂ are input to the control terminals (bases) of the first correction transistor Q ₁ and the second correction transistor Q _2, respectively. Correction current source 124 includes a transistor _{M 10} is a P-channel MOSFET. The gate of the transistor _{M 10} is connected to the bias1 terminal, the transistor _M 12, _{M 3} form a current mirror circuit, a constant current _{I 2} the correction current source 124 generates the tail current tail current source 104 generates Proportional to I.

The above is an example of the configuration of the differential amplifier 100. Next, the operation will be described.
Now, it is assumed that a mismatch occurs between the resistance values of the resistors R ₁ and R ₂ and R ₁ = R, R ₂ = R + ΔR. At this time, the current I _M1 of the transistor M ₁ increases by ΔI, and the current I _M2 of the transistor M ₂ decreases by ΔI.
I _M1 = I / 2 + ΔI
I _M2 = I / 2−ΔI

The source voltage V _S2 of the second input transistor M ₂ is lower than the source voltage V _{S1 of} the first input transistor M ₁ . Then, it increases the correction current _{I CMP2} flowing through the transistor _{Q 2} of the correction differential pair 122, the correction current _{I CMP1} flowing through the transistor _{Q 1} is reduced.
I _CMP1 = I ₂ / 2-ΔI ′
_{I CMP2 = I 2/2 +} ΔI '

The correction current generated by the correction circuit 120 is superimposed on the differential current flowing from the input differential pair 102 into the constant current circuit 106. Therefore, the corrected differential currents are I _M1 + I _CMP1 and I _M2 + I _CMP2 . That is, the increase ΔI of the current I _M1 of the transistor M ₁ cancels out with the decrease ΔI ′ of the current I _M1 of the transistor Q ₁ , and the decrease ΔI of the current I _M2 of the transistor M ₂ becomes the current I _{M1 of the} transistor Q _2. The amount of increase ΔI ′ cancels out.

The correction circuit 120 uses the difference between the source voltages V _S1 and V _S2 due to the mismatch between the resistors R ₁ and R ₂ , in other words, the input offset voltage V _OS of the differential amplifier 100 as the differential correction currents _ICMP1 and _ICMP2. The drain currents I _M1 + I _CMP1 and I _M2 + I _CMP2 flowing into the constant current circuit 106 are fed back so as to be constant.

When the voltage follower circuit 200 is configured as shown in FIG. 3, feedback is applied so that V _IN = V _OUT is established. Therefore, the source voltages V _S1 and V _S2 of the first input transistor M ₁ and the second input transistor M ₂ are equal, and the input offset voltage V _OS can be brought close to zero.

The above is the operation of the differential amplifier 100. According to the differential amplifier 100, the correction effect of the correction circuit 120, it is possible to make the input offset voltage V _OS to zero. This correction effect is effective for resistance mismatch ΔR caused by various factors such as process variations, temperature fluctuations, and stresses.

Figure 4 (a), (b) is a diagram showing a correction effect of the input offset voltage _{V OS} at the differential amplifier 100 of FIG. FIG. 4A shows the dependency of the input offset voltage V _{OS on} the input voltage _VIN . The design value of the resistors R ₁ and R ₂ is 100 kΩ, (i) shows the characteristic when R ₁ is increased by 4 kΩ from the design value, and (ii) is the case when R ₂ is increased by 4 kΩ from the design value. The characteristics of For comparison, characteristics (iii) and (iv) of the conventional differential amplifier 100R of FIG. (V) shows the characteristic when the resistance mismatch ΔR is zero.

In the conventional circuit in which the correction circuit 120 is not provided, an input offset voltage V _OS of ± 7 mV is generated for a mismatch of 4 kΩ, whereas the differential amplifier 100 including the correction circuit 120 allows the input offset voltage V _{OS The OS} can be reduced to about ± 1 mV.

4 (b) shows the dependence on the difference ΔR of the resistance value of the input offset voltage V _OS. (I) and (ii) show characteristics when R ₁ and R ₂ fluctuate in the differential amplifier 100 of FIG. (Iii) and (iv) show the characteristics when R ₁ and R ₂ fluctuate in the conventional differential amplifier 100R, respectively. From the comparison between (i) and (iii), or the comparison between (ii) and (iv), it can be seen that the input offset voltage _VOS is significantly reduced by providing the correction circuit 120.

  FIG. 5 is a circuit diagram showing another configuration example (100A) of the differential amplifier 100. As shown in FIG. In the differential amplifier 100A of FIG. 5, the correction circuit 120A includes current mirror circuits 126 and 128 in addition to the correction differential pair 122A and the correction current source 124A.

The first correction transistor Q ₁ and the second correction transistor Q ₂ constituting the correction differential pair 122A are NPN bipolar transistors, and have opposite polarities to the P-channel first input transistor M ₁ and the second input transistor M _2. It is. Correction current source 124A is connected to the emitter connected to the common transistors _Q 1, _{Q 2,} and generates a constant current _{I 2.} Correction current source 124A includes transistors _{M 11} to be biased in the same manner as the transistors _M 4, _{M 5} of the constant current circuit 106, a constant current _{I 2,} the current _{I M4, I M5} generated by the constant current circuit 106 Proportional relationship.

The current mirror circuit 126, a current flowing through the first correction transistor _{Q 1} folding, the current mirror circuit 128, folding the current flowing through the second correction transistor _{Q 2.} The current mirror circuits 126 and 128 generate differential correction currents _ICMP1 and _ICMP2 .

  Also with this configuration, the same effect as that of the differential amplifier 100 of FIG. 3 can be obtained.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
The MOSFET shown in FIGS. 2, 3, and 5 may be replaced with a bipolar transistor. In this case, the source of the first terminal may be read as the emitter, and the drain of the second terminal may be read as the collector. Conversely, the bipolar transistors shown in FIGS. 2, 3, and 5 may be replaced with MOSFETs.

(Second modification)
FIG. 6 is a circuit diagram of a differential amplifier 100B according to a second modification. This differential amplifier 100B is understood to have a configuration in which the differential amplifier 100 of FIG. 2 is inverted from top to bottom, the P channel and the N channel are replaced, and the NPN type is replaced with the PNP type.

(Modification 3)
In the embodiment, the differential amplifier 100 is used for the voltage follower circuit, but the application of the differential amplifier 100 is not limited thereto. The differential amplifier 100 may be used to constitute a non-inverting or inverting input terminal amplifier.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Differential amplifier, 102 ... Input differential pair, 104 ... Tail current source, 106 ... Constant current circuit, 108 ... Phase compensation circuit, 110 ... Output stage, 120 ... Correction circuit, 122 ... Correction differential pair, 124 ... Correction current source, 200 ... Voltage follower circuit, 202 ... Smoothing capacitor, 204 ... Voltage source, M ₁ ... First input transistor, M ₂ ... Second input transistor, Q ₁ ... First correction transistor, Q ₂ ... Second correction Transistor.

Claims (12)

An input differential pair that includes a first input transistor and a second input transistor, and generates a differential current according to the voltages of the inverting input terminal and the non-inverting input terminal;
A tail current source for supplying a tail current to the input differential pair;
A first resistor provided between a first terminal of the first input transistor and the tail current source;
A second resistor provided between the first terminal of the second input transistor and the tail current source;
A constant current circuit connected to a second terminal of the first input transistor and a second terminal of the second input transistor and generating a constant current;
An output stage connected to the second terminal of the first input transistor and the second terminal of the second input transistor to generate an output voltage;
Connected to the second terminal of the first input transistor and the second terminal of the second input transistor, and according to a potential difference between the first terminal of the first input transistor and the first terminal of the second input transistor A correction circuit for generating a differential correction current;
A differential amplifier comprising: The correction circuit includes:
A correction difference that includes a first correction transistor and a second correction transistor, and that generates the differential correction current according to the voltages of the first terminal of the first input transistor and the first terminal of the second input transistor. Moving pair,
A correction current source for supplying a current to the correction differential pair;
The differential amplifier according to claim 1, comprising:   The differential amplifier according to claim 2, wherein the first correction transistor and the second correction transistor have the same polarity as the first input transistor and the second input transistor. The first correction transistor and the second correction transistor are opposite in polarity to the first input transistor and the second input transistor,
3. The differential circuit according to claim 2, wherein the correction circuit further includes a current mirror circuit that folds back currents flowing through the first correction transistor and the second correction transistor to generate the differential correction current. amplifier. The input differential pair is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor),
4. The differential amplifier according to claim 2, wherein the first correction transistor and the second correction transistor are PNP type bipolar transistors. The input differential pair is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor),
5. The differential amplifier according to claim 2, wherein the first correction transistor and the second correction transistor are NPN bipolar transistors. The input differential pair is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor),
4. The differential amplifier according to claim 2, wherein the first correction transistor and the second correction transistor are NPN bipolar transistors. The input differential pair is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor),
5. The differential amplifier according to claim 2, wherein the first correction transistor and the second correction transistor are PNP type bipolar transistors. An inverting input terminal and a non-inverting input terminal;
A first input transistor having a control terminal connected to the inverting input terminal;
A second input transistor having a control terminal connected to the non-inverting input terminal;
A tail current source for supplying tail current;
A first resistor provided between the tail current source and a first terminal of the first input transistor;
A second resistor provided between the tail current source and the first terminal of the second input transistor;
A control terminal connected to the first terminal of the first input transistor, a first correction transistor having the same polarity as the first input transistor;
A control terminal connected to the first terminal of the second input transistor, a second correction transistor having the same polarity as the second input transistor;
A correction current source connected to the first terminal of the first correction transistor and the first terminal of the second correction transistor;
A first current source connected to a second terminal of the first input transistor and a second terminal of the first correction transistor;
A second current source connected to the second terminal of the second input transistor and the second terminal of the second correction transistor;
An output stage connected to the second terminal of the first input transistor and the second terminal of the second input transistor to generate an output voltage;
A differential amplifier comprising: An inverting input terminal and a non-inverting input terminal;
A first input transistor having a control terminal connected to the inverting input terminal;
A second input transistor having a control terminal connected to the non-inverting input terminal;
A tail current source for supplying tail current;
A first resistor provided between the tail current source and a first terminal of the first input transistor;
A second resistor provided between the tail current source and the first terminal of the second input transistor;
A control terminal connected to the first terminal of the first input transistor, a first correction transistor having a polarity opposite to that of the first input transistor;
A control terminal connected to the first terminal of the second input transistor; a second correction transistor having a polarity opposite to that of the second input transistor;
A correction current source connected to the first terminal of the first correction transistor and the first terminal of the second correction transistor;
A first current mirror circuit for turning back a current flowing through the first correction transistor;
A second current mirror circuit for turning back the current flowing through the second correction transistor;
A first current source connected to a second terminal of the first input transistor and an output terminal of the first current mirror circuit;
A second current source connected to a second terminal of the second input transistor and an output terminal of the second current mirror circuit;
An output stage connected to the second terminal of the first input transistor and the second terminal of the second input transistor to generate an output voltage;
A differential amplifier comprising:   11. The differential amplifier according to claim 1, wherein the differential amplifier is monolithically integrated on one semiconductor substrate.   A voltage follower circuit comprising the differential amplifier according to claim 1.

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