JP2018056285A - Electronic device, manufacturing method for the same, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an electronic device which achieves high heat radiation performance and can inhibit performance degradation caused by heat and impurities.SOLUTION: An electronic device 1A includes: a semiconductor element 10 having a terminal surface 10a provided with a terminal 11; a barrier layer 20 provided on a back surface 10b of the semiconductor element 10 which is opposite to a terminal surface 10a side; a metal layer 30 provided on the barrier layer 20; and a resin layer 40 in which the semiconductor element 10, the barrier layer 20, and the metal layer 30 are embedded. The semiconductor element 10 provided with the barrier layer 20 and the metal layer 30 is embedded in the resin layer 40 so that the metal layer 30 is exposed. Heat generated by the semiconductor element 10 is transmitted to the metal layer 30 through the barrier layer 20, and is radiated. The barrier layer 20 can inhibit intrusion of components of the metal layer 30 and impurities from the outside into the semiconductor element 10.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an electronic device, an electronic device manufacturing method, and an electronic apparatus.

There is known an electronic device in which a semiconductor element such as an IC (Integrated Circuit) is embedded in a resin layer and a rewiring layer is provided on the resin layer.
Regarding the formation of such an electronic device, for example, a semiconductor element is placed on a support with its terminals facing the support, the semiconductor element is sealed with a resin layer, and after separation of the support, on the resin layer A technique for forming a rewiring layer connected to a terminal of a semiconductor element is known. There is also known a technique in which a resin layer having a relatively low thermal conductivity covering a semiconductor element is thinned by grinding to improve heat dissipation from the semiconductor element that generates heat during operation.

JP 2001-308116 A Japanese Patent Laid-Open No. 7-7134

  In an electronic device including a semiconductor element embedded in a resin layer, when the resin layer is thinned by grinding, the surface (back surface) opposite to the terminal side surface (terminal surface) of the semiconductor element is exposed from the resin layer. Grinding to increase the heat dissipation effect from the semiconductor element.

  However, when the back surface of the semiconductor element is exposed from the resin layer by grinding in this way, impurities such as metals may adhere to the back surface of the semiconductor element during or after grinding. When impurities adhering to the back surface diffuse into the semiconductor element, the performance of the semiconductor element and the electronic device including the semiconductor element may be deteriorated.

  According to one aspect, a semiconductor element having a terminal surface provided with terminals, a barrier layer provided on a back surface opposite to the terminal surface side of the semiconductor element, and a metal provided on the barrier layer There is provided an electronic device including a layer and a resin layer in which the semiconductor element provided with the barrier layer and the metal layer is embedded so that the metal layer is exposed.

  Moreover, according to one viewpoint, the manufacturing method of the above electronic devices and the electronic device containing the above electronic devices are provided.

  A high-performance electronic device with excellent heat dissipation is realized. Moreover, an electronic apparatus using such an electronic device is realized.

FIG. 6 is a diagram (part 1) illustrating a method for forming an electronic device according to one embodiment. It is FIG. (2) which shows the formation method of the electronic device which concerns on one form. It is a figure which shows the formation method of the electronic device which concerns on another form. It is a figure which shows the 1st structural example of the electronic device which concerns on 1st Embodiment. It is explanatory drawing of an example of the semiconductor element used for an electronic device. It is a figure which shows the 2nd structural example of the electronic apparatus which concerns on 1st Embodiment. It is a figure which shows the 3rd structural example of the electronic apparatus which concerns on 1st Embodiment. It is explanatory drawing (the 1) of the formation method of the electronic device which concerns on 1st Embodiment. It is explanatory drawing (the 2) of the formation method of the electronic device which concerns on 1st Embodiment. It is explanatory drawing (the 3) of the formation method of the electronic device which concerns on 1st Embodiment. It is explanatory drawing (the 4) of the formation method of the electronic device which concerns on 1st Embodiment. It is explanatory drawing (the 5) of the formation method of the electronic device which concerns on 1st Embodiment. It is explanatory drawing (the 6) of the formation method of the electronic device which concerns on 1st Embodiment. It is explanatory drawing (the 7) of the formation method of the electronic device which concerns on 1st Embodiment. It is explanatory drawing (the 8) of the formation method of the electronic device which concerns on 1st Embodiment. It is explanatory drawing (the 9) of the formation method of the electronic device which concerns on 1st Embodiment. It is a figure which shows an example of the electronic device which concerns on 1st Embodiment. It is a figure which shows the structural example of the electronic apparatus which concerns on 2nd Embodiment. It is explanatory drawing (the 1) of the formation method of the electronic device which concerns on 2nd Embodiment. It is explanatory drawing (the 2) of the formation method of the electronic device which concerns on 2nd Embodiment. It is explanatory drawing (the 3) of the formation method of the electronic device which concerns on 2nd Embodiment. It is explanatory drawing (the 4) of the formation method of the electronic device which concerns on 2nd Embodiment. It is a figure which shows an example of the electronic device which concerns on 2nd Embodiment. It is a figure which shows the structural example of the electronic apparatus which concerns on 3rd Embodiment. It is explanatory drawing (the 1) of the formation method of the electronic device which concerns on 3rd Embodiment. It is explanatory drawing (the 2) of the formation method of the electronic device which concerns on 3rd Embodiment. It is explanatory drawing (the 3) of the formation method of the electronic device which concerns on 3rd Embodiment. It is a figure which shows an example of the electronic device which concerns on 3rd Embodiment. It is a figure which shows an example of the electronic device which concerns on 4th Embodiment. It is a figure which shows an example of the electronic device which concerns on 5th Embodiment.

First, an electronic device according to one embodiment is described.
1 and 2 illustrate a method for forming an electronic device according to one embodiment. 1A to 1D, FIG. 2A, and FIG. 2B are schematic cross-sectional views of the main part of each process in forming an electronic device.

  First, as illustrated in FIG. 1A, the adhesive layer 120 is formed on the support 110. For the support 110, a metal substrate, a glass substrate, a printed substrate, a semiconductor substrate, a ceramic substrate, or the like is used. For the adhesive layer 120, in addition to an adhesive film in which an adhesive is formed on a substrate, a material in which an adhesive is applied on a support 110 by a spin coating method, a spray coating method, a printing method, or the like is used. As the pressure-sensitive adhesive for the pressure-sensitive adhesive layer 120, a heat-foaming pressure-sensitive adhesive that foams by heating to reduce the pressure-sensitive adhesive force, a UV-foaming pressure-sensitive adhesive that foams by irradiation with ultraviolet rays and has a pressure-sensitive adhesive strength, etc. are used.

  Next, as shown in FIG. 1B, the semiconductor element 130 (semiconductor chip) on the adhesive layer 120 is face-down with the surface (terminal surface) 130a on which the terminal 131 is provided facing the adhesive layer 120 side. It is arranged with.

  FIG. 1B illustrates one semiconductor element 130, but a plurality of semiconductor elements 130 may be provided on the adhesive layer 120. In addition to one or more semiconductor elements 130, various electronic components such as a chip capacitor may be provided on the adhesive layer 120. In the following FIG. 1C, FIG. 1D, FIG. 2A and FIG. 2B, and in FIG. 3A to FIG. One semiconductor element 130 will be described as an example.

  The semiconductor element 130 on the adhesive layer 120 is sealed with a resin layer 140 as shown in FIG. Thereby, the substrate 150 in which the semiconductor element 130 is embedded in the resin layer 140 is formed on the adhesive layer 120. For the resin layer 140, a thermosetting resin, a thermoplastic resin, an ultraviolet curable resin, or the like is used. The resin layer 140 may include an insulating filler. The resin layer 140 is formed by, for example, molding. The resin layer 140 is cured by a method according to the type of the resin.

  It should be noted that the resin layer 140 does not necessarily need to be completely cured at this stage, and is cured to such an extent that the substrate 150 peeled from the adhesive layer 120 can be handled while maintaining its shape as described later. That's fine.

  Next, as illustrated in FIG. 1D, the substrate 150 is peeled from the adhesive layer 120 and separated from the adhesive layer 120 and the support 110. Peeling of the substrate 150 from the adhesive layer 120 is performed by reducing the adhesive strength of the adhesive layer 120 by heating, ultraviolet irradiation, or the like. The separated resin layer 140 of the substrate 150 is cured (completely cured) by a method corresponding to the type of the resin. The terminal surface 130a of the semiconductor element 130 is exposed on the surface 150a of the substrate 150 peeled from the adhesive layer 120.

  Next, as shown in FIG. 2A, a rewiring layer 160 is formed on the surface 150a of the substrate 150 where the terminal surface 130a of the semiconductor element 130 is exposed. The rewiring layer 160 includes an insulating portion 162 and a conductor portion 163 such as a wiring and a via provided in the insulating portion 162 and connected to the terminal 131 of the semiconductor element 130. For example, as shown in FIG. 2A, the redistribution layer 160 causes the terminal 131 of the semiconductor element 130 to be rearranged to the terminal 161 located outside the area of the semiconductor element 130 (its terminal surface 130a) (Fan− out).

Through the steps as described above, an electronic device 100A as shown in FIG. 2A is obtained.
The substrate 150 and the substrate provided with the rewiring layer 160 are formed as a wafer including a plurality of structural portions as shown in FIGS. 1C, 1D, and 2A, for example. Can be done. In that case, the wafer that has been processed up to the formation of the rewiring layer 160 is cut into pieces by dicing at a position around the structure portion, thereby being separated into individual structure portions. Thereby, an electronic device 100A as shown in FIG. 2A is obtained.

  The electronic device 100A shown in FIG. 2A has a structure in which a semiconductor element 130 that generates heat in accordance with its operation is covered with a resin layer 140. Therefore, the heat dissipation from the semiconductor element 130 is lowered, and there is a possibility that the semiconductor element 130 is overheated, resulting in damage and performance deterioration.

  In order to improve the heat dissipation of the semiconductor element 130, for example, the resin layer 140 of the substrate 150 is ground and thinned by back grinding. Thereby, an electronic device 100B as shown in FIG. 2B is obtained. For example, when the back surface 130b of the semiconductor element 130 is exposed from the resin layer 140 (the surface 150b of the substrate 150) by grinding, a high heat dissipation effect is obtained. On the other hand, since the back surface 130b is exposed from the resin layer 140, the semiconductor element 130 is easily affected by impurities from outside during or after grinding. This point will be described with reference to FIG.

FIG. 3 is a diagram illustrating a method for forming an electronic device according to another embodiment. FIGS. 3A to 3D are schematic cross-sectional views of the main part of each process in forming an electronic device.
In this example, as shown in FIG. 3A, a metal member in which a semiconductor element 130 is disposed on an adhesive layer 120 on a support 110 and copper (Cu) or the like is used outside thereof. 170 is arranged. The metal member 170 is a metal frame surrounding the semiconductor element 130 or a plurality of metal pillars provided around the semiconductor element 130. The metal frame and the metal column are provided, for example, for the purpose of adjusting the flow of the resin layer 140 during molding and suppressing the displacement of the semiconductor element 130 due to the flow of the resin layer 140. In addition, the metal frame and the metal pillar are provided for the purpose of use as a part of the heat conduction path or the electric conduction path, for example.

  Next, as illustrated in FIG. 3B, the semiconductor element 130 and the metal member 170 on the adhesive layer 120 are sealed with the resin layer 140. Thereby, the substrate 150 in which the semiconductor element 130 and the metal member 170 are embedded in the resin layer 140 is formed. Thereafter, as shown in FIG. 3C, the substrate 150 is separated from the adhesive layer 120 and the support 110.

  3D, the rewiring layer 160 including the conductor portion 163 connected to the terminal 131 is formed on the surface 150a of the separated substrate 150 where the terminal surface 130a of the semiconductor element 130 is exposed. It is formed. The substrate 150 is further ground from the side opposite to the rewiring layer 160 side, and the back surface 130b of the semiconductor element 130 is exposed from the resin layer 140 (the surface 150b of the substrate 150). In this example, the semiconductor element 130 is ground together with the resin layer 140 to be thinned. As the resin layer 140 and the semiconductor element 130 are ground, the metal member 170 is also ground.

Through the steps as described above, an electronic device 100C as shown in FIG. 3D is obtained.
The substrate 150 may be formed as a wafer including a plurality of structural portions shown in FIGS. 3B and 3C, for example. The rewiring layer 160 is formed on the substrate 150 and the substrate 150 is ground. For example, the wafer may be formed as a wafer including a plurality of structure portions shown in FIG. In this case, the wafer that has been subjected to the formation of the rewiring layer 160 and the grinding of the substrate 150 is cut by dicing at a position around the structure portion, and is separated into individual structure portions. Thereby, an electronic device 100C as shown in FIG. 3D is obtained.

  As described above, when the metal member 170 is ground together with the resin layer 140 and the semiconductor element 130, the back surface 130b of the semiconductor element 130 exposed from the resin layer 140 by grinding is left with a residue of the metal member 170 ground together, for example, copper. Such as metal grinding scraps can adhere. As described above, the residual component adhering to the back surface 130b of the semiconductor element 130 may be diffused into the semiconductor element 130 due to heat applied during the subsequent process or the operation of the electronic device 100C. For example, a metal such as copper used for the metal member 170 is relatively easy to diffuse into the semiconductor material (the semiconductor substrate of the semiconductor element 130). When the residual component diffuses into the semiconductor element 130, the active layer (layer in which circuit elements such as transistors are formed) is adversely affected, and the performance of the semiconductor element 130 may be deteriorated.

  Here, the influence caused by residue from grinding adhered to the back surface 130b of the semiconductor element 130 exposed from the resin layer 140 and thermal diffusion of the components of the residue has been described. In addition, not only such grinding residue but also various impurities may be attached to the back surface 130b of the semiconductor element 130 exposed from the resin layer 140 from the outside. In such a case as well, the impurity may diffuse into the semiconductor element 130 and the performance of the semiconductor element 130 may deteriorate due to the diffusion.

  If the resin layer 140 is covered without exposing the back surface 130b of the semiconductor element 130 in order to suppress adhesion of various impurities including residues during grinding, as described above, the heat dissipation from the semiconductor element 130 is reduced. There is a possibility of causing damage and performance deterioration due to overheating.

In view of the above points, here, a technique as described below as an embodiment is employed to realize an electronic device that has high heat dissipation and can suppress performance deterioration due to heat and impurities.
First, the first embodiment will be described.

  FIG. 4 is a diagram illustrating a first configuration example of the electronic device according to the first embodiment. FIG. 4 is a schematic cross-sectional view of a relevant part of a first configuration example of the electronic device. FIG. 5 is an explanatory diagram of an example of a semiconductor element used in an electronic device. FIG. 5 shows a schematic cross-sectional view of an essential part of an example of a semiconductor element.

4A includes a semiconductor element 10 (semiconductor chip), a barrier layer 20, a metal layer 30, a resin layer 40, and a rewiring layer 50.
Here, the semiconductor element 10 includes, for example, a semiconductor substrate 12 such as silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), as shown in FIG. And a wiring layer 13 formed on the semiconductor substrate 12. Circuit elements such as transistors, resistors, and capacitors are formed on the semiconductor substrate 12. FIG. 5 shows a transistor 14 as an example. A region of the semiconductor substrate 12 where a circuit element such as the transistor 14 is formed is referred to as an active layer. The wiring layer 13 includes a conductor portion 16 such as a wiring and a via provided in the insulating portion 15 and connected to a circuit element such as the transistor 14. The terminal 11 of the semiconductor element 10 is provided on the outermost conductor portion 16 of the wiring layer 13.

  As shown in FIG. 4, the barrier layer is formed on the surface (back surface) 10 b opposite to the surface (terminal surface) 10 a side of the semiconductor element 10, that is, on the semiconductor substrate 12 shown in FIG. 5. 20 is provided.

  For the barrier layer 20, a material that does not diffuse into the semiconductor element 10 or hardly diffuses, for example, a material that hardly diffuses than the component of the metal layer 30 provided thereon is used. The barrier layer 20 is made of such a material and the component of the metal layer 30 provided thereon is not diffused into the semiconductor element 10 or the component of the metal layer 30 is diffused into the semiconductor element 10. Materials to suppress are used. The barrier layer 20 is made of a material containing at least one of titanium (Ti), tungsten (W), and tantalum (Ta) as a component. For example, the barrier layer 20 includes a single kind of titanium, tungsten, or tantalum metal, or a nitride thereof, or a stacked body of a single kind of metal or nitride thereof, or two or more of titanium, tungsten, and tantalum. An alloy or a laminate thereof is used. The barrier layer 20 is not limited to the conductor material, and an insulating material may be used as long as the above-described conditions required for the material are satisfied.

  For example, as shown in FIG. 4, the barrier layer 20 is provided so as to cover the entire back surface 10 b of the semiconductor element 10. The thickness of the barrier layer 20 is 0.1 μm to 2 μm, preferably 0.1 μm to 0.8 μm. When the barrier layer 20 is thinned, the heat conduction efficiency of the heat generated in the semiconductor element 10 to the metal layer 30 is increased.

  A metal layer 30 is provided on the barrier layer 20 as shown in FIG. For the metal layer 30, a material exhibiting high thermal conductivity, for example, a material exhibiting higher thermal conductivity than the barrier layer 20 is used. For the metal layer 30, a material containing at least one of copper, nickel (Ni), and cobalt (Co) as a component is used. For example, for the metal layer 30, a single kind of copper, nickel, or cobalt, or a laminate thereof, or an alloy containing two or more of copper, nickel, and cobalt, or a laminate thereof, or the like is used.

  For example, as shown in FIG. 4, the metal layer 30 is provided inside the edge of the barrier layer 20 that covers the back surface 10 b of the semiconductor element 10. The thickness of the metal layer 30 is 10 μm to 200 μm. The thickness of the barrier layer 20 is set to be thinner than the metal layer 30.

  The semiconductor element 10 provided with the barrier layer 20 and the metal layer 30 is embedded in the resin layer 40 as shown in FIG. The terminal surface 10 a of the semiconductor element 10 is exposed on one surface 40 a of the resin layer 40, and the metal layer 30 is exposed on the other surface 40 b of the resin layer 40. For the resin layer 40, a thermosetting resin, a thermoplastic resin, an ultraviolet curable resin, or the like is used. The resin layer 40 may include a filler such as silicon oxide (SiO), aluminum oxide (AlO), and aluminum nitride (AlN).

  A rewiring layer 50 is provided on the surface 40 a of the resin layer 40 from which the terminal surface 10 a of the semiconductor element 10 is exposed. The rewiring layer 50 includes an insulating portion 52 and a conductor portion 53 such as a wiring and a via provided in the insulating portion 52. A resin material such as epoxy, polyimide, polybenzoxazole or the like is used for the insulating portion 52. A conductor material such as copper or aluminum (Al) is used for the conductor portion 53. The conductor portion 53 is connected to the terminal 11 of the semiconductor element 10. The terminal 51 of the electronic device 1 </ b> A is provided on the outermost conductor portion 53 of the rewiring layer 50.

  In the electronic device 1A having the above configuration, heat generated in the semiconductor element 10 during operation is exposed from the resin layer 40 on the barrier layer 20 through the relatively thin barrier layer 20 on the back surface 10b of the semiconductor element 10. It is transmitted to the metal layer 30 that exhibits a relatively high thermal conductivity. Thereby, compared with what the back surface 10b of the semiconductor element 10 was covered with the resin layer 40, the thermal radiation from the semiconductor element 10 is performed efficiently, and the damage and performance degradation of the semiconductor element 10 resulting from overheating are suppressed. .

  In the electronic device 1A, the material of the barrier layer 20 is appropriately selected, and the diffusion of the components of the barrier layer 20 into the semiconductor element 10 is suppressed. Such a barrier layer 20 is interposed between the semiconductor element 10 and the metal layer 30, and diffusion of components of the metal layer 30 into the semiconductor element 10 is suppressed. Further, the barrier layer 20 suppresses the intrusion of impurities from the outside into the semiconductor element 10 (the back surface 10b), and the performance degradation of the semiconductor element 10 due to the impurities from the outside is suppressed.

As a result, the electronic device 1 </ b> A that has high heat dissipation from the semiconductor element 10 and can suppress deterioration in performance of the semiconductor element 10 due to heat and impurities is realized.
FIG. 6 is a diagram illustrating a second configuration example of the electronic device according to the first embodiment. FIG. 6 shows a schematic cross-sectional view of a relevant part of a second configuration example of the electronic device.

  An electronic device 1B shown in FIG. 6 is different from the electronic device 1A (FIG. 4) in that a thin semiconductor element 10 is embedded in a resin layer 40. Other configurations of the electronic apparatus 1B are the same as those of the electronic apparatus 1A. By using the thin semiconductor element 10, the resin layer 40 and the electronic device 1B can be thinned.

  A thin electronic device that has high heat dissipation from the semiconductor element 10 due to the barrier layer 20 on the back surface 10b of the semiconductor element 10 and the metal layer 30 on the barrier layer 20 and suppresses performance deterioration of the semiconductor element 10 due to heat and impurities. 1B is realized.

FIG. 7 is a diagram illustrating a third configuration example of the electronic device according to the first embodiment. FIG. 7 is a schematic cross-sectional view of a relevant part of a third configuration example of the electronic device.
The electronic device 1C shown in FIG. 7 is the above-mentioned electronic device in that a metal member 60 located outside the semiconductor element 10 provided with the barrier layer 20 and the metal layer 30 is embedded in the resin layer 40. 1B (FIG. 6). The other configuration of the electronic device 1C is the same as that of the electronic device 1B.

  The metal member 60 is a metal frame surrounding the semiconductor element 10 or a plurality of metal pillars provided around the semiconductor element 10. Providing such a metal member 60 adjusts the flow of the resin layer 40 when forming the electronic device 1 </ b> C as will be described later, and suppresses misalignment of the semiconductor element 10 due to the flow of the resin layer 40. Further, the metal member 60 may be used as a part of the heat conduction path or the electric conduction path.

  A thin electronic device that has high heat dissipation from the semiconductor element 10 due to the barrier layer 20 on the back surface 10b of the semiconductor element 10 and the metal layer 30 on the barrier layer 20 and suppresses performance deterioration of the semiconductor element 10 due to heat and impurities. 1C is realized.

Next, a method for forming an electronic device according to the first embodiment will be described using the electronic device 1C (FIG. 7) as an example.
8 to 16 are explanatory views of the method for forming the electronic device according to the first embodiment.

  FIG. 8 is a view showing an example of a wafer on which semiconductor elements are formed. FIG. 8A is a schematic perspective view of the wafer as viewed from the terminal surface side of the formed semiconductor element, and FIG. 8B is a perspective view of the wafer as viewed from the back side of the formed semiconductor element. A schematic diagram is shown, and FIG. 8C shows a schematic cross-sectional view of the main part of the wafer.

  As shown in FIG. 8A to FIG. 8C, a wafer 70 is prepared in which a group of semiconductor elements 10 is formed so as to be aligned vertically and horizontally. The front surface 70a of the wafer 70 includes a terminal surface 10a of the group of semiconductor elements 10 provided with the terminals 11. The back surface 70b of the wafer 70 includes the back surface 10b of the semiconductor element 10 group opposite to the terminal surface 10a. Is included. A scribe line 71 (illustrated by a dotted frame in FIG. 8C) is provided between adjacent semiconductor elements 10 as a cutting position during dicing.

  FIG. 9 is a diagram illustrating an example of a wafer grinding process. FIG. 9A is a schematic perspective view of the wafer as viewed from the back side of the formed semiconductor element, and FIG. 9B is a schematic cross-sectional view of the main part of the wafer.

  As shown in FIGS. 9A and 9B, the wafer 70 on which the semiconductor element 10 group is formed has the back surface 70b side, that is, the back surface 10b side of the semiconductor element 10 group (semiconductor substrate 12 (FIG. 5)). Is ground by back grinding. Thereby, the semiconductor element 10 group formed on the wafer 70 is thinned. For example, the wafer 70 is ground from the back surface 70b side so that the thickness becomes 50 μm to 500 μm.

  FIG. 10 shows an example of the barrier layer forming step. FIG. 10A shows a schematic perspective view of the wafer as viewed from the formed barrier layer side, and FIG. 10B shows a schematic cross-sectional view of the main part of the wafer on which the barrier layer is formed. .

  As shown in FIGS. 10A and 10B, the barrier layer 20 is formed on the back surface 70 b of the ground wafer 70. The barrier layer 20 is formed on the entire back surface 70 b of the wafer 70. The barrier layer 20 is made of a material such as titanium, tungsten, or tantalum. A sputtering method is used to form the barrier layer 20 using such a material. For example, the barrier layer 20 having a thickness of 0.1 μm to 0.8 μm is formed by sputtering.

  FIG. 11 is a diagram illustrating an example of the seed layer forming step. FIG. 11A shows a schematic perspective view of the wafer as viewed from the formed seed layer side, and FIG. 11B shows a schematic cross-sectional view of the main part of the wafer on which the seed layer is formed. .

  A seed layer 31 is formed on the formed barrier layer 20 as shown in FIGS. 11 (A) and 11 (B). The seed layer 31 is formed on the entire barrier layer 20. A material such as copper is used for the seed layer 31. For example, the seed layer 31 having a thickness of 0.1 μm to 0.8 μm is formed by sputtering.

  FIG. 12 is a diagram illustrating an example of a metal deposition process. FIG. 12A is a schematic perspective view of a wafer as viewed from the deposited metal side, and FIG. 12B is a schematic cross-sectional view of the main part of the wafer on which metal is deposited.

  On the formed seed layer 31, first, as shown in FIGS. 12A and 12B, a resist 80 is formed. The resist 80 has an opening 81 in a region corresponding to each semiconductor element 10 of the wafer 70. The resist 80 covers a region corresponding to the scribe line 71. In this example, the resist 80 covering the region corresponding to the scribe line 71 is formed with a width larger than the width of the scribe line 71 as shown in FIG.

  After the formation of the resist 80, the metal 32 is deposited in the opening 81 of the resist 80 as shown in FIGS. The metal 32 is deposited by depositing the metal 32 on the seed layer 31 exposed in the opening 81 of the resist 80 by electrolytic plating using the resist 80 as a mask and the seed layer 31 formed earlier as a power feeding layer. Done. For example, as the metal 32, copper having a thickness of 10 μm to 200 μm is deposited on the seed layer 31 in the opening 81 of the resist 80.

  Although illustration is omitted here, the surface 70a of the wafer 70 including the terminal surface 10a of the semiconductor element 10 may be protected with a resist or the like before the metal 32 is deposited by electrolytic plating. It is preferable in terms of suppressing the contamination and damage of 10a.

  FIG. 13 is a diagram illustrating an example of a metal layer forming process. FIG. 13A shows a schematic perspective view of the wafer as viewed from the formed metal layer side, and FIG. 13B shows a schematic cross-sectional view of the main part of the wafer on which the metal layer is formed. .

  After the formation of the metal 32, as shown in FIGS. 13A and 13B, the resist 80 is removed, and the seed layer 31 exposed after the removal of the resist 80 is removed. The seed layer 31 is removed by dry etching or wet etching.

  By removing the seed layer 31 exposed after the removal of the resist 80, the seed layers 31 in the region group corresponding to each semiconductor element 10 surrounded by the scribe line 71 are separated from each other. Thereby, a metal layer 30 including the seed layer 31 and the metal 32 deposited thereon is formed in a region corresponding to each semiconductor element 10. In this example, since the resist 80 is formed in advance with a width larger than the width of the scribe line 71 (FIG. 12), the metal layer 30 formed by removing the resist 80 and the seed layer 31 is located inside the scribe line 71. Will come to be located.

  13, the structure in which the barrier layer 20 is formed on the back surface 10b of each semiconductor element 10 of the wafer 70 and the metal layer 30 is formed on the barrier layer 20 is obtained. In this structure, direct contact between the back surface 10b of each semiconductor element 10 and the metal layer 30 is avoided.

  Although not shown here, after the resist 80 is removed and the exposed seed layer 31 is removed, the underlying barrier layer 20 may be removed by etching. Even in such a method, direct contact between the back surface 10b of each semiconductor element 10 and the metal layer 30 is avoided.

  FIG. 14 is a diagram illustrating an example of the singulation process. FIG. 14A is a schematic perspective view of a semiconductor element group separated into pieces, and FIG. 14B is a schematic cross-sectional view of a main part of the semiconductor element group divided into pieces.

  The wafer 70 that has been formed up to the formation of the metal layer 30 is cut at the position of the scribe line 71 by dicing using a dicer (dicing saw). As a result, a group of individual semiconductor elements 10 as shown in FIGS. 14A and 14B is obtained.

  Each semiconductor element 10 has a structure in which a barrier layer 20 is formed on the back surface 10 b and a metal layer 30 is formed on the barrier layer 20. In this example, as described above, the metal layer 30 is located inside the edge of the back surface 10b (and the barrier layer 20) of the semiconductor element 10. This is because the resist 80 is previously formed with a width larger than the width of the scribe line 71 (FIG. 12), and the metal layer 30 is formed inside the scribe line 71 by removing the resist 80 and the seed layer 31 (FIG. 13). is there.

  When the metal layer 30 is formed at such a position, the dicer cuts the barrier layer 20 and the semiconductor element 10 in the singulation process of FIG. 14, but does not contact the metal layer 30 but the metal layer 30. Do not cut. Therefore, generation | occurrence | production of the cutting waste of the metal layer 30 can be suppressed at the time of the cutting | disconnection by a dicer. Thereby, it is suppressed that the cutting waste of the metal layer 30 adheres to the side surface (semiconductor substrate 12 (FIG. 5) exposed by the individualization) of the separated semiconductor element 10, and the attached cutting waste is the active layer. Can be adversely affected.

  As described above, each semiconductor element in which the barrier layer 20 is formed on the back surface 10b opposite to the terminal surface 10a and the metal layer 30 is formed on the barrier layer 20 by the method described with reference to FIGS. 10 is obtained. The semiconductor device 10 thus obtained is used to form the electronic device 1C (FIG. 7).

  FIG. 15 illustrates an example of a method for forming an electronic device. FIG. 15A to FIG. 15D are schematic cross-sectional views of the main part of each process in forming an electronic device. FIG. 16 is an explanatory view of a metal member. FIG. 16A shows a schematic plan view of a relevant part for explaining an example of a metal frame, and FIG. 16B shows a schematic plan view of a relevant part for explaining an example of a metal column.

  First, as shown in FIG. 15A, the semiconductor element 10 in which the barrier layer 20 and the metal layer 30 are formed on the adhesive layer 120 formed on the support 110 as described above has its terminals. The face 10a faces the adhesive layer 120 side, and is disposed face down. A metal member 60 using copper, nickel, cobalt or the like is further disposed on the adhesive layer 120 outside the semiconductor element 10 on which the barrier layer 20 and the metal layer 30 are formed.

  The metal member 60 is a metal frame 61 surrounding the semiconductor element 10 on which the barrier layer 20 and the metal layer 30 are formed, for example, as shown in FIG. Alternatively, the metal member 60 is a plurality of metal pillars 62 provided around the semiconductor element 10 on which the barrier layer 20 and the metal layer 30 are formed, for example, as shown in FIG. The metal frame 61 and the metal pillar 62 are provided, for example, for the purpose of adjusting the flow of the resin layer 40 during molding, which will be described later, and suppressing the displacement of the semiconductor element 10 due to the flow of the resin layer 40. Moreover, the metal frame 61 and the metal pillar 62 are provided for the purpose of being used as a part of a heat conduction path or an electric conduction path, for example.

  As the metal member 60, for example, the height from the adhesive layer 120 is higher than the semiconductor element 10 on the adhesive layer 120, and the height of the metal layer 30 formed on the semiconductor element 10 via the barrier layer 20. Something like that is placed.

  FIG. 15A illustrates one semiconductor element 10 in which the barrier layer 20 and the metal layer 30 are formed, but a plurality of such semiconductor elements 10 may be provided on the adhesive layer 120. Good. In this case, the metal member 60 is disposed so as to surround one or more semiconductor elements 10 on which the barrier layer 20 and the metal layer 30 are formed. In addition, in each region surrounded by the metal member 60, various electronic components such as a chip capacitor may be provided in addition to one or a plurality of semiconductor elements 10 in which the barrier layer 20 and the metal layer 30 are formed. Good. Here, for the sake of convenience, a case where one semiconductor element 10 in which the barrier layer 20 and the metal layer 30 are formed is provided in a region surrounded by the metal member 60 will be described as an example.

  After the semiconductor element 10 on which the barrier layer 20 and the metal layer 30 are formed, and the metal member 60 are disposed on the adhesive layer 120, they are sealed with the resin layer 40 as shown in FIG. The

  For the resin layer 40, a thermosetting resin, a thermoplastic resin, an ultraviolet curable resin, or the like is used. The resin layer 40 may contain a filler such as silicon oxide. The resin layer 40 is formed by molding. For example, the metal member 60 adjusts the flow of the resin layer 40 at the time of molding and suppresses the displacement of the semiconductor element 10 on which the barrier layer 20 and the metal layer 30 are formed.

  Further, as described above, when the metal layer 30 is formed on the inner side of the back surface 10b of the semiconductor element 10 and the edge of the barrier layer 20, a step is thereby formed, so that the barrier layer 20 and the metal layer 30 are formed by the anchor effect. The adhesion between the semiconductor element 10 and the resin layer 40 is increased.

  The formed resin layer 40 is cured by a method according to the type of the resin. Thereby, the substrate 2 in which the semiconductor element 10 in which the barrier layer 20 and the metal layer 30 are formed and the metal member 60 is sealed with the resin layer 40 is formed on the adhesive layer 120.

  The resin layer 40 does not necessarily need to be completely cured at this stage, but is cured to such an extent that the substrate 2 peeled from the adhesive layer 120 can be handled while maintaining its shape as described later. If it is, it is enough. In addition, the curing condition of the resin layer 40 at this stage is set such that the adhesive force of the adhesive layer 120 is maintained based on the materials of the resin layer 40 and the adhesive layer 120. Alternatively, the material of the adhesive layer 120 is set based on the material of the resin layer 40 and the curing conditions.

  The formed substrate 2 is peeled from the adhesive layer 120 and separated from the adhesive layer 120 and the support 110 as shown in FIG. Peeling of the substrate 2 from the adhesive layer 120 is performed by reducing the adhesive strength of the adhesive layer 120 by a process such as heating or ultraviolet irradiation. The resin layer 40 of the substrate 2 separated from the adhesive layer 120 and the support 110 is cured (completely cured) by a technique according to the type of the resin.

  Next, as shown in FIG. 15D, the rewiring layer 50 is formed on the surface of the substrate 2 peeled from the adhesive layer 120, that is, the surface 40a where the terminal surface 10a of the semiconductor element 10 is exposed. The redistribution layer 50 includes an insulating part 52 and a conductor part 53 such as a wiring and a via provided in the insulating part 52 and connected to the terminal 11 of the semiconductor element 10. A resin material such as epoxy or polyimide is used for the insulating portion 52. A conductor material such as copper or aluminum is used for the conductor portion 53. For example, as shown in FIG. 15D, the rewiring layer 50 rearranges the terminals 11 of the semiconductor element 10 into terminals 51 located outside the area of the semiconductor element 10.

  For example, a photosensitive resin is used as the material of the insulating portion 52, and the photosensitive resin film formation, the patterning by exposure and development, the film formation of the conductor material of the conductor portion 53, and the patterning by etching are repeated a predetermined number of times. Thus, a predetermined number of rewiring layers 50 are formed. The outermost conductor portion 53 may be formed as the terminal 51, and a surface treatment film such as a laminated film of nickel and gold may be formed on the surface of the terminal 51.

  The substrate 2 on which the rewiring layer 50 is formed is further ground by back grinding from the side opposite to the rewiring layer 50 side, as shown in FIG. At that time, the metal layer 30 and the metal member 60 of the substrate 2 are ground together with the resin layer 40. By grinding, the metal layer 30 and the metal member 60 are exposed on the surface 40b of the resin layer 40 (the surface opposite to the surface 40a side where the terminal surface 10a of the semiconductor element 10 is exposed).

  At the time of grinding, with the grinding of the metal layer 30 and the metal member 60, those grinding scraps can be generated, but the grinding scraps do not adhere to the back surface 10b of the semiconductor element 10. For this reason, defects caused by adhesion of the grinding dust to the back surface 10b of the semiconductor element 10, for example, components of the grinding dust attached to the back surface 10b are thermally diffused to adversely affect the active layer of the semiconductor element 10 and cause performance degradation. Such a problem can be avoided.

  Further, since the metal layer 30 is exposed from the resin layer 40 by grinding, the heat generated in the semiconductor element 10 is transmitted to the metal layer 30 through the barrier layer 20 and is efficiently radiated from the metal layer 30. Therefore, overheating of the semiconductor element 10 and damage and performance deterioration of the semiconductor element 10 due to the overheating can be suppressed.

  As described above, the semiconductor element 10 on which the barrier layer 20 and the metal layer 30 are formed and the metal member 60 disposed outside the semiconductor layer 10 by the method described with reference to FIGS. The electronic device 1C embedded in the resin layer 40 so as to be exposed is obtained.

  The substrate 2 may be formed as a wafer including a plurality of structural portions shown in FIGS. 15B and 15C, for example. The rewiring layer 50 is formed on the substrate 2 and the substrate 2 is ground. For example, the wafer may be formed as a wafer including a plurality of structure portions shown in FIG. In this case, the wafer that has been subjected to the formation of the rewiring layer 50 and the grinding of the substrate 2 is cut by dicing at a position around the structure portion, and is separated into individual structure portions. Thereby, an electronic device 1C as shown in FIG. 15D is obtained.

The electronic device 1C as described above may be further provided with a heat radiating member.
FIG. 17 is a diagram illustrating an example of an electronic device according to the first embodiment. FIG. 17 is a schematic cross-sectional view of an essential part of an example of an electronic device.

  In FIG. 17, a heat dissipation member 200 such as a heat sink is provided on the resin layer 40 where the metal layer 30 is exposed of the electronic device 1 </ b> C as described above via a thermal interface material (TIM) 210. An electronic device 1Ca is shown. The heat radiating member 200 is made of a material having high thermal conductivity such as copper or aluminum. In addition, the heat radiating member 200 may be various heat radiating members such as those having a plate-like or needle-like fin in addition to a flat plate-like one.

  When the metal layer 30 exposed from the resin layer 40 is connected to the heat dissipation member 200 via the TIM 210, the heat generated in the semiconductor element 10 is transferred to the metal layer 30 through the barrier layer 20 and further dissipated through the TIM 210. It is transmitted to the member 200 and radiated to the outside. The heat generated in the semiconductor element 10 can be efficiently radiated to the outside, and overheating of the semiconductor element 10, damage to the semiconductor element 10 due to the overheating, and performance deterioration can be suppressed.

  Further, in the electronic device 1Ca shown in FIG. 17, the metal member 60 exposed from the resin layer 40 together with the metal layer 30 is also connected to the heat dissipation member 200 via the TIM 210. Accordingly, a heat conduction path that penetrates the resin layer 40 and connects between the rewiring layer 50 and the heat dissipation member 200 is formed outside the semiconductor element 10. Thereby, efficient heat conduction between the rewiring layer 50 and the heat dissipation member 200 using the metal member 60 becomes possible. For example, heat generated in the semiconductor element 10 and transferred to the rewiring layer 50 can be efficiently transferred to the heat dissipation member 200 through the metal member 60 to be dissipated.

  As shown in FIG. 17, the rewiring layer 50 can be provided with a conductor portion 53 a connected to the metal member 60. Moreover, bumps 54 such as solder can be mounted on the terminals 51 of the rewiring layer 50 as shown in FIG.

  Although the electronic devices 1C and 1Ca have been described here as examples, the electronic device 1A (FIG. 4) and the electronic device 1B (FIG. 6) can be similarly formed according to the above example. In this case, grinding of the wafer 70 as shown in FIGS. 9A and 9B is omitted in forming the electronic device 1A. In forming the electronic devices 1A and 1B, the arrangement of the metal member 60 as shown in FIG. 15A is omitted. On the resin layer 40 where the metal layer 30 of the electronic devices 1A and 1B is exposed, the heat dissipation member 200 is provided via the TIM 210.

Next, a second embodiment will be described.
FIG. 18 is a diagram illustrating a configuration example of an electronic device according to the second embodiment. FIG. 18 is a schematic cross-sectional view of an essential part of a configuration example of an electronic device.

  The electronic device 1D shown in FIG. 18 is different from the electronic device 1C (FIG. 7) in that the metal layer 30 group is provided separately at a plurality of locations on the barrier layer 20. Other configurations of the electronic device 1D are the same as those of the electronic device 1C.

  For example, as shown in FIG. 18, each metal layer 30 is disposed inside the edges of the semiconductor element 10 and the barrier layer 20. The group of metal layers 30 provided on the barrier layer 20 on the back surface 10b of the semiconductor element 10 together with the metal member 60 from the surface 40b of the resin layer 40 (the surface opposite to the surface 40a side on which the rewiring layer 50 is provided). Exposed.

  Similar to the electronic device 1C, a thin electronic device 1D that realizes high heat dissipation from the semiconductor element 10 and suppresses performance degradation of the semiconductor element 10 due to heat and impurities is realized. Further, in the electronic device 1D, the stress generated in the semiconductor element 10 and the barrier layer 20 due to the presence of the metal layer 30 is relieved by arranging the metal layer 30 group separately at a plurality of locations on the barrier layer 20. Thus, the influence of stress on the performance of the semiconductor element 10 is suppressed.

Next, a method for forming the electronic device 1D having the above configuration will be described.
19 to 22 are explanatory views of a method for forming an electronic device according to the second embodiment.
In forming the electronic device 1D, the steps of FIGS. 19 to 22 are performed after the steps of FIGS. 8 to 11 described in the first embodiment.

  FIG. 19 is a diagram illustrating an example of a metal deposition process. FIG. 19A shows a schematic perspective view of the wafer as viewed from the deposited metal side, and FIG. 19B shows a schematic cross-sectional view of the main part of the wafer on which the metal is deposited.

  First, as shown in FIGS. 19A and 19B, a resist 80 is formed on the seed layer 31 formed as shown in FIG. The resist 80 has openings 81 in a plurality of locations on the semiconductor element 10 of the wafer 70 where a metal layer 30 group (a metal 32 described later) is formed, in this example, in regions corresponding to four locations. As shown in FIG. 19B, the resist 80 covers a region corresponding to the scribe line 71 with a width larger than the width of the scribe line 71 (dotted line frame), for example.

  After the formation of the resist 80, the metal 32 is deposited in the opening 81 of the resist 80 by electrolytic plating using the seed layer 31 as a power feeding layer, as shown in FIGS. 19A and 19B. In the region corresponding to each semiconductor element 10, the metal 32 is separated and deposited at a plurality of locations, so that the amount of the metal 32 deposited on the entire wafer 70 is smaller than when deposited without separation. The stress generated in the wafer 70 due to the presence of the metal 32 is reduced. As a result, warpage of the wafer 70 can be suppressed, and for example, dicing as described later and formation of the rewiring layer 50 can be performed with high accuracy.

  FIG. 20 is a diagram illustrating an example of a metal layer forming process. FIG. 20A is a schematic perspective view of the wafer as viewed from the formed metal layer side, and FIG. 20B is a schematic cross-sectional view of the main part of the wafer on which the metal layer is formed. .

  20A and 20B, the resist 80 is removed, and the seed layer 31 exposed after the removal of the resist 80 is removed by etching. Note that after the seed layer 31 is removed, the underlying barrier layer 20 may be removed.

  By removing the seed layer 31 exposed after the removal of the resist 80, the seed layers 31 of the region group corresponding to each semiconductor element 10 surrounded by the scribe line 71 are separated from each other. At the same time, a plurality of locations in the region corresponding to each semiconductor element 10, in this example, four seed layers 31 under the metal 32 are separated from each other. As a result, metal layers 30 including the seed layer 31 and the metal 32 deposited thereon are formed, for example, at four locations in the region corresponding to each semiconductor element 10. In this example, each metal layer 30 is formed inside the scribe line 71.

  20, the structure in which the barrier layer 20 is formed on the back surface 10b of each semiconductor element 10 of the wafer 70 and the metal layer 30 group is formed on the barrier layer 20 is obtained. In this structure, direct contact between the back surface 10b of each semiconductor element 10 and the metal layer 30 group is avoided.

  FIG. 21 is a diagram showing an example of the singulation process. FIG. 21A shows a schematic perspective view of an individual semiconductor element group, and FIG. 21B shows a schematic cross-sectional view of a main part of an individual semiconductor element group.

  The wafer 70 that has been formed up to the formation of the metal layer 30 is cut at the position of the scribe line 71 by dicing using a dicer. As a result, a group of individual semiconductor elements 10 as shown in FIGS. 21A and 21B is obtained.

  Each semiconductor element 10 has a structure in which a barrier layer 20 is formed on the back surface 10b, and a group of metal layers 30 is formed at a plurality of locations on the barrier layer 20, in this example, at four locations. Since the metal layer 30 group is formed inside the scribe line 71 (FIG. 20), at the time of cutting, the dicer does not come into contact with the metal layer 30 group, the generation of the cutting waste, the generated cutting waste of the semiconductor element 10 of the semiconductor element 10 Adhesion to the side surfaces and the influence of the attached cutting waste on the semiconductor element 10 can be suppressed.

  As described above, the barrier layer 20 is formed on the back surface 10b opposite to the terminal surface 10a by the method described with reference to FIGS. 8 to 11 and 19 to 21, and metal layers are formed at a plurality of locations on the barrier layer 20. The semiconductor element 10 in which 30 groups are formed is obtained. The semiconductor device 10 thus obtained is used to form the electronic device 1D.

FIG. 22 illustrates an example of a method for forming an electronic device. FIGS. 22A to 22D are schematic cross-sectional views of the main part of each process in forming an electronic device.
First, as shown in FIG. 22A, the semiconductor element 10 in which the barrier layer 20 and the metal layer 30 group are formed on the adhesive layer 120 formed on the support 110 adheres the terminal surface 10a thereof. It is arranged face down toward the layer 120 side. A metal member 60 such as a metal frame or a metal column is further disposed on the adhesive layer 120.

  FIG. 22A illustrates one semiconductor element 10 in which the barrier layer 20 and the metal layer 30 group are formed. A plurality of such semiconductor elements 10 are provided on the adhesive layer 120. Also good. In this case, the metal member 60 is disposed so as to surround one or more semiconductor elements 10 on which the barrier layer 20 and the metal layer 30 group are formed. Various electronic components such as a chip capacitor may be provided in each region surrounded by the metal member 60. Here, for the sake of convenience, a case where one semiconductor element 10 in which the barrier layer 20 and the metal layer 30 are formed is provided in a region surrounded by the metal member 60 will be described as an example.

  After the semiconductor element 10 having the barrier layer 20 and the metal layer 30 group formed thereon and the metal member 60 are disposed on the adhesive layer 120, they are sealed with the resin layer 40 as shown in FIG. Is done. The resin layer 40 is formed by molding. By forming the metal layer 30 group on the inner side of the edge of the semiconductor element 10, the adhesion between the semiconductor element 10 on which the barrier layer 20 and the metal layer 30 group are formed and the resin layer 40 due to an anchor effect due to a step. Will increase. The formed resin layer 40 is cured (for example, semi-cured) by a method according to the type of the resin. As a result, the substrate 2 in which the semiconductor element 10 in which the barrier layer 20 and the metal layer 30 group are formed and the metal member 60 are sealed with the resin layer 40 is formed on the adhesive layer 120.

  The formed substrate 2 is separated from the adhesive layer 120 and separated from the adhesive layer 120 and the support 110 as shown in FIG. The separated resin layer 40 of the substrate 2 is cured (completely cured) by a method corresponding to the type of the resin.

  Next, as shown in FIG. 22D, the insulating portion 52 and the conductor portion 53 are included on the surface of the substrate 2 peeled from the adhesive layer 120, that is, the surface 40a where the terminal surface 10a of the semiconductor element 10 is exposed. A rewiring layer 50 is formed. The substrate 2 on which the rewiring layer 50 is formed is further ground by back grinding as shown in FIG. In the substrate 2, the metal layer 30 group and the metal member 60 are ground together with the resin layer 40. By grinding, the metal layer 30 group and the metal member 60 are exposed on the surface 40b of the resin layer 40 (the surface opposite to the surface 40a side).

  Grinding debris that can be generated with the grinding of the metal layer 30 group and the metal member 60 does not adhere to the back surface 10b of the semiconductor element 10, and therefore, it is possible to avoid problems that occur in the semiconductor element 10 due to adhesion of the grinding debris. it can. Further, since the metal layer 30 group is exposed from the resin layer 40 by grinding, the heat generated in the semiconductor element 10 is efficiently radiated, and the semiconductor element 10 is overheated, resulting in damage to the semiconductor element 10 and performance deterioration. Can be suppressed.

  As described above, the semiconductor element 10 in which the barrier layer 20 and the metal layer 30 group are formed and the metal member 60 are formed by the method described with reference to FIGS. 8 to 11 and 19 to 22. An electronic device 1D embedded in the resin layer 40 so that 60 is exposed is obtained.

  The substrate 2 may be formed as a wafer including a plurality of structural portions shown in FIGS. 22B and 22C, for example, and a rewiring layer 50 is formed on the substrate 2 and the substrate 2 is ground. For example, the wafer may be formed as a wafer including a plurality of structure portions shown in FIG. In this case, the wafer that has been subjected to the formation of the rewiring layer 50 and the grinding of the substrate 2 is cut by dicing at a position around the structure portion, and is separated into individual structure portions. Thereby, an electronic device 1D as shown in FIG. 22D is obtained.

The electronic device 1D as described above may be further provided with a heat dissipation member.
FIG. 23 is a diagram illustrating an example of an electronic apparatus according to the second embodiment. FIG. 23 is a schematic cross-sectional view of an essential part of an example of an electronic device.

  FIG. 23 shows an electronic device 1Da in which a heat dissipation member 200 such as a heat sink is provided on the resin layer 40 from which the metal layer 30 group is exposed of the electronic device 1D as described above via a TIM 210.

  The group of metal layers 30 exposed from the resin layer 40 is connected to the heat radiating member 200 via the TIM 210, so that heat generated in the semiconductor element 10 is efficiently radiated to the outside, and the semiconductor element 10 is overheated. Damage to the semiconductor element 10 and performance degradation can be suppressed. Further, the metal member 60 exposed from the resin layer 40 is also connected to the heat radiating member 200 via the TIM 210, so that the heat conduction that connects the rewiring layer 50 and the heat radiating member 200 through the resin layer 40 is achieved. A path is formed. Thereby, efficient heat conduction between the rewiring layer 50 and the heat dissipation member 200 is possible.

  As shown in FIG. 23, the rewiring layer 50 can be provided with a conductor portion 53 a connected to the metal member 60. Also, bumps 54 such as solder can be mounted on the terminals 51 of the rewiring layer 50 as shown in FIG.

  Similarly, in the electronic device 1A (FIG. 4) and the electronic device 1B (FIG. 6) described in the first embodiment, the metal layer 30 group is separated on the barrier layer 20 at a plurality of locations. Can be provided. In that case, the heat dissipation member 200 can be provided on the resin layer 40 from which the metal layer 30 group is exposed via the TIM 210.

Next, a third embodiment will be described.
FIG. 24 is a diagram illustrating a configuration example of an electronic device according to the third embodiment. FIG. 24 is a schematic cross-sectional view of a main part of a configuration example of an electronic device.

  An electronic device 1E shown in FIG. 24 is different from the electronic device 1C (FIG. 7) in that a metal layer 30 having the same size is provided on the barrier layer 20. Other configurations of the electronic device 1E are the same as those of the electronic device 1C.

25 to 27 are explanatory views of a method for forming an electronic device according to the third embodiment.
In the formation of the electronic device 1E, the steps of FIGS. 25 to 27 are performed after the steps of FIGS. 8 to 11 described in the first embodiment.

  FIG. 25 is a diagram illustrating an example of a seed layer formation and metal deposition process. FIG. 25A shows a schematic perspective view of a wafer as viewed from the deposited metal side, and FIG. 25B shows a schematic cross-sectional view of an essential part of the wafer on which metal is deposited.

  A metal 32 is deposited on the seed layer 31 formed as shown in FIG. 11 as shown in FIGS. 25 (A) and 25 (B). In this example, the resist 80 is not formed as described above, and the metal 32 is deposited following the formation of the seed layer 31. Therefore, the steps required for forming the resist 80, that is, the formation of an opening by applying a resist material, exposure and development, and the like are not required.

  FIG. 26 is a diagram illustrating an example of the singulation process. FIG. 26A shows a schematic perspective view of a separated semiconductor element group, and FIG. 26B shows a schematic cross-sectional view of an essential part of the separated semiconductor element group.

  The wafer 70 that has been formed up to the formation of the metal 32 is cut at the position of the scribe line 71 by dicing using a dicer. As a result, a group of separated semiconductor elements 10 as shown in FIGS. 26A and 26B is obtained.

  Each semiconductor element 10 has a structure in which a barrier layer 20 is formed on the back surface 10b, and a metal layer 30 including a seed layer 31 and a metal 32 having the same size is formed on the barrier layer 20. In the singulation process for obtaining each semiconductor element 10, the dicer cuts the metal layer 30, the barrier layer 20, and the semiconductor element 10. At the time of this cutting | disconnection, generation | occurrence | production of the cutting waste of the metal layer 30 is suppressed by setting individualization conditions appropriately. Alternatively, the generated cutting waste of the metal layer 30 is removed by an appropriate cleaning process after cutting. By using such a method, it is possible to suppress the cutting waste of the metal layer 30 from adhering to the side surface of the semiconductor element 10 and to suppress the influence of the attached cutting waste on the semiconductor element 10.

  As described above, the barrier layer 20 is formed on the back surface 10b opposite to the terminal surface 10a by the method described with reference to FIGS. 8 to 11 and FIGS. 25 and 26, and a metal of the same size is formed on the barrier layer 20. The semiconductor element 10 in which the layer 30 is formed is obtained. The semiconductor device 10 thus obtained is used to form the electronic device 1E.

FIG. 27 illustrates an example of a method for forming an electronic device. FIGS. 27A to 27D are schematic cross-sectional views of relevant parts of the respective steps in forming an electronic device.
First, as shown in FIG. 27A, the semiconductor element 10 in which the barrier layer 20 and the metal layer 30 are formed on the adhesive layer 120 formed on the support 110 has its terminal surface 10a as an adhesive layer. It is arranged face down toward the 120 side. A metal member 60 such as a metal frame or a metal column is further disposed on the adhesive layer 120.

  FIG. 27A illustrates one semiconductor element 10 on which the barrier layer 20 and the metal layer 30 are formed. However, even if a plurality of such semiconductor elements 10 are provided on the adhesive layer 120, FIG. Good. In this case, the metal member 60 is disposed so as to surround one or more semiconductor elements 10 on which the barrier layer 20 and the metal layer 30 are formed. Various electronic components such as a chip capacitor may be provided in each region surrounded by the metal member 60. Here, for the sake of convenience, a case where one semiconductor element 10 in which the barrier layer 20 and the metal layer 30 are formed is provided in a region surrounded by the metal member 60 will be described as an example.

  After the semiconductor element 10 having the barrier layer 20 and the metal layer 30 formed thereon and the metal member 60 are disposed on the adhesive layer 120, they are sealed with the resin layer 40 as shown in FIG. The The resin layer 40 is formed by molding. The formed resin layer 40 is cured (for example, semi-cured) by a method according to the type of the resin. Thereby, the substrate 2 in which the semiconductor element 10 in which the barrier layer 20 and the metal layer 30 are formed and the metal member 60 is sealed with the resin layer 40 is formed on the adhesive layer 120.

  The formed substrate 2 is peeled off from the adhesive layer 120 and separated from the adhesive layer 120 and the support 110 as shown in FIG. The separated resin layer 40 of the substrate 2 is cured (completely cured) by a method corresponding to the type of the resin.

  Next, as illustrated in FIG. 27D, the rewiring layer 50 including the insulating portion 52 and the conductor portion 53 is formed on the surface 40 a of the substrate 2 that is peeled from the adhesive layer 120. The substrate 2 on which the rewiring layer 50 is formed is further ground by back grinding as shown in FIG. In the substrate 2, the metal layer 30 and the metal member 60 are ground together with the resin layer 40. The metal layer 30 and the metal member 60 are exposed on the surface 40b of the resin layer 40 by grinding.

  Grinding debris that can be generated along with the grinding of the metal layer 30 and the metal member 60 does not adhere to the back surface 10b of the semiconductor element 10, and therefore, it is possible to avoid problems that occur in the semiconductor element 10 due to adhesion of the grinding debris. . Further, since the metal layer 30 is exposed from the resin layer 40 by grinding, the heat generated in the semiconductor element 10 is efficiently radiated to suppress overheating of the semiconductor element 10 and damage and performance deterioration of the semiconductor element 10 due to the heat. be able to.

  As described above, the semiconductor element 10 in which the barrier layer 20 and the metal layer 30 are formed, and the metal member 60 are converted into the metal layer 30 and the metal member 60 by the method described with reference to FIGS. The electronic device 1E embedded in the resin layer 40 so as to be exposed is obtained. As described above, by setting the metal layer 30 provided on the barrier layer 20 to the same size as the barrier layer 20, it is possible to reduce the number of processes and efficiently form the electronic device 1E.

Similar to the electronic device 1C, a thin electronic device 1E is realized which has high heat dissipation from the semiconductor element 10 and can suppress deterioration in performance of the semiconductor element 10 due to heat and impurities.
The substrate 2 may be formed as a wafer including a plurality of structural portions shown in FIGS. 27B and 27C, for example. The rewiring layer 50 is formed on the substrate 2 and the substrate 2 is ground. For example, the wafer may be formed as a wafer including a plurality of structure portions shown in FIG. In this case, the wafer that has been subjected to the formation of the rewiring layer 50 and the grinding of the substrate 2 is cut by dicing at a position around the structure portion, and is separated into individual structure portions. Thereby, an electronic device 1E as shown in FIG. 27D is obtained.

The electronic device 1E as described above may be further provided with a heat radiating member.
FIG. 28 is a diagram illustrating an example of an electronic apparatus according to the third embodiment. FIG. 28 is a schematic cross-sectional view of an essential part of an example of an electronic device.

  FIG. 28 shows an electronic device 1Ea in which a heat dissipation member 200 such as a heat sink is provided on the resin layer 40 from which the metal layer 30 is exposed in the electronic device 1E as described above via a TIM 210.

  The metal layer 30 exposed from the resin layer 40 is connected to the heat radiating member 200 via the TIM 210, so that heat generated in the semiconductor element 10 is efficiently radiated to the outside, and the semiconductor element 10 is overheated. Damage and performance degradation of the semiconductor element 10 can be suppressed. Further, the metal member 60 exposed from the resin layer 40 is also connected to the heat radiating member 200 via the TIM 210, so that the heat conduction that connects the rewiring layer 50 and the heat radiating member 200 through the resin layer 40 is achieved. A path is formed. Thereby, efficient heat conduction between the rewiring layer 50 and the heat dissipation member 200 is possible.

  As shown in FIG. 28, the rewiring layer 50 can be provided with a conductor portion 53 a connected to the metal member 60. Further, as shown in FIG. 28, bumps 54 such as solder can be mounted on the terminals 51 of the rewiring layer 50.

  Similarly, in the electronic device 1A (FIG. 4) and the electronic device 1B (FIG. 6) described in the first embodiment, a metal layer 30 having the same size can be provided on the barrier layer 20. . In that case, the heat dissipation member 200 can be provided on the resin layer 40 from which the metal layer 30 is exposed via the TIM 210.

Next, a fourth embodiment will be described.
The electronic devices 1A, 1B, 1C, 1Ca, 1D, 1Da, 1E, 1Ea and the like can be mounted on various substrates such as circuit boards, semiconductor elements, semiconductor devices, and other electronic devices. An example in which electronic devices 1A, 1B, 1C, 1Ca, 1D, 1Da, 1E, 1Ea and the like are mounted on a substrate (referred to as an electronic device) will be described as a fourth embodiment.

FIG. 29 is a diagram illustrating an example of an electronic device according to the fourth embodiment. FIG. 29 is a schematic cross-sectional view of an essential part of an example of an electronic apparatus according to the fourth embodiment.
As an example, FIG. 29 illustrates an electronic device 300 in which the electronic device 1Ca (FIG. 17) described in the first embodiment is mounted on a substrate 310. The substrate 310 is a circuit board, a semiconductor element, or a semiconductor device including a semiconductor element, or an electronic device including a circuit board, a semiconductor element, or a semiconductor device. The board 310 has a terminal 311 at a position corresponding to the terminal 51 provided on the rewiring layer 50 of the electronic device 1Ca on the surface side on which the electronic device 1Ca is mounted. The corresponding terminals 51 and 311 of the electronic device 1Ca and the substrate 310 are connected using bumps 54 such as solder.

  As described above, in the electronic device 1Ca, the heat dissipation from the semiconductor element 10 is high due to the barrier layer 20 on the back surface 10b of the semiconductor element 10 and the metal layer 30 provided thereon and exposed from the resin layer 40. Degradation of the performance of the semiconductor element 10 due to the impurities can be suppressed. Further, in the electronic device 1Ca, the metal member 60 penetrating the resin layer 40 forms a heat conduction path between the rewiring layer 50 and the heat dissipation member 200, and efficient heat conduction between them can be performed. . By mounting such an electronic device 1Ca on the substrate 310, a high-performance electronic device 300 having excellent heat dissipation can be realized.

  Here, the electronic device 300 in which the electronic device 1Ca is mounted on the substrate 310 is taken as an example, but the electronic device in which other electronic devices 1A, 1B, 1C, 1D, 1Da, 1E, 1Ea, etc. are mounted on the substrate 310 is also the same. Can be realized.

Next, a fifth embodiment will be described.
An electronic device in which the electronic devices 1A, 1B, 1C, 1Ca, 1D, 1Da, 1E, 1Ea and the like are mounted on various substrates can be mounted on various electronic devices. For example, it can be used for various electronic devices such as computers (personal computers, supercomputers, servers, etc.), smart phones, mobile phones, tablet terminals, sensors, cameras, audio devices, measuring devices, inspection devices, and manufacturing devices.

FIG. 30 is a diagram illustrating an example of an electronic apparatus according to the fifth embodiment. FIG. 30 schematically illustrates an example of an electronic apparatus according to the fifth embodiment.
As shown in FIG. 30, for example, the electronic device 300 as shown in FIG. 29 is mounted (built in) various electronic devices 400. As described above, the electronic device 1Ca having a configuration in which the metal layer 30 provided on the back surface 10b of the semiconductor element 10 via the barrier layer 20 is exposed from the resin layer 40 in which they are embedded is excellent in heat dissipation. A high-performance electronic device 300 is realized. By mounting such an electronic device 300, a highly reliable and high-performance electronic device 400 can be realized.

  Here, the electronic device 300 in which the electronic device 1Ca is mounted on the substrate 310 as shown in FIG. 29 is taken as an example, but other electronic devices 1A, 1B, 1C, 1D, 1Da, 1E, 1Ea and the like are variously used. Similarly, an electronic device mounted on a substrate can be mounted on various electronic devices.

Specific examples of the electronic device described above will be described below.
[Example 1]
The back surface of the silicon wafer on which the semiconductor element was formed was ground to a wafer thickness of 300 μm. A titanium layer having a thickness of 0.2 μm was formed as a barrier layer on the wafer by sputtering, and then a copper layer having a thickness of 0.3 μm was formed as a seed layer. A resist film is formed as a protective film on the wafer surface on the side where the terminal surface of the semiconductor element is present, and then copper is electroplated using a seed layer to form a copper film having a thickness of 80 μm on the entire back surface of the wafer. did. The wafer is singulated and includes a titanium layer formed in contact with the back surface of the semiconductor element, and a copper layer (seed layer and copper film) formed on the titanium layer and not in contact with the back surface of the semiconductor element. A semiconductor element having a planar size of 5 mm × 5 mm was prepared.

  A stainless steel substrate having a planar size of 170 mm × 170 mm and a thickness of 0.3 mm was used as a support substrate, and a heat-foaming type adhesive layer was attached thereon. A copper frame having a thickness of 350 μm and having an opening space with a plane size of 8 mm × 8 mm is disposed on the adhesive layer, a flip chip bonder is used in the opening space, and the terminal surface of the semiconductor element is an adhesive layer It arranged so that it might touch.

  A wafer-like substrate having a thickness of 0.5 mm and a diameter of 150 mm is applied on a pressure-sensitive adhesive layer on which a frame and a semiconductor element are arranged by applying a resin material containing 90% by weight of silicon oxide as a filler. (Mold resin substrate) was formed.

After applying heat at 180 ° C. to peel off the mold resin substrate from the adhesive layer, the mold resin substrate was completely cured at 200 ° C. for 1 hour.
A photosensitive epoxy varnish is applied by spin coating on the surface of the cured mold resin substrate where the terminal surface of the semiconductor element is exposed, pre-baked, exposed, developed, cured, and oxygen plasma treated, with a thickness of 8 μm. An insulating layer having an opening with a diameter of 30 μm was formed in the terminal portion of the semiconductor element. After forming a titanium layer having a thickness of 0.1 μm and a copper layer having a thickness of 0.3 μm as a seed layer by sputtering, a photoresist having openings in regions where vias and wirings are to be formed is formed. Was used for electrolytic plating of copper. After electrolytic plating, the photoresist was peeled off, and the seed layer exposed by peeling was removed by wet etching and dry etching to form vias and wirings. Finally, a solder resist was formed, and a nickel layer and a gold layer were formed on the surface of the wiring.

  Thereafter, the mold resin substrate was ground from the back surface so as to have a thickness of 330 μm, and the copper frame and the copper layer on the back surface of the semiconductor element were exposed. Finally, the mold resin substrate was separated into individual electronic devices.

[Example 2]
The back surface of the silicon wafer on which the semiconductor elements were formed was ground to a wafer thickness of 100 μm. A titanium layer having a thickness of 0.1 μm was formed as a barrier layer on the wafer by sputtering, and then a copper layer having a thickness of 0.2 μm was formed as a seed layer. After a resist film is formed as a protective film on the wafer surface on the side where the terminal surface of the semiconductor element exists, a photoresist is formed on the wafer back surface by providing an opening only in a required portion of the copper film. Then, a copper film having a thickness of 50 μm was formed by copper electroplating using a seed layer. Thereafter, the photoresist is peeled off, the wafer is separated into pieces, and a titanium layer formed on the back surface of the semiconductor element and a copper layer (seed layer and copper film) partially formed on the titanium layer are included. A semiconductor element having a plane size of 4 mm × 4 mm was prepared.

  A glass substrate having a planar size of 170 mm × 170 mm and a thickness of 0.3 mm was used as a support substrate, and an ultraviolet foam adhesive layer was attached thereon. A copper foil having a thickness of 5 μm is pasted on the adhesive layer, a photoresist having an opening having a diameter of 100 μm and a height of 200 μm is formed thereon, and the photoresist is obtained by electrolytic plating using the copper foil as a seed layer. A copper film having a diameter of 100 μm and a height of 160 μm was formed in the opening. After removing the photoresist, the exposed copper foil of the seed layer was removed by etching, and a copper column having a diameter of 100 μm and a height of 140 μm to 150 μm was formed on the adhesive layer. On the adhesive layer, a flip chip bonder was used, and the semiconductor element was disposed so that the terminal surface thereof was in contact with the adhesive layer.

  A wafer-like substrate having a thickness of 0.2 mm and a diameter of 150 mm is applied on a pressure-sensitive adhesive layer on which pillars and semiconductor elements are arranged by applying a resin material containing 88% by weight of silicon oxide as a filler. (Mold resin substrate) was formed.

After irradiating ultraviolet rays from the glass substrate side and peeling the mold resin substrate from the adhesive layer, the mold resin substrate was completely cured at 220 ° C. for 1 hour.
A photosensitive epoxy varnish is applied by spin coating on the surface of the cured mold resin substrate where the terminal surface of the semiconductor element is exposed, pre-baked, exposed, developed, cured, and oxygen plasma treated, with a thickness of 5 μm. An insulating layer having an opening with a diameter of 20 μm was formed in the terminal portion of the semiconductor element. After forming a titanium layer having a thickness of 0.1 μm and a copper layer having a thickness of 0.2 μm as a seed layer by sputtering, a photoresist having openings in regions where vias and wirings are to be formed is formed. Was used for electrolytic plating of copper. After electrolytic plating, the photoresist was peeled off, and the seed layer exposed by peeling was removed by wet etching and dry etching to form vias and wirings. Finally, a solder resist was formed, and a nickel layer and a gold layer were formed on the surface of the wiring.

  Thereafter, the mold resin substrate was ground from the back surface to a thickness of 130 μm to expose the copper pillar and the copper layer on the back surface of the semiconductor element. Finally, the mold resin substrate was separated into individual electronic devices.

1A, 1B, 1C, 1Ca, 1D, 1Da, 1E, 1Ea, 100A, 100B, 100C, 300 Electronic device 2, 150, 310 Substrate 10, 130 Semiconductor element 10a, 130a Terminal surface 10b, 130b Back surface 11, 51, 131 , 161, 311 Terminal 12 Semiconductor substrate 13 Wiring layer 14 Transistor 15, 52, 162 Insulating part 16, 53, 53a, 163 Conductor part 20 Barrier layer 30 Metal layer 31 Seed layer 32 Metal 40, 140 Resin layer 40a, 40b, 150a , 150b Surface 50, 160 Redistribution layer 54 Bump 60, 170 Metal member 61 Metal frame 62 Metal pillar 70 Wafer 70a Front surface 70b Back surface 71 Scribe line 80 Resist 81 Opening 110 Support body 120 Adhesive layer 200 Heat dissipation member 210 TIM
400 electronic equipment

Claims (10)

A semiconductor element having a terminal surface provided with terminals;
A barrier layer provided on a back surface opposite to the terminal surface side of the semiconductor element;
A metal layer provided on the barrier layer;
The electronic device, wherein the semiconductor element provided with the barrier layer and the metal layer includes a resin layer embedded so that the metal layer is exposed. The barrier layer includes titanium, tungsten or tantalum,
The electronic device according to claim 1, wherein the metal layer includes copper, nickel, or cobalt.   The electronic device according to claim 1, wherein the metal layer is provided inside an edge of the barrier layer.   The electronic device according to claim 1, wherein the metal layer is provided separately at a plurality of locations on the barrier layer.   5. The electronic device according to claim 1, further comprising a metal member embedded in the resin layer, located outside the semiconductor element, and penetrating the resin layer.   6. The electronic device according to claim 1, further comprising a heat dissipating member provided on the metal layer exposed from the resin layer.   The electronic device according to claim 1, further comprising a rewiring layer provided on the resin layer and including a conductor portion connected to the terminal. A step of sealing a semiconductor element having a terminal surface provided with terminals, a barrier layer provided on the back surface opposite to the terminal surface side, and a metal layer provided on the barrier layer with a resin layer When,
And a step of grinding the resin layer and exposing the metal layer. The step of sealing with the resin layer includes the step of sealing the semiconductor element provided with the barrier layer and the metal layer and the metal member disposed outside the semiconductor element with the resin layer. ,
The method for manufacturing an electronic device according to claim 8, wherein the step of grinding the resin layer and exposing the metal layer includes a step of grinding the resin layer and a part of the metal member. A substrate,
An electronic device mounted on the substrate,
The electronic device is
A semiconductor element having a terminal surface provided with terminals;
A barrier layer provided on a back surface opposite to the terminal surface side of the semiconductor element;
A metal layer provided on the barrier layer;
The semiconductor device provided with the barrier layer and the metal layer includes a resin layer embedded so that the metal layer is exposed.

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