JP2018037626A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve a capacitance density of a MIM capacitative element while inhibiting deterioration in design flexibility in an area of a capacitative film.SOLUTION: In a semiconductor device 100 having a laminated structure where a lower electrode 11, a lower capacitative film 12, a middle electrode 13, an upper capacitative film 14 and an upper electrode 15 are laminated in this order on a first interlayer insulation film 2: the lower electrode 11 is not covered with the lower capacitative film 12, the middle electrode 13, the upper capacitative film 14 and the upper electrode 15 and has conduction regions which are electrically connected with vias 16 for the lower electrode, respectively; and the middle electrode 13 is not covered with the upper capacitative film 14 and the upper electrode 15 and has conduction regions which are electrically connected with vias 17 for the middle electrode; and the upper capacitative film 14 and the upper electrode 15 have lamination regions laminated on the lower electrode 11 without involving the lower capacitive film 12 and the middle electrode 13; and the upper electrode 15 has in each lamination region, a conduction region which is electrically connected with vias 18 for the upper electrode.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  As a capacitive element formed inside a wiring layer of a semiconductor device, there is an MIM (Metal-Insulator-Metal) capacitive element shown in FIG. In this MIM capacitor element, an interlayer insulating film 102 and a lower electrode 103 are stacked in this order on a semiconductor substrate 101, and a capacitor film 104 and an upper electrode 105 are stacked in this order on the lower electrode 103. A MIM capacitor element 110 sandwiched between the lower electrode 103 and the upper electrode 105 is formed. An interlayer insulating film 106 is laminated on the interlayer insulating film 102 so as to cover the lower electrode 103, the capacitor film 104, and the upper electrode 105, and a via 107 electrically connected to the lower electrode 103 and an upper portion are formed on the interlayer insulating film 106. A via 108 that is electrically connected to the electrode 105 is formed. That is, as shown in FIG. 1, a stacked body of the capacitor film 104 and the upper electrode 105 having a width smaller than that of the lower electrode 103 is disposed on the lower electrode 103 in a cross-sectional view, Vias 107 and 108 are formed on the upper electrode 105 so as to be electrically connected thereto.

  By the way, in general, the capacitance per unit layout area (hereinafter sometimes abbreviated as “capacitance density”) is high in the MIM capacitance element, and the capacitance density does not vary with respect to the voltage applied to the MIM capacitance element. It is required that linearity be maintained between the charge amount and the voltage. It is known that the capacitance density of the MIM capacitive element is expressed as the sum of a term proportional to the first power, a term proportional to the square and a constant term with respect to the applied voltage, and the former proportionality coefficient is the primary voltage. The coefficient, the latter proportionality coefficient, is called the secondary voltage coefficient.

In response to these demands, various efforts have been made to solve individual problems.
For example, in order to increase the capacitance density of the MIM capacitor element, silicon nitride SiN or hafnium oxide HfO having a high dielectric constant has been introduced instead of silicon oxide SiO that has been conventionally used as a capacitor film of the MIM capacitor element.

  On the other hand, a method for increasing the capacitance density by stacking MIM capacitor elements has also been proposed. For example, in US Patent Application Publication No. 2003/0197215 (Patent Document 1) and JP 2012-164714 (Patent Document 2), as shown in FIG. A semiconductor device in which the capacitance density is increased is disclosed. In the semiconductor device shown in FIG. 2, an interlayer insulating film 112 and a lower electrode 113 are stacked in this order on a semiconductor substrate 111, and a lower capacitor film 114 and a middle electrode 115 are stacked in this order on the lower electrode 113. A lower MIM capacitor element 116 is formed by sandwiching the lower capacitor film 114 between the lower electrode 113 and the middle electrode 115. Further, the upper capacitive film 117 and the upper electrode 118 are laminated in this order on the middle electrode 115, thereby forming the upper MIM capacitive element 119 having the upper capacitive film 117 sandwiched between the middle electrode 115 and the upper electrode 118. An interlayer insulating film 120 is laminated on the interlayer insulating film 112 so as to cover the lower electrode 113, the lower capacitor film 114, the middle electrode 115, the upper capacitor film 117, and the upper electrode 118. A via 121 conducting to the lower electrode 113, a via 122 conducting to the middle electrode 115, and a via 123 conducting to the upper electrode 118 are formed. That is, as shown in FIG. 2, a laminated body of the lower capacitive film 114 and the middle electrode 115, which is narrower than the lower electrode 113, is disposed on the lower electrode 113 in a sectional view, and the lower MIM capacitive element 116. Further, a laminated body of the upper capacitive film 117 and the upper electrode 118, which is narrower than the middle electrode 115, is disposed on the middle electrode 115 to form the upper MIM capacitive element 119. Then, vias 121, 122, and 123 are formed on the lower electrode 113, the middle electrode 115, and the upper electrode 118 so as to be electrically connected thereto.

  In order to improve the linearity by lowering the secondary voltage coefficient of the MIM capacitor, Japanese Patent Laid-Open No. 2002-151649 (Patent Document 3) discloses that silicon nitride SiN having a positive secondary voltage coefficient and negative two Using the property of silicon oxide SiO having the next voltage coefficient, it is disclosed that MIM capacitor elements having these as insulating capacitor films are connected in parallel.

US Patent Application Publication No. 2003/0197215 JP 2012-164714 A JP 2002-151649 A JP 2004-253481 A

Here, a number of methods have been proposed as a method for improving the capacitance density of the MIM capacitor element and a method for improving the linearity. It is preferable to improve these characteristics simultaneously.
However, when the MIM capacitor element is stacked, as shown in FIG. 2, the upper capacitor film 117 and the upper part of the upper MIM capacitor element 119 are formed on the middle electrode 115 which is a part of the lower MIM capacitor element 116 and the upper part. A stacked body of the electrodes 118 is formed, and the lower electrode 113, the middle electrode 115, and the upper electrode 118 are formed in the order of steps so that the area becomes smaller. A via 121 is formed in a region of the lower electrode 113 where the middle electrode 115 is not formed, that is, a stepped portion, and a via 122 is formed in the stepped portion of the middle electrode 115 where the upper electrode 118 is not formed. .

  Therefore, when viewed from above, the area of the upper electrode 118, that is, the area of the upper surface of the upper MIM capacitor 119, has a manufacturing margin 125 from the area of the middle electrode 115, that is, the area of the upper surface of the lower MIM capacitor 116, and the middle electrode 115. Must be less than the area deducted over the entire circumference. Here, as shown in FIG. 2, the manufacturing margin 125 refers to a region where the upper electrode 118 on the middle electrode 115 is not laminated, and a laminated body including the upper capacitor film 117 and the upper electrode 118 from above the middle electrode 115, and The via 122 is provided so as not to drop off.

  Since there is a restriction that it is necessary to secure such a manufacturing margin 125, not only an increase in capacitance density due to the stacking of MIM capacitor elements is hindered, but also the upper surface (upper electrode) of the upper MIM capacitor element 119. 118) and the area of the upper surface of the lower MIM capacitor 116 (the upper surface of the middle electrode 115) cannot be freely designed. Therefore, in the method of improving the linearity between the charge amount and the voltage of the MIM capacitor by connecting two MIM capacitors having different secondary voltage coefficient characteristics in parallel, Since the linearity is improved by adjusting the area, it may affect the securing of the linearity.

In particular, when trying to obtain the same capacitance value as that of the non-stacked MIM capacitor shown in FIG. 1 by the stacked MIM capacitor shown in FIG. 2, the layout area of the lower MIM capacitor 116 is reduced. The area of the upper MIM capacitor element 119 formed on the MIM capacitor element 116 is significantly affected by the restriction due to the manufacturing margin 125.
The present invention has been made in view of such problems, and a semiconductor device and a semiconductor device capable of improving the capacitance density of the MIM capacitor element while suppressing a decrease in the degree of freedom in designing the area of the capacitor film It aims at providing the manufacturing method of.

  In order to achieve the above object, according to a semiconductor device of one embodiment of the present invention, a lower electrode, a lower capacitor film, a middle electrode, an upper capacitor film, and an upper electrode are stacked on an insulating film from the lower layer side. A laminated structure, an interlayer insulating film covering the laminated structure, a lower electrode via formed in the interlayer insulating film, electrically connected to the lower electrode, an intermediate electrode via electrically connected to the middle electrode, and an upper electrode via electrically connected to the upper electrode The lower electrode has a conductive region that is not covered by the lower capacitor film, the middle electrode, the upper capacitor film, and the upper electrode, and is electrically connected to the lower electrode via. A conductive region that is not covered by the film and the upper electrode and is electrically connected to the middle electrode via, and the upper capacitor film and the upper electrode have a stacked region that is stacked on the lower electrode without the lower capacitor film and the middle electrode. The upper electrode The semiconductor device having a conductive region electrically connected to the use vias, is provided.

  According to the semiconductor device of one embodiment of the present invention, it is possible to improve the capacitance density of the MIM capacitor element while suppressing a reduction in the degree of freedom in designing the area of the capacitor film of the MIM capacitor element.

It is sectional drawing which shows an example of the conventional MIM capacitive element. It is sectional drawing which shows an example of the conventional laminated | stacked MIM capacitive element. It is a top view which shows an example of the semiconductor device which concerns on one Embodiment of this invention. It is AA sectional drawing of FIG. It is BB sectional drawing of FIG. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention. FIG. 7 is a cross-sectional view showing a continuation of the manufacturing process of FIG. 6.

  In the following detailed description, numerous specific specific configurations are described to provide a thorough understanding of embodiments of the invention. However, it will be apparent that other embodiments may be practiced without limitation to such specific specific configurations. Further, the following embodiments do not limit the invention according to the claims, but include all combinations of characteristic configurations described in the embodiments. The drawings referred to in the following description are for explaining the configuration of the semiconductor device including the MIM capacitor element, and the size, thickness, dimensions, and the like of each part shown in the drawings are different from the actual dimensional relationship. There is.

FIG. 3 is a top view showing an example of a semiconductor device according to an embodiment of the present invention. 4 is a schematic diagram showing the AA cross section of FIG. 3, and FIG. 5 is a schematic diagram showing the BB cross section of FIG.
A semiconductor device 100 according to an embodiment of the present invention includes a lower electrode 11, a lower capacitor film 12, a middle electrode 13, an upper capacitor film 14, and an upper portion on a first interlayer insulating film 2 stacked on a silicon substrate 1. The electrode 15 includes a laminated structure 10 laminated in this order, and a second interlayer insulating film 5 is formed so as to cover the laminated structure 10. The laminated structure 10 constitutes the lower MIM capacitive element 3 and the upper MIM capacitive element 4.

As shown in FIG. 3, the silicon substrate 1 has a substantially square shape when viewed from above. A first interlayer insulating film 2 is formed on the entire surface of the silicon substrate 1.
As shown in FIG. 4, the lower MIM capacitive element 3 includes a lower electrode 11 formed on the first interlayer insulating film 2, a lower capacitive film 12 stacked on the lower electrode 11, and a lower capacitive film. 12 and a middle electrode 13 stacked on the top.

As shown in FIG. 3, the lower electrode 11 is formed in a substantially square shape when viewed from above.
The lower capacitive film 12 has a substantially rectangular shape, and is disposed at a substantially central portion of the lower electrode 11 so that the sides of the lower capacitive film 12 and the sides of the lower electrode 11 are substantially parallel to each other when viewed from above. The length of the lower capacitive film 12 in the longitudinal direction is set such that the end of the lower capacitive film 12 is slightly inside the end of the lower electrode 11 in a top view.

The middle electrode 13 has the same shape as the lower electrode 11 in a top view.
As shown in FIG. 5, the upper MIM capacitive element 4 includes a middle electrode 13, an upper capacitive film 14 formed on the middle electrode 13, and an upper electrode 15 formed on the upper capacitive film 14. .
As shown in FIG. 3, the upper capacitive film 14 has a substantially rectangular shape having a width equal to that of the lower capacitive film 12 in a top view, intersects the middle electrode 13 at the center in the longitudinal direction of the middle electrode 13, and the middle electrode 13 The upper capacitive film 14 is disposed over the middle electrode 13 and the lower electrode 11 so that both ends in the longitudinal direction of the upper capacitive film 14 are directly laminated on the lower electrode 11. The upper capacitive film 14 is arranged so that each side of the upper capacitive film 14 and each side of the lower electrode 11 are parallel to each other, and the length of the upper capacitive film 14 in the longitudinal direction is the upper capacitance in a top view. The length of the end portion of the film 14 is set slightly inside the end portion of the lower electrode 11.

The upper electrode 15 has the same width as the upper capacitive film 14 in a top view, and is stacked across the middle electrode 13 along the upper capacitive film 14.
A second interlayer insulating film 5 is laminated on the first interlayer insulating film 2 so as to cover the lower electrode 11, the middle electrode 13, and the upper electrode 15, and the second interlayer insulating film 5 is electrically connected to the lower electrode 11. Vias (lower electrode vias) 16 to be formed, vias (intermediate electrode vias) 17 connected to the middle electrode 13, and vias (upper electrode vias) 18 connected to the upper electrode 15 are formed. Specifically, as shown in FIG. 3, the via 16 is a region of the lower electrode 11 that is not covered with the lower capacitor film 12, the middle electrode 13, the upper capacitor film 14, and the upper electrode 15 (lower electrode via and It is formed in a conducting region a1 that conducts. The via 17 is formed in a region (a conductive region conducting to the middle electrode via) a <b> 2 of the middle electrode 13 that is not covered with the upper capacitive film 14 and the upper electrode 15. The via 18 is a region within the upper electrode 15 (for the upper electrode) included in the stacked region a3 in which the upper capacitor film 14 and the upper electrode 15 are stacked on the lower electrode 11 without the lower capacitor film 12 and the middle electrode 13 interposed therebetween. A conductive region conducting to the via) a4.

The upper electrode 15, the middle electrode 13, and the lower electrode 11 are made of, for example, titanium nitride TiN, titanium Ti, tantalum nitride TaN, tantalum Ta, or the like. The upper capacitor film 14 and the lower capacitor film 12 are made of, for example, silicon oxide SiO, silicon nitride SiN, or the like.
The vias 16 to 18 are made of, for example, tungsten W or aluminum Al. The first interlayer insulating film 2 and the second interlayer insulating film 5 are made of, for example, silicon oxide SiO.

Here, dielectric materials having different secondary voltage coefficients are used as the upper capacitor film 14 and the lower capacitor film 12, and the voltage dependency coefficient of the entire MIM capacitor element including the upper MIM capacitor element 4 and the lower MIM capacitor element 3 is zero. As described above, by adjusting the areas of the upper capacitor film 14 and the lower capacitor film 12, the linearity of the entire MIM capacitor element can be improved.
That is, as described in detail in Patent Document 3, as the upper capacitor film 14 and the lower capacitor film 12, for example, silicon nitride SiN having a positive secondary voltage coefficient and silicon oxide having a negative secondary voltage coefficient The area of the upper capacitor film 14 and the lower capacitor film 12 is adjusted so that the secondary voltage coefficient becomes zero using SiO. As a result, the voltage dependency of the entire MIM capacitive element including the upper MIM capacitive element 4 and the lower MIM capacitive element 3 can be made zero, and as a result, the linearity of the entire MIM capacitive element is improved. be able to.

  Further, the upper electrode 15 is disposed so as to overlap the lower electrode 11 through the upper capacitive film 14 across the middle electrode 13 in the top view, and in the portion where the upper electrode 15 does not overlap the middle electrode 13 in the top view, The upper surface of the upper electrode 15 and the upper surface of the middle electrode 13 are made to have substantially the same height, and a via 18 is formed in this portion. With this configuration, the via 17 and the via 18 can have the same depth. Here, as described in detail in Patent Document 4, for example, when a via hole for forming a via is formed by means such as plasma etching, if the depths of the via 17 and the via 18 are different, Plasma-induced damage is applied to the upper capacitive film 14 for a longer time than the difference. However, since the via 17 and the via 18 have the same depth, the time during which plasma-induced damage is applied to the upper capacitive film 14 can be further shortened. As a result, it is possible to suppress the deterioration of the reliability of the MIM capacitor due to the deterioration of the upper capacitor film due to the plasma induced damage.

Here, it is desirable that the film thickness of the upper electrode 15 and the middle electrode 13 is sufficiently thicker than the film thickness of the upper capacitor film 14, and that the upper electrode 15 and the middle electrode 13 have the same thickness. With such a configuration, the depths of the vias 17 and 18 are made more uniform, and the reliability of the entire semiconductor device 100 as the MIM capacitor element can be further improved.
Further, the upper electrode 15 is disposed so as to straddle the middle electrode 13 without covering both ends of the middle electrode 13, and both ends of the upper electrode 15 do not overlap with the middle electrode 13 and the lower capacitive film 12 in a top view. Arranged so as to overlap the lower electrode 11 through the upper capacitive film 14, vias 17 for the middle electrode 13 at both ends of the middle electrode 13, vias 18 for the upper electrode 15 at both ends of the upper electrode 15, A via 16 for the lower electrode 11 is formed in a region where the middle electrode 13 and the upper electrode 15 are not formed. Therefore, the middle electrode 13 and the upper electrode 15 have a shape in which the both end portions do not overlap with each other, and may have any shape as long as the vias 16 to 18 can be formed at the ends. That is, the middle electrode 13 and the upper electrode 15 may have the same shape in a top view, and the middle electrode 13 may be larger than the upper electrode 15.

  Therefore, as in the conventional stacked MIM capacitor shown in FIG. 2, the lower electrode 113, the middle electrode 115, and the upper electrode 118 are stacked stepwise so that the area decreases in order, and the edges of each electrode are stacked. Compared with the case where vias are formed, the area restriction on each electrode can be reduced. That is, in the semiconductor device 100 according to this embodiment, the area of the upper electrode 15 is less than the area of the middle electrode 13, and the manufacturing margin for preventing the stacked body of the upper electrode 15 and the upper capacitive film 14 from dropping from the middle electrode 13 is Compared to the case where the lower MIM capacitive element and the upper MIM capacitive element are stacked so that the area becomes smaller as it goes to the upper layer as in the prior art, it can be set to a larger value, and the degree of freedom of design increases.

Therefore, the area adjustment can be performed more easily when the linearity of the MIM capacitive element is ensured by combining different insulating capacitive films as the upper MIM capacitive element 4 and the lower MIM capacitive element 3. As a result, linearity can be ensured with higher accuracy, and the capacitance density of the MIM capacitor element can be increased.
Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 6A, after forming a semiconductor element (not shown) on the silicon substrate 1, a first interlayer insulating film 2 is deposited by, for example, a CVD method. Here, for the purpose of flattening the base of the thin film resistor, the surface of the first interlayer insulating film 2 may be polished by a CMP method or the like.
Next, as shown in FIG. 6B, the lower electrode 11 is formed on the first interlayer insulating film 2 by, for example, sputtering, and the lower electrode 11 is patterned by photolithography and etching.

  Next, as shown in FIG. 6C, a lower capacitive film 12 and a middle electrode 13 are formed in this order on the lower electrode 11, and a laminate of the lower capacitive film 12 and the middle electrode 13 is formed by photolithography and Patterning is performed by etching. At this time, as shown in FIG. 3, the stacked body of the lower capacitor film 12 and the middle electrode 13 has a rectangular shape when viewed from above, and is patterned so as to be disposed near the center of the lower electrode 11.

  Next, as shown in FIG. 7A, the upper capacitor film 14 and the upper electrode 15 are formed so as to cover the middle electrode 13 and the lower electrode 11. Thereafter, the stacked body of the upper capacitive film 14 and the upper electrode 15 is patterned by performing photolithography and etching. At this time, as shown in FIG. 3, when viewed from above, both ends of the middle electrode 13 are not covered but straddle the middle part, and the laminated body of the upper capacitive film 14 and the upper electrode 15 intersects the middle electrode 13 at the central portion. In addition, the upper capacitor film 14 is patterned in a state of being directly laminated on the lower electrode 11.

  In the above patterning process, the middle electrode 13 and the upper electrode 15 that are metals and the lower capacitor film 12 and the upper capacitor film 14 that are insulators are etched, but the lower capacitor film 12 and the upper capacitor film 14 are not completely etched. Thus, the lower capacitor film 12 and the upper capacitor film 14 can be used as a hard mask for the middle electrode 13 and the lower electrode 11 to prevent unintended etching on the already patterned electrode. That is, when patterning the upper capacitive film 14 and the upper electrode 15, for example, by leaving a part of the upper capacitive film 14 on the middle electrode 13, etching to the already patterned middle electrode 13 can be prevented.

  Subsequently, as shown in FIG. 7B, the second electrode 11, the lower capacitor film 12, the middle electrode 13, the upper capacitor film 14, and the upper electrode 15 are covered on the first interlayer insulating film 2. The interlayer insulating film 5 is deposited by, for example, the CVD method. As shown in FIGS. 4 and 5, a portion where the lower electrode 11, the upper capacitor film 14, and the upper electrode 15 are stacked except for the stacked portion of the lower capacitor film 12 and the middle electrode 13 in a top view. Then, a via 18 for the upper electrode 15 that is electrically connected to the upper electrode 15 is formed. In addition, when viewed from above, a middle electrode that is electrically connected to the middle electrode 13 is formed in a portion where the lower electrode 11, the lower capacitance film 12, and the middle electrode 13 are laminated, excluding the laminated body portion of the upper capacitive film 14 and the upper electrode 15. 13 vias 17 are formed. Similarly, a via 16 for the lower electrode 11 that is electrically connected to the lower electrode 11 is formed in a portion of the lower electrode 11 where the middle electrode 13 and the upper electrode 15 are not formed in a top view.

As a result, the semiconductor device 100 having the MIM capacitive element in which the lower MIM capacitive element 3 and the upper MIM capacitive element 4 are stacked as shown in FIGS. 3 to 5 is formed.
In the above-described embodiment, the case where the middle electrode 13 and the upper electrode 15 are rectangles having the same shape in a top view as shown in FIG. 3 and these are arranged so as to be orthogonal to each other at the center thereof has been described. However, it is not limited to this. For example, even when the laminated body of the middle electrode 13 and the lower capacitive film 12 and the laminated body of the upper electrode 15 and the upper capacitive film 14 are arranged in an L shape so as to overlap each other only at one end. Can be applied. Further, the laminated body of the middle electrode 13 and the lower capacitive film 12 and the laminated body of the upper electrode 15 and the upper capacitive film 14 may have different widths, and the lower capacitive film 12 is directly laminated on the lower electrode 11. The area of the portion where the upper capacitance film 14 is directly stacked on the lower electrode 11 may not coincide with the area of the portion where the upper capacitance film 14 is directly laminated on the lower electrode 11. Further, the lower electrode 11 does not have to be square in a top view, and similarly, the stacked body of the middle electrode 13 and the lower capacitive film 12 and the stacked body of the upper electrode 15 and the upper capacitive film 14 may not be rectangular. .

  As mentioned above, although one Embodiment of this invention was described, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 1st interlayer insulation film 5 2nd interlayer insulation film 11 Lower electrode 12 Lower capacity film 13 Middle electrode 14 Upper capacity film 15 Upper electrodes 16-18 Via

Claims (3)

A laminated structure in which a lower electrode, a lower capacitive film, a middle electrode, an upper capacitive film and an upper electrode are laminated on the insulating film from the lower layer side,
An interlayer insulating film covering the laminated structure;
A plurality of vias formed in the interlayer insulating film and including a lower electrode via that is conductive to the lower electrode, a middle electrode via that is conductive to the middle electrode, and an upper electrode via that is conductive to the upper electrode; ,
The lower electrode has a conductive region that is not covered with the lower capacitive film, the middle electrode, the upper capacitive film, and the upper electrode and is electrically connected to the lower electrode via,
The middle electrode has a conduction region that is not covered with the upper capacitive film and the upper electrode and is electrically connected to the middle electrode via,
The upper capacitor film and the upper electrode have a stacked region that is stacked on the lower electrode without the lower capacitor film and the middle electrode, and the upper electrode has a via hole for the upper electrode in the stacked region. A semiconductor device having a conduction region that conducts with the semiconductor device. The middle electrode and the upper electrode are rectangles included in the lower electrode in a top view,
2. The semiconductor device according to claim 1, wherein the lower capacitor film and the middle electrode and the upper capacitor film and the upper electrode intersect so that both ends do not overlap each other. Forming a lower electrode on the insulating film;
A step of laminating a lower capacitive film and a middle electrode in this order on the lower electrode, and patterning the lower electrode so as to cover a region excluding a conductive region electrically connected to a lower electrode via;
An upper capacitive film and an upper electrode are stacked in this order on the middle electrode and the lower electrode, and a conduction region that is electrically connected to the middle electrode via of the middle electrode and the lower electrode via of the lower electrode are stacked. Patterning so as to cover a region excluding a conductive region conductive with
Laminating an interlayer insulating film covering the lower electrode, the lower capacitive film, the middle electrode, the upper capacitive film and the upper electrode;
Forming the lower electrode via that is conductive to the conductive region of the lower electrode, the middle electrode via that is conductive to the conductive region of the middle electrode, and the upper electrode via that is conductive to the upper electrode; When,
A method for manufacturing a semiconductor device, comprising:

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