JP2018037128A - Peak hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a peak hold circuit capable of decreasing a rate of change in charging voltage of a hold capacitor due to a leakage current.SOLUTION: A peak hold circuit 1 charging input voltage Vin to a hold capacitor C1 and holding a peak value of voltage charged into the hold capacitor, includes: a switching element Q1 in which a drain is connected to a power supply Vcc; a first resistance R1 connected to a source of the switching element at one end; a second resistance R2 connected to the other end of the first resistance at one end, and connected to a ground GND at the other end; and an operational amplifier OP1 which amplifies differential voltage between voltage from the other end of the first resistance and the one end of the second resistance and the input voltage, and outputs the amplified voltage to gates of the hold capacitor and the switching element. A peak hold voltage Vpeak is taken out from the other end of the first resistance and the one end of the second resistance.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a peak hold circuit that charges an input voltage to a hold capacitor and holds a peak value of the charged voltage.

  As a conventional peak hold circuit, a peak hold circuit described in Patent Document 1 is known. The peak hold circuit includes a comparator for comparing an input signal and a comparison reference signal, a first resistor and a second resistor for resistance-dividing the output signal of the comparator and outputting a comparison reference signal from a common connection point thereof. The capacitor comprises a capacitor connected in series with a first resistor and a second resistor to the output terminal of the comparator, and is configured to take out the peak hold voltage of the input signal from between both ends of the capacitor.

  In such a peak hold circuit, in order to guarantee the hold time, a hold capacitor is connected to the outside of the integrated circuit (IC). That is, a capacitor is externally attached. In this case, the hold capacitor is connected to the terminal of the IC. Usually, an electrostatic discharge protection element (ESD protection element) or the like is connected to this terminal.

JP-A-4-191667

  For this reason, when the junction temperature increases, the leakage current of the ESD protection element increases, and the charge charged in the capacitor is discharged. As a result, the voltage held in the capacitor decreases with time, and the hold time (guaranteed time) is shortened. For this reason, it has been desired to reduce the rate of change of the charging voltage of the hold capacitor due to the leakage current.

  An object of the present invention is to provide a peak hold circuit that can reduce the rate of change of the charging voltage of the hold capacitor due to a leakage current by increasing the voltage charged to the hold capacitor.

  In order to solve the above problems, a peak hold circuit according to the present invention is a peak hold circuit that charges an input voltage to a hold capacitor and holds a peak value of the voltage charged in the hold capacitor. A first switching element to which the main terminal is connected, a first resistor having one end connected to the second main terminal of the first switching element, one end connected to the other end of the first resistor, and the other end serving as a reference A second resistor connected to a potential, a voltage from the other end of the first resistor and a voltage from one end of the second resistor, and the input voltage are amplified, and the amplified voltage is supplied to the capacitor and the first resistor. And an amplifier circuit that outputs to a control terminal of the switching element, and a peak hold voltage is extracted from the other end of the first resistor and one end of the second resistor.

  According to the present invention, the amplifier circuit amplifies the voltage difference between the voltage from the other end of the first resistor and the one end of the second resistor and the input voltage, and controls the amplified voltage to the hold capacitor and the first switching element. Since the signal is output to the terminal, the hold capacitor is charged by the amplified voltage.

  In addition, the current flowing through the first switching element increases, and the voltage at one end of the second resistor further increases. For this reason, the peak hold voltage taken out from the other end of the first resistor and one end of the second resistor also increases. At this time, a value obtained by multiplying the combined resistance value of the first resistor and the second resistor by the second resistance value and the peak hold voltage, and the threshold value of the first switching element. A voltage obtained by adding the voltage is applied to the hold capacitor.

  Therefore, by increasing the voltage charged in the hold capacitor, the rate of change of the charge voltage of the hold capacitor due to the leakage current can be reduced.

It is a circuit block diagram of the peak hold circuit of Example 1 of this invention. It is a circuit block diagram of the peak hold circuit of Example 2 of this invention. It is a circuit block diagram of the peak hold circuit of Example 3 of this invention.

  Hereinafter, some embodiments of the peak hold circuit of the present invention will be described in detail with reference to the drawings.

Example 1
1 is a circuit configuration diagram of a peak hold circuit according to a first embodiment of the present invention. A peak hold circuit 1 shown in FIG. 1 includes an IC, charges an input voltage Vin to an external hold capacitor C1 with respect to the IC, and holds a peak value of the voltage charged in the hold capacitor C1.

  The peak hold circuit 1 includes a power supply Vcc, a switching element Q1, a first resistor R1, a second resistor R2, an operational amplifier (amplifier circuit) OP1, a diode D1, and a resistor R3.

  The switching element Q1 corresponds to the first switching element of the present invention, is made of a MOSFET, and has a drain (first main terminal) connected to the power supply Vcc. One end of the first resistor R1 is connected to the source of the switching element Q1. The second resistor R2 has one end connected to the other end of the first resistor R1 and the other end connected to the ground GND that is a reference potential.

  The operational amplifier OP1 amplifies the difference voltage between the voltage from the other end of the first resistor R1 and one end of the second resistor R2 and the input voltage Vin, and the amplified voltage is applied to the hold capacitor C1 via the diode D1 and the resistor R3. Output to one end and the gate (control terminal) of the switching element Q1. The other end of the hold capacitor C1 is connected to the ground GND.

  A zener diode D2 for electrostatic discharge protection is connected to both ends of the hold capacitor C1. Further, the peak hold voltage Vpeak is extracted from the other end of the first resistor R1 and one end of the second resistor R2. The peak hold voltage Vpeak is the maximum value of the input voltage Vin.

  As described above, according to the peak hold circuit of the first embodiment, the operational amplifier OP1 amplifies and amplifies the difference voltage between the voltage from the other end of the first resistor R1 and one end of the second resistor R2 and the input voltage Vin. Since the voltage is output to the hold capacitor C1 and the gate of the switching element Q1, the hold capacitor C1 is charged by the amplified voltage.

  Further, the current flowing through the switching element Q1 increases, and the voltage at one end of the second resistor R2 further increases. For this reason, the peak hold voltage Vpeak extracted from the other end of the first resistor R1 and one end of the second resistor R2 also increases.

  At this time, a value obtained by multiplying the combined resistance value of the first resistor R1 and the second resistor R2 by the second resistance value R2 and the peak hold voltage Vpeak, and the switching element Q1 A voltage obtained by adding the threshold voltage Vth is the voltage VC1 applied to the hold capacitor C1. The voltage VC1 is expressed by equation (1).

  Voltage VC1 = Vpeak × {(R1 + R2) / R2} + Vth (1)

  Therefore, by increasing the voltage charged to the hold capacitor C1, the rate of change of the charge voltage of the hold capacitor due to the leakage current can be reduced. For example, when a voltage change of −10 mV occurs after a certain period of time, the change rate is −10% when the charge voltage Vc1 of the hold capacitor C1 is 100 mV, but −10% when the charge voltage Vc1 of the hold capacitor C1 is 10V. The rate of change is 0.1%. That is, the higher the voltage charged in the hold capacitor C1, the better. The gain of the operational amplifier OP1 may be varied to use the entire range of the power supply voltage Vcc.

  As a result, the influence of the voltage drop due to the leakage current of the electrostatic protection element or the like can be reduced, and the capacitance of the hold capacitor C1 can be reduced if the hold time is the same.

(Example 2)
FIG. 2 is a circuit configuration diagram of the peak hold circuit according to the second embodiment of the present invention. The peak hold circuit according to the second embodiment shown in FIG. 2 includes a first capacitor voltage changing circuit that changes the voltage applied to the hold capacitor C1 according to the voltage value of the power supply. The first capacitor voltage changing circuit includes a third resistor R4, a second switching element Q2, and a comparator CP1.

  The third resistor R4 is connected between the other end of the second resistor R2 and the ground GND. The switching element Q2 corresponds to the second switching element of the present invention, is made of a MOSFET, and is connected to both ends of the third resistor R4. The comparator CP1 compares the voltage of the power supply Vcc and the voltage of the reference power supply V1, and when the voltage of the power supply Vcc is equal to or higher than the voltage of the reference power supply V1, the switching element Q2 is turned on. When the voltage is less than the voltage, the switching element Q2 is turned off.

  Next, the operation of the peak hold circuit of the second embodiment configured as described above will be explained. First, when the voltage of the power supply Vcc is equal to or higher than the voltage of the reference power supply V1, the comparator CP1 outputs an H level to the gate of the second switching element Q2. For this reason, since the second switching element Q2 is turned on, the other end of the second resistor R2 is connected to the ground GND, so that the circuit of the first embodiment is the same.

  For this reason, the value obtained by dividing the combined resistance value of the first resistor R1 and the second resistor R2 by the second resistance value R2 and the peak hold voltage Vpeak, and the switching element Q1 A voltage obtained by adding the threshold voltage Vth is the voltage VC1 applied to the hold capacitor C1. The voltage VC1 is expressed by the above-described equation (1).

  Next, when the voltage of the power supply Vcc is less than the voltage of the reference power supply V1, the comparator CP1 outputs the L level to the gate of the second switching element Q2. For this reason, the second switching element Q2 is turned off. For this reason, the third resistor R4 is connected between the other end of the second resistor R2 and the ground GND.

  Therefore, the peak hold voltage Vpeak is set to a value obtained by dividing the combined resistance value of the first resistor R1, the second resistor R2, and the third resistor R4 by the combined resistance value of the second resistance value R2 and the third resistor R4. A voltage VC1 applied to the hold capacitor C1 is a voltage obtained by adding the value obtained by the multiplication and the threshold voltage Vth of the switching element Q1.

  In this case, the voltage VC1 is expressed by Expression (2).

  Voltage VC1 = Vpeak × {(R1 + R2 + R4) / (R2 + R4)} + Vth (2)

  Thus, according to the peak hold circuit of the second embodiment, the voltage applied to the hold capacitor C1 can be changed according to the voltage value of the power supply Vcc. Thereby, the voltage charged in the hold capacitor C1 can be maximized.

(Example 3)
FIG. 3 is a circuit configuration diagram of the peak hold circuit according to the third embodiment of the present invention. The peak hold circuit according to the third embodiment shown in FIG. 3 includes a second capacitor voltage changing circuit that changes the voltage applied to the hold capacitor C1 in accordance with the value of the input voltage Vin. The second capacitor voltage changing circuit includes a third resistor R4, a second switching element Q2, a comparator CP2, a latch circuit 10, and an inverter 11.

  Since the connection of the third resistor R4 and the second switching element Q2 is the same as those shown in FIG. 2, the description thereof is omitted.

  The comparator CP2 compares the voltage at the connection point between the first resistor R1 and the second resistor R2 with the voltage of the reference power supply, and outputs a comparison output to the latch circuit 10. The latch circuit 10 latches the comparison output of the comparator CP2, and the latch output is input to the inverter 11. The output of the inverter 11 is output to the gate of the second switching element Q2.

  Next, the operation of the peak hold circuit of the third embodiment configured as described above will be described. First, when the voltage at the connection point between the first resistor R1 and the second resistor R2, that is, the peak hold voltage Vpeak (peak hold voltage Vpeak = the maximum value of the input voltage Vin) is equal to or higher than the voltage of the reference power supply V1, The comparator CP2 inputs the H level to the inverter 11 via the latch circuit 10. The phase is inverted by the inverter 11 and the L level is output to the gate of the second switching element Q2. For this reason, the second switching element Q2 is turned off. For this reason, the third resistor R4 is connected between the other end of the second resistor R2 and the ground GND.

  Therefore, the peak hold voltage Vpeak is set to a value obtained by dividing the combined resistance value of the first resistor R1, the second resistor R2, and the third resistor R4 by the combined resistance value of the second resistance value R2 and the third resistor R4. A voltage VC1 applied to the hold capacitor C1 is a voltage obtained by adding the value obtained by the multiplication and the threshold voltage Vth of the switching element Q1. That is, in this case, the voltage VC1 is expressed by the above-described equation (2).

  Next, when the voltage at the connection point between the first resistor R1 and the second resistor R2, that is, the peak hold voltage Vpeak (peak hold voltage Vpeak = the maximum value of the input voltage Vin) is less than the voltage of the reference power supply V1. The comparator CP 2 inputs the L level to the inverter 11 via the latch circuit 10. The phase is inverted by the inverter 11 and the H level is output to the gate of the second switching element Q2. For this reason, since the second switching element Q2 is turned on, the other end of the second resistor R2 is connected to the ground GND, so that the circuit of the first embodiment is the same.

  For this reason, the value obtained by dividing the combined resistance value of the first resistor R1 and the second resistor R2 by the second resistance value R2 and the peak hold voltage Vpeak, and the switching element Q1 A voltage obtained by adding the threshold voltage Vth is the voltage VC1 applied to the hold capacitor C1. That is, in this case, the voltage VC1 is expressed by the above-described equation (1).

  Thus, according to the peak hold circuit of the third embodiment, the voltage applied to the hold capacitor C1 can be changed according to the value of the input voltage Vin. Thereby, the voltage charged in the hold capacitor C1 can be maximized.

Vcc Power supply Vin Input voltage V1 Reference voltage GND Ground Q1, Q2 Switching element D1 Diode D2 Zener diodes R1-R4 Resistor C1 Hold capacitor OP1 Operational amplifier CP1, CP2 Comparator 10 Latch circuit 11 Inverter

Claims (5)

A peak hold circuit that charges an input voltage to a hold capacitor and holds a peak value of the voltage charged in the hold capacitor,
A first switching element having a first main terminal connected to a power source;
A first resistor having one end connected to the second main terminal of the first switching element;
A second resistor having one end connected to the other end of the first resistor and the other end connected to a reference potential;
Amplifying the difference voltage between the voltage from the other end of the first resistor and one end of the second resistor and the input voltage, and outputting the amplified voltage to the control terminal of the hold capacitor and the first switching element With circuit,
A peak hold circuit that extracts a peak hold voltage from the other end of the first resistor and one end of the second resistor.   2. The peak hold circuit according to claim 1, further comprising a first capacitor voltage changing circuit that changes a voltage applied to the hold capacitor in accordance with a voltage value of the power supply.   The peak hold circuit according to claim 1, further comprising a second capacitor voltage changing circuit that changes a voltage applied to the hold capacitor in accordance with a value of the input voltage. The first capacitor voltage changing circuit includes:
A third resistor connected between the other end of the second resistor and the reference potential;
A second switching element connected to both ends of the third resistor;
The power supply voltage is compared with a reference voltage. When the power supply voltage is equal to or higher than the reference voltage, the second switching element is turned on. When the power supply voltage is lower than the reference voltage, the second switching element is turned on. A comparator that turns off the switching element;
The peak hold circuit according to claim 2, further comprising: The second capacitor voltage changing circuit includes:
A third resistor connected between the other end of the second resistor and the reference potential;
A second switching element connected to both ends of the third resistor;
An inverter having an output terminal connected to a control terminal of the second switching element;
When the voltage at the connection point between the first resistor and the second resistor is equal to or higher than a reference voltage, an H level is output to the input terminal of the inverter, and when the voltage at the connection point is less than the reference voltage. A comparator that outputs an L level to the input terminal of the inverter;
The peak hold circuit according to claim 3, further comprising:

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