JP2018033180A - Level shifter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level shifter that can implement high speed operation without reducing reliability.SOLUTION: According to one embodiment, a level shifter 1 includes: high voltage PMOS transistors P1 and P2; high voltage depletion type NMOS transistors NA1 and NA2 having respective gates supplied with control signals IN1 and IN2; low voltage NMOS transistors N1 and N2 having respective gates supplied with control signals IN3 and IN4; and a timing control section for generating the control signal IN1 corresponding to an inverted signal of an input signal IN and the control signal IN3 different from the control signal IN1, and generating the control signal IN2 corresponding to a non-inverted signal of the input signal IN and the control signal IN4 different from the control signal IN2.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a level shifter, for example, a level shifter suitable for high-speed operation.

  The internal voltage of the semiconductor device is lowered as power consumption is reduced. This increases the potential difference between the internal voltage and the external voltage of the semiconductor device. A level shifter that interfaces the inside and the outside of a semiconductor device is required to operate at high speed without reducing reliability even when the potential difference between the input voltage and the output voltage is large.

  Non-patent document 1 discloses a level shifter capable of realizing high-speed operation.

Wen-Tai Wang et al., "Level Shifters for High-speed 1-V to 3.3-V Interfaces in a 0.13-um Cu-Interconnection / Low-k CMOS Technology", IEEE, 2001, pp307-310

  However, in the level shifter disclosed in Non-Patent Document 1, a voltage exceeding the breakdown voltage may be applied to the low breakdown voltage MOS transistor used in the level shifter. As a result, the low-breakdown-voltage MOS transistor is destroyed or deteriorated, resulting in a problem that the reliability of the level shifter is lowered. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the level shifter includes a high breakdown voltage first and second PMOS transistor, and a high breakdown voltage first and second depletion type NMOS transistor in which first and second control signals are supplied to the respective gates. And the first and second NMOS transistors having low breakdown voltages in which the third and fourth control signals are supplied to the respective gates, and the first control signal corresponding to the inverted signal of the input signal and the first control signal are different. A timing control unit that generates the third control signal and generates the second control signal corresponding to the normal rotation signal of the input signal and the fourth control signal different from the second control signal. .

  According to the embodiment, it is possible to provide a level shifter that can realize high-speed operation without reducing reliability.

FIG. 3 is a diagram illustrating a configuration example of a level shifter according to the first exemplary embodiment; 3 is a timing chart showing the operation of the level shifter according to the first exemplary embodiment; FIG. 3 is a diagram illustrating a first specific configuration example of the level shifter according to the first embodiment. It is a figure which shows the 1st modification of the level shifter shown in FIG. It is a figure which shows the 2nd modification of the level shifter shown in FIG. FIG. 6 is a diagram illustrating a second specific configuration example of the level shifter according to the first embodiment. It is a figure which shows the 1st modification of the level shifter shown in FIG. FIG. 6 is a diagram illustrating a configuration example of a level shifter according to a second exemplary embodiment. 6 is a diagram illustrating a first specific configuration example of a level shifter according to a second embodiment; FIG. FIG. 10 is a diagram illustrating a second specific configuration example of the level shifter according to the second exemplary embodiment. It is a figure which shows the structure of the level shifter of a related technique. It is a timing chart which shows operation | movement of the level shifter of a related technique.

<Examination by the inventor>
Before describing the level shifter according to the present embodiment, the contents studied by the present inventor regarding related technologies will be described.

  FIG. 11 is a diagram illustrating a configuration of a level shifter according to a related technique disclosed in Non-Patent Document 1. The level shifter shown in FIG. 11 includes high breakdown voltage PMOS transistors P1, P2, high breakdown voltage depletion type NMOS transistors NA1, NA2, and low breakdown voltage NMOS transistors N1, N2.

  The high breakdown voltage MOS transistor is a MOS transistor that does not break down until the voltage between two terminals of the source, drain, and gate reaches the high power supply voltage VDDQ. The low breakdown voltage MOS transistor is a MOS transistor that does not break down until the voltage between two terminals of the source, drain, and gate reaches the low power supply voltage VDD. A high breakdown voltage MOS transistor has a feature that a gate insulating film is thicker than a low breakdown voltage MOS transistor, for example. The depletion type MOS transistor is sometimes called a native MOS transistor or a 0-Vth type MOS transistor. The threshold voltage Vth of the depletion type MOS transistor is 0 V to −0. It is about several volts.

  The level shifter shown in FIG. 11 includes low breakdown voltage NMOS transistors N1 and N2 as transistors that receive low voltage input signals INL and INR. Thereby, even when the voltage level of the power supply voltage VDD is low or the potential difference between the power supply voltages VDD and VDDQ is large, a high-speed level shift operation is possible. Further, the level shifter shown in FIG. 11 includes high breakdown voltage depletion type NMOS transistors NA1, NA2 between the low breakdown voltage NMOS transistors N1, N2 and the power supply voltage terminal to which the high voltage power supply voltage VDDQ is supplied, respectively. It has. As a result, the voltages of the nodes INT1 and INT2 are kept low, so that a voltage exceeding the breakdown voltage is not applied to the low breakdown voltage NMOS transistors N1 and N2. Thereby, the deterioration of the low breakdown voltage NMOS transistors N1 and N2 is suppressed.

  However, the inventor has discovered that a voltage exceeding the withstand voltage may be applied to the low withstand voltage NMOS transistors N1 and N2 of the level shifter shown in FIG.

  FIG. 12 is a timing chart for explaining the problem of the level shifter of the related technology. For example, when the input signal IN rises from L level (reference voltage VSS) to H level (power supply voltage VDD), the inverted signal INR of the input signal falls from H level to L level accordingly. As a result, the gate voltage of the high breakdown voltage depletion type NMOS transistor NA2 and the gate voltage of the low breakdown voltage NMOS transistor N2 simultaneously fall from the H level to the L level.

  Here, generally, the response speed of the low breakdown voltage MOS transistor is faster than the response speed of the high breakdown voltage MOS transistor. That is, the response speed of the low breakdown voltage NMOS transistor N2 is faster than the response speed of the high breakdown voltage depletion type NMOS transistor NA2. For this reason, there is a possibility that the on-resistance of the high breakdown voltage depletion type NMOS transistor NA1 has not yet increased sufficiently when the low breakdown voltage NMOS transistor N2 is turned off. In that case, since the voltage of the node INT2 becomes high, a voltage exceeding the breakdown voltage is applied to the low breakdown voltage NMOS transistor N2. For example, when the threshold voltage Vth of the high breakdown voltage depletion type NMOS transistor NA2 is −0.5V and the power supply voltage VDD is 1.0V, the voltage of the node INT2 is as high as VDD−Vt = 1.5V. A voltage exceeding the withstand voltage is applied to the transistor N2. As a result, the low breakdown voltage NMOS transistor N2 is deteriorated. As a result, the reliability of the level shifter is lowered.

  Hereinafter, embodiments will be described with reference to the drawings. Since the drawings are simple, the technical scope of the embodiments should not be narrowly interpreted based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including operation steps and the like) are not necessarily essential except when clearly indicated and clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

<Embodiment 1>
FIG. 1 is a diagram illustrating a configuration example of the level shifter 1 according to the first embodiment. The level shifter 1 according to the present embodiment applies a voltage exceeding the breakdown voltage to the low breakdown voltage NMOS transistor by controlling the conduction state of the low breakdown voltage NMOS transistor and the high breakdown voltage depletion type NMOS transistor by different control signals. I'm trying not to be. Thereby, deterioration of the low breakdown voltage NMOS transistor is suppressed. That is, the level shifter 1 according to the present embodiment can realize high-speed operation without reducing reliability. This will be specifically described below.

  The level shifter 1 shown in FIG. 1 includes a level shift unit 11, a timing control circuit (first timing control circuit) 12, a timing control circuit (second timing control circuit) 13, and an inverter INV1. The timing control circuits 12 and 13 and the inverter INV1 constitute a timing control unit.

  The level shifter 11 includes a high breakdown voltage PMOS transistor (first PMOS transistor) P1, a high breakdown voltage PMOS transistor (second PMOS transistor) P2, and a high breakdown voltage depletion type NMOS transistor (first depletion type NMOS transistor) NA1. A high breakdown voltage depletion type NMOS transistor (second depletion type NMOS transistor) NA2, a low breakdown voltage NMOS transistor (first NMOS transistor) N1, and a low breakdown voltage NMOS transistor (second NMOS transistor) N2. .

  The high voltage PMOS transistors P1 and P2 are connected in parallel between a power supply voltage terminal (first power supply voltage terminal; hereinafter referred to as a power supply voltage terminal VDDQ) to which a high voltage power supply voltage VDDQ is supplied and a reference voltage terminal VSS. And the respective gates are connected to the respective drains.

  More specifically, in the high voltage PMOS transistor P1, the source is connected to the power supply voltage terminal VDDQ, the drain is connected to the node LSDL, and the gate is connected to the node LSDR. In the high voltage PMOS transistor P2, the source is connected to the power supply voltage terminal VDDQ, the drain is connected to the node LSDR, and the gate is connected to the node LSDL.

  The high breakdown voltage depletion type NMOS transistors NA1 and NA2 are provided in series with the high breakdown voltage PMOS transistors P1 and P2 between the high breakdown voltage PMOS transistors P1 and P2 and the reference voltage terminal VSS, respectively.

  More specifically, in the high breakdown voltage depletion type NMOS transistor NA1, the source is connected to the node INT1, the drain is connected to the node LSDL, and the control signal (first control signal) IN1 is supplied to the gate. In the high breakdown voltage depletion type NMOS transistor NA2, the source is connected to the node INT2, the drain is connected to the node LSDR, and the control signal (second control signal) IN2 is supplied to the gate.

  The low breakdown voltage NMOS transistors N1 and N2 are provided in series with the high breakdown voltage depletion type NMOS transistors NA1 and NA2 between the high breakdown voltage depletion type NMOS transistors NA1 and NA2 and the reference voltage terminal VSS, respectively. .

  More specifically, in the low breakdown voltage NMOS transistor N1, the source is connected to the reference voltage terminal VSS, the drain is connected to the node INT1, and the control signal (third control signal) IN3 is supplied to the gate. In the low breakdown voltage NMOS transistor N2, the source is connected to the reference voltage terminal VSS, the drain is connected to the node INT2, and the control signal (fourth control signal) IN4 is supplied to the gate.

  The timing control circuit 12 is provided between a power supply voltage terminal (second power supply voltage terminal; hereinafter referred to as a power supply voltage terminal VDD) to which a low power supply voltage VDD lower than the power supply voltage VDDQ is supplied and a reference voltage terminal VSS. The control signals IN1 and IN3 are generated by inverting an input signal (hereinafter referred to as an input signal IN) supplied from the outside to the input terminal IN. That is, the timing control circuit 12 generates the control signals IN1 and IN3 corresponding to the inverted signal of the input signal IN. However, the control signals IN1 and IN3 are different signals. Note that the input signal IN indicates a potential within a range between the power supply voltage VDD and the reference voltage terminal VSS.

  The timing control circuit 13 is provided between the power supply voltage terminal VDD and the reference voltage terminal VSS, and inverts an inverted signal of the input signal IN to generate control signals IN2 and IN4. That is, the timing control circuit 13 generates the control signals IN2 and IN4 corresponding to the normal rotation signal of the input signal IN. However, the control signals IN2 and IN4 are different signals.

  That is, the timing control unit including the timing control circuits 12 and 13 and the inverter INV1 is provided between the power supply voltage terminal VDD and the reference voltage terminal VSS, and controls the control signal IN1 corresponding to the inverted signal of the input signal IN and the control signal. A control signal IN3 different from IN1 is generated, and a control signal IN2 corresponding to the normal rotation signal of the input signal IN and a control signal IN4 different from the control signal IN2 are generated.

  For example, the timing control unit generates control signals IN1 and IN2 having a smaller slew rate at the time of rising than the control signals IN3 and IN4, and a control signal IN3 having a smaller slew rate at the time of falling than the control signals IN1 and IN2. , IN4. Thereby, the low breakdown voltage NMOS transistors N1 and N2 can be turned off after increasing the on-resistance of the high breakdown voltage depletion type NMOS transistors NA1 and NA2 to a predetermined value or more. Further, the low breakdown voltage NMOS transistors N1 and N2 can be turned on before the on-resistances of the high breakdown voltage depletion type NMOS transistors NA1 and NA2 are reduced below a predetermined value. As a result, it is possible to prevent a voltage exceeding the breakdown voltage from being applied to the low breakdown voltage NMOS transistors N1 and N2.

(Operation of level shifter 1)
Next, the operation of the level shifter 1 according to the present embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing the operation of the level shifter 1. In FIG. 2, Vgs (NA2) represents the gate-source voltage of the high breakdown voltage depletion type NMOS transistor NA2, and Vgs (N2) represents the gate-source voltage of the low voltage NMOS transistor N2. .

  First, the input signal IN falls from the H level (power supply voltage VDD) to the L level (reference voltage VSS). Thereby, the inverted signal INR of the input signal IN rises from the L level to the H level (time t0 to t1). At this time, the timing control circuit 13 falls the control signal IN2 from the H level to the L level (time t0 to t1), and the control signal IN4 is changed from the H level to the L level at a slew rate smaller than that of the control signal IN2. Fall to the level (time t0 to t2). Thereby, after the on-resistance of the high breakdown voltage depletion type NMOS transistor NA2 becomes sufficiently large, the low breakdown voltage NMOS transistor N2 is turned off. Thereby, since the voltage of the node INT2 is kept small, a voltage exceeding the breakdown voltage is not applied to the low breakdown voltage NMOS transistor N2. Thereby, the deterioration of the low breakdown voltage NMOS transistor N2 is suppressed.

  Note that the potential of the node INT2 is obtained by subtracting the threshold voltage Vth (NA2) from the gate-source voltage Vgs (NA2) of the high breakdown voltage depletion type NMOS transistor NA2. Therefore, the potential of the node INT2 when the low breakdown voltage NMOS transistor N2 is turned off is about 0−Vth = | Vth |. Here, the threshold voltage Vth (NA2) is 0 V to −0. Since the voltage is about several volts, a voltage exceeding the breakdown voltage is not applied to the low breakdown voltage NMOS transistor N2.

  In contrast, although not shown, the timing control circuit 12 raises the control signal IN3 from the L level to the H level (time t0 to t1), and the control signal IN1 has a slew rate smaller than that of the control signal IN3 (slowly). Ii) rise from L level to H level (time t0 to t2). Thereby, the low breakdown voltage NMOS transistor N1 is turned on while the on-resistance of the high breakdown voltage depletion type NMOS transistor NA1 is large. As a result, the voltage of the node INT1 is kept small, and thus no voltage exceeding the breakdown voltage is applied to the low breakdown voltage NMOS transistor N1. Thereby, the deterioration of the low breakdown voltage NMOS transistor N1 is suppressed.

  Since the low breakdown voltage NMOS transistor N2 is turned off and the low breakdown voltage NMOS transistor N1 is turned on, the potential of the node LSDR rises to about the power supply voltage VDDQ, and the potential of the node LSDL falls to about the reference voltage VSS. The voltage of the node LSDR is output to the outside from the output terminal OUT.

  Next, the input signal IN rises from the L level to the H level. Thereby, the inverted signal INR of the input signal IN falls from the H level to the L level (time t3 to t5). At this time, the timing control circuit 13 raises the control signal IN4 from the L level to the H level (time t3 to t5) and changes the control signal IN2 from the L level to the H level at a slew rate smaller than that of the control signal IN4. The level is raised (time t3 to t6). Thereby, the low breakdown voltage NMOS transistor N2 is turned on while the on-resistance of the high breakdown voltage depletion type NMOS transistor NA2 is large. Thereby, since the voltage of the node INT2 is kept small, a voltage exceeding the breakdown voltage is not applied to the low breakdown voltage NMOS transistor N2. Thereby, the deterioration of the low breakdown voltage NMOS transistor N2 is suppressed.

  As described above, the potential of the node INT2 is obtained by subtracting the threshold voltage Vth (NA2) from the gate-source voltage Vgs (NA2) of the high breakdown voltage depletion type NMOS transistor NA2. Here, since the voltage level of the control signal IN2 has not yet reached the H level (power supply voltage VDD) when the low voltage NMOS transistor N2 is switched from off to on, Vgs (NA2) is lower than the power supply voltage VDD. . Therefore, the potential of the node INT2 is also lower than VDD. Therefore, a voltage exceeding the withstand voltage is not applied to the low withstand voltage NMOS transistor N2.

  In contrast, although not shown, the timing control circuit 12 causes the control signal IN1 to fall from the H level to the L level (time t3 to t5), and the control signal IN3 has a slew rate smaller than that of the control signal IN1 (slowly). (D) The signal falls from the H level to the L level (time t3 to t6). Thereby, after the on-resistance of the high breakdown voltage depletion type NMOS transistor NA1 becomes sufficiently large, the low breakdown voltage NMOS transistor N1 is turned off. As a result, the voltage of the node INT1 is kept small, and thus no voltage exceeding the breakdown voltage is applied to the low breakdown voltage NMOS transistor N1. Thereby, the deterioration of the low breakdown voltage NMOS transistor N1 is suppressed.

  Since the low breakdown voltage NMOS transistor N1 is turned off and the low breakdown voltage NMOS transistor N2 is turned on, the potential of the node LSDL rises to about the power supply voltage VDDQ, and the potential of the node LSDR falls to about the reference voltage VSS. The voltage of the node LSDR is output to the outside from the output terminal OUT.

  More specifically, the timing control circuit 13 has a high breakdown voltage at the time when the gate-source voltage of the low breakdown voltage NMOS transistor N2 decreases and becomes lower than the threshold voltage of the low breakdown voltage NMOS transistor N2 (time t1 in FIG. 2). The control signals IN2 and IN4 are generated so that the gate-source voltage of the depletion type NMOS transistor NA2 is lower than the sum of the threshold voltage of the high breakdown voltage depletion type NMOS transistor NA2 and the power supply voltage VDD. Further, the timing control circuit 13 is a high withstand voltage depletion type at a time point (time t4 in FIG. 2) when the gate-source voltage of the low voltage NMOS transistor N2 rises and becomes equal to or higher than the threshold voltage of the low voltage NMOS transistor N2. The control signals IN2 and IN4 are generated so that the gate-source voltage of the NMOS transistor NA2 is lower than the sum of the threshold voltage of the high breakdown voltage depletion type NMOS transistor NA2 and the power supply voltage VDD.

  Similarly, the timing control circuit 12 includes the gate-source of the high breakdown voltage depletion type NMOS transistor NA1 when the voltage between the gate and source of the low breakdown voltage NMOS transistor N1 decreases and becomes lower than the threshold voltage of the low breakdown voltage NMOS transistor N1. The control signals IN1 and IN3 are generated so that the inter-voltage becomes lower than the sum of the threshold voltage of the high breakdown voltage depletion type NMOS transistor NA1 and the power supply voltage VDD. Further, the timing control circuit 12 generates a gate-source of the high breakdown voltage depletion type NMOS transistor NA1 when the voltage between the gate and source of the low breakdown voltage NMOS transistor N1 rises and becomes equal to or higher than the threshold voltage of the low breakdown voltage NMOS transistor N1. The control signals IN1 and IN3 are generated so that the inter-voltage becomes lower than the sum of the threshold voltage of the high breakdown voltage depletion type NMOS transistor NA1 and the power supply voltage VDD.

  As described above, the level shifter 1 according to the present embodiment controls the low breakdown voltage NMOS transistors N1 and N2 and the high breakdown voltage depletion type NMOS transistors NA1 and NA2 with different control signals, thereby reducing the low breakdown voltage NMOS transistor. The voltage exceeding the withstand voltage is not applied to N1 and N2. Thereby, deterioration of the low voltage NMOS transistors N1 and N2 is suppressed. That is, the level shifter 1 according to the present embodiment can realize high-speed operation without reducing reliability.

(First specific configuration example of the level shifter 1)
FIG. 3 is a diagram showing a first specific configuration example of the level shifter 1 as the level shifter 1a. In FIG. 3, the timing control circuit 12 includes a low breakdown voltage PMOS transistor (third PMOS transistor) P11, a low breakdown voltage NMOS transistor (third NMOS transistor) N11, and a resistance element (first resistance element) R1. The timing control circuit 13 includes a low breakdown voltage PMOS transistor (fourth PMOS transistor) P13, a low breakdown voltage NMOS transistor (fourth NMOS transistor) N13, and a resistance element (second resistance element) R2.

  In the timing control circuit 12, the low breakdown voltage PMOS transistor P11 and the low breakdown voltage NMOS transistor N11 are provided in series between the power supply voltage terminal VDD and the reference voltage terminal VSS, and an input signal IN is supplied to each gate. Yes. The resistance element R1 is provided between the low breakdown voltage PMOS transistor P11 and the low breakdown voltage NMOS transistor N11. Then, the timing control circuit 12 generates a voltage at a node between the low breakdown voltage PMOS transistor P11 and the resistance element R1 as a control signal IN3, and controls a voltage at the node between the low breakdown voltage NMOS transistor N11 and the resistance element R1. Generated as signal IN1. As a result, the timing control circuit 12 may generate a control signal IN1 having a smaller slew rate at the time of rising than the control signal IN3 and a control signal IN3 having a smaller slew rate at the time of falling than the control signal IN1. it can. The slew rate of the control signals IN1 and IN3 can be adjusted by adjusting the size of the low breakdown voltage PMOS transistor P11, the size of the low breakdown voltage NMOS transistor N11, and the resistance value of the resistance element R1.

  In the timing control circuit 13, the low breakdown voltage PMOS transistor P13 and the low breakdown voltage NMOS transistor N13 are provided in series between the power supply voltage terminal VDD and the reference voltage terminal VSS, and each gate has an inverted signal of the input signal IN. Have been supplied. The resistance element R2 is provided between the low breakdown voltage PMOS transistor P13 and the low breakdown voltage NMOS transistor N13. Then, the timing control circuit 13 generates a voltage at a node between the low breakdown voltage PMOS transistor P13 and the resistance element R2 as a control signal IN4, and controls a voltage at the node between the low breakdown voltage NMOS transistor N13 and the resistance element R2. Generated as signal IN2. As a result, the timing control circuit 13 may generate a control signal IN2 having a smaller slew rate at the time of rising than the control signal IN4 and a control signal IN4 having a smaller slew rate at the time of falling than the control signal IN2. it can. The slew rate of the control signals IN2 and IN4 can be adjusted by adjusting the size of the low breakdown voltage PMOS transistor P13, the size of the low breakdown voltage NMOS transistor N13, and the resistance value of the resistance element R2.

  The inverter INV1 includes a low breakdown voltage PMOS transistor P15 and a low breakdown voltage NMOS transistor N15. The low breakdown voltage PMOS transistor P15 and the low breakdown voltage NMOS transistor N15 are provided in series between the power supply voltage terminal VDD and the reference voltage terminal VSS. The inverter INV1 receives the input signal IN at the gates of the low breakdown voltage PMOS transistor P15 and the low breakdown voltage NMOS transistor N15, and inputs the voltage at the node between the low breakdown voltage PMOS transistor P15 and the low breakdown voltage NMOS transistor N15. Output as an inverted signal of IN.

  The other configuration of the level shifter 1a shown in FIG. 3 is the same as that of the level shifter 1 shown in FIG.

(First Modification of Level Shifter 1a)
FIG. 4 is a diagram showing a first modification of the level shifter 1a shown in FIG. 3 as a level shifter 1b. Compared with the timing control circuits 12 and 13 shown in FIG. 3, the timing control circuits 12 and 13 shown in FIG. 4 include transfer gates T1 and T2 as resistance elements R1 and R2.

  The transfer gate T1 includes a low breakdown voltage PMOS transistor P12 and a low breakdown voltage NMOS transistor N12. The transfer gate T2 includes a low breakdown voltage PMOS transistor P14 and a low breakdown voltage NMOS transistor N14. The other configuration of the level shifter 1b shown in FIG. 4 is the same as that of the level shifter 1a shown in FIG.

(Second Modification of Level Shifter 1a)
FIG. 5 is a diagram showing a second modification of the level shifter 1a shown in FIG. 3 as a level shifter 1c. Compared with the level shift unit 11 shown in FIG. 3, the level shift unit 11 shown in FIG. 5 further includes high breakdown voltage PMOS transistors P3 and P4.

  The high breakdown voltage PMOS transistor P3 is provided between the drain of the high breakdown voltage PMOS transistor P1 and the node LSDL, and a control signal IN3 is supplied to the gate thereof. The high voltage PMOS transistor P4 is provided between the drain of the high voltage PMOS transistor P2 and the node LSDR, and a control signal IN4 is supplied to the gate thereof. The other configuration of the level shifter 1c shown in FIG. 5 is the same as that of the level shifter 1a shown in FIG.

  The level shifter 1c shown in FIG. 5 can achieve the same effect as the level shifter 1a shown in FIG.

(Second specific configuration example of the level shifter 1)
FIG. 6 is a diagram illustrating a second specific configuration example of the level shifter 1 as the level shifter 1d. In FIG. 6, the timing control circuit 12 includes a low breakdown voltage PMOS transistor (third PMOS transistor) P21, a low breakdown voltage PMOS transistor (fourth PMOS transistor) P22, a low breakdown voltage NMOS transistor (third NMOS transistor) N21, and a low breakdown voltage NMOS transistor. (Fourth NMOS transistor) N22. The timing control circuit 13 includes a low breakdown voltage PMOS transistor (fifth PMOS transistor) P23, a low breakdown voltage PMOS transistor (sixth PMOS transistor) P24, a low breakdown voltage NMOS transistor (fifth NMOS transistor) N23, and a low breakdown voltage NMOS transistor (sixth NMOS transistor). ) N24.

  In the timing control circuit 12, a low voltage PMOS transistor P21 and a low voltage NMOS transistor N21 are provided in series between a power supply voltage terminal VDD and a reference voltage terminal VSS, and an input signal IN is supplied to each gate. Yes. The low breakdown voltage PMOS transistor P22 and the low breakdown voltage NMOS transistor N22 are provided in series between the power supply voltage terminal VDD and the reference voltage terminal VSS, and an inverted signal of the input signal IN is supplied to each gate. Then, the timing control circuit 12 generates the voltage of the node between the low voltage PMOS transistor P21 and the low voltage NMOS transistor N21 as the control signal IN1, and the node between the low voltage PMOS transistor P22 and the low voltage NMOS transistor N22. Is generated as the control signal IN3. Here, the driving capability of the low breakdown voltage PMOS transistor P21 is smaller than the driving capability of the low breakdown voltage PMOS transistor P22. On the other hand, the drive capability of the low voltage NMOS transistor N21 is greater than the drive capability of the low voltage NMOS transistor N22. As a result, the timing control circuit 12 may generate a control signal IN1 having a smaller slew rate at the time of rising than the control signal IN3 and a control signal IN3 having a smaller slew rate at the time of falling than the control signal IN1. it can. Note that the slew rates of the control signals IN1 and IN3 can be adjusted by adjusting the driving capabilities of the transistors P21, P22, N21, and N22.

  In the timing control circuit 13, a low voltage PMOS transistor P23 and a low voltage NMOS transistor N23 are provided in series between a power supply voltage terminal VDD and a reference voltage terminal VSS, and an input signal IN is supplied to each gate. Yes. The low breakdown voltage PMOS transistor P24 and the low breakdown voltage NMOS transistor N24 are provided in series between the power supply voltage terminal VDD and the reference voltage terminal VSS, and an inverted signal of the input signal IN is supplied to each gate. Then, the timing control circuit 13 generates a voltage at a node between the low breakdown voltage PMOS transistor P23 and the low breakdown voltage NMOS transistor N23 as a control signal IN2, and a node between the low breakdown voltage PMOS transistor P24 and the low breakdown voltage NMOS transistor N24. Is generated as a control signal IN4. Here, the drive capability of the low breakdown voltage PMOS transistor P23 is smaller than the drive capability of the low breakdown voltage PMOS transistor P24. On the other hand, the drive capability of the low voltage NMOS transistor N23 is greater than the drive capability of the low voltage NMOS transistor N24. As a result, the timing control circuit 13 may generate a control signal IN2 having a smaller slew rate at the time of rising than the control signal IN4 and a control signal IN4 having a smaller slew rate at the time of falling than the control signal IN2. it can. Note that the slew rates of the control signals IN2 and IN4 can be adjusted by adjusting the driving capabilities of the transistors P23, P24, N23, and N24.

  The other configuration of the level shifter 1d shown in FIG. 6 is the same as that of the level shifter 1a shown in FIG.

  In the level shifter 1d shown in FIG. 6, each timing control circuit generates two different control signals from two inverters. Accordingly, the level shifter 1d shown in FIG. 6 can easily adjust the timing between the control signals IN1 and IN3 and the timing between the control signals IN2 and IN4.

(Modification of level shifter 1d)
FIG. 7 is a diagram showing a modification of the level shifter 1d shown in FIG. 6 as a level shifter 1e. The level shift unit 11 shown in FIG. 7 further includes high voltage PMOS transistors P3 and P4 as compared with the level shift unit 11 shown in FIG.

  The high breakdown voltage PMOS transistor P3 is provided between the drain of the high breakdown voltage PMOS transistor P1 and the node LSDL, and a control signal IN3 is supplied to the gate thereof. The high voltage PMOS transistor P4 is provided between the drain of the high voltage PMOS transistor P2 and the node LSDR, and a control signal IN4 is supplied to the gate thereof. The other configuration of the level shifter 1e shown in FIG. 7 is the same as that of the level shifter 1d shown in FIG.

  The level shifter 1e shown in FIG. 7 can achieve the same effect as the level shifter 1d shown in FIG.

<Embodiment 2>
FIG. 8 is a diagram of a configuration example of the level shifter 1f according to the second embodiment. Compared with the level shifter 1 shown in FIG. 1, the level shifter 1f shown in FIG. 8 includes only the timing control circuit 12 among the timing control circuits 12 and 13, and includes inverters INV2 and INV3 instead of the inverter INV1. The timing control circuit 12 and the inverters INV2 and INV3 constitute a timing control unit.

  The timing control circuit 12 is provided between the power supply voltage terminal VDD and the reference voltage terminal VSS, and generates control signals IN1 and IN3 corresponding to the inverted signal of the input signal IN. However, the control signals IN1 and IN3 are different signals.

  Inverters INV2 and INV3 have the same circuit configuration as inverter INV1, and output inverted signals of control signals IN1 and IN3 as control signals IN4 and IN2, respectively. Since the control signals IN1 and IN3 are different signals, it can be said that the control signals IN2 and IN4 are also different signals.

  That is, the timing control unit including the timing control circuit 12 and the inverters INV2 and INV3 is provided between the power supply voltage terminal VDD and the reference voltage terminal VSS, and controls the control signal IN1 corresponding to the inverted signal of the input signal IN and the control signal. A control signal IN3 different from IN1 is generated, and a control signal IN2 corresponding to the normal rotation signal of the input signal IN and a control signal IN4 different from the control signal IN2 are generated.

  For example, the timing control unit generates control signals IN1 and IN2 having a smaller slew rate at the time of rising than the control signals IN3 and IN4, and a control signal IN3 having a smaller slew rate at the time of falling than the control signals IN1 and IN2. , IN4. Accordingly, the on-resistances of the high breakdown voltage depletion type NMOS transistors NA1 and NA2 can be set to a predetermined value or more before the low breakdown voltage NMOS transistors N1 and N2 are turned off. Further, after the low breakdown voltage NMOS transistors N1 and N2 are turned on, the on resistances of the high breakdown voltage depletion type NMOS transistors NA1 and NA2 can be set to a predetermined value or more. As a result, it is possible to prevent a voltage exceeding the breakdown voltage from being applied to the low breakdown voltage NMOS transistors N1 and N2.

  The operation of the level shifter 1f shown in FIG. 8 is the same as that of the level shifter 1 shown in FIG.

  The level shifter according to the present embodiment can achieve the same effects as the level shifter according to the first embodiment.

(First specific configuration example of the level shifter 1f)
FIG. 9 is a diagram illustrating a first specific configuration example of the level shifter 1f as the level shifter 1g. In FIG. 9, the timing control circuit 12 includes a low breakdown voltage PMOS transistor P11, a low breakdown voltage NMOS transistor N11, and a resistance element R1. The specific connection relationship is the same as that of the timing control circuit 12 shown in FIG. The resistance element R1 may be a transfer gate or the like.

(Second specific configuration example of the level shifter 1f)
FIG. 10 is a diagram illustrating a second specific configuration example of the level shifter 1f as the level shifter 1h. In FIG. 10, the timing control circuit 12 includes a low breakdown voltage PMOS transistor P21, a low breakdown voltage PMOS transistor P22, a low breakdown voltage NMOS transistor N21, and a low breakdown voltage NMOS transistor N22. The specific connection relationship is the same as that of the timing control circuit 12 shown in FIG.

As described above, the level shifter according to the above embodiment controls the conduction state of the low breakdown voltage NMOS transistor and the high breakdown voltage depletion type NMOS transistor using different control signals, thereby increasing the breakdown voltage of the low breakdown voltage NMOS transistor. The voltage exceeding is not applied. Thereby, deterioration of the low breakdown voltage NMOS transistor is suppressed. Thereby, the level shifter according to the above embodiment can realize high-speed operation without deteriorating reliability.

As described above, the level shifter 1 according to the present embodiment controls the low breakdown voltage NMOS transistors N1 and N2 and the high breakdown voltage depletion type NMOS transistors NA1 and NA2 with different control signals, thereby reducing the low breakdown voltage NMOS transistor. The voltage exceeding the withstand voltage is not applied to N1 and N2. Thereby, deterioration of the low voltage NMOS transistors N1 and N2 is suppressed. That is, the level shifter 1 according to the present embodiment can realize high-speed operation without reducing reliability.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

1 level shifter 1a to 1h level shifter 11 level shift unit 12, 13 timing control circuit INV1 to INV3 inverter P1 to P4 high breakdown voltage PMOS transistor N1, N2 low breakdown voltage NMOS transistor NA1, NA2 high breakdown voltage depletion type NMOS transistor P11 to P15 low breakdown voltage PMOS Transistors N11 to N15 Low breakdown voltage NMOS transistors P21 to P24 Low breakdown voltage PMOS transistors N21 to N24 Low breakdown voltage NMOS transistors R1, R2 Resistance elements

Claims (15)

First and second MOS transistors provided in parallel between a first power supply voltage terminal and a reference voltage terminal, each gate being connected to each other's drain;
Third and fourth MOS transistors provided between the first and second MOS transistors and the reference voltage terminal, respectively, and supplied with first and second control signals to the respective gates;
Fifth and sixth MOS transistors, which are provided between the third and fourth MOS transistors and the reference voltage terminal, respectively, and third and fourth control signals are supplied to the respective gates;
The first to fourth control signals are switched between a predetermined high level and a predetermined low level, respectively, and conduction between the first MOS transistor and the reference voltage terminal, and between the second MOS transistor and the reference voltage terminal. Controls non-conducting switching,
In the transition from conduction to non-conduction between the first MOS transistor and the reference voltage terminal, the first control signal becomes a predetermined low level earlier than the third control signal becomes a predetermined low level.
In the transition from conduction to non-conduction between the second MOS transistor and the reference voltage terminal, the second control signal becomes a predetermined low level earlier than the fourth control signal becomes a predetermined low level.
A level shifter in which the gate oxide film thickness of the fifth and sixth MOS transistors is thinner than the gate oxide film thickness of the first to fourth MOS transistors. In the transition from non-conduction to conduction between the first MOS transistor and the reference voltage terminal, the third control signal is at a predetermined high level earlier than the first control signal is at a predetermined high level.
In the transition from non-conduction to conduction between the second MOS transistor and the reference voltage terminal, the fourth control signal is at a predetermined high level earlier than the second control signal is at a predetermined high level.
The level shifter according to claim 1. Provided between the second power supply voltage terminal supplied with the second power supply voltage lower than the first power supply voltage supplied to the first power supply voltage terminal and the reference voltage terminal, and corresponds to the inverted signal of the input signal. Generating the third control signal different from the first control signal and the first control signal, and different from the second control signal and the second control signal corresponding to the normal rotation signal of the input signal A timing control unit for generating a fourth control signal;
The level shifter according to claim 2. The first and second MOS transistors are PMOS transistors, the third and fourth MOS transistors are depletion type NMOS transistors, and the fifth and sixth MOS transistors are NMOS transistors;
The level shifter according to claim 3. The timing controller is
The gate-source voltage of the third MOS transistor at the time when the gate-source voltage of the fifth MOS transistor decreases and becomes lower than the threshold voltage of the fifth MOS transistor is equal to the threshold voltage of the third MOS transistor and the second MOS transistor. The gate-source voltage of the third MOS transistor at a time when the gate-source voltage of the fifth MOS transistor rises and becomes equal to or higher than the threshold voltage of the fifth MOS transistor so as to be lower than the sum of the power supply voltage. Generating the first and third control signals so as to be lower than the sum of the threshold voltage of the third MOS transistor and the second power supply voltage,
The gate-source voltage of the fourth MOS transistor at the time when the gate-source voltage of the sixth MOS transistor decreases and becomes lower than the threshold voltage of the sixth MOS transistor is the threshold voltage of the fourth MOS transistor and the second MOS transistor. The voltage between the gate and the source of the fourth MOS transistor when the voltage between the gate and the source of the sixth MOS transistor rises and becomes equal to or higher than the threshold voltage of the sixth MOS transistor so as to be lower than the sum with the power supply voltage. 4. The level shifter according to claim 3, wherein the second and fourth control signals are generated such that the second control signal is lower than a sum of a threshold voltage of the fourth MOS transistor and the second power supply voltage. The timing controller is
A first timing control circuit for generating the first and third control signals;
A second timing control circuit for generating the second and fourth control signals,
The first timing control circuit includes:
Seventh and eighth MOS transistors provided in series between the second power supply voltage terminal and the reference voltage terminal, and supplied with the input signal to the respective gates;
A first resistance element provided between the seventh and eighth MOS transistors,
The second timing control circuit includes:
Ninth and tenth MOS transistors, which are provided in series between the second power supply voltage terminal and the reference voltage terminal, and are supplied with an inverted signal of the input signal at their gates,
A second resistance element provided between the ninth and tenth MOS transistors,
The first timing control circuit generates a voltage of a node between the seventh MOS transistor and the first resistance element as the third control signal, and a node between the eighth MOS transistor and the first resistance element. Is generated as the first control signal,
The second timing control circuit generates a voltage of a node between the ninth MOS transistor and the second resistance element as the fourth control signal, and between the tenth MOS transistor and the second resistance element. The voltage of the node is generated as the second control signal,
The gate oxide film thickness of the seventh to tenth MOS transistors is thinner than the gate oxide film of the first to fourth MOS transistors.
The level shifter according to claim 3. The seventh and ninth MOS transistors are PMOS transistors, and the eighth and tenth MOS transistors are NMOS transistors.
The level shifter according to claim 6. Each of the first and second resistance elements is a transfer gate constituted by a PMOS transistor and an NMOS transistor having a gate oxide film thickness smaller than that of the first to fourth MOS transistors.
The level shifter according to claim 6. The timing controller is
A first timing control circuit for generating the first and third control signals;
A second timing control circuit for generating the second and fourth control signals,
The first timing control circuit includes:
Seventh and eighth MOS transistors provided in series between the second power supply voltage terminal and the reference voltage terminal, and supplied with the input signal to the respective gates;
Ninth and tenth MOS transistors provided in series between the second power supply voltage terminal and the reference voltage terminal and supplied with the input signal to the respective gates;
The second timing control circuit includes:
Eleventh and twelfth MOS transistors, which are provided in series between the second power supply voltage terminal and the reference voltage terminal, and are supplied with an inverted signal of the input signal at their gates;
A thirteenth and a fourteenth MOS transistor provided in series between the second power supply voltage terminal and the reference voltage terminal, and supplied with an inverted signal of the input signal at each gate;
The drive capability of the seventh MOS transistor is smaller than the drive capability of the ninth MOS transistor, the drive capability of the eighth MOS transistor is greater than the drive capability of the tenth MOS transistor,
The driving capability of the eleventh MOS transistor is smaller than the driving capability of the thirteenth MOS transistor, the driving capability of the twelfth MOS transistor is larger than the driving capability of the fourteenth MOS transistor,
The first timing control circuit generates a voltage at a node between the seventh MOS transistor and the eighth MOS transistor as the first control signal, and a node between the ninth MOS transistor and the tenth MOS transistor. Is generated as the third control signal,
The second timing control circuit generates a voltage at a node between the eleventh MOS transistor and the twelfth MOS transistor as the second control signal, and a node between the thirteenth MOS transistor and the fourteenth MOS transistor. Is generated as the fourth control signal,
The gate oxide film thickness of the seventh to fourteenth MOS transistors is thinner than the gate oxide film of the first to fourth MOS transistors.
The level shifter according to claim 3. The seventh, ninth, eleventh and thirteenth MOS transistors are PMOS transistors, and the eighth, tenth, twelfth and fourteenth MOS transistors are NMOS transistors.
The level shifter according to claim 9. The timing controller is
Seventh and eighth MOS transistors provided in series between the second power supply voltage terminal and the reference voltage terminal, and supplied with the input signal to the respective gates;
A first resistance element provided between the seventh and eighth MOS transistors,
The timing controller generates a voltage at a node between the seventh MOS transistor and the first resistance element as the third control signal, and a voltage at a node between the eighth MOS transistor and the first resistance element. Is generated as the first control signal, an inverted signal of the third control signal is generated as the second control signal, an inverted signal of the first control signal is generated as the fourth control signal,
The gate oxide film thickness of the seventh and eighth MOS transistors is thinner than the gate oxide film of the first to fourth MOS transistors,
The level shifter according to claim 3. The seventh MOS transistor is a PMOS transistor, and the eighth MOS transistor is an NMOS transistor;
The level shifter according to claim 11. The first resistance element is a transfer gate composed of a PMOS transistor and an NMOS transistor having a gate oxide film thickness smaller than that of the first to fourth MOS transistors.
The level shifter according to claim 11. The timing controller is
Seventh and eighth MOS transistors provided in series between the second power supply voltage terminal and the reference voltage terminal, and supplied with the input signal to the respective gates;
Ninth and tenth MOS transistors provided in series between the second power supply voltage terminal and the reference voltage terminal and supplied with the input signal to the respective gates;
The drive capability of the seventh MOS transistor is smaller than the drive capability of the ninth MOS transistor, the drive capability of the eighth MOS transistor is greater than the drive capability of the tenth MOS transistor,
The timing control unit generates a voltage at a node between the seventh MOS transistor and the eighth MOS transistor as the first control signal, and generates a voltage at a node between the ninth MOS transistor and the tenth MOS transistor. Generating as a third control signal, generating an inverted signal of the first control signal as the fourth control signal, generating an inverted signal of the third control signal as the second control signal,
The gate oxide film thickness of the seventh to tenth MOS transistors is thinner than the gate oxide film of the first to fourth MOS transistors.
The level shifter according to claim 3. The seventh and ninth MOS transistors are PMOS transistors, and the eighth and tenth MOS transistors are NMOS transistors.
The level shifter according to claim 14.

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