JP2018032973A - Semiconductor integrated circuit and method of operating the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily check the state of a resistance change element.SOLUTION: A semiconductor integrated circuit includes a crossbar switch circuit, and a determination circuit 102 which measures the electric potential of a data output side wiring of a reconfigurable circuit including the crossbar switch circuit, compares the measured electric potential with a predetermined electric potential threshold, and, on the basis of the result of the comparison, determines a failure of the crossbar switch circuit targeted in the reconfigurable circuit.SELECTED DRAWING: Figure 23

Description

  The present invention relates to a semiconductor integrated circuit and an operation method thereof.

  Reconfigurable circuits (programmable logic integrated circuits) such as field-programmable gate arrays (FPGAs) rewrite the memory that stores the operation of the logic operation circuit and the connection of the logic operation circuit, so that the logic operation can be performed even after manufacturing. The wiring connection can be changed. As the memory element, an SRAM (Static Random Access Memory) cell, an antifuse, a floating gate MOS (Metal Oxide Semiconductor) transistor, or the like is used. However, since it is formed in the same layer as the transistor, the chip area is increased, resulting in an increase in manufacturing cost, a decrease in circuit operation speed, and an increase in operating power. Thus, a reconfigurable circuit using a resistance change element that can be formed in a wiring layer has been proposed (see, for example, Non-Patent Document 1, Patent Documents 1 and 2).

  As shown in FIG. 1A, the resistance change element (RE) includes a first wiring layer (T1), a second wiring layer (T2), a first wiring layer, and a second wiring layer. And a solid electrolyte material (IC) formed between the two. FIG. 1B is a diagram showing a symbolic expression of the variable resistance element shown in FIG. As shown in FIG. 1C, the resistance value can be changed by applying a forward bias set voltage (VSET) or a reverse bias reset voltage (VRST) to both ends of the variable resistance element. The ratio of the low resistance state (ON state) to the high resistance state (OFF state) is 10 to the fifth power or more. For this reason, the resistance change element described above functions as a switch unit that can electrically connect or disconnect between two wirings.

  In addition, when the variable resistance element is used for switching, a complementary (1T2R) switch cell structure using one transistor and two pairs of variable resistance elements has been proposed (see, for example, Patent Documents 3 and 4). .) FIG. 1D is a diagram illustrating an example of a switch cell having a 1T2R structure. In the 1T2R switch cell shown in FIG. 1D, one terminal of the first variable resistance element, one terminal of the second variable resistance element, and the drain terminal of the transistor are connected. The first resistance change element and the second resistance change element are atom transfer type elements using an ion conductive layer. Further, as shown in FIG. 2, the switch cell having the 1T2R structure is disposed in the vicinity of the intersection of the orthogonal signal lines, and is used for switching the signal path as a crossbar switch circuit. For this reason, as shown in FIG. 3, in the reconfigurable circuit, it is used when a functional block for switching between logic blocks or switching a signal path is mounted. Note that a logic block of a certain scale and a functional block for switching the connection to the logic block and a signal path in the vicinity thereof are regarded as one logic element (LE). Logic elements are arranged in tiles and connected together to achieve a larger scale reconfigurable circuit.

  As shown in FIG. 4, an address decoder and a read / write driver circuit for writing resistance change elements in the switch cells and checking the state after writing are arranged around the LEs arranged in a tile shape. Connected. As shown in FIGS. 5 and 6, by applying a write voltage from the driver to the variable resistance elements (RE1, RE2) in a certain switch, the variable resistance element is changed from a high (low) resistance state to a low (high) ) Change to the resistance state. The operation of turning on / off each switch cell existing in the crossbar switch circuit based on a switch pattern that can realize a desired data path is called a configuration operation (write operation) of the reconfigurable circuit.

  After the configuration operation, the state written in the variable resistance element is nonvolatile, and the state is maintained under a voltage equal to or lower than the set voltage (VSET) or the reset voltage (VRST). At an application operating voltage (VDD, where VDD <| VSET | or VDD <| VRST |), data (signal) processing is executed through a desired path as shown in FIG. The operation of transmitting a signal and processing data according to the switch state (pattern) written by the configuration operation is called an application operation of the reconfigurable circuit.

Japanese Patent No. 4356542 International Publication No. 2012/043502 International Publication No. 2013/190742 International Publication No. 2014/030393

M. Miyamura, et al., “First demonstration of logic mapping on nonvolatile programmable cell using complimentary atom switch,” I. IEDMT.

  When the circuit scale of the reconfigurable circuit becomes large and becomes equal to or more than 100,000 gates corresponding to logic gates, the number of resistance change elements used exceeds 1 mega. For this reason, after the configuration operation, there is a bit that changes from the ON state to the OFF state in the variable resistance element in the reconfigurable circuit if it is held in a long-term or high-temperature environment or the application operation is continued. Occurs (holding failure). As a result, as shown in FIG. 8, signal transmission is not performed at the switch location where the retention failure has occurred, and signal processing is not normally performed.

  It is desirable to periodically check the state of the resistance change element so that the application operation is not performed in a state where the holding failure has occurred. However, in order to check the state of a given variable resistance element, care must be taken that all signal states on the associated path do not change before and after the check. For this reason, there is a problem that processing for stopping / restarting the application operation is complicated and time overhead is increased, and the response (real time) of the signal is lowered. On the other hand, as shown in FIG. 9, since the voltage / current driver for reading the state of the resistance change element and the driving force of the buffer that outputs a signal to the crossbar switch circuit are batting, the resistance in parallel with the application operation There is a problem that it is difficult to read the state of the change element.

  An object of the present invention is to provide a semiconductor integrated circuit and an operation method thereof that solve the above-described problems.

The semiconductor integrated circuit of the present invention is
A crossbar switch circuit;
The potential of the data output side wiring of the reconfigurable circuit including the crossbar switch circuit is measured, and the measured potential is compared with a predetermined potential threshold. Based on the result of the comparison, the reconfigurable circuit And a determination circuit for determining a defect of the crossbar switch circuit to be subjected to the above.
Further, the operation method of the semiconductor integrated circuit of the present invention is as follows.
The potential of the data output side wiring of the reconfigurable circuit including the crossbar switch circuit is measured, the measured potential is compared with a predetermined potential threshold, and the reconfigurable circuit in the reconfigurable circuit is compared based on the comparison result. A determination circuit that determines a defect in the target crossbar switch circuit is operated during the application operation of the reconfigurable circuit to which the application voltage is applied.

  As described above, in the present invention, the state of the resistance change element can be easily confirmed.

It is a figure which shows an example of the structure of a resistance value element. It is a figure which shows the symbolic expression of the resistance value element shown to Fig.1 (a). It is a figure which shows an example of the operation | movement method for changing the resistance value of the resistance value element shown to Fig.1 (a). It is a figure which shows an example of the switch cell comprised from two resistance value elements and a transistor. It is a figure which shows an example of the crossbar switch circuit by which the switch cell is arrange | positioned at the signal intersection. It is a figure which shows an example of the basic composition (functional block) of a reconfigurable circuit. It is a figure which shows an example of the reconfigurable circuit containing the write circuit of a switch cell. It is a figure which shows an example of the writing method of the resistance change element (RE1) of a switch cell. It is a figure which shows an example of the write-in method of the resistance change element (RE2) of a switch cell. It is a figure which shows an example of the signal transmission (application operation | movement) in the crossbar switch in which the ON / OFF switch pattern was written by the configuration. It is a figure which shows an example of signal transmission failure and generation | occurrence | production of a floating node by generation | occurrence | production of the retention defect bit which changed from ON to OFF. An example of driving force batting between a voltage / current driver for reading the state of the resistance change element and a buffer for outputting a signal to the crossbar switch circuit by simultaneously executing the application operation and the state of reading the state of the resistance change element. FIG. It is a figure which shows an example of the data output side wiring (RH) of a crossbar switch, and a driving force determination circuit. It is a figure which shows an example of the internal structure of the driving force determination circuit shown in FIG. It is a figure which shows an example of the operation | movement method of the driving force determination circuit shown in FIG. 10 (when holding | maintenance defect does not generate | occur | produce). It is a figure which shows an example of the floating state generation | occurrence | production of RH [m '] node by generation | occurrence | production of a holding defect. It is a figure which shows an example of the operation | movement method of the driving force determination circuit shown in FIG. 10 (when the holding defect has generate | occur | produced). It is a figure which shows an example of the cyclic | annular check of whether the maintenance defect has generate | occur | produced. It is a flowchart for demonstrating an example of the operation | movement flow at the time of a patrol check. It is a figure which shows an example of the prohibition state of the driving force determination check operation before and after signal transition. It is a flowchart for demonstrating an example of the operation | movement flow until the position identification of a defect occurrence bit after a holding defect generation | occurrence | production detection and repair. It is a figure which shows the other example of the internal structure of the driving force determination circuit shown in FIG. FIG. 12 is a diagram illustrating an example of an operation method of the driving force determination circuit illustrated in FIG. 11 (when no holding failure occurs). 12 is a flowchart for explaining an operation method of the driving force determination circuit shown in FIG. 11. It is a figure for demonstrating the change of the gating area | region information of a clock, and a cyclic | annular check condition. It is a figure which shows other embodiment of the semiconductor integrated circuit of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  As the variable resistance element (shown in FIG. 1A) used in the switch cell in this embodiment, ReRAM (Resistance Random Access Memory) using a transition metal oxide or NanoBridge (registered trademark) using an ionic conductor. ), Etc., as long as it is a resistance change element that changes and is held by applying a voltage of a certain level or more for a predetermined time or more. In addition, from the viewpoint of high disturbance resistance when the signal is continuously passed through and used, the resistance change element has a polarity in the direction of voltage application for resistance change, as shown in FIG. Such a bipolar variable resistance element. Furthermore, the resistance change element is a bipolar resistance change element, two are connected in series so that the resistance change polarity is opposite, and a switch (transistor) is arranged at a connection point of the two switches. A configuration as shown in FIG. 1D is more desirable. In the switch cell shown in FIG. 1D, the two resistance change elements can be programmed to a low resistance state (ON state) or a high resistance state (OFF state).

  A crossbar switch circuit for switching signal paths is configured using switch cells. In the crossbar switch circuit, a switch cell is disposed in the vicinity of a cross point between the signal wiring (RV) and the signal wiring (RH) orthogonal thereto. When the switch cell shown in FIG. 1D is used, the electrode TR1 on the side not shared between the resistance change elements of the two resistance change elements (RE [1], RE [2]) as shown in FIG. And TR2 respectively. By changing the state of the resistance change element in each switch cell, the RV signal line in the crossbar switch is electrically connected to an arbitrary RH signal line, and a signal can be transmitted.

  A reconfigurable circuit having at least a logic block and a routing connection block includes at least the crossbar switch circuit described above as shown in FIG. The reconfigurable circuit can execute desired signal processing according to the switch pattern by rewriting the switch in the crossbar switch circuit. The memory inside the logic block may be mounted with a crossbar switch circuit. In this case, the two input signal lines of the crossbar switch circuit are connected to the operating voltage (VDD) or GND. Further, the reconfigurable circuit includes an address decoder for accessing each resistance change element, in addition to a logic block and a routing connection block for performing signal processing, as shown in FIG. It includes at least a driver for supplying a write current / voltage.

  In the switch cell shown in FIG. 1D, a voltage / current is applied to each variable resistance element as shown in FIG. 5 and FIG. State) and a low resistance state (set state), and the switch cell is turned on / off. The operation of turning on and off each switch cell existing in the crossbar switch circuit so as to achieve a switch pattern that realizes a desired data transmission path is referred to as a configuration operation (write operation) of the reconfigurable circuit. To do.

  The state written to the variable resistance element after the configuration operation is maintained under a voltage equal to or lower than the set voltage (VSET) or the reset voltage (VRST). Therefore, at the subsequent application operating voltage (VDD, where VDD <| VSET | or VDD <| VRST |), data (signal) is processed through a desired path as shown in FIG. The operation of transmitting data and processing data according to the switch state (pattern) written by the configuration operation will be referred to as an application operation of the reconfigurable circuit.

  Transistors for connecting / disconnecting between the write driver and the crossbar switch circuit and connecting / disconnecting between the signal transmission buffer between the logic blocks and the crossbar switch circuit are arranged around each crossbar switch. At least a switching element is arranged and connected. Each switch is opened and closed during the configuration operation and during the application operation (FIGS. 5 to 7).

  Of the two terminals of the above-described transistor switch that is rendered conductive by the configuration operation as shown in FIG. 5, the terminal that is not connected to the wiring in the crossbar switch, or electrically described above via a decode circuit. A driving force determination circuit (driving force determination circuit 100) is connected to a node having the same potential as the terminal as shown in FIG. In the driving force determination circuit 100, a driving circuit (output buffer for the signal IN [n]) for pulling up to the VDD potential that is an application operating voltage or pulling down to the GND potential is a node (RH [m] ]) Is electrically connected via a switch element to determine whether the potential level of the target node is normally VDD or GND.

  As shown in FIG. 11, the driving force determination circuit 100 includes a precharge circuit 120, a potential measurement unit 130 that is a voltage monitor circuit, connection changeover switches (SW1 and SW2), and a control circuit that controls the operation timings thereof. It is sufficient that at least the control unit 110 is included. As shown in FIG. 12, the driving force determination circuit 100 accesses the node to be evaluated while precharging the node with a certain intermediate potential between VDD and GND using the precharge circuit 120. The precharge circuit 120 drives the potential of the data output side wiring to a predetermined potential and sets it to a high impedance state after driving. The intermediate potential of the precharge circuit 120 is preferably VDD / 2. At the same time that SW1 is turned off, the switch SW [m] is turned on, and the voltage level measured by the potential measuring unit 130 is evaluated. The potential measuring unit 130 measures the potential of the data output side wiring. The control unit 110 has a predetermined potential threshold (Vth_low: second potential) nearer to the GND potential than the predetermined potential threshold (Vth_high: first potential threshold) near the VDD potential. It is determined whether it is lower than (potential threshold). When the observation potential of the potential measurement unit 130 is a predetermined potential close to the VDD potential or a predetermined potential close to the GND potential, the control unit 110 determines that the evaluation target node (RH [m]) of the crossbar is defective in holding. It is determined that the input signal circuit (the drive circuit, the output buffer for the IN [n] signal in FIG. 10) is normally connected via the switch cell having no connection. On the other hand, when the observation voltage of the potential measurement unit 130 is not higher than (Vth_high) or lower than (Vth_low), the control unit 110 determines that a holding failure has occurred as shown in FIGS. 13 and 14. judge. Vth_high is preferably between (VDD * 0.7 to VDD * 0.9), and Vth_low is preferably between (VDD * 0.1 to VDD * 0.3).

  The driving force determination circuit 100 has high impedance, and it is confirmed that the resistance change element does not change from the ON state to the OFF state (no holding failure occurs) without changing the signal state in the crossbar switch. Can be confirmed. Therefore, it is possible to check whether there is a holding failure without stopping the application operation in the holding failure check and performing recovery work after the check.

As shown in FIG. 15 and FIG. 16, the presence or absence of holding failure by the driving force determination circuit is automatically checked for the next different output signal line after confirming the normal operation of the output signal line with the crossbar. The operation may be performed. The control unit 110 turns on SW1, turns on SW2, turns off SW [m], and performs precharging (step S1). Subsequently, the control unit 110 turns off SW1, turns on SW2, turns on SW [m], and the potential measurement unit 130 measures the potential of the data output side wiring. The controller 110 determines whether the potential V measured by the potential measuring unit 130 is higher than Vth_high or lower than Vth_low (step S2). When the potential V measured by the potential measuring unit 130 is higher than Vth_high or lower than Vth_low, the driving force determination circuit 100 sets RH [m] to RH [m + 1] and performs a check operation on the next different output signal line. carry out. On the other hand, when the potential V measured by the potential measuring unit 130 is not higher than Vth_high and not lower than Vth_low, the control unit 110 determines that a holding failure has been detected in RH [m], and performs a rewrite operation ( Step S3).
However, as shown in FIG. 17, even during the application operation, the driving force determination circuit 100 does not execute the check operation before and after the timing at which the signal node inside the reconfigurable circuit transitions. Alternatively, even if the driving force determination circuit 100 performs the check operation, the check result obtained at that time is ignored. In the case of an application in which each data is latched by a flip-flop at the rising edge of the clock, the driving force determination circuit 100 may set a period during which the flip-flop setup / hold is violated as a check prohibition period.

  After the holding failure is detected, the switch cell having the holding failure may be repaired in the process flow shown in the flowchart of FIG. After detecting a holding failure (step S11), the application is stopped (step S12). The switch cells on the data line (RH [m ′]) where the defect is detected are sequentially accessed from n ′ = 0 in the same manner as the configuration operation, and a voltage lower than the Vset voltage is applied. The resistance value of each variable resistance element is read by monitoring the flowing current. One side (RE1) of the variable resistance element is read in the switch cell (step S13), and then the resistance value on the opposite side (RE2) is read (step S14). The defective switch location is identified from the state mismatch between RE1 and RE2 (steps S15 and S16), and the set operation is performed on RE1 and RE2 of the defective switch cell [n ′, m ′] (transition from high resistance to low resistance state) The defective cell may be repaired (step S17). This eliminates the need to read the switch pattern data for configuration of the reconfigurable circuit from the outside of the reconfigurable circuit.

  As shown in FIG. 19, the determination circuit may further include a steady voltage source / current monitor circuit. As shown in FIG. 19, the driving force determination circuit 101 includes a precharge circuit 121, a potential measurement unit 131 that is a voltage monitor circuit, connection switching switches (SW1, SW2, and SW3), and a current measurement that is a current monitor circuit. It suffices to include at least the unit 141 and the control unit 111 that is a control circuit that controls the operation timing of the unit 141.

Also, as shown in FIGS. 20 and 21, an output level corresponding to the potential measured by the potential measuring unit 131 is set. The control unit 111 turns on SW1, turns on SW2, turns off SW3, turns off SW [m], and performs precharging (step S21). Subsequently, the control unit 111 turns off SW1, turns on SW2, turns off SW3, turns on SW [m], and the potential measurement unit 131 measures the potential of the data output side wiring. The control unit 111 determines whether the potential V measured by the potential measurement unit 131 is higher than Vth_high or lower than Vth_low (step S22). When the potential V measured by the potential measuring unit 130 is higher than Vth_high, the output level of the power supply circuit is set to VDD-dV (step S23). When the potential V measured by the potential measuring unit 130 is lower than Vth_low, the output level of the power supply circuit is set to dV (step S24).
Thereafter, the control unit 111 turns off SW1, turns off SW2, turns on SW3, turns on SW [m], and the current measuring unit 141 measures the current flowing through the data output side wiring. The control unit 111 determines whether or not the absolute value | Is | of the current value measured by the current measurement unit 141 is larger than Ith (step S25). When the absolute value | Is | of the current value measured by the current measuring unit 141 is larger than Ith, the driving force determination circuit 101 sets RH [m] to RH [m + 1] and performs a check operation on the next different output signal line. To implement. On the other hand, when the absolute value | Is | of the current value measured by the current measuring unit 141 is not larger than Ith, the control unit 111 determines that a holding failure is detected in RH [m], and performs a rewrite operation ( Step S26). Thus, it is only necessary to generate a potential difference dV between the determination target node and the output node of the power supply circuit and to monitor the current value flowing at that time. The driving force determination circuit 101 confirms that the current value is larger than the threshold value (Ith), and determines that the observation node is connected to the input signal circuit (driving circuit) via a switch cell having a sufficiently low resistance. You may do it. Although a signal is passed, it is possible to detect a defective switch cell that impedes transmission delay. The current threshold (Ith) is preferably between 100 uA and 0.1 uA.

  The reconfigurable circuit may have a gating circuit for clock control. In this case, the clock signal introduced into the logic element can be gated in units of each logic element or a certain logic element. As shown in FIG. 22, when checking the crossbar switch cell in the logic element of the gating area based on the gating information from the gating controller, the check prohibition section is not set as shown in FIG. A check operation may be performed. That is, the check conditions may be changed according to the state of the logic cell to be inspected.

Example 1
As the variable resistance element used in the switch cell as shown in FIGS. 1A to 1D, NanoBridge (registered trademark) using an ion conductor is used. As shown in FIG. 1C, the resistance change state of the variable resistance element is changed and maintained by applying a voltage of a certain level or higher for a predetermined time or longer. The resistance change element is a bipolar type having a polarity in the direction of application of a voltage for changing resistance. Further, the ratio of the low resistance state (ON state) to the high resistance state (OFF state) of the variable resistance element is 10 to the fifth power or more. In the switch cell, as shown in FIG. 1D, two bipolar variable resistance elements are connected in series to face each other, and a transistor is arranged (connected) at the connection point of the two switches.

  A crossbar switch circuit for switching signal paths is configured using the above-described switch cell. As shown in FIG. 2, in the crossbar switch circuit, a switch cell is arranged in the vicinity of a cross point between a signal wiring (RV) and a signal wiring (RH) orthogonal thereto, and two resistance change elements (RE [1] ], RE [2]) are connected to the electrodes TR1 and TR2 on the side not shared between the variable resistance elements. By changing the state of the resistance change element in each switch cell, the RV signal line in the crossbar switch is electrically connected to an arbitrary RH signal line and can transmit a signal.

  The reconfigurable circuit based on the logic block and the routing / connection block includes the crossbar switch circuit described above as shown in FIG. By rewriting the switch in the crossbar switch circuit, desired signal propagation according to the switch pattern can be executed and signal processing can be performed. In order to rewrite the switch, as shown in FIG. 4, in addition to the logic block for performing signal processing and the routing / connection block, an address decoder for accessing each resistance change element, and a driver circuit for supplying current / voltage Have

  Using the address decoder and the write driver, each resistance change element is set to a high resistance state (reset state) and a low resistance state (set state) as shown in FIGS. The operation from the high resistance state to the low resistance state is called a set operation, and the operation from the low resistance state to the high resistance state is called a reset operation. In addition, an operation of turning on and off each switch cell existing in the crossbar so as to obtain a switch pattern that realizes a desired data transmission path is a configuration operation (write operation) of the reconfigurable circuit.

  The state written to the variable resistance element after the configuration operation is maintained under a voltage equal to or lower than the set voltage (VSET) or the reset voltage (VRST). At the subsequent application operating voltage (VDD, where VDD <| VSET | or VDD <| VRST |), data (signal) processing can be executed through a desired path as shown in FIG. An operation of transmitting a signal and processing data according to a switch state (pattern) written by the configuration operation is an application operation of the reconfigurable circuit.

  In addition, a switch element including transistors for connecting and disconnecting between the write driver and the crossbar switch circuit and between the signal transmission buffer and the crossbar switch circuit between the logic blocks is provided around each crossbar switch. Is arranged. 5-7, each switch opens and closes during configuration operation and application operation.

  Of the two terminals of the transistor switch that becomes conductive in the configuration operation shown in FIG. 5, the terminal that is not connected to the wiring in the crossbar switch, or the same electrical potential as the terminal described above electrically via the decode circuit As shown in FIG. 10, the driving force determination circuit 100 is connected to the node to be. In the driving power determination circuit 100, a driving circuit (output buffer for the signal IN [n]) for pulling up to the VDD potential that is the application operating voltage or pulling down to the GND potential is a node (RH [m]) to be determined. ) Is electrically connected via a switch element to determine whether the potential level of the target node is normally VDD or GND.

  As shown in FIG. 11, the driving force determination circuit 100 includes a precharge circuit 120, a potential measurement unit 130 that is a voltage monitor circuit, connection changeover switches (SW1 and SW2), and a control circuit that controls the operation timings thereof. And a control unit 110. As shown in FIG. 12, the SW1 is turned on, and the precharge circuit 120 is used to access the node to be evaluated while precharging the node at a certain intermediate potential (VDD / 2) between VDD and GND. Complete address decoding. Further, the node and the power supply monitor circuit are electrically connected by previously turning on SW2. Next, the switch SW [m] is turned on at the same time when the SW1 is turned off or at a slightly delayed timing. After a predetermined time has elapsed after opening and closing SW [m], control unit 110 evaluates the voltage level measured by potential measuring unit 130. The potential measured by the potential measuring unit 130 is higher than a predetermined potential close to the VDD potential (Vth_high = VDD * 0.9) or lower than a predetermined potential close to the GND potential (Vth_low = VDD * 0.1). In this case, the control unit 110 outputs the input signal circuit (driving circuit, IN [n] signal in FIG. 10) via the switch cell in which the evaluation target node (RH [m]) of the crossbar has no retention failure. Buffer)).

  On the other hand, when a holding failure occurs and the target node (RH [m ′]) is not normally connected to the input signal circuit (the output buffer of the signal IN [n ′]) as shown in FIG. Become. As shown in FIG. 14, since the node is not pulled up to VDD or pulled down to GND, the potential measured by the potential measuring unit 130 is not higher than (Vth_high), lower than (Vth_low), and there is a retention failure. It can be determined that it occurred.

  Since the driving force determination circuit 100 has high impedance, if the application operation is normally performed, all signal lines in the crossbar are driven so as to be electrically at the VDD or GND potential. Even when connected to the circuit 100, the signal state in the crossbar switch is not changed. Even if it fluctuates, it is not a continuous fluctuation that exceeds the inversion threshold of a CMOS (Complementary MOS) circuit that receives a signal in the subsequent stage as OUT [m], and erroneous data transmission does not occur. For this reason, it is possible to confirm that the resistance change element has not changed from the ON state to the OFF state, that is, no retention failure has occurred without causing erroneous data transmission. Therefore, it is possible to check whether there is a holding defect without stopping the operation of the application and performing recovery work after the check.

  As shown in FIG. 15 and FIG. 16, the driving force determination circuit 100 checks whether there is a holding defect and automatically checks the normal operation of the output signal line with the crossbar, and then automatically checks the next different output signal line. Perform check operation. However, as illustrated in FIG. 17, the driving force determination circuit 100 does not perform the check operation before and after the timing at which the signal node in the reconfigurable circuit transitions even during the application operation. Alternatively, even if the driving force determination circuit 100 performs the check operation, the check result obtained at that time is ignored. For example, in the case of an application in which each data is latched by a flip-flop at the rising edge of the clock, the driving power determination circuit 100 sets a period during which the flip-flop setup / hold is violated as a prohibited period for the check operation.

  FIG. 18 is a flowchart illustrating an example of the flow of processing after detection of a holding failure. After detecting a holding failure (step S11), the application is stopped (step S12). The switch cells on the data line (RH [m ′]) where the defect is detected are sequentially accessed from n ′ = 0 in the same manner as the configuration operation, and a voltage lower than the Vset voltage is applied. The resistance value of each variable resistance element is read by monitoring the flowing current. One side (RE1) of the variable resistance element is read in the switch cell (step S13), and then the resistance value on the opposite side (RE2) is read (step S14). A defective switch location is identified from the state mismatch between RE1 and RE2 (steps S15 and S16). The occurrence probability (F) of retention failure is on the order of several ppm / year even at 150 ° C. storage. For this reason, the probability that two resistance change elements in the same switch cell change from the low resistance state to the high resistance state at the same time due to poor holding is as low as FxF / 2 (= 10 to the 12th power), and RE1 and RE2 It can be determined that the switch cell in a high resistance state on only one side is a defective switch cell [n ′, m ′] in which the signal path is cut off. A set operation (returns from the high resistance to the low resistance state) is performed on RE1 and RE2 of the defective switch cell [n ′, m ′] to repair the defective cell (step S17). As a result, the application operation can be executed again. By identifying the defective switch location from the state mismatch between RE1 and RE2, the switch pattern data for configuration of the reconfigurable circuit need not be read again from outside the reconfigurable circuit and referenced.

(Example 2)
As shown in FIG. 19, the driving force determination circuit 101 includes a precharge circuit 121, a potential measurement unit 131 that is a voltage monitor circuit, connection switching switches (SW1, SW2, and SW3), and a current measurement that is a current monitor circuit. It suffices to include at least the unit 141 and the control unit 111 that is a control circuit that controls the operation timing of the unit 141. As shown in FIG. 20 and FIG. 21, the SW1 is turned on, and the precharge circuit 121 is used to precharge the node at a certain intermediate potential (VDD / 2) between VDD and GND, while accessing the node to be evaluated. To complete the address decoding. Further, the node and the power supply monitor circuit are electrically connected by previously turning on SW2. Next, the switch SW [m] is turned on at the same time when the SW1 is turned off or at a slightly delayed timing. After a predetermined time has elapsed after opening and closing SW [m], the control unit 111 determines the voltage level measured by the potential measurement unit 131. When the potential measured by the potential measuring unit 131 is higher than a predetermined potential close to the VDD potential (Vth_high = VDD * 0.9) or lower than a predetermined potential close to the GND potential (Vth_low = VDD * 0.1) The node to be evaluated (RH [m]) of the crossbar is electrically connected to the input signal circuit (driving circuit, output buffer for the IN [n] signal in FIG. 10) via a switch cell having no retention failure. It is determined that

  Next, when the potential measured by the potential measuring unit 131 is higher than Vth_high, the output level of the power supply circuit is set to VDD−dV (= VDD * 0.9), and when lower than Vth_low, the output level of the power supply circuit is set. Is set to dV (= VDD * 0.1). By returning SW2 to the OFF state and turning SW3 to the ON state, a potential difference dV (= 0.1V) is generated between the determination target node and the output node of the power supply circuit, and the current value flowing at that time is measured. The unit 141 measures. When the absolute value of the current value measured by the current measuring unit 141 is a value exceeding a threshold value (Ith), for example, 10 uA, the control unit 11 has a crossbar evaluation target node (RH [m]) of at least 10 kΩ or less. It is determined that the input signal circuit (drive circuit) is normally connected via a switch cell having a series resistance or less.

  On the other hand, when a retention failure occurs and the target node (RH [m ′]) is not normally connected to the input signal circuit (the output buffer of the signal IN [n ′]) as shown in FIG. Become. Therefore, since the node is not pulled up to VDD or pulled down to GND, the monitored voltage does not exceed (Vth_high) or falls below (Vth_low), and it can be determined that a holding failure has occurred.

  The change in the signal state in the crossbar switch is not a change exceeding the inversion threshold of the CMOS circuit that receives a signal in the subsequent stage as OUT [m], and no erroneous data transmission occurs. Therefore, it is possible to confirm that the resistance change element has not changed from the ON state to the OFF state, that is, no holding failure has occurred without causing erroneous sending. Therefore, it is possible to check whether there is a retention failure without stopping the operation of the application and performing recovery work after the check.

  The drive circuit described above can continuously apply the differential potential dV (= 0.1 V) within a range that does not cause erroneous data transmission. From the measured current value, it is possible to calculate the resistance value of the switch cell that connects between the input signal circuit (the output buffer of the signal IN [n ′]) and the target node (RH [m ′]). . Holding failure can be detected at the stage where the ON state shifts to the high resistance side (-10 kΩ) by a precursory phenomenon that transitions from the ON state (˜1 kΩ) to the OFF state (˜100 MΩ).

(Example 3)
The reconfigurable circuit includes a gating circuit for clock control, and can gate a clock signal introduced to the logic element in units of each logic element or a certain logic element. Thereby, the clock of the logic element which does not need to perform signal processing is stopped, and the power consumption of the reconfigurable circuit can be reduced. When checking the crossbar switch cell in the logic element of the gating area based on the gating information from the gating controller as shown in FIG. 22, the check operation is performed without setting the check prohibition section as shown in FIG. To implement.

  The present invention has the following effects. Without changing the signal state in the crossbar switch during the application operation, it can be appropriately confirmed that the resistance change element has not changed from the ON state to the OFF state, that is, no holding failure has occurred. For this reason, in the holding failure check, it is possible to avoid complicated processing for stopping and restarting the application operation, and there is no time overhead.

(Other embodiments)
FIG. 23 is a diagram showing another embodiment of the present invention. The semiconductor integrated circuit illustrated in FIG. 23 includes a crossbar switch circuit and a driving force determination circuit 102. The driving force determination circuit 102 measures the potential of the data output side wiring of the reconfigurable circuit including the crossbar switch circuit. The driving force determination circuit 102 compares the measured potential with a predetermined potential threshold value. Further, the driving force determination circuit 102 determines a defect of the target crossbar switch circuit in the reconfigurable circuit based on the comparison result.

  As described above, the potential of the data output side wiring of the reconfigurable circuit is measured, and the defect of the crossbar switch circuit is determined based on the measured voltage value, so that the state of the resistance change element can be easily confirmed. it can.

  The processing performed by each component provided in each of the driving force determination circuits 100 to 102 described above may be performed by a logic circuit that is produced according to the purpose. Further, a computer program (hereinafter referred to as a program) in which processing contents are described as a procedure is recorded on a recording medium readable by each of the driving force determination circuits 100 to 102, and the program recorded on the recording medium is determined as a driving force. The circuits 100 to 102 may be read and executed. Recording media that can be read by each of the driving force determination circuits 100 to 102 include a floppy (registered trademark) disk, a magneto-optical disk, a DVD (Digital Versatile Disc), a CD (Compact Disc), and a Blu-ray (registered trademark) Disc. In addition to a transferable recording medium such as the above, a ROM (Read Only Memory), a RAM (Random Access Memory), a HDD (Hard Disc Drive), or the like built in each of the driving force determination circuits 100 to 102 is indicated. The program recorded on the recording medium is read by a CPU (Central Processing Unit) provided in each of the driving force determination circuits 100 to 102, and the same processing as described above is performed under the control of the CPU. Here, the CPU operates as a computer that executes a program read from a recording medium on which the program is recorded.

A part or all of the above embodiment can be described as in the following supplementary notes, but is not limited thereto.
(Appendix 1) Crossbar switch circuit;
The potential of the data output side wiring of the reconfigurable circuit including the crossbar switch circuit is measured, and the measured potential is compared with a predetermined potential threshold. Based on the result of the comparison, the reconfigurable circuit A semiconductor integrated circuit having a determination circuit for determining a defect of a crossbar switch circuit to be subjected to
(Supplementary note 2) In Supplementary note 1, the determination circuit determines that the crossbar switch circuit is defective when the measured potential is equal to or less than a first potential threshold value and equal to or greater than a second threshold value. The semiconductor integrated circuit as described.
(Supplementary Note 3) The crossbar switch circuit is configured using a switch cell using a resistance change element,
The switch cell includes a first variable resistance element, a second variable resistance element, and at least one transistor that can be programmed to a low resistance state or a high resistance state, and one terminal of the first variable resistance element. The semiconductor integrated circuit according to appendix 2, wherein one terminal of the second variable resistance element and a drain terminal of the transistor are connected.
(Supplementary note 4) The semiconductor integrated circuit according to supplementary note 3, wherein the first resistance change element and the second resistance change element are bipolar resistance change elements, and are arranged so that resistance change polarities face each other. circuit.
(Supplementary Note 5) The determination circuit includes:
A precharge circuit for driving the potential of the data output side wiring to a predetermined potential to be in a high impedance state after driving;
The semiconductor integrated circuit according to any one of appendices 1 to 4, further comprising: a voltage monitor circuit that measures a potential of the data output side wiring.
(Appendix 6) The determination circuit measures the current value that flows at the time of application of the steady voltage, compares the measured current value with a predetermined current threshold value, and reconfigurable based on the result of the comparison 6. The semiconductor integrated circuit according to any one of appendices 1 to 5, wherein a defect of a target crossbar switch circuit in the circuit is determined.
(Supplementary note 7) An operation method for operating the determination circuit included in the semiconductor integrated circuit according to any one of supplementary notes 1 to 6 during an application operation of a reconfigurable circuit to which an application voltage is applied.
(Supplementary note 8) The operation method according to supplementary note 7, wherein the determination circuit is not operated before or after the signal of the wiring in the crossbar switch during application operation is changed, or the determination result in the determination circuit is ignored.
(Supplementary Note 9) When the semiconductor integrated circuit includes a clock gating circuit, the judgment condition of the judgment circuit is changed based on gating information from the clock gating circuit. How it works.
(Additional remark 10) The process which stops an application after a test | inspection node detects the error which is not electrically connected with the determination circuit which the semiconductor integrated circuit of any one of additional remark 1 to 6 has,
A process of measuring resistance values of two resistance change elements of the switch cell connected to the node that has detected the error;
A process of determining the switch cell as a defective cell when one of the two variable resistance elements is in a high resistance state and the other variable resistance element is in a low resistance state;
An operation method of performing a set operation on the determined defective cell so as to shift the two resistance change elements in the defective cell from a high resistance state to a low resistance state.
(Supplementary note 11) The semiconductor integrated circuit according to supplementary note 4, wherein the first variable resistance element and the second variable resistance element are atomic transfer type elements using an ion conductive layer.
(Supplementary Note 12) A potential measuring unit connected to the data output side wiring of the reconfigurable circuit including the crossbar switch circuit and measuring the potential of the wiring;
A control unit that compares the potential measured by the potential measurement unit with a preset value, and determines a defect of a target crossbar switch circuit in the reconfigurable circuit based on a result of the comparison; A determination circuit.

DESCRIPTION OF SYMBOLS 100,101 Driving force determination circuit 102 Determination circuit 110,111 Control part 120,121 Precharge circuit 130,131 Potential measurement part 141 Current measurement part

Claims (10)

A crossbar switch circuit;
The potential of the data output side wiring of the reconfigurable circuit including the crossbar switch circuit is measured, and the measured potential is compared with a predetermined potential threshold. Based on the result of the comparison, the reconfigurable circuit A semiconductor integrated circuit having a determination circuit for determining a defect of a crossbar switch circuit to be subjected to The semiconductor circuit according to claim 1,
The determination circuit is a semiconductor integrated circuit that determines that the crossbar switch circuit is defective when the measured potential is not more than a first potential threshold and not less than a second threshold. The semiconductor integrated circuit according to claim 2,
The crossbar switch circuit is configured using a switch cell using a resistance change element,
The switch cell includes a first variable resistance element, a second variable resistance element, and at least one transistor that can be programmed to a low resistance state or a high resistance state, and one terminal of the first variable resistance element. And a first terminal of the second variable resistance element and a drain terminal of the transistor. The semiconductor integrated circuit according to claim 3,
The first variable resistance element and the second variable resistance element are bipolar variable resistance elements, and are arranged so that resistance change polarities face each other. The semiconductor integrated circuit according to claim 1, wherein
The determination circuit includes:
A precharge circuit for driving the potential of the data output side wiring to a predetermined potential to be in a high impedance state after driving;
A semiconductor integrated circuit having a voltage monitor circuit for measuring a potential of the data output side wiring; The semiconductor integrated circuit according to any one of claims 1 to 5,
The determination circuit applies a steady voltage and measures a current value flowing at the time of application, compares the measured current value with a predetermined current threshold, and based on a result of the comparison, an object in the reconfigurable circuit The semiconductor integrated circuit which judges the defect of the crossbar switch circuit which becomes.   An operation method for operating the determination circuit included in the semiconductor integrated circuit according to claim 1 during an application operation of a reconfigurable circuit to which an application voltage is applied. The operation method according to claim 7,
An operation method in which the determination circuit is not operated before or after the signal of the wiring in the crossbar switch during application operation is changed, or the determination result in the determination circuit is ignored. The operating method according to claim 7 or claim 8,
When the semiconductor integrated circuit includes a clock gating circuit, an operation method for changing a determination condition of the determination circuit based on gating information from the clock gating circuit. A process of stopping an application after the inspection node detects an error that is not electrically connected to the determination circuit included in the semiconductor integrated circuit according to any one of claims 1 to 6,
A process of measuring resistance values of two resistance change elements of the switch cell connected to the node that has detected the error;
A process of determining the switch cell as a defective cell when one of the two variable resistance elements is in a high resistance state and the other variable resistance element is in a low resistance state;
An operation method of performing a set operation on the determined defective cell so as to shift the two resistance change elements in the defective cell from a high resistance state to a low resistance state.

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