JP2018031573A - Control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To access an EEPROM as normal as possible even a microcomputer different from a microcomputer detecting power source abnormality, accesses the EEPROM, in abnormality of the power source such as instantaneous interruption.SOLUTION: A control device includes two microcomputers 11, 12 communicatable to each other, and an EEPROM 13 accessed by both microcomputers 11, 12, and the EEPROM 13 includes a chip select terminal CS, and is constituted to receive the access when a High signal is input to the terminal CS and not to receive the access when a terminal CS low signal is input. One of the microcomputers 11 is constituted to detect occurrence of instantaneous stop, and changes an access command output terminal O1 connected to the chip select terminal CS to a Low output state so that a Low signal is forcibly input to the chip select terminal CS of the EEPROM 13 when the occurrence of instantaneous stop is detected.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a control device for performing combustion control of a combustion device such as a gas fan heater or an instantaneous water heater.

  In the following Patent Document 1, the applicant of the present application describes a main microcomputer that performs general control of the combustion device and performs a cutoff operation that shuts off the fuel supply, and a fuel supply cutoff operation that is independent of the main control device. When the main microcomputer and the sub microcomputer receive a signal for knowing the operation state of the combustion device, the main microcomputer and the sub microcomputer receive a signal indicating a predetermined stop signal. Disclosed is a combustion control device configured to perform an emergency shut-off operation.

  In such a conventional combustion control device, the main microcomputer performs general control of the combustion device, the combustion operation is executed, and the EEPROM for storing and holding various control information that must be stored even when the power is shut off (Rewritable non-volatile memory) is connected to the main microcomputer.

Japanese Patent No. 4877604

  In the above prior art, the sub-microcomputer is configured to perform auxiliary processing such as emergency shutdown processing. However, the applicant of the present application performs various operation control processes of the combustion apparatus on a plurality of microcomputers (microcontrollers or microcomputers). In order to achieve this, it is necessary to make each microcomputer accessible to the EEPROM.

  On the other hand, many combustion devices such as gas fan heaters and instantaneous water heaters are operated by a commercial power supply. However, during an access to the EEPROM, a momentary power failure (instantaneous power failure, for example, a power failure of less than 1 second) or a momentary voltage drop ( If the power supply voltage (5V) of the EEPROM drops due to an abnormality in the commercial power supply (for example, when the voltage drops to about 90% or less for a short time of about 2 seconds or less) The data obtained by accessing at that timing is not guaranteed, and in the worst case, the data stored in the EEPROM may be damaged. In particular, if correction value data associated with a combustion operation such as a threshold correction for flame detection by combustion is damaged, there is a possibility that the subsequent combustion operation cannot be performed normally.

  In addition, when an abnormality such as a momentary power failure occurs, it is also required to perform the minimum necessary data maintenance before the power supply voltage of the microcomputer drops. It is preferable to perform processing such as detecting a predetermined abnormality and immediately stopping access to the EEPROM when the abnormality is detected.

  However, if a microcomputer that detects an instantaneous power outage or the like is accessing the EEPROM, and if an instantaneous power outage or the like is detected, access to the EEPROM can be stopped immediately, but another microcomputer is accessing the EEPROM. Even if a momentary power failure or the like is detected, if an access stop command is issued by communication between microcomputers, the power supply voltage of the EEPROM may drop before another microcomputer stops accessing the EEPROM. .

  Therefore, in the present invention, in a control device provided with at least two microcomputers for various operation control, when a power supply abnormality such as a momentary power failure occurs, a microcomputer other than the microcomputer that detects the power supply abnormality accesses the EEPROM. However, it is an object of the present invention to enable the EEPROM access as normally as possible.

  In order to achieve the above object, the present invention takes the following technical means.

  That is, the control device of the present invention includes first and second microcomputers (a microcontroller or a microcomputer) configured to be able to communicate with each other, and a nonvolatile memory element accessed by the first and second microcomputers. The memory element has a chip select terminal. When a predetermined valid signal is input to the terminal, the memory element accepts access by the first and second microcomputers, but inputs a predetermined invalid signal to the terminal. Is configured not to accept access of the first and second microcomputers, and the first and second microcomputers operate to input the valid signal to the chip select terminal when accessing the storage element In addition, the first microcomputer is configured to be able to detect a predetermined abnormality of the power supply, and when the predetermined abnormality of the power supply is detected, It said invalid signal regardless state of access to the serial memory element has been assumed to operate so as to input to the chip select terminals of the memory device (claim 1).

  According to the control device of the present invention, for example, a predetermined value of the commercial AC power supply that appears as a sign that the control power supply voltage supplied to the microcomputer or the storage element is lowered, for example, the zero cross point of the commercial AC power supply waveform is not detected for 50 milliseconds or longer. When the first microcomputer detects an abnormality, the first microcomputer operates to forcibly input an invalid signal to the chip select terminal of the storage element before the control power supply voltage of the microcomputer or the storage element drops. Therefore, even if the second microcomputer is accessing the storage element when the power supply abnormality is detected, the storage element can be shifted to a stable standby state while the control power supply voltage is being supplied. It is possible to avoid the important data being stored from being damaged or unexpected damage to the memory cells.

  The control device of the present invention includes first and second microcomputers configured to be able to communicate with each other, and a nonvolatile memory element accessed by the first and second microcomputers, the memory element being a chip select. A terminal is provided, and when the predetermined valid signal is input to the terminal, the access of the first and second microcomputers is accepted, but when the predetermined invalid signal is input to the terminal, the first and second The second microcomputer transmits predetermined access start information to the first microcomputer before accessing the storage element, and to the first microcomputer at the end of the access. The first microcomputer is configured to detect a predetermined abnormality of the power source and the second microcomputer is accessing the storage element. It said invalid signal and detects a predetermined abnormal power can be made to operate so as to input to the chip select terminals of the memory device (claim 2).

  According to this configuration, in addition to the function and effect of the invention according to claim 1, the following function and effect can be achieved. That is, when the first microcomputer detects a predetermined abnormality of the power supply while accessing the nonvolatile memory element, the first microcomputer forcibly interrupts the access itself, thereby causing various kinds of power supply interruptions during access. The occurrence of defects can be reduced. On the other hand, when the second microcomputer detects a predetermined abnormality of the power supply while accessing the nonvolatile memory element, the first microcomputer operates to force the invalid signal to be input to the chip select terminal. The time lag from when abnormality is detected until the storage element is made in an access invalid state can be shortened as much as possible.

  The operation when the first microcomputer detects a power supply abnormality is a predetermined input / output port of the first microcomputer for setting an invalid signal to the chip select terminal of the memory element. It may be a state change. For example, a predetermined input / output port of the first microcomputer can be normally set in a high impedance state, and can be changed to a low signal output state or a high signal output state when a power supply abnormality is detected. In addition, it is possible to configure the circuit so that the above action occurs by setting the Low signal output state or the High signal output state in normal times and changing the state to the high impedance state when power supply abnormality is detected. The predetermined input / output port is preferably an access command output terminal for outputting a valid signal to the chip select terminal when the first microcomputer accesses the storage element. An input / output terminal different from the terminal may be used.

  In the control device of the present invention, the first microcomputer is configured to perform communication for requesting re-access to the storage element to the second microcomputer after the predetermined abnormality of the power source is resolved. (Claim 3) According to this, for example, when the zero-cross point of the commercial AC power supply waveform can be detected, the fact that the abnormality of the commercial AC power supply has been resolved before the control power supply voltage generated and output from the commercial AC power supply has dropped. When the first microcomputer detects that the second microcomputer can access the non-volatile memory element by canceling the signal output operation that forcibly inputs the invalid signal to the chip select terminal, the second microcomputer Communication for requesting re-access to the storage element is performed. On the other hand, the second microcomputer can be configured to re-access the previous nonvolatile memory element when communication requesting re-access is made, so that the second microcomputer is accessing the nonvolatile memory element. When the nonvolatile memory element is forcibly shifted to the access invalid state by the first microcomputer, data consistency can be ensured by allowing the second microcomputer to re-access. When the commercial AC power supply fails and the control power supply voltage to the microcomputer drops, the first and second microcomputers are in a power-off state and are reset when power is supplied again. .

  In addition, the control device of the present invention can preferably have the following configuration as a specific configuration. That is, the first and second microcomputers can each include an access command output terminal connected to the chip select terminal of the storage element.

  The access command output terminal of the first microcomputer can be configured to be selectively controllable to any one of a plurality of states including a high signal output state, a low signal output state, and a high impedance state.

  The access command output terminal of the second microcomputer has at least two or three states including a high signal output state and a low signal output state and / or a high impedance state (high signal output state and low signal output state). Two states, or two states of a high signal output state and a high impedance state, or three states of a high signal output state, a low signal output state, and a high impedance state) can be selectively switched and controlled. Can be configured.

  The wiring impedance between the chip select terminal and the access command output terminal of the first microcomputer is made smaller than the wiring impedance between the chip select terminal and the access command output terminal of the second microcomputer. A pull-down resistor can be connected to the chip select terminal.

  The chip select terminal may be an input terminal in a high impedance state, and one of the valid signal and the invalid signal may be a High signal and the other may be a Low signal.

  With the configuration described above, the first microcomputer causes the chip select terminal to input the valid signal by switching the access command output terminal of the first microcomputer to a high signal output state during access to the storage element. Can do. Further, when the first microcomputer does not access the memory element, the access command output terminal of the first microcomputer is switched to the high impedance state, so that the chip select terminal is changed depending on the output state of the access command output terminal of the second microcomputer. The input signal is switched between a valid signal and an invalid signal.

  In addition, the second microcomputer can input the valid signal to the chip select terminal by switching the access command output terminal of the second microcomputer to a high signal output state during access to the storage element. On the other hand, when not accessing, the input signal of the chip select terminal is changed depending on the output state of the access command output terminal of the first microcomputer by switching the access command output terminal of the second microcomputer to the high impedance state or the low signal output state. Switch between valid and invalid signals. Note that the access command output terminal of the second microcomputer may be in the low signal output state because the wiring impedance between the access command output terminal of the second microcomputer and the chip select terminal is high and the low signal output state. This is because it can be equated with the high impedance state.

  Then, the operation when the first microcomputer detects a predetermined abnormality of the power supply can switch the access command output terminal of the first microcomputer to a Low signal output state.

  According to such a configuration, both microcomputers can control the input signal of the chip select terminal, respectively, and the access instruction output of the first microcomputer that detects the power supply abnormality regardless of the state of the access instruction output terminal of the second microcomputer. By setting the terminal to the Low signal output state, it becomes possible to forcibly input an invalid signal to the chip select terminal, and it is possible to improve the data reliability of the nonvolatile memory element even with a simple circuit configuration. .

  In order to prevent the first and second microcomputers from accessing the nonvolatile memory element at the same time, the access status between the two microcomputers is confirmed by communication, and the other microcomputer accesses the nonvolatile memory element. In the meantime, it is preferable to wait for access to the nonvolatile memory element by itself until the access is completed. Alternatively, when the second microcomputer accesses the nonvolatile memory element, it requests access permission from the first microcomputer, and the second microcomputer stores the nonvolatile memory only while the first microcomputer permits access. It can also be configured to allow access to the element.

  Further, the power source that the first microcomputer detects an abnormality may be a commercial AC power source, and the control device 1 of the present invention uses the DC power source voltage supplied to the power terminals of both the microcomputer and the nonvolatile memory element as the commercial AC power source. A power supply circuit unit composed of a switching power supply circuit or a regulator generated from the power supply circuit, and when the commercial AC power supply is momentarily interrupted or dropped, the DC power supply voltage is applied for a predetermined time, for example, about 100 milliseconds. It is preferable to provide a capacitor such as an electrolytic capacitor on the output side of the switching power supply circuit or the regulator. This capacitor may be mounted as a smoothing circuit.

  According to the present invention, in the event of a power failure such as a momentary power failure or a momentary power failure, even if a microcomputer other than the microcomputer that detects the power failure is accessing the EEPROM, the EEPROM is accessed as normally as possible. it can.

It is a schematic circuit diagram of the control apparatus which concerns on one Embodiment of this invention.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

  FIG. 1 shows a schematic circuit configuration of a control device 1 built in a combustion device such as a gas fan heater, in particular, a power supply circuit configuration. The power supply circuit portion of the control device 1 is a commercial AC power source and a 15V DC power source. A switching power supply circuit 2 that generates and outputs a voltage (first DC power supply voltage), and a zero cross detection circuit 3 that detects a zero cross point of a commercial AC power supply waveform on the input side of the power supply circuit 2 and outputs a detection pulse at the zero cross point And a first regulator 4 that generates and outputs a 5V DC power supply voltage (5V-1) from the 15V DC power supply voltage, and a second regulator 5 that generates and outputs a 5V DC power supply voltage (5V-2) from the 15V DC power supply voltage. And. A smoothing circuit comprising an electrolytic capacitor C1 is provided on the output side of the switching power supply circuit 2, a smoothing circuit comprising an electrolytic capacitor C2 is provided on the output side of the first regulator 4, and an output side of the second regulator 5 is provided on the output side. Is provided with a smoothing circuit comprising an electrolytic capacitor C3.

  The control device 1 includes two microcomputers, a main microcomputer 11 (first microcomputer) and a sub-microcomputer 12 (second microcomputer), which are connected so as to be able to communicate with each other as a control center. The output of the first regulator 4 is supplied as a control power supply voltage to the power supply terminals Vcc of both the microcomputers 11 and 12.

  In addition, the microcomputers 11 and 12 are configured to be able to distribute and assign the operation control processes of various control valves, fan motors, igniters, and other control target devices provided in the combustion device. That is, each of the microcomputers 11 and 12 is provided with an operation command signal output port capable of outputting an operation command signal to the control target device. The main microcomputer 11 controls the opening / closing operation of the opening / closing solenoid valve for opening / closing the fuel supply path, Various operation controls necessary for the combustion operation of the combustion equipment can be distributed and assigned to the two microcomputers 11 and 12 such that the sub microcomputer 12 controls the opening degree of the proportional valve that adjusts the flow rate of the fuel supply path.

  The zero-cross detection waveform output from the zero-cross detection circuit 3 is input to the power supply monitoring signal input terminal of the main microcomputer 11, and the main microcomputer 11 monitors the interval between the zero-cross detection pulses, and this interval is a predetermined value or more ( For example, it can be configured to detect that a momentary power failure (a predetermined abnormality of the power supply) has occurred in the commercial power supply.

  The control device 1 also includes an EEPROM 13 as a common rewritable nonvolatile memory element that can be accessed by both the microcomputers 11 and 12. The output of the second regulator 5 is supplied to the power supply terminal Vcc of the EEPROM 13 as an operating power supply voltage. It is also possible to supply the same output of the first regulator 5 as the microcomputers 11 and 12 to the power supply terminal Vcc of the EEPROM 13.

  Both the microcomputers 11 and 12 and the EEPROM 13 are connected to a data bus (not shown). The main microcomputer 11 can read / write access to the EEPROM 13 via the data bus, and the sub-microcomputer 12 can also be accessed via the data bus. The EEPROM is configured to allow read / write access.

  The EEPROM 13 includes a chip select terminal CS. When a high signal (valid signal) is input to the terminal CS, the EEPROM 13 accepts access from any one of the microcomputers 11 and 12, but the chip select terminal CS When a Low signal (invalid signal) is input, access from both the microcomputers 11 and 12 is not accepted, and an internal access operation to the memory cell is not performed.

  The main microcomputer 11 and the sub microcomputer 12 include access command output terminals O1 and O2 connected to the chip select terminal CS, respectively. The access command output terminals O1 and O2 are constituted by one of a large number of input / output ports provided in the microcomputers 11 and 12, respectively. The input / output ports of the microcomputers 11 and 12 are configured to function as input terminals and output terminals by internal setting control, and when set as input terminals, the terminals are in a high impedance state and output When set as a terminal, it can be switched to either a high signal output state or a low signal output state.

  In the present embodiment, the access command output terminals O1 and O2 of both the microcomputers 11 and 12 are in any one of three states: a high signal output state at the time of output setting and a low signal output state, and a high impedance state at the time of input setting. It is configured to be switched.

  Also, the wiring impedance between the chip select terminal CS and the access command output terminal O1 of the main microcomputer 11 is very small. On the other hand, the wiring impedance (resistance value) between the chip select terminal CS and the access command output terminal O2 of the sub-microcomputer 12 is increased by providing, for example, a 1 kΩ resistor R1 in the middle of the wiring.

  In addition, a pull-down resistor R2 of about 10 kΩ, for example, is connected to the chip select terminal CS, so that when the access command output terminals O1 and O2 of any of the microcomputers 11 and 12 are in a high signal output state, the chip select terminal When a valid signal (High signal) is input to CS, but no High signal is output from any of the access command output terminals O1 and O2, the input voltage of the chip select terminal CS is pulled down, and an invalid signal (Low) Signal) is input. As the EEPROM 13, an input to the chip select terminal CS that enables access by a Low signal and disables access by a High signal may be adopted. In this case, for example, in the circuit shown in FIG. This can be handled by providing a NOT circuit at the select terminal CS. Of course, it is possible to cope with this problem by improving the connection circuit between the access command output terminals O1 and O2 of both the microcomputers 11 and 12 and the chip select terminal CS.

  Next, an access processing method when the microcomputers 11 and 12 access the EEPROM 13 will be described.

  When the main microcomputer 11 tries to access the EEPROM 13, after confirming that the sub-microcomputer 11 is not accessing the EEPROM 13, an access prohibition command to the EEPROM 13 is transmitted to the sub-microcomputer 12 by communication, and the access command The access to the EEPROM 13 is started by setting the output terminal O1 to the High signal output state. After the access is completed, the access command output terminal O1 is set to a high impedance state, an invalid signal is input to the chip select terminal CS, and an access permission command to the EEPROM 13 is transmitted to the sub-microcomputer 12 by communication.

  When a momentary power failure is detected while the main microcomputer 11 is accessing, the main microcomputer 11 immediately stops or interrupts access to the EEPROM 13. When the write access is being performed, it is preferable to perform the write process again if the instantaneous interruption is resolved.

  The sub-microcomputer 11 is configured to access the EEPROM 13 when an access prohibition command is not issued from the main microcomputer 11, and waits until an access permission command is issued from the main microcomputer 11 when the access prohibition command is issued. .

  Further, when the sub-microcomputer 12 tries to access the EEPROM 13, the sub-microcomputer 12 transmits information indicating that the access to the EEPROM 13 is started to the main microcomputer 11. With this information, the main microcomputer 11 can confirm whether or not the sub-microcomputer is accessing the EEPROM 13. Further, the sub-microcomputer 12 switches the access command output terminal O2 to the High signal output state, thereby inputting a valid signal (High signal) to the chip select terminal CS of the EEPROM 13 and starting access to the EEPROM 13. After the access is completed, the sub-microcomputer 12 sets the access command output terminal O2 to the high impedance state, inputs an invalid signal (Low signal) to the chip select terminal CS, and transmits information indicating that the access is completed to the main microcomputer 11. It is configured to

  When the main microcomputer 11 detects the occurrence of instantaneous interruption while the sub-microcomputer 12 is accessing the EEPROM 13, the processing speed is too slow if the access interruption command is transmitted by communication between the microcomputers. By switching the access command output terminal O1 from the high impedance state to the Low signal output state, an invalid signal (Low signal) is forcibly input to the chip select terminal CS.

  If an instantaneous power failure is detected immediately after the access by the microcomputers 11 and 12 is completed, it takes about 5 milliseconds for the writing process in the EEPROM 13 or the like. Even if it exists, since the control power supply voltage to both the microcomputers 11 and 12 and the EEPROM 13 is maintained for about 100 milliseconds, the influence due to the occurrence of the instantaneous power failure is small.

  Further, when the main microcomputer 11 forcibly inputs an invalid signal to the chip select terminal CS while the sub-microcomputer 12 is accessing the EEPROM 13, the main microcomputer 11 stops the instantaneous power interruption on the condition that the control power supply voltage is held. After the cancellation, the sub-microcomputer 12 is configured to perform communication requesting access again. When the re-access request is made from the main microcomputer, the sub-microcomputer 12 performs the previous access again. That is, in the case of read access, the same data is read again. If it is a write access, the same data is written again.

  According to the present embodiment, even if a momentary power failure occurs when the sub-microcomputer 12 is accessing the EEPROM 13, the main microcomputer 11 operates to forcibly input an invalid signal to the chip select terminal of the EEPROM 13. The EEPROM 13 can be protected. Further, when no power failure occurs and there is almost no influence on the control power supply voltage supplied to both microcomputers 11 and 12 and EEPROM 13, both microcomputers 11 and 12 continue various controls. The reliability of data acquired by the sub-microcomputer 12 by read access to the EEPROM 13 that is forcibly invalidated by the data 11 or data written by the sub-microcomputer 12 to the EEPROM 13 is not guaranteed. Reliability can be ensured by requesting access again.

  The present invention is not limited to the above-described embodiment, and the design can be changed as appropriate. For example, in the above-described embodiment, the configuration in which the abnormality of the commercial AC power supply is detected based on the interval between the zero cross points of the commercial AC voltage waveform is exemplified. However, for example, the commercial AC voltage value is monitored and the voltage level is set to the normal value. On the other hand, when the ratio becomes smaller than a predetermined ratio (for example, 50% or more), an instantaneous drop occurs in the commercial AC power supply, which may greatly reduce the control power supply voltage supplied to the microcomputers 11 and 12 and the EEPROM 13. As a thing, it can also be detected that the power supply is abnormal.

1 control device 11 first microcomputer (main microcomputer)
O1 Access command output terminal 12 Second microcomputer (sub microcomputer)
O2 access command output terminal 13 Nonvolatile memory element (EEPROM)
CS Chip select terminal R1 Wiring impedance R2 Pull-down resistor

Claims (4)

First and second microcomputers configured to be able to communicate with each other, and a nonvolatile memory element accessed by the first and second microcomputers,
The memory element has a chip select terminal, and when a predetermined valid signal is input to the terminal, accepts access of the first and second microcomputers, but inputs a predetermined invalid signal to the terminal. When configured to not accept access of the first and second microcomputers,
The first and second microcomputers operate to input the valid signal to the chip select terminal when accessing the storage element,
The first microcomputer is configured to be able to detect a predetermined abnormality of the power supply, and when the predetermined abnormality of the power supply is detected, the invalid signal is stored regardless of an access state of the storage element of the second microcomputer. A control device that operates to input to the chip select terminal of the element. .
First and second microcomputers configured to be able to communicate with each other, and a non-volatile memory element accessed by the first and second microcomputers, the memory element includes a chip select terminal, and the terminal has a predetermined value The first and second microcomputer access is accepted when a valid signal is input, but the first and second microcomputer access is not accepted when a predetermined invalid signal is input to the terminal. And
The second microcomputer transmits predetermined access start information to the first microcomputer before accessing the storage element, and transmits predetermined access end information to the first microcomputer when the access ends. And
The first microcomputer is configured to detect a predetermined abnormality of the power supply, and when the second microcomputer detects a predetermined abnormality of the power supply while accessing the storage element, the invalid signal is sent to the chip of the storage element. A control device that operates to input to the select terminal.   3. The control device according to claim 2, wherein the first microcomputer is configured to perform communication for requesting re-access to the storage element to the second microcomputer after a predetermined abnormality of the power source is resolved. The control unit. In the control device according to claim 1, 2, or 3,
The first and second microcomputers each have an access command output terminal connected to the chip select terminal of the storage element,
The access command output terminal of the first microcomputer is configured to be selectively switchable to any one of a plurality of states including a high signal output state, a low signal output state, and a high impedance state,
The access command output terminal of the second microcomputer is configured to be selectively controllable to any one of a plurality of states including a high signal output state and a low signal output state and / or a high impedance state.
The wiring impedance between the chip select terminal and the access command output terminal of the first microcomputer is smaller than the wiring impedance between the chip select terminal and the access command output terminal of the second microcomputer, and the chip A pull-down resistor is connected to the select terminal,
The chip select terminal is an input terminal in a high impedance state, one of the valid signal and the invalid signal is a high signal, and the other is a low signal.
The first microcomputer inputs the valid signal to the chip select terminal by switching the access command output terminal of the first microcomputer to a high signal output state during access to the storage element, and when not accessing The access command output terminal of the first microcomputer is configured to be switched to a high impedance state,
The second microcomputer inputs the valid signal to the chip select terminal by switching the access command output terminal of the second microcomputer to a high signal output state during access to the storage element, and when not accessing The access command output terminal of the second microcomputer is configured to switch to a high impedance state or a low signal output state,
The control device, wherein the operation when the first microcomputer detects a predetermined abnormality of the power supply is to switch the access command output terminal of the first microcomputer to a Low signal output state.

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