JP3509569B2 - Distribution line switchgear control device - Google Patents
Distribution line switchgear control deviceInfo
- Publication number
- JP3509569B2 JP3509569B2 JP23197898A JP23197898A JP3509569B2 JP 3509569 B2 JP3509569 B2 JP 3509569B2 JP 23197898 A JP23197898 A JP 23197898A JP 23197898 A JP23197898 A JP 23197898A JP 3509569 B2 JP3509569 B2 JP 3509569B2
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- Prior art keywords
- power supply
- voltage
- control
- storage unit
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、配電線の区分開閉
器の開閉を制御する配電線の開閉器制御装置に関する。
【０００２】
【従来の技術】従来、いわゆる配電線自動化システム等
のこの種の開閉器制御装置は、配電線の区分開閉器毎に
設けられ、ほぼ図３に示すように構成される。
【０００３】そして、配電線１の各区分開閉器２の開閉
器制御装置３は、コンピュータ構成の制御処理部４及び
区分開閉器２を開閉する開閉器駆動部５を有し、区分開
閉器２の両側の変圧器６，７から系統電源が給電されて
動作する。
【０００４】さらに、制御処理部４はＣＰＵ８に制御プ
ログラム等を記憶したＲＯＭ構成の記憶部９，ＥＥＰＲ
ＯＭからなる書換自在の不揮発性の記憶部１０等をバス
接続して形成され、ＣＰＵ８により記憶部９の監視制御
のプログラム等を読出して実行する。
【０００５】そして、変圧器６，７の２次側電圧や図示
省略した事故区間検出用の時限タイマの動作等から区分
開閉器２の負荷側自己区間の系統事故等に基づく系統電
圧の消失，復旧等を監視，検出し、この監視，検出によ
り開閉器駆動部５を介して区分開閉器２を開閉する。
【０００６】また、運用履歴の把握等を行うため、系統
事故や装置故障等の異常が発生すると、ＣＰＵ８は区分
開閉器２の開閉状態や前記時限タイマの動作時限等の各
種制御状態を記憶部１０に書込んでその記憶内容を書換
え、記憶部１０は書込まれた各種の状態情報を系統停電
中等にも保持する。
【０００７】さらに、開閉器制御装置３が遠方監視制御
の子局機能を備える場合には、制御処理部４は記憶部９
の通信制御のプログラムを実行して変電所，電力会社営
業所等に設けられた監視制御の親局（中央装置）と専用
の通信線（図２の破線）又は配電線を介して情報をやり
とりする。
【０００８】そして、記憶部１０に記憶された情報は現
場操作又は親局との通信等により、必要に応じて外部装
置等に読出される。
【０００９】ところで、記憶部１０の書込み、読出しを
行うため、従来は図４に示すようにＣＰＵ８の書込制御
端子ｗｒ＊ ，読出制御端子ｒｄ＊ に記憶部１０の書
込制御端子ＷＲ＊ ，読出制御端子ＲＴ＊ が接続さ
れ、制御処理部４のデバイス選択用のアドレス選択回路
１１に記憶部１０の選択制御端子ＣＥ＊ が接続され
る。
【００１０】なお、各端子ｗｒ＊ ，…，ＣＥ＊ の＊
はローレベル（以下Ｌという）アクティブであることを
示す。
【００１１】そして、記憶部１０の書込みの際は、選択
制御端子ＣＥ＊ がＬになって記憶部１０が選択され、
この状態でＣＰＵ８の書込制御端子ｗｒ＊ からＬの書
込制御信号が出力され、ＣＰＵ８の読出制御端子ｒｄ
＊ がハイレベル（以下Ｈという）に保持され、記憶部
１０の書込制御端子ＷＲ＊ がＬの書込許可，読出制御
端子ＲＴ＊ がＨの読出不許可になる。
【００１２】このとき、記憶部１０は制御端子ＷＲ＊
＝Ｌ，制御端子ＲＴ＊ ＝Ｈ，制御端子ＣＥ＊ ＝Ｌの
条件を満足し、書込サイクルで動作してデータバスの状
態情報が書込まれる。
【００１３】
【発明が解決しようとする課題】前記従来の配電線の開
閉器制御装置の場合、系統給電に基づく直流の駆動電源
が系統の瞬時電圧低下（瞬低），事故停電等によって容
易に変動し、不安定であるため、いわゆる電子回路構成
の図３，図４の制御処理部４は電源投入時だけでなく、
電源投入後の運用中にも不安定な状態になり易く、誤動
作するおそれがある。
【００１４】すなわち、装置の電源投入又は系統の瞬
低，事故停電等からの復旧（復帰）による駆動電源の立
上りの際、図５の（ａ）に示すように駆動電源の電圧Ｖ
ｃｃが電圧消失状態のＬから電圧 のＨに上昇するまで
は、制御処理部４のＣＰＵ８が動作しておらず、その
間、制御端子ｗｒ＊ ，ｒｄ＊ 等のＣＰＵ８の各端子
のレベルはＣＰＵ８の制御を受けず、外乱（ノイズ等）
によって容易に変動する。
【００１５】なお、図５において、（ａ）は図示省略し
た電源部から制御処理部４に供給される駆動電源の電圧
Ｖｃｃを示し、（ｂ）はＣＰＵ８の読出制御端子ｒｄ
＊ のレベル，（ｃ）は記憶部１０の読出制御端子ＲＴ
＊ のレベル，（ｄ）は記憶部１０の書込制御端子ＷＲ
＊ ，選択制御端子ＣＥ＊ のレベルを示し、図中の
ｈ，ｌは各端子のＨ，Ｌのしきい値を示す。
【００１６】そして、電圧ＶｃｃがＬからＨに立上って
安定するまでの過渡期間ΔＴに、図５の（ｂ）に示すよ
うにＣＰＵ８の読出制御端子ｒｄ＊ のレベルが外乱等
によって変動し、電圧ＶｃｃがＨに立上る前に読出制御
端子ｒｄ＊ がＨに変化すると、同図の（ｃ）に示すよ
うに記憶部１０の読出制御端子ＲＴ＊ が連動してＨに
変化する。
【００１７】このとき、図５の（ｄ）に示すように記憶
部１０の書込制御端子ＷＲ＊ ，選択制御端子ＣＥ＊
が共にＬになっていれば、制御端子ＷＲ＊ ＝Ｌ，制御
端子ＲＴ＊ ＝Ｈ，制御端子ＣＥ＊ ＝Ｌの条件を満足
し、記憶部１０が誤って書込サイクルに入り、書込みに
誤制御される。
【００１８】そして、記憶部１０が書込みに誤制御され
ると、誤った情報が記憶部１０に書込まれ、その記憶情
報の信頼性の向上等を図ることができない問題点があ
る。
【００１９】本発明は、駆動電源の電圧が立上る際の制
御処理部の不揮発性の記憶部の書込みの誤制御を防止
し、その記憶情報の信頼性の向上等を図ることを課題と
する。
【００２０】
【課題を解決するための手段】前記の課題を解決するた
めに、本発明の配電線の開閉器制御装置においては、制
御処理部の駆動電源の電圧と所定のしきい値の電圧とを
比較し，駆動電源の立上りにより駆動電源の電圧がしき
い値の電圧より高くなるまで電源不安定の検出信号を出
力する電源状態検出部と、電源不安定の検出信号が出力
される間記憶部の書込みに関連する制御端子を禁止レベ
ルにクランプし，不揮発性の記憶部の書込みを禁止する
書込禁止ゲート部とを備える。
【００２１】したがって、電源投入又は系統の瞬低，事
故停電等からの復旧（復帰）による駆動電源の立上りの
際、駆動電源の電圧が所定のしきい値の電圧より高くな
り、いわゆるオン電圧以上になるまで電源状態検出部か
ら電源不安定の検出信号が出力される。
【００２２】そして、この電源不安定の検出信号が出力
される間は、書込禁止ゲート部により記憶部の書込みに
関連する制御端子が制御禁止のレベルに保持され、記憶
部の書込み制御が禁止される。
【００２３】そのため、駆動電源の電圧が立上る過渡期
間に外乱等によって記憶部１０が誤って書込みに制御さ
れることがなく、その記憶情報の信頼性の向上等が図ら
れる。
【００２４】
【発明の実施の形態】本発明の実施の１形態につき、図
１及び図２を参照して説明する。図１は開閉器制御装置
の制御処理部を示し、同図において、図３，図４と同一
符号は同一もしくは相当するものを示す。
【００２５】そして、図３の変圧器６，７の２次側出力
が給電される電源部１２は、整流，平滑等により電圧Ｖ
ｃｃの直流の駆動電源等の各種の直流電源を形成し、制
御処理部４等に給電する。
【００２６】つぎに、駆動電源の立上りの際にいわゆる
禁止ゲート信号を形成するため、制御処理部４に電源状
態検出部１３を設ける。
【００２７】この検出部１３は、例えば電源部１２の適
当な直流電圧を分圧等して駆動電源のオン電圧に設定さ
れた所定のしきい値の電圧ＶＨ を出力する基準電源１
４を備え、電源部１２の駆動電源の電圧Ｖｃｃと基準電
源１４のしきい値の電圧ＶＨ とを比較器１５により比較
する。
【００２８】この比較器１５の出力信号は、駆動電源の
立上りの際、電圧Ｖｃｃが電圧ＶＨ に上昇するまではＨ
に保持され、電圧Ｖｃｃが電圧ＶＨ に達したときに、
Ｌに反転する。
【００２９】そして、比較器１５の出力信号を遅延器１
６により遅延して反転し、電圧Ｖｃｃが電圧ＶＨ に上
昇した後微小時間τが経過し、電圧Ｖｃｃが確実に電圧
ＶＨ より高くなるまでの間、Ｌの電源不安定の検出信号
を形成してリセット端子ｒｓｔ＊ から出力する。
【００３０】また、記憶部１０の読出制御端子ＲＴ＊
の前段にローアクティブのアンドゲートが形成する書込
禁止ゲート部１７を設け、この書込禁止ゲート部１７に
よりＣＰＵ８の読出制御端子ｒｄ＊ の出力信号と電源
状態検出部１３のリセット端子ｒｓｔ＊ の出力信号と
を論理積処理し、リセット端子ｒｓｔ＊ の出力信号が
Ｈに反転するまで記憶部１０の読出制御端子ＲＴ＊ を
Ｌにクランプし、その間、外乱等による読出制御端子Ｒ
Ｔ＊ のＨへの変化を禁止する。
【００３１】したがって、図２の（ａ）に示す電圧Ｖｃ
ｃの立上りの過渡期間ΔＴに、同図の（ｂ）に示すよう
にＣＰＵ８の読出制御端子ｒｄ＊ の出力信号が外乱等
でＨに変動しても、その間は同図の（ｃ）に示すリセッ
ト端子ｒｓｔ＊ のＬの電源不安定の検出信号により、
記憶部１０の読出制御端子ＲＴ＊ が同図の（ｄ）に示
すようにＬに保たれ、記憶部１０は書込サイクルに入る
ことがなく、誤って書込みに制御されることがない。
【００３２】なお、図２の（ｅ）は記憶部１０の制御端
子ＷＲ＊ ，ＣＥ＊ のレベルを示す。 ところで、遅
延器１６の遅延時間τは、駆動電源のしきい値ｈの電圧
や基準電源１４のしきい値の電圧ＶＨ 等に応じて適当
に設定すればよい。
【００３３】さらに、しきい値の電圧ＶＨ の設定等に
よっては、遅延器１６を省き、比較器１５の出力信号を
そのまま反転して電源不安定の検出信号としてもよい。
【００３４】そして、電源状態検出部１３，書込禁止ゲ
ート部１７等の構成は図１のものに限られるものではな
く、例えば記憶部１０の入力条件等によっては、論理レ
ベルが図１と逆であってもよい。
【００３５】また、書込禁止ゲート部１７により記憶部
１０の書込みに関連する他の制御端子を制御禁止のレベ
ルにクランプするようにしてもよい。
【００３６】
【発明の効果】本発明は、以下に記載する効果を奏す
る。電源状態検出部１３及び書込禁止ゲート部１７を設
けたため、電源投入又は系統の瞬低，事故停電等からの
復旧（復帰）による駆動電源の立上りの際、駆動電源の
電圧が所定のしきい値の電圧より高くなるまで、電源状
態検出部１３から電源不安定の検出信号を出力し、この
信号が出力される間、書込禁止ゲート部１７により記憶
部１０の書込みに関連する制御端子を制御禁止のレベル
に保持し、記憶部１０の書込み制御を禁止することがで
きる。
【００３７】したがって、駆動電源の電圧が立上る過渡
期間に記憶部１０が誤って書込みに制御されることがな
く、その記憶情報の信頼性を著しく向上することができ
る。DETAILED DESCRIPTION OF THE INVENTION
[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the divisional opening and closing of distribution lines.
Field of the Invention The present invention relates to a distribution line switch control device for controlling switching of a switch.
[0002]
2. Description of the Related Art Conventionally, a so-called distribution line automation system, etc.
This type of switchgear control device
3 and is configured substantially as shown in FIG.
[0003] Opening and closing of each section switch 2 of the distribution line 1
Device control device 3 includes a control processing unit 4 having a computer configuration and
It has a switch drive unit 5 for opening and closing the segment switch 2, and
System power is supplied from transformers 6 and 7 on both sides of
Operate.
[0004] Further, the control processing unit 4 sends a control program to the CPU 8.
ROM storage unit 9 for storing programs, etc., EEPR
A rewritable nonvolatile storage unit 10 made of OM
Monitor and control the storage unit 9 by the CPU 8
Is read and executed.
[0005] The secondary voltages of the transformers 6 and 7 and
Classified based on the operation of the timed timer for detecting the omitted accident section
System power based on system accidents etc. in the load-side self-section of switch 2
Monitors and detects pressure loss and recovery, etc.
The switch 2 is opened and closed via the switch drive unit 5.
Further, in order to grasp the operation history, etc.
When an abnormality such as an accident or equipment failure occurs, the CPU 8
Each of the switching state of the switch 2 and the operation time limit of the timed timer, etc.
Writes the seed control state to the storage unit 10 and rewrites the stored contents
In addition, the storage unit 10 stores the written various state information in a system power outage.
Hold in the middle.
[0007] Further, the switch control device 3 is a remote monitoring control.
If the slave station function is provided, the control processing unit 4
Substation and power company
Dedicated to the master station (central unit) for monitoring and control provided at offices, etc.
Exchange information via communication lines (broken lines in FIG. 2) or distribution lines.
To take.
The information stored in the storage unit 10 is
External equipment as necessary by field operation or communication with the master station.
The data is read out to a location or the like.
By the way, writing and reading of the storage unit 10 are performed.
Conventionally, as shown in FIG.
Terminal wr*, Read control terminal rd*In the storage unit 10
Control terminal WR*, Read control terminal RT*Is connected
Address selection circuit for device selection of the control processing unit 4
11 is a selection control terminal CE of the storage unit 10.*Is connected
You.
Each terminal wr*, ..., CE*of*
Is active low (hereinafter referred to as L)
Show.
When writing to the storage unit 10, the selection
Control terminal CE*Becomes L and the storage unit 10 is selected,
In this state, the write control terminal wr of the CPU 8*To L
And a read control terminal rd of the CPU 8 is output.
*Is held at a high level (hereinafter referred to as H), and the storage unit
10 write control terminals WR*Is L write enable, read control
Terminal RT*Is not allowed to read H.
At this time, the storage unit 10 stores the control terminal WR*
= L, control terminal RT*= H, control terminal CE*= L
Satisfies the conditions, operates in the write cycle, and
State information is written.
[0013]
SUMMARY OF THE INVENTION
In the case of a switchgear controller, a DC drive power source based on the system power supply
Is affected by instantaneous voltage drop (jump) of the system, accidental power failure, etc.
Because it fluctuates easily and is unstable, so-called electronic circuit configuration
The control processing unit 4 shown in FIGS. 3 and 4 is not only turned on when the power is turned on.
Easily become unstable during operation after power-on, causing malfunction
There is a risk of making.
That is, when the power of the apparatus is turned on or the system
Low, drive power supply on recovery from accidental power failure, etc.
At the time of rising, as shown in FIG.
Until cc rises from L in the voltage lost state to H in the voltage
Indicates that the CPU 8 of the control processing unit 4 is not operating and that
Control terminal wr*, Rd*Each terminal of CPU8 such as
Is not under the control of the CPU 8 and is subject to disturbances (noise, etc.).
Easily fluctuates.
In FIG. 5, (a) is not shown.
Of the driving power supplied from the power supply unit to the control processing unit 4
Vb, and (b) shows the read control terminal rd of the CPU 8.
*And (c) indicates the read control terminal RT of the storage unit 10.
*, And (d) indicates the write control terminal WR of the storage unit 10.
*, Selection control terminal CE*Indicates the level of
h and l indicate the threshold values of H and L of each terminal.
Then, when the voltage Vcc rises from L to H
As shown in FIG.
Read control terminal rd of CPU 8*Level is disturbance
Read control before the voltage Vcc rises to H.
Terminal rd*Changes to H, as shown in FIG.
The read control terminal RT of the storage unit 10*Is linked to H
Change.
At this time, as shown in FIG.
Write control terminal WR of unit 10*, Selection control terminal CE*
Are both L, the control terminal WR*= L, control
Terminal RT*= H, control terminal CE*Satisfies = L
Then, the storage unit 10 mistakenly enters a write cycle, and
Erroneous control.
If the storage unit 10 is erroneously controlled to write,
Then, erroneous information is written into the storage unit 10, and the stored information is
There is a problem that cannot improve the reliability of
You.
According to the present invention, when the voltage of the drive power supply rises,
Prevents erroneous control of writing to the nonvolatile storage unit of the control unit
And to improve the reliability of the stored information.
I do.
[0020]
Means for Solving the Problems To solve the above problems,
For example, in the distribution line switch control apparatus of the present invention,
The voltage of the drive power supply of the control unit and the voltage of the predetermined threshold
In comparison, the drive power supply voltage rises due to the rise of the drive power supply.
Output signal until the voltage becomes higher than
Power supply status detector and power unstable detection signal output
Control terminals related to writing to the memory
To lock in the memory and prohibit writing to nonvolatile storage
A write-protection gate unit.
Therefore, when the power is turned on or the system is sagged,
Rise of the drive power supply due to recovery (recovery) from a power failure
When the voltage of the driving power supply becomes higher than a predetermined threshold voltage,
Until the voltage reaches the so-called ON voltage.
Outputs a detection signal of power supply instability.
The power instability detection signal is output.
During this time, the write-protection gate
The associated control terminal is held at the control disable level and stored
The write control of the unit is prohibited.
Therefore, the transition period when the voltage of the drive power supply rises
The storage unit 10 is mistakenly controlled to write
And the reliability of the stored information is improved.
It is.
[0024]
BRIEF DESCRIPTION OF THE DRAWINGS FIG.
1 and FIG. Figure 1 shows a switch control device
3 shows a control processing unit, which is the same as FIG. 3 and FIG.
Symbols indicate the same or equivalent ones.
The secondary outputs of the transformers 6 and 7 shown in FIG.
The power supply unit 12 to which power is supplied has a voltage V
cc direct current drive power supply, etc.
The power is supplied to the control processing unit 4 and the like.
Next, when the drive power supply rises, a so-called
In order to form the inhibit gate signal, the control
A state detection unit 13 is provided.
The detection unit 13 is, for example, an appropriate
Divide the appropriate DC voltage and set it to the ON voltage of the drive power supply.
The predetermined threshold voltage VHReference power supply 1 that outputs
4 and the voltage Vcc of the drive power supply of the power supply
Source 14 threshold voltage VH Is compared with the comparator 15
I do.
The output signal of the comparator 15 is
At the time of rising, the voltage Vcc becomes the voltage VH Until it rises to
And the voltage Vcc isHWhen it reaches
Invert to L.
Then, the output signal of the comparator 15 is
6, the voltage Vcc is inverted.HOn
After a short time τ elapses after the rise, the voltage Vcc
VH Until it becomes higher, the detection signal of L power instability
To form a reset terminal rst*Output from
The read control terminal RT of the storage unit 10*
Formed by a low-active AND gate before the stage
A prohibition gate section 17 is provided.
The read control terminal rd of the CPU 8*Output signal and power supply
The reset terminal rst of the state detector 13*Output signal and
Is ANDed and the reset terminal rst*Output signal is
Until inverted to H, the read control terminal RT of the storage unit 10*To
L, during which the read control terminal R
T*To H is prohibited.
Therefore, the voltage Vc shown in FIG.
As shown in (b) of FIG.
To the read control terminal rd of the CPU 8*Output signal is disturbance
, And during that time, the reset shown in FIG.
Terminal rst*By the detection signal of the power instability of L of
Read control terminal RT of storage unit 10*Is shown in (d) of FIG.
Storage unit 10 enters a write cycle.
And writing is not erroneously controlled.
FIG. 2E shows the control terminal of the storage unit 10.
Child WR*, CE*Indicates the level of By the way, late
The delay time τ of the extender 16 is the voltage of the threshold value h of the driving power supply.
And the threshold voltage V of the reference power supply 14HAppropriate according to etc.
Should be set to.
Further, the threshold voltage VHFor setting of
Therefore, the delay unit 16 is omitted and the output signal of the comparator 15 is
The signal may be inverted as it is and used as a detection signal of power supply instability.
Then, the power supply state detecting unit 13 and the write inhibit
The configuration of the port section 17 and the like is not limited to that of FIG.
For example, depending on the input conditions of the storage unit 10 or the like, the logic level
The bell may be the reverse of FIG.
Further, the write-inhibiting gate unit 17 allows the storage unit
The level of other control terminals related to writing of 10 is prohibited.
You may make it clamp to a clamp.
[0036]
The present invention has the following effects.
You. A power supply state detector 13 and a write-protect gate 17 are provided.
Power failure, system power sag, accidental power outage, etc.
When the drive power supply rises due to recovery (recovery),
Until the voltage rises above the specified threshold voltage,
A power instability detection signal is output from the
Stored by the write inhibit gate unit 17 while the signal is output
The control terminal related to the writing of the part 10 is set to the control prohibition level.
And the write control of the storage unit 10 can be prohibited.
Wear.
Therefore, a transient when the voltage of the drive power supply rises
The storage unit 10 is not erroneously controlled to write during the period.
And the reliability of the stored information can be significantly improved.
You.
【図面の簡単な説明】
【図１】本発明の実施の１形態の回路結線図である。
【図２】（ａ）〜（ｅ）は図１の各部の波形図である。
【図３】従来装置の全体構成を説明する回路結線図であ
る。
【図４】図３の一部の詳細な回路結線図である。
【図５】（ａ）〜（ｄ）は図４の各部の波形図である。
【符号の説明】
４ 制御処理部
１０ 記憶部
１２ 電源部
１３ 電源状態検出部
１７ 書込禁止ゲート部BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit connection diagram according to an embodiment of the present invention. 2 (a) to 2 (e) are waveform diagrams of respective parts in FIG. FIG. 3 is a circuit connection diagram illustrating the entire configuration of a conventional device. FIG. 4 is a detailed circuit connection diagram of a part of FIG. 3; 5 (a) to 5 (d) are waveform diagrams of respective parts in FIG. [Description of Signs] 4 Control processing unit 10 Storage unit 12 Power supply unit 13 Power supply state detection unit 17 Write inhibit gate unit
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H02J 3/00 - 5/00 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. 7 , DB name) H02J 3/00-5/00
Claims (1)
タ構成の制御処理部に、前記区分開閉器の開閉及び制御
の状態情報が書換自在に書込まれる不揮発性の記憶部を
備えた配電線の開閉器制御装置において、 前記制御処理部の駆動電源の電圧と所定のしきい値の電
圧とを比較し，前記駆動電源の立上りにより前記駆動電
源の電圧が前記しきい値の電圧より高くなるまで電源不
安定の検出信号を出力する電源状態検出部と、 前記電源不安定の検出信号が出力される間前記記憶部の
書込みに関連する制御端子を制御禁止のレベルにクラン
プし，前記記憶部の書込みを禁止する書込禁止ゲート部
とを備えたことを特徴とする配電線の開閉器制御装置。(57) [Claim 1] Non-volatile nonvolatile information in which status information of opening and closing and control of the segmented switch is rewritably written to a control processing unit having a computer configuration for controlling the opening and closing of the segmented switch. In the distribution line switch control device provided with the storage unit, the voltage of the drive power supply of the control processing unit is compared with a voltage of a predetermined threshold value, and when the drive power supply rises, the voltage of the drive power supply is A power supply state detection unit that outputs a power supply instability detection signal until the voltage becomes higher than a threshold voltage, and prohibits control of a control terminal related to writing in the storage unit while the power supply instability detection signal is output. A write-protect gate unit that clamps to a level and prohibits writing to the storage unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23197898A JP3509569B2 (en) | 1998-08-18 | 1998-08-18 | Distribution line switchgear control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23197898A JP3509569B2 (en) | 1998-08-18 | 1998-08-18 | Distribution line switchgear control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000059997A JP2000059997A (en) | 2000-02-25 |
| JP3509569B2 true JP3509569B2 (en) | 2004-03-22 |
Family
ID=16932034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23197898A Expired - Fee Related JP3509569B2 (en) | 1998-08-18 | 1998-08-18 | Distribution line switchgear control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3509569B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4489913B2 (en) * | 2000-07-25 | 2010-06-23 | 株式会社平和 | Circuit board with electronic devices for gaming machines |
| JP5502311B2 (en) * | 2008-11-25 | 2014-05-28 | 株式会社東芝 | Slave station equipment for distribution line automation |
-
1998
- 1998-08-18 JP JP23197898A patent/JP3509569B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000059997A (en) | 2000-02-25 |
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