CN216212350U

CN216212350U - Power management chip and memory protection system

Info

Publication number: CN216212350U
Application number: CN202122304481.3U
Authority: CN
Inventors: 林立
Original assignee: Zhuhai Amicro Semiconductor Co Ltd
Current assignee: Zhuhai Amicro Semiconductor Co Ltd
Priority date: 2021-09-23
Filing date: 2021-09-23
Publication date: 2022-04-05
Anticipated expiration: 2031-09-23

Abstract

The utility model discloses a power management chip and a memory protection system, compared with the prior art, the power management chip and the memory protection system control a VCC power supply to be powered down before a VDD power supply when the system is powered down, so that the risk of uncontrollable circuit working logic when the VDD power supply drops below a normal working voltage under the condition of the prior power down can be avoided. Particularly, when the power-down speed of the VDD power supply is slow, the VCC power supply still supplies power to the memory, and if the memory is just in a working state at the moment, the data of the memory may be abnormal due to the disorder of the output of the communication interface.

Description

Power management chip and memory protection system

Technical Field

The utility model relates to the field of power-down protection of memories, in particular to a power management chip and a memory protection system.

Background

During the power-down process of the system, if the memory is just in a working state, such as reading or writing or erasing the contents in the memory, errors may be caused in the contents of the memory, which may be represented as data stored in the memory being rewritten, an incorrect writing of an operated memory block, and even an error occurring in an unoperated memory block. In general, the problem of memory errors in the power-down process can be solved by adopting the self-contained write protection of the memory. However, some electronic products are powered by a plurality of power supplies, and when a system is powered down, the power-down speeds of different power supplies are different and the power-down time sequence is not controlled, so that the self-contained write protection of the memory cannot provide better memory erasing protection.

SUMMERY OF THE UTILITY MODEL

In order to solve the problems, the utility model provides a power management chip and a memory protection system, which solve the problem of data abnormity possibly occurring in the power failure process of a memory by controlling the power failure time sequences of different power supplies. The specific technical scheme of the utility model is as follows:

a power management chip comprises a first power output port and a second power output port; the first power output port is used for outputting a VDD power supply and supplying power to the main control chip; the second power supply output port is used for outputting a VCC power supply and supplying power to the main control chip and the memory; the power management chip is used for configuring power-down time sequences of the VCC power supply and the VDD power supply, and when a system where the power management chip is located is powered down, the power management chip controls the VCC power supply to be powered down before the VDD power supply.

Compared with the prior art, the technical scheme has the advantages that the VCC power supply is configured by the power management chip and is powered down before the VDD power supply, so that the risk that the working logic of the circuit is uncontrollable when the VDD power supply falls below the normal working voltage under the condition of power down firstly can be avoided. Particularly, when the power-down speed of the VDD power supply is slow, the VCC power supply still supplies power to the memory, and if the memory is just in a working state at the moment, the data of the memory may be abnormal due to the disorder of the output of the communication interface.

A memory protection system comprises a main control chip, a memory and a power management chip; the main control chip is connected with the power management chip and the memory and used for executing a power-down protection process of the memory, and the main control chip is powered by a VCC power supply and a VDD power supply output by the power management chip; the memory is connected with the power management chip and the main control chip and used for storing data, and the memory is powered by a VCC power supply output by the power management chip; when the system is powered down, the VCC power supply is powered down before the VDD power supply.

Compared with the prior art, this technical scheme is in when the system falls the power failure, control VCC power falls the power failure before the VDD power, can avoid the VDD power and fall the uncontrollable risk of circuit working logic that exists when normal operating voltage is below under the circumstances of falling the power failure earlier. Particularly, when the power-down speed of the VDD power supply is slow, the VCC power supply still supplies power to the memory, and if the memory is just in a working state at the moment, the data of the memory may be abnormal due to the disorder of the output of the communication interface.

Further, the main control chip comprises an IO pin and a first SPI interface; and when the voltage value of the VCC power supply falls to a preset voltage value, the main control chip stops the IO pin operation and the first SPI interface operation. And stopping related operations of data transmission to prevent the memory from generating data exception.

Further, the memory comprises a second SPI interface, which is adapted to the first SPI interface; the main control chip and the memory communicate through the first SPI interface and the second SPI interface.

Drawings

FIG. 1 is a diagram illustrating a memory protection system according to an embodiment of the utility model.

Detailed Description

The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It should be understood that the following specific examples are illustrative only and are not intended to limit the utility model.

In the following description, specific details are given to provide a thorough understanding of the embodiments. However, it will be understood by those of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the embodiments.

In electronic products powered by a plurality of power supplies, the problems of uncontrollable power-down speeds and power-down time sequences of different power supplies exist mostly. For example, in a certain system, because the CPU core and the IO port need different voltages, two power supplies, namely, a VCC power supply and a VDD power supply, are required to ensure normal operation. It should be noted that the VCC power supply refers to a power supply voltage, that is, a voltage that is connected to a circuit and operates the circuit, and the VCC power supply may also supply power to an external device. The VDD power supply refers to an operating voltage, i.e., a voltage inside a device (or a chip), and generally, a VCC power supply voltage value is greater than a VDD power supply voltage value. The VCC power supply supplies power to the memory of the system, and the VDD power supply and the VCC power supply power to a main control chip of the system together. When the system is powered off, the VCC power supply and the VDD power supply start to be powered off randomly due to no corresponding control means, and which power supply starts to be powered off first cannot be determined. If the VDD power supply starts to power down before the VCC power supply, the memory is still above the normal operating voltage, and if the memory is just performing the read/write task again, the data exception is likely to occur. Since a logic error may have occurred during the power down of VDD power by the master resulting in the memory receiving the wrong command.

Therefore, the present invention provides a power management chip, where the power management chip includes a first power output port and a second power output port; the first power output port is used for outputting a VDD power supply and supplying power to the main control chip; the second power supply output port is used for outputting a VCC power supply and supplying power to the main control chip and the memory; the power management chip is used for configuring power-down time sequences of the VCC power supply and the VDD power supply, and when a system where the power management chip is located is powered down, the power management chip controls the VCC power supply to be powered down before the VDD power supply.

It should be noted that the main control chip is provided with a first power access port matched with the first power output port, and a second power access port matched with the second power output port, and the first power access port and the second power access port respectively provide a VDD power supply and a VCC power supply for the main control chip to transmit the power management chip. Similarly, the memory is provided with a third power supply access port matched with the second power supply output port and used for providing a VCC power supply transmitted by the power supply management chip for the memory. The power management chip is configured with the VCC power supply which is powered down before the VDD power supply, so that the risk of abnormal data of the memory caused by disordered communication interface output which may occur when the VCC power supply supplies power to the memory and the memory is just in a working state under the condition that the VDD power supply is powered down first can be avoided.

The embodiment of the utility model provides a control method of a power management chip, which comprises the following steps: when a system where a power management chip is located is powered off, the power management chip controls the VCC power supply to be powered off firstly, when the voltage value of the VCC power supply falls to a preset voltage value, a power-off protection process of a memory is triggered, and then after the power-off protection process of the memory is finished, the power management chip controls the VDD power supply to be powered off; the VCC power supply and the VDD power supply power for the main control chip, and the VCC power supply supplies power for the memory.

As one embodiment, the memory power-down protection process includes: and the power management chip controls the power-down process of the VCC power supply, so that the main control chip sends out an instruction for stopping the operation related to the data transmission of the memory when detecting that the voltage value of the VCC power supply is equal to a preset voltage value. And stopping the related operation of data transmission, and ensuring that the memory does not execute the tasks related to the data transmission under the condition of low voltage, thereby avoiding the data exception of the memory to the maximum extent.

As shown in fig. 1, an embodiment of the present invention provides a memory protection system, where the system includes a main control chip, a memory, and the power management chip; the main control chip is connected with the power management chip and the memory and used for executing a power-down protection process of the memory, and the main control chip is powered by a VCC power supply and a VDD power supply output by the power management chip; the memory is connected with the power management chip and the main control chip and used for storing data, and the memory is powered by a VCC power supply output by the power management chip; when the system is powered down, the VCC power supply is powered down before the VDD power supply.

It should be noted that the memory refers to a non-volatile memory (non-volatile memory), such as a non-FLASH, nand-FLASH, etc., for storing data. Nonvolatile memory technology is a technology that data is not lost when a system is shut down or suddenly and unexpectedly shut down, and plays a key role in the system, such as storage of code and storage of key data. A system power down during the operation of the memory, or the erasing of the memory, may cause errors in the contents of the memory. The system power-down refers to a process that the system voltage changes from a normal value to 0, and since the process is not completed instantly, when the voltage begins to drop, each device in the system can continue to do its own things until the voltage drops below the actual working voltage, and the system stops working.

For example, the nominal operating voltage of the memory is 3.3V-2.7V, and the memory can still operate normally when the voltage drops from 3.3V to 2.7V. However, if one goes further down from 2.7V, the memory can still operate due to a certain voltage support, but it will be in an unstable state, i.e. it may still work, but it is not guaranteed that the working result is correct. For example, when a command to erase data at an a address is received, the a address may be resolved to a B address, and then the data at the B address may be erased, or a command to write the a address may be received but written to the B address. Therefore, to make the memory reliable and stable, power down safety under various scenes must be ensured. For example, a system cannot be started due to random power failure in the updating process of the system, or the power failure occurs in the process of normally reading and writing the memory, most data being transmitted is lost, but other data of the memory cannot be mistaken, otherwise, the data is lost if the data is not mistaken, and the data cannot be started if the data is directly changed into the brick if the data is serious.

When the circuit is powered by multiple power supplies, referring to fig. 1, there is a risk if the main power supply VDD is first turned off, and then the memory power supply VCC is turned off. The specific reason is as described above, so the power-down sequence of the VCC power supply and the VDD power supply should be configured appropriately.

As one embodiment, the main control chip includes an IO (INPUT/OUTPUT) pin and a first SPI (Serial Peripheral Interface), where the IO pin and the first SPI are both used for data interaction between the main control chip and the memory. And when the voltage value of the VCC power supply falls to a preset voltage value, the main control chip stops the IO pin operation and the first SPI interface operation. Therefore, as the data transmission is stopped, the safety of the data in the memory can be ensured even if the voltage value of the VCC power supply is reduced to be lower than the working voltage value of the memory subsequently. It should be noted that the memory includes a second SPI interface adapted to the first SPI interface, and the main control chip and the memory communicate with each other through the first SPI interface and the second SPI interface. When the main control chip stops the operation of the first SPI interface, the second SPI interface naturally also stops because there is no data transmission. Then, after the main control chip stops the related operation of data transmission, the power management chip controls the power-down of the VDD power supply. At this time, the communication between the main control chip and the memory is stopped, and the power-down behavior of the VDD power supply is safe for the memory.

The embodiment of the utility model provides a memory protection method, which comprises the following steps: when the system is powered off, the system firstly controls the VCC power supply to be powered off, then executes the power-off protection process of the memory, and controls the VDD power supply to be powered off after the power-off protection process of the memory is finished; the VCC power supply and the VDD power supply power for the main control chip, and the VCC power supply supplies power for the memory.

As one embodiment, the memory power-down protection process includes: the system is in the control the in-process that the VCC power supply falls down, when the system detects the voltage value of VCC power supply falls to predetermineeing the voltage value, the system stops IO pin operation and first SPI interface operation. As described above, when the nominal operating voltage of the memory is 3.3V-2.7V, the preset voltage value may be preferably set to 3.0V. When the voltage value of the VCC power supply drops to 3.0V, the related operation of data transmission is stopped, so that the operation of the memory can be stopped before the voltage value of the VCC power supply drops to the normal working voltage of the memory, and under the condition of no operation, the content error of the memory can be avoided. Meanwhile, the time for executing the power-down protection process of the memory is reserved, and the phenomenon that the memory is subjected to abnormal data tampering due to the fact that the VDD power supply starts to be powered down when the main control chip does not stop related operations of data transmission is avoided, and the memory receives an error command.

As one embodiment, the protection method further includes: before the system is powered down, the system configures the power-down time sequences of the VCC power supply and the VDD power supply through the power management chip, and configures the VCC power supply to be powered down before the VDD power supply is powered down when the system is powered down. The Power Management Integrated Circuits (PMICs) perform functions of converting, distributing, detecting and other Power Management functions in the electronic device system.

Compared with the prior art, the power management chip controls the VCC power supply to power down before the VDD power supply, so that the risk of uncontrollable working logic of the circuit when the VDD power supply falls below the normal working voltage under the condition of power down before the VDD power supply is controlled can be avoided. Particularly, when the power-down speed of the VDD power supply is slow, the VCC power supply still supplies power to the memory, and if the memory is just in a working state at the moment, the data of the memory may be abnormal due to the disorder of the output of the communication interface.

In addition, in the description of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the utility model has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power management chip is characterized in that the power management chip comprises a first power output port and a second power output port; wherein the content of the first and second substances,

the first power supply output port is used for outputting a VDD power supply and supplying power to the main control chip;

the second power supply output port is used for outputting a VCC power supply and supplying power to the main control chip and the memory;

the power management chip is used for configuring power-down time sequences of the VCC power supply and the VDD power supply, and when a system where the power management chip is located is powered down, the power management chip controls the VCC power supply to be powered down before the VDD power supply.

2. A memory protection system, comprising a master chip, a memory, and the power management chip of claim 1; wherein the content of the first and second substances,

the main control chip is connected with the power management chip and the memory and used for executing a power-down protection process of the memory, and the main control chip is powered by a VCC power supply and a VDD power supply output by the power management chip;

the memory is connected with the power management chip and the main control chip and used for storing data, and the memory is powered by a VCC power supply output by the power management chip;

when the system is powered down, the VCC power supply is powered down before the VDD power supply.

3. The memory protection system according to claim 2, wherein the main control chip comprises an IO pin and a first SPI interface; and when the voltage value of the VCC power supply falls to a preset voltage value, the main control chip stops the IO pin operation and the first SPI interface operation.

4. A memory protection system according to claim 3, wherein said memory includes a second SPI interface, said second SPI interface being compatible with said first SPI interface; the main control chip and the memory communicate through the first SPI interface and the second SPI interface.