JP2018029149A - Power semiconductor device and manufacturing method thereof - Google Patents

Power semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP2018029149A
JP2018029149A JP2016161092A JP2016161092A JP2018029149A JP 2018029149 A JP2018029149 A JP 2018029149A JP 2016161092 A JP2016161092 A JP 2016161092A JP 2016161092 A JP2016161092 A JP 2016161092A JP 2018029149 A JP2018029149 A JP 2018029149A
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
power semiconductor
power
die pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2016161092A
Other languages
Japanese (ja)
Other versions
JP6667401B2 (en
Inventor
隆之 清水
Takayuki Shimizu
隆之 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2016161092A priority Critical patent/JP6667401B2/en
Publication of JP2018029149A publication Critical patent/JP2018029149A/en
Application granted granted Critical
Publication of JP6667401B2 publication Critical patent/JP6667401B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor device that has a uniform thickness insulator without making insulator thickness thicker.SOLUTION: The power semiconductor device comprises a lead frame encapsulated in resin having a die pad on which a power device is mounted and a lead which is placed by facing to the die pad and on which a control device is mounted, and a compression insulating plate which is provided such that the power device contacts on a rear surface contrary to a main surface having the power device mounted, and which is composed of a granular resin compression plate.SELECTED DRAWING: Figure 5

Description

本発明は電力用半導体装置に関し、特に、リードフレームに搭載された電力用半導体装置に関する。   The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device mounted on a lead frame.

電力用半導体装置は、家電機器、産業用機械等において、比較的大きな電力を制御、整流するために利用されている。使用時に発熱するため、電力半導体装置には放熱性が要求される。また数千Ｖ以上の高電圧が印加されることから電力用半導体装置と外部との間で絶縁が必要となる。   Power semiconductor devices are used to control and rectify relatively large power in home appliances, industrial machines, and the like. Since heat is generated during use, heat dissipation is required for the power semiconductor device. In addition, since a high voltage of several thousand volts or more is applied, insulation is required between the power semiconductor device and the outside.

ここで、ＩＰＭ(Intelligent Power Module)は電力用デバイスと制御用デバイスとを備えたモジュールである。配線材料にリードフレームを用いる場合、電力用デバイスと制御用デバイスは物理的に切り離されたダイパッド上にそれぞれ搭載され、電力用デバイスは電力用金属細線でリードフレームと電気的に接続され、制御用デバイスは金属細線でリードフレームおよび電力用デバイスと電気的に接続される。   Here, the IPM (Intelligent Power Module) is a module including a power device and a control device. When a lead frame is used as the wiring material, the power device and the control device are mounted on a physically separated die pad, and the power device is electrically connected to the lead frame with a power metal thin wire for control purposes. The device is electrically connected to the lead frame and the power device with a fine metal wire.

電力用デバイスの発熱に対する放熱構造としては様々な手法がある。全体を封止樹脂によって覆ったディスクリートＩＣパッケージのように、電力用半導体装置で最もシンプルな構造は、高放熱かつ絶縁性を有する封止樹脂を用いて、放熱部としての役割も果たす絶縁部を封止樹脂で薄く形成したフルモールド構造となる。   There are various methods for dissipating heat generated by power devices. The simplest structure of a power semiconductor device, such as a discrete IC package that is entirely covered with a sealing resin, uses a sealing resin that has high heat dissipation and insulation, and has an insulating part that also serves as a heat dissipation part. The full mold structure is formed thinly with a sealing resin.

樹脂封止には、１種類の樹脂を用いたトランスファーモールド法が使用されることが多いが、この手法では厚みの薄い絶縁部を形成する際に、封止樹脂が均一に行き渡らず、均一な厚さの絶縁部を形成することが困難であった。   In resin sealing, a transfer molding method using one kind of resin is often used. However, in this method, when forming a thin insulating portion, the sealing resin is not uniformly distributed and is uniform. It was difficult to form a thick insulating portion.

これに対し、特許文献１ではダイパッドの裏面にシート状の絶縁材を貼り付けて放熱板上に搭載した後、樹脂で封止した構成が開示されている。この構成は放熱部が放熱板で構成される構造には適用できるが、放熱部が絶縁部で構成されるフルモールド構造には適用できない。   On the other hand, Patent Document 1 discloses a configuration in which a sheet-like insulating material is attached to the back surface of a die pad and mounted on a heat sink, and then sealed with a resin. This configuration can be applied to a structure in which the heat radiating portion is constituted by a heat radiating plate, but cannot be applied to a full mold structure in which the heat radiating portion is constituted by an insulating portion.

また、特許文献２ではフルモールド構造の半導体装置において、放熱部としての役割を果たす厚みの薄い絶縁部をトランスファーモールド法で他の部分と同時に形成する構成が開示されている。一般に、フィラーを含む粘性のある弾性体を、後に絶縁部となる狭い間隙部分に充填する場合、フィラーの目詰まりを防ぐため、間隙厚さの１／２〜１／３程度の直径のフィラーは使用することができない。フルモールド構造の電力用半導体装置にとって、絶縁部には放熱性が必要であるが、絶縁部にフィラーを充填するためには、上述した理由から、フィラー直径の３倍より大きい厚さの絶縁部（間隙）としなければならない。特許文献２には、絶縁部の厚さについては言及がないが、絶縁部を厚くすると、モジュールのサイズが大きくなると言う問題があった。   Patent Document 2 discloses a configuration in which a thin insulating portion serving as a heat radiating portion is formed simultaneously with other portions by a transfer molding method in a semiconductor device having a full mold structure. Generally, when a viscous elastic body containing a filler is filled into a narrow gap portion that will later become an insulating portion, a filler having a diameter of about 1/2 to 1/3 of the gap thickness is used to prevent clogging of the filler. Cannot be used. For a power semiconductor device having a full mold structure, the insulating portion needs to have heat dissipation. However, in order to fill the insulating portion with a filler, the insulating portion having a thickness larger than three times the filler diameter is used for the reason described above. (Gap). Patent Document 2 does not mention the thickness of the insulating part, but there is a problem that the module size increases when the insulating part is thickened.

特開２００２−１６４４９２号公報JP 2002-164492 A 特開平１−２６８１５９号公報JP-A-1-268159

本発明は上記のような問題を解決するためになされたものであり、ダイパッドの裏面側の絶縁部の厚みを厚くすることなく、均一な厚さの絶縁部を有する電力用半導体装置を提供することを目的とする。   The present invention has been made to solve the above-described problems, and provides a power semiconductor device having an insulating portion having a uniform thickness without increasing the thickness of the insulating portion on the back surface side of the die pad. For the purpose.

本発明に係る電力用半導体装置は、電力用デバイスが搭載されたダイパッドと、前記ダイパッドに対向して配置され、制御用デバイスが搭載されたリードと、を有したリードフレームを樹脂で封止した電力用半導体装置であって、前記電力用デバイスが搭載された主面とは反対側の前記ダイパッドの裏面に接するように設けられた、粒状樹脂の圧縮板で構成される圧縮絶縁板を備えている。   A power semiconductor device according to the present invention has a lead frame having a die pad on which a power device is mounted and a lead on which the control device is mounted facing the die pad and sealed with a resin. A power semiconductor device, comprising: a compression insulating plate formed of a granular resin compression plate provided in contact with the back surface of the die pad opposite to the main surface on which the power device is mounted. Yes.

本発明に係る電力用半導体装置によれば、ダイパッドの裏面側には圧縮絶縁板が存在しているので、絶縁部が均一な厚さとなり、また、封止樹脂が流入しにくい隙間が存在しないので、ボイドおよびウェルドなどが発生することを抑制でき、電界集中が起こりにくい構造となって、高い絶縁耐圧を達成できる。   According to the power semiconductor device of the present invention, since the compression insulating plate exists on the back side of the die pad, the insulating portion has a uniform thickness and there is no gap in which the sealing resin does not easily flow. Therefore, generation of voids, welds, and the like can be suppressed, and electric field concentration is unlikely to occur, so that a high withstand voltage can be achieved.

リードフレーム状態の電力用半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device for electric power of a lead frame state. リードフレーム状態の電力用半導体装置を下金型内に載置した状態を示す断面図である。It is sectional drawing which shows the state which mounted the power semiconductor device of the lead frame state in the lower metal mold | die. 圧縮絶縁板の構成を模式的に示す図である。It is a figure which shows the structure of a compression insulating board typically. 金型内に封止樹脂を注入する工程を示す断面図である。It is sectional drawing which shows the process of inject | pouring sealing resin in a metal mold | die. 本発明に係る実施の形態１の電力用半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the power semiconductor device of Embodiment 1 which concerns on this invention. リードフレーム状態の電力用半導体装置を下金型内に載置した状態を示す断面図である。It is sectional drawing which shows the state which mounted the power semiconductor device of the lead frame state in the lower metal mold | die. 金型内に封止樹脂を注入する工程を示す断面図である。It is sectional drawing which shows the process of inject | pouring sealing resin in a metal mold | die. 本発明に係る実施の形態２の電力用半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device for electric power of Embodiment 2 which concerns on this invention. リードフレーム状態の電力用半導体装置を下金型内に載置した状態を示す断面図である。It is sectional drawing which shows the state which mounted the power semiconductor device of the lead frame state in the lower metal mold | die. 金型内に封止樹脂を注入する工程を示す断面図である。It is sectional drawing which shows the process of inject | pouring sealing resin in a metal mold | die. 本発明に係る実施の形態３の電力用半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the power semiconductor device of Embodiment 3 which concerns on this invention. 厚みの薄い絶縁部を形成する際の問題点を説明する図である。It is a figure explaining the problem at the time of forming a thin insulating part. 本発明に係る実施の形態３の電力用半導体装置の部分断面図である。It is a fragmentary sectional view of the power semiconductor device of Embodiment 3 which concerns on this invention. 絶縁部の厚さに対する放熱特性を示す図である。It is a figure which shows the thermal radiation characteristic with respect to the thickness of an insulation part. 本発明に係る実施の形態４の電力用半導体装置の部分断面図である。It is a fragmentary sectional view of the power semiconductor device of Embodiment 4 which concerns on this invention. リードフレーム状態の電力用半導体装置を下金型内に載置した状態を示す断面図である。It is sectional drawing which shows the state which mounted the power semiconductor device of the lead frame state in the lower metal mold | die. 金型内に封止樹脂を注入する工程を示す断面図である。It is sectional drawing which shows the process of inject | pouring sealing resin in a metal mold | die. 本発明に係る実施の形態５の電力用半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the power semiconductor device of Embodiment 5 which concerns on this invention. 一般的なフルモールド構造の電力用半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device for electric power of a general full mold structure. 電力用半導体装置を裏面側から見た外観図である。It is the external view which looked at the semiconductor device for electric power from the back side.

＜はじめに＞
発明の実施の形態の説明に先立って、一般的なフルモールド構造の電力用半導体装置の構成について説明する。 <Introduction>
Prior to the description of the embodiment of the invention, the configuration of a general power semiconductor device having a full mold structure will be described.

図１９は、一般的なフルモールド構造の電力用半導体装置９０の構成を示す断面図である。図１９に示すように電力用半導体装置９０は、全体が封止樹脂によって封止され、対向する２つの側面のうち、一方の側面からパワーアウターリード１ｃが突出し、他方の側面から制御アウターリード１ｂが突出している。パワーアウターリード１ｃおよび制御アウターリード１ｂは、窪み部１１が設けられた電力用半導体装置９０の裏面側に向けて折り曲げられている。   FIG. 19 is a cross-sectional view showing a configuration of a power semiconductor device 90 having a general full mold structure. As shown in FIG. 19, the power semiconductor device 90 is entirely sealed with a sealing resin, and the power outer lead 1 c protrudes from one of the two opposing side surfaces, and the control outer lead 1 b from the other side surface. Is protruding. The power outer lead 1c and the control outer lead 1b are bent toward the back side of the power semiconductor device 90 provided with the recess 11.

パワーアウターリード１ｃは、パッケージ内においてパワーインナーリード１ｅに連続し、パワーインナーリード１ｅはダイパッド１ａに連続している。また、制御アウターリード１ｂはパッケージ内において制御インナーリード１ｄに連続している。これら一連のパワーアウターリード１ｃ、パワーインナーリード１ｅ、ダイパッド１ａおよび一連の制御アウターリード１ｂ、制御インナーリード１ｄはリードフレームを構成している。   The power outer lead 1c is continuous with the power inner lead 1e in the package, and the power inner lead 1e is continuous with the die pad 1a. The control outer lead 1b is continuous with the control inner lead 1d in the package. The series of power outer leads 1c, power inner leads 1e, die pad 1a, and series of control outer leads 1b, control inner leads 1d constitute a lead frame.

ダイパッド１ａ上にはＲＣ−ＩＧＢＴ（Reverse Conducting-Insulated Gate Bipolar Transistor）５が搭載され、制御インナーリード１ｄ上にはＩＣチップ６が搭載されている。ダイパッド１ａとＲＣ−ＩＧＢＴ５は鉛（Ｐｂ）フリーはんだＳＤにより接合され、制御インナーリード１ｄとＩＣチップ６とは導電性接着剤ＡＤにより接合されている。   An RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) 5 is mounted on the die pad 1a, and an IC chip 6 is mounted on the control inner lead 1d. The die pad 1a and the RC-IGBT 5 are joined by lead (Pb) free solder SD, and the control inner lead 1d and the IC chip 6 are joined by a conductive adhesive AD.

ＲＣ−ＩＧＢＴ５のはんだ接合面とは反対側の表面には、図示されないソース電極およびゲート電極が設けられ、ソース電極は直径０．３ｍｍのアルミワイヤ７を介してパワーインナーリード１ｅに電気的に接続されている。また、ゲート電極は、アルミワイヤ７よりも直径が小さい細線ワイヤ８を介してＩＣチップ６と電気的に接続されている。なお、ＩＣチップ６と制御インナーリード１ｄとは細線ワイヤ８を介して電気的に接続されている。なお、細線ワイヤ８には例えば金、または金を主成分とする合金、Ａｇ、Ｃｕなどを用いることができ、アルミワイヤ７はアルミニウム（Ａｌ）以外に、Ａｌを主成分とする合金、Ａｇ、Ｃｕなど他の金属、合金を用いることができる。   A source electrode and a gate electrode (not shown) are provided on the surface opposite to the solder joint surface of the RC-IGBT 5, and the source electrode is electrically connected to the power inner lead 1 e through an aluminum wire 7 having a diameter of 0.3 mm. Has been. The gate electrode is electrically connected to the IC chip 6 through a fine wire 8 having a diameter smaller than that of the aluminum wire 7. The IC chip 6 and the control inner lead 1d are electrically connected via a thin wire 8. For example, gold or an alloy containing gold as a main component, Ag, Cu or the like can be used for the thin wire 8, and the aluminum wire 7 can be made of an alloy containing Al as a main component other than aluminum (Al), Ag, Cu, etc. Other metals such as Cu and alloys can be used.

ダイパッド１ａは、パワーアウターリード１ｃおよびパワーインナーリード１ｅに比べて、ＲＣ−ＩＧＢＴ５の搭載面とは反対のダイパッド裏面側に向けて低くなるように段差が設けられている。これは、ダイパッド１ａの裏面側に存在する絶縁部９の厚みを薄くして、放熱部としても機能させるためである。なお、絶縁部９を含めて電力用半導体装置９０を樹脂封止する封止樹脂には、樹脂と高熱伝導性フィラーの混合物で構成される高熱伝導樹脂を使用する。高熱伝導樹脂は、フィラー量が多いほど熱伝導率は増加する。   The die pad 1a is provided with a step so as to become lower toward the back side of the die pad opposite to the mounting surface of the RC-IGBT 5 compared to the power outer lead 1c and the power inner lead 1e. This is to reduce the thickness of the insulating portion 9 existing on the back side of the die pad 1a so as to function as a heat radiating portion. Note that as the sealing resin for resin-sealing the power semiconductor device 90 including the insulating portion 9, a high thermal conductive resin composed of a mixture of a resin and a high thermal conductive filler is used. High thermal conductivity resin increases thermal conductivity as the amount of filler increases.

高熱伝導樹脂の樹脂は、熱可塑性樹脂でも熱硬化性樹脂でも良く、接着性を得ることができる樹脂でれば良い。また、フィラーは無機材料の粒子であるＳｉＯ２、Ａｌ２Ｏ３、ＢＮなど電気絶縁性と高熱伝導性が両立する材料であれば良い。 The resin of the high thermal conductive resin may be a thermoplastic resin or a thermosetting resin, and may be a resin capable of obtaining adhesiveness. The filler may be any material that has both electrical insulation and high thermal conductivity, such as SiO 2 , Al 2 O 3 , and BN, which are particles of inorganic material.

図２０は電力用半導体装置９０を裏面側から見た外観図である。図２０におけるＡ−Ａ線での断面図が、図１９に相当する。   FIG. 20 is an external view of the power semiconductor device 90 as seen from the back side. A sectional view taken along line AA in FIG. 20 corresponds to FIG.

＜実施の形態１＞
以下、図１〜図５を用いて本発明に係る実施の形態１について説明する。図１はＲＣ−ＩＧＢＴ５およびＩＣチップ６を搭載し、アルミワイヤ７および細線ワイヤ８をワイヤボンディングしたリードフレーム状態の電力用半導体装置を示す断面図である。なお、以下においては図１９および図２０を用いて説明した電力用半導体装置９０と同一の構成については同一の符号を付し、重複する説明は省略する。 <Embodiment 1>
Hereinafter, Embodiment 1 according to the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing a power semiconductor device in a lead frame state in which an RC-IGBT 5 and an IC chip 6 are mounted and an aluminum wire 7 and a fine wire 8 are wire-bonded. In the following, the same components as those of the power semiconductor device 90 described with reference to FIGS. 19 and 20 are denoted by the same reference numerals, and redundant description is omitted.

図２はリードフレーム状態の電力用半導体装置を下金型ＬＭ内に載置した状態を示しているが、下金型ＬＭの底面上には、粒状の封止樹脂を圧縮して薄板状にした圧縮絶縁板２０（圧縮板）が載置されている。圧縮絶縁板２０のダイパッド１ａ側の主面は熱硬化性樹脂の樹脂膜ＲＣＴで覆われており、ダイパッド１ａの裏面が樹脂膜ＲＣＴに接するように、リードフレーム状態の電力用半導体装置が下金型ＬＭ内に載置される。   FIG. 2 shows a state in which the power semiconductor device in the lead frame state is placed in the lower mold LM. On the bottom surface of the lower mold LM, a granular sealing resin is compressed into a thin plate shape. The compressed insulating plate 20 (compressed plate) is placed. The main surface of the compression insulating plate 20 on the die pad 1a side is covered with a resin film RCT of thermosetting resin, and the power semiconductor device in the lead frame state is a lower metal so that the back surface of the die pad 1a is in contact with the resin film RCT. Placed in mold LM.

圧縮絶縁板２０は下金型ＬＭの底面全体を覆う大きさを有しており、その厚さは２００〜５００μｍ程度である。また、樹脂膜ＲＣＴの厚さは２０〜５０μｍであり、平均フィラー粒径と同じ程度で良い。   The compression insulating plate 20 has a size that covers the entire bottom surface of the lower mold LM, and has a thickness of about 200 to 500 μm. Further, the thickness of the resin film RCT is 20 to 50 μm and may be the same as the average filler particle size.

圧縮絶縁板２０は、粒径が２２０μｍ以下で、例えばエポキシ等の熱硬化性樹脂で構成される粒状樹脂（フィラーはシリカまたは窒化ボロン）を、１５０℃以上の温度に保ち１ＭＰａ以上の圧力で圧縮することで形成される。   The compression insulating plate 20 has a particle size of 220 μm or less, and compresses a granular resin (filler is silica or boron nitride) made of a thermosetting resin such as epoxy at a pressure of 1 MPa or more while maintaining a temperature of 150 ° C. or more. It is formed by doing.

図３は、図２における“Ａ”部の詳細図であり、圧縮絶縁板２０の構成を模式的に示しており、粒状樹脂ＰＲが圧縮されて潰され、板状に成型されている。   FIG. 3 is a detailed view of the “A” portion in FIG. 2, schematically showing the configuration of the compression insulating plate 20. The granular resin PR is compressed and crushed and molded into a plate shape.

図２に示すように、リードフレーム状態の電力用半導体装置を下金型ＬＭ内に載置し、上金型ＵＭと下金型ＬＭとを合わせて金型を閉じ、トランスファーモールド法より金型内に封止樹脂を流入する。この封止樹脂には、圧縮絶縁板２０の形成に用いた樹脂と同じものを用いることができる。   As shown in FIG. 2, the power semiconductor device in the lead frame state is placed in the lower mold LM, the upper mold UM and the lower mold LM are combined and the mold is closed, and the mold is transferred by the transfer mold method. The sealing resin flows into the inside. As the sealing resin, the same resin as used for forming the compression insulating plate 20 can be used.

図４は、閉じた金型内に、注入ゲートＧＡを介して溶融した状態の封止樹脂ＲＳを注入する工程を示している。図４に示されるように、上金型ＵＭと下金型ＬＭとで構成されるキャビティ内全体に封止樹脂ＲＳを充填し、キャビティ内で封止樹脂を硬化させてパッケージを形成し、金型を開いてパッケージを取り出す。その後、ポストキュアなど追加硬化過程を経てパッケージの外形を加工し、また、パワーアウターリード１ｃおよび制御アウターリード１ｂをパッケージの裏面側に向けるように曲げ加工することで、図５に示す電力用半導体装置１００が完成する。   FIG. 4 shows a process of injecting the molten sealing resin RS into the closed mold through the injection gate GA. As shown in FIG. 4, the entire cavity formed by the upper mold UM and the lower mold LM is filled with the sealing resin RS, and the sealing resin is cured in the cavity to form a package. Open the mold and remove the package. Thereafter, the outer shape of the package is processed through an additional curing process such as post-cure, and the power outer lead 1c and the control outer lead 1b are bent so as to face the back side of the package, whereby the power semiconductor shown in FIG. The apparatus 100 is completed.

一般的にトランスファーモールド法では、パッケージの側面から内部に向かって封止樹脂を注入する。このときダイパッドの裏面と金型の底面との間の隙間（後に絶縁部となる）が狭いので、トランスファーモールドでは流動抵抗およびフィラーの目詰まりによって封止樹脂が流入しにくい。その結果、絶縁部への封止樹脂の充填が遅れたり、最終充填部位となることでボイドおよびウェルドなどが発生し、絶縁耐圧が低下する可能性があった。しかし、上述した実施の形態１の電力用半導体装置１００では、予め、下金型ＬＭの底面上に圧縮絶縁板２０を搭載し、圧縮絶縁板２０にダイパッド１ａの裏面が接するようにリードフレーム状態の電力用半導体装置を載置するので、ダイパッド１ａの裏面には均一な厚さの絶縁部が設けられることとなる。また、封止樹脂が流入しにくい隙間が存在せず、ボイドおよびウェルドなどが発生することを抑制できる。   Generally, in the transfer molding method, a sealing resin is injected from the side surface of the package toward the inside. At this time, since the gap between the back surface of the die pad and the bottom surface of the mold (which will later become an insulating portion) is narrow, in the transfer mold, the sealing resin hardly flows in due to flow resistance and filler clogging. As a result, the filling of the sealing resin into the insulating portion is delayed or a final filling portion is generated, so that voids and welds may occur, and the withstand voltage may decrease. However, in the power semiconductor device 100 according to the first embodiment described above, the compression insulating plate 20 is previously mounted on the bottom surface of the lower mold LM, and the lead frame state is such that the back surface of the die pad 1a is in contact with the compression insulating plate 20. Since the power semiconductor device is mounted, an insulating portion having a uniform thickness is provided on the back surface of the die pad 1a. Moreover, there is no gap in which the sealing resin is difficult to flow in, and generation of voids and welds can be suppressed.

また、圧縮絶縁板２０のダイパッド１ａ側の主面は樹脂膜ＲＣＴで覆われているので、圧縮絶縁板２０とダイパッド１ａの裏面との密着性が向上し、ボイドの発生をさらに抑制して、電界集中が起こりにくい構造となって、高い絶縁耐圧を達成できる。   Moreover, since the main surface of the compression insulating plate 20 on the die pad 1a side is covered with the resin film RCT, adhesion between the compression insulating plate 20 and the back surface of the die pad 1a is improved, and generation of voids is further suppressed. A structure in which electric field concentration hardly occurs, and a high withstand voltage can be achieved.

＜実施の形態２＞
次に、図６〜図８を用いて本発明に係る実施の形態２について説明する。なお、以下においては図１９および図２０を用いて説明した電力用半導体装置９０と同一の構成については同一の符号を付し、重複する説明は省略する。 <Embodiment 2>
Next, Embodiment 2 according to the present invention will be described with reference to FIGS. In the following, the same components as those of the power semiconductor device 90 described with reference to FIGS. 19 and 20 are denoted by the same reference numerals, and redundant description is omitted.

図６は、図１に示したリードフレーム状態の電力用半導体装置を下金型ＬＭ内に載置した状態を示しており、下金型ＬＭの底面上には、粒状の封止樹脂を圧縮して薄板状にした圧縮絶縁板２０が載置されている。なお、図示は省略しているが上金型ＵＭには円筒状の可動ブロックが組み込まれており、上金型ＵＭと下金型ＬＭとを合わせて構成されるキャビティ内に可動ブロックを挿入することができる。なお、可動ブロックの抜き差しにはサーボモータ等を用いるが、可動ブロックの技術は公知であるので説明は省略する。   FIG. 6 shows a state where the power semiconductor device in the lead frame state shown in FIG. 1 is placed in the lower mold LM, and a granular sealing resin is compressed on the bottom surface of the lower mold LM. Then, the compression insulating plate 20 made into a thin plate shape is placed. Although not shown, a cylindrical movable block is incorporated in the upper mold UM, and the movable block is inserted into a cavity formed by combining the upper mold UM and the lower mold LM. be able to. A servo motor or the like is used for inserting / removing the movable block. However, since the technique of the movable block is well known, description thereof is omitted.

図７は、閉じた金型内に、注入ゲートＧＡ１およびＧＡ２を介して、それぞれ溶融した状態の２種類の封止樹脂ＲＳ１（第１の封止樹脂）および封止樹脂ＲＳ２（第２の封止樹脂）を注入する工程を示している。すなわち、上金型ＵＭと下金型ＬＭとで構成されるキャビティには、対向する２つの側面のうち、一方の側面から注入ゲートＧＡ１を介して溶融した状態の封止樹脂ＲＳ１が注入され、他方の側面から注入ゲートＧＡ２を介して溶融した状態の封止樹脂ＲＳ２が注入される。この封止樹脂ＲＳ１およびＲＳ２の一方には、圧縮絶縁板２０の形成に用いた樹脂と同じものを用いることができる。   FIG. 7 shows two types of sealing resin RS1 (first sealing resin) and sealing resin RS2 (second sealing resin) in a melted state in a closed mold via injection gates GA1 and GA2. The step of injecting a (stopping resin) is shown. That is, in the cavity constituted by the upper mold UM and the lower mold LM, the sealing resin RS1 in a melted state is injected from one of the two side surfaces through the injection gate GA1, The molten sealing resin RS2 is injected from the other side surface through the injection gate GA2. As one of the sealing resins RS1 and RS2, the same resin as that used for forming the compression insulating plate 20 can be used.

ここで、ＲＣ−ＩＧＢＴ５側のキャビティ側面に設けた注入ゲートＧＡ１から注入される封止樹脂ＲＳ１は、５０Ｐａ・ｓｅｃ以下の粘度を有し、ＩＣチップ６側のキャビティ側面に設けた注入ゲートＧＡ２から注入される封止樹脂ＲＳ２は、２０Ｐａ・ｓｅｃ以下の粘度を有している。なお、封止樹脂ＲＳ１およびＲＳ２を同じ樹脂とした場合は、フィラー量によって粘度を調整し、ＩＣチップ６側から注入される樹脂の粘度を、ＲＣ−ＩＧＢＴ５側から注入される樹脂の粘度よりも小さくする。   Here, the sealing resin RS1 injected from the injection gate GA1 provided on the cavity side surface on the RC-IGBT5 side has a viscosity of 50 Pa · sec or less, and from the injection gate GA2 provided on the cavity side surface on the IC chip 6 side. The sealing resin RS2 to be injected has a viscosity of 20 Pa · sec or less. When the sealing resins RS1 and RS2 are the same resin, the viscosity is adjusted by the amount of filler, and the viscosity of the resin injected from the IC chip 6 side is higher than the viscosity of the resin injected from the RC-IGBT5 side. Make it smaller.

これにより、ＩＣチップ６に接続される細線ワイヤ８のワイヤの変形を抑制することができる。なお、封止樹脂ＲＳ２のフィラー量を、封止樹脂ＲＳ１のフィラー量よりも少なくすることで、封止樹脂ＲＳ２の接着力は封止樹脂ＲＳ１の接着力よりも強くなる。   Thereby, the deformation | transformation of the wire of the fine wire 8 connected to IC chip 6 can be suppressed. In addition, the adhesive force of sealing resin RS2 becomes stronger than the adhesive force of sealing resin RS1 by making the filler amount of sealing resin RS2 smaller than the filler amount of sealing resin RS1.

また、封止樹脂ＲＳ１およびＲＳ２の注入は同時に行い、注入圧力などの注入条件も同じとする。なお、ＩＣチップ６側から注入する封止樹脂ＲＳ２の注入速度を封止樹脂ＲＳ１の注入速度よりも遅くすることで、細線ワイヤ８のワイヤの変形をさらに抑制することができる。   Further, the sealing resins RS1 and RS2 are injected at the same time, and the injection conditions such as the injection pressure are the same. In addition, the deformation | transformation of the wire of the fine wire 8 can further be suppressed by making the injection | pouring speed | velocity | rate of sealing resin RS2 inject | poured from the IC chip 6 side slower than the injection | pouring speed | velocity | rate of sealing resin RS1.

図７に示されるように、上金型ＵＭと下金型ＬＭとで構成されるキャビティ内全体に封止樹脂ＲＳ１およびＲＳ２を充填し、キャビティ内で封止樹脂ＲＳ１およびＲＳ２を硬化させてパッケージを形成し、金型を開いてパッケージを取り出す。その後、ポストキュアなど追加硬化過程を経てパッケージの外形を加工し、また、パワーアウターリード１ｃおよび制御アウターリード１ｂをパッケージの裏面側に向けるように曲げ加工することで、図８に示す電力用半導体装置２００が完成する。   As shown in FIG. 7, the entire cavity formed by the upper mold UM and the lower mold LM is filled with the sealing resins RS1 and RS2, and the sealing resins RS1 and RS2 are cured in the cavity to be packaged. And open the mold and take out the package. Thereafter, the external shape of the package is processed through an additional curing process such as post-cure, and the power outer lead 1c and the control outer lead 1b are bent so as to face the back side of the package, whereby the power semiconductor shown in FIG. The device 200 is completed.

なお、電力用半導体装置２００の製造工程においては、封止樹脂ＲＳ１およびＲＳ２の注入開始直後に可動ブロック１０をキャビティ内に可動ブロック１０を挿入し、樹脂注入完了後に可動ブロック１０を抜き出す。可動ブロック１０を抜き出す際に、樹脂注入の際に樹脂と共にキャビティ内に流入した空気を脱気することができ、パッケージ内に空気が残ることを防止できる。また、キャビティ内に可動ブロック１０を挿入しておくことで、狭間部に樹脂が流れ難くなり、樹脂がせき止められる仕組みにより、封止樹脂ＲＳ１と封止樹脂ＲＳ２の停止位置を均一にすることができる。なお、可動ブロック１０の挿入位置は細線ワイヤ８の配置領域とアルミワイヤ７の配置領域との間に設ければ良い。   In the manufacturing process of the power semiconductor device 200, the movable block 10 is inserted into the cavity immediately after the injection of the sealing resins RS1 and RS2 is started, and the movable block 10 is extracted after the resin injection is completed. When the movable block 10 is extracted, the air that flows into the cavity together with the resin when the resin is injected can be degassed, and air can be prevented from remaining in the package. In addition, by inserting the movable block 10 in the cavity, it becomes difficult for the resin to flow into the narrow space, and the stopping position of the sealing resin RS1 and the sealing resin RS2 can be made uniform by a mechanism in which the resin is blocked. it can. The insertion position of the movable block 10 may be provided between the arrangement area of the thin wire 8 and the arrangement area of the aluminum wire 7.

＜実施の形態３＞
次に、図９〜図１４を用いて本発明に係る実施の形態３について説明する。なお、以下においては図１９および図２０を用いて説明した電力用半導体装置９０と同一の構成については同一の符号を付し、重複する説明は省略する。 <Embodiment 3>
Next, Embodiment 3 according to the present invention will be described with reference to FIGS. In the following, the same components as those of the power semiconductor device 90 described with reference to FIGS. 19 and 20 are denoted by the same reference numerals, and redundant description is omitted.

図９は、図１に示したリードフレーム状態の電力用半導体装置を下金型ＬＭ内に載置した状態を示しており、下金型ＬＭの底面上には、粒状の封止樹脂を圧縮して無機物粒子（フィラー）の最大粒径に相当する厚さ、すなわち５５μｍ程度の厚さの薄板状の圧縮絶縁板２０Ａが載置されている。   FIG. 9 shows a state where the power semiconductor device in the lead frame state shown in FIG. 1 is placed in the lower mold LM, and a granular sealing resin is compressed on the bottom surface of the lower mold LM. A thin plate-like compression insulating plate 20A having a thickness corresponding to the maximum particle size of the inorganic particles (filler), that is, a thickness of about 55 μm is placed.

圧縮絶縁板２０Ａのダイパッド１ａ側の主面は熱硬化性樹脂の樹脂膜ＲＣＴで覆われており、ダイパッド１ａの裏面が樹脂膜ＲＣＴに接するように、リードフレーム状態の電力用半導体装置が下金型ＬＭ内に載置される。   The main surface of the compression insulating plate 20A on the die pad 1a side is covered with a resin film RCT of a thermosetting resin, and the power semiconductor device in the lead frame state is a lower metal so that the back surface of the die pad 1a is in contact with the resin film RCT. Placed in mold LM.

なお、図示は省略しているが上金型ＵＭには円筒状の可動ブロックが組み込まれており、上金型ＵＭと下金型ＬＭとを合わせて構成されるキャビティ内に可動ブロックを挿入することができる。なお、可動ブロックの抜き差しにはサーボモータ等を用いるが、可動ブロックの技術は公知であるので説明は省略する。   Although not shown, a cylindrical movable block is incorporated in the upper mold UM, and the movable block is inserted into a cavity formed by combining the upper mold UM and the lower mold LM. be able to. A servo motor or the like is used for inserting / removing the movable block. However, since the technique of the movable block is well known, description thereof is omitted.

図１０は、閉じた金型内に、注入ゲートＧＡ１およびＧＡ２を介して、それぞれ溶融した状態の２種類の封止樹脂ＲＳ１およびＲＳ２を注入する工程を示している。すなわち、上金型ＵＭと下金型ＬＭとで構成されるキャビティには、対向する２つの側面のうち、一方の側面から注入ゲートＧＡ１を介して溶融した状態の封止樹脂ＲＳ１が注入され、他方の側面から注入ゲートＧＡ２を介して溶融した状態の封止樹脂ＲＳ２が注入される。   FIG. 10 shows a process of injecting two kinds of molten sealing resins RS1 and RS2 into the closed mold through the injection gates GA1 and GA2, respectively. That is, in the cavity constituted by the upper mold UM and the lower mold LM, the sealing resin RS1 in a melted state is injected from one of the two side surfaces through the injection gate GA1, The molten sealing resin RS2 is injected from the other side surface through the injection gate GA2.

ここで、ＲＣ−ＩＧＢＴ５側のキャビティ側面に設けた注入ゲートＧＡ１から注入される封止樹脂ＲＳ１は、５０Ｐａ・ｓｅｃ以下の粘度を有し、ＩＣチップ６側のキャビティ側面に設けた注入ゲートＧＡ２から注入される封止樹脂ＲＳ２は、２０Ｐａ・ｓｅｃ以下の粘度を有している。なお、封止樹脂ＲＳ１およびＲＳ２を同じ樹脂とした場合は、フィラー量によって粘度を調整し、ＩＣチップ６側から注入される樹脂の粘度を、ＲＣ−ＩＧＢＴ５側から注入される樹脂の粘度よりも小さくする。これは、ＩＣチップ６に接続される細線ワイヤ８のワイヤの変形を抑制するためである。なお、封止樹脂ＲＳ２のフィラー量を、封止樹脂ＲＳ１のフィラー量よりも少なくすることで、封止樹脂ＲＳ２の接着力は封止樹脂ＲＳ１の接着力よりも強くなる。   Here, the sealing resin RS1 injected from the injection gate GA1 provided on the cavity side surface on the RC-IGBT5 side has a viscosity of 50 Pa · sec or less, and from the injection gate GA2 provided on the cavity side surface on the IC chip 6 side. The sealing resin RS2 to be injected has a viscosity of 20 Pa · sec or less. When the sealing resins RS1 and RS2 are the same resin, the viscosity is adjusted by the amount of filler, and the viscosity of the resin injected from the IC chip 6 side is higher than the viscosity of the resin injected from the RC-IGBT5 side. Make it smaller. This is to suppress the deformation of the thin wire 8 connected to the IC chip 6. In addition, the adhesive force of sealing resin RS2 becomes stronger than the adhesive force of sealing resin RS1 by making the filler amount of sealing resin RS2 smaller than the filler amount of sealing resin RS1.

また、封止樹脂ＲＳ１およびＲＳ２の注入は同時に行い、注入圧力などの注入条件も同じとする。なお、ＩＣチップ６側から注入する封止樹脂ＲＳ２の注入速度を封止樹脂ＲＳ１の注入速度よりも遅くすることで、細線ワイヤ８のワイヤの変形をさらに抑制することができる。   Further, the sealing resins RS1 and RS2 are injected at the same time, and the injection conditions such as the injection pressure are the same. In addition, the deformation | transformation of the wire of the fine wire 8 can further be suppressed by making the injection | pouring speed | velocity | rate of sealing resin RS2 inject | poured from the IC chip 6 side slower than the injection | pouring speed | velocity | rate of sealing resin RS1.

図１０に示されるように、上金型ＵＭと下金型ＬＭとで構成されるキャビティ内全体に封止樹脂ＲＳ１およびＲＳ２を充填し、キャビティ内で封止樹脂ＲＳ１およびＲＳ２を硬化させてパッケージを形成し、金型を開いてパッケージを取り出す。その後、ポストキュアなど追加硬化過程を経てパッケージの外形を加工し、また、パワーアウターリード１ｃおよび制御アウターリード１ｂをパッケージの裏面側に向けるように曲げ加工することで、図１１に示す電力用半導体装置３００が完成する。   As shown in FIG. 10, sealing resin RS1 and RS2 are filled in the entire cavity constituted by the upper mold UM and the lower mold LM, and the sealing resins RS1 and RS2 are cured in the cavity to be packaged. And open the mold and take out the package. Thereafter, the external shape of the package is processed through an additional curing process such as post cure, and the power outer lead 1c and the control outer lead 1b are bent so as to face the back side of the package, whereby the power semiconductor shown in FIG. The device 300 is completed.

なお、電力用半導体装置３００の製造工程においては、実施の形態２の電力用半導体装置２００の製造工程と同様に、キャビティ内に可動ブロック１０の挿入を行い、樹脂注入完了後に可動ブロック１０を抜き出すことで、キャビティ内の空気を脱気する。可動ブロック１０を用いることによる効果は実施の形態２と同じである。   In the manufacturing process of power semiconductor device 300, similarly to the manufacturing process of power semiconductor device 200 of the second embodiment, movable block 10 is inserted into the cavity, and movable block 10 is extracted after resin injection is completed. As a result, the air in the cavity is degassed. The effect obtained by using the movable block 10 is the same as that of the second embodiment.

図１２は、図１９に示した電力用半導体装置９０における厚みの薄い絶縁部９を形成する際の問題点を説明する図である。図１２において、ダイパッド１ａの裏面と下金型ＬＭの底面との間の隙間の間隔ｄが、フィラーの最大粒径の１〜４倍に相当する５５〜２２０μｍである場合、当該隙間に封止樹脂を充填しようとすると、流入口でフィラーＦＬが目詰まりして充填できない。そのため、隙間の間隔はフィラーＦＬの最大粒径の４倍よりも大きくする必要がある。   FIG. 12 is a diagram for explaining a problem when forming thin insulating portion 9 in power semiconductor device 90 shown in FIG. In FIG. 12, when the gap d between the back surface of the die pad 1 a and the bottom surface of the lower mold LM is 55 to 220 μm corresponding to 1 to 4 times the maximum particle size of the filler, sealing is performed in the gap. When filling the resin, the filler FL is clogged at the inlet and cannot be filled. For this reason, the gap interval needs to be larger than four times the maximum particle size of the filler FL.

しかし、上述した実施の形態３の電力用半導体装置３００では、予め、下金型ＬＭの底面上にフィラーの最大粒径に相当する厚さの圧縮絶縁板２０Ａを搭載し、圧縮絶縁板２０Ａにダイパッド１ａの裏面が接するようにリードフレーム状態の電力用半導体装置を載置するので、図１３に示されるように、ダイパッド１ａの裏面と下金型ＬＭの底面との間には厚さｄ１の圧縮絶縁板２０Ａが存在することとなる。ここで、厚さｄ１はフィラーの最大粒径に相当する厚さ、すなわち５５μｍであるので、フィラーの最大粒径の１〜４倍に相当する５５〜２２０μｍの間隔ｄよりも小さくなる（ｄ１＜ｄ）。すなわち電力用半導体装置３００では、絶縁部の厚さを電力用半導体装置９０の４分の１程度まで薄くできる。なお、本実施の形態の圧縮絶縁板２０Ａは、最大粒径が５５μｍのフィラーを有する封止樹脂をフィラーの最大粒径程度まで圧縮することで厚さ５５μｍを達成している。   However, in the power semiconductor device 300 of the third embodiment described above, the compression insulating plate 20A having a thickness corresponding to the maximum particle size of the filler is previously mounted on the bottom surface of the lower mold LM, and the compression insulating plate 20A is mounted. Since the power semiconductor device in the lead frame state is placed so that the back surface of the die pad 1a is in contact, as shown in FIG. 13, a thickness d1 is provided between the back surface of the die pad 1a and the bottom surface of the lower mold LM. There will be a compression insulating plate 20A. Here, since the thickness d1 is a thickness corresponding to the maximum particle size of the filler, that is, 55 μm, it is smaller than the interval d of 55 to 220 μm corresponding to 1 to 4 times the maximum particle size of the filler (d1 < d). That is, in the power semiconductor device 300, the thickness of the insulating portion can be reduced to about one-fourth that of the power semiconductor device 90. Note that the compression insulating plate 20A of the present embodiment achieves a thickness of 55 μm by compressing a sealing resin having a filler having a maximum particle size of 55 μm to about the maximum particle size of the filler.

ここで、図１４は絶縁部の厚さに対する放熱特性を示す図である。図１４においては横軸に絶縁部の厚さ（ｍｍ）を示し、縦軸に電力用デバイスの温度（Ｔｊ）と絶縁部裏面の温度（Ｔｆ）との温度差ΔＴｊ-ｆ（℃）を示している。   Here, FIG. 14 is a diagram showing heat dissipation characteristics with respect to the thickness of the insulating portion. In FIG. 14, the horizontal axis indicates the thickness (mm) of the insulating portion, and the vertical axis indicates the temperature difference ΔTj−f (° C.) between the temperature (Tj) of the power device and the temperature (Tf) of the back surface of the insulating portion. ing.

そして、電力用デバイスの温度をＴｊとし、絶縁部裏面全面に熱伝導率１．５Ｗ／ｍ・Ｋのグリスを２０μｍの厚さで塗布した場合のグリス表面の温度をＴｆとし、発熱密度が１Ｗ／ｍｍ２以上のＲＣ−ＩＧＢＴ５を用いた場合で、封止樹脂の熱伝導率が３Ｗ／ｍ・Ｋを想定してシミュレーションした結果を特性Ｔ１として図１４に示している。 The temperature of the power device is Tj, the temperature of the grease surface when a grease with a thermal conductivity of 1.5 W / m · K is applied to the entire back surface of the insulating portion with a thickness of 20 μm is Tf, and the heat generation density is 1 W. FIG. 14 shows the result of simulation assuming that the thermal conductivity of the sealing resin is 3 W / m · K in the case of using RC-IGBT5 of / mm 2 or more as characteristic T1.

図１４より、温度差ΔＴｊ-ｆを２５℃以下とするには絶縁部の厚さを２２０μｍ（０．２２ｍｍ）以下にする必要があることが判る。   FIG. 14 shows that the thickness of the insulating portion needs to be 220 μm (0.22 mm) or less in order to set the temperature difference ΔTj−f to 25 ° C. or less.

実施の形態３の電力用半導体装置３００では、圧縮絶縁板２０Ａの厚さをフィラーの最大粒径に相当する厚さ５５μｍにすることで、図１４より温度差ΔＴｊ-ｆを１０℃程度まで下げることができ、放熱特性をより改善することができる。また、絶縁部をさらに薄くすることで、電力用半導体装置をより小型化することができる。   In the power semiconductor device 300 of the third embodiment, the temperature difference ΔTj−f is lowered to about 10 ° C. from FIG. 14 by setting the thickness of the compression insulating plate 20A to 55 μm, which corresponds to the maximum particle size of the filler. The heat dissipation characteristics can be further improved. In addition, the power semiconductor device can be further downsized by further reducing the thickness of the insulating portion.

＜実施の形態４＞
次に、図１５を用いて本発明に係る実施の形態４について説明する。なお、以下においては図１９および図２０を用いて説明した電力用半導体装置９０と同一の構成については同一の符号を付し、重複する説明は省略する。 <Embodiment 4>
Next, Embodiment 4 according to the present invention will be described with reference to FIG. In the following, the same components as those of the power semiconductor device 90 described with reference to FIGS. 19 and 20 are denoted by the same reference numerals, and redundant description is omitted.

図１５は、実施の形態４の電力用半導体装置４００の特徴的な構成を示す部分拡大図である。図１５に示されるように電力用半導体装置４００においては、下金型ＬＭの底面上に、粒状の封止樹脂を圧縮して薄板状にした圧縮絶縁板２０Ｂが載置されている。圧縮絶縁板２０Ｂのダイパッド１ａ側の主面は熱硬化性樹脂の樹脂膜ＲＣＴで覆われており、ダイパッド１ａの裏面が樹脂膜ＲＣＴに接している。なお、実施の形態２において図１０を用いて説明したように、上金型ＵＭと下金型ＬＭとで構成されるキャビティ内全体に封止樹脂ＲＳ１およびＲＳ２を充填し、キャビティ内で封止樹脂ＲＳ１およびＲＳ２を硬化させてパッケージを形成し、金型を開いてパッケージを取り出す工程等は実施の形態２と同じである。また、封止樹脂ＲＳ１およびＲＳ２の注入開始直後に可動ブロック１０をキャビティ内に可動ブロック１０を挿入し、樹脂注入完了後に可動ブロック１０を抜き出す工程も同じである。   FIG. 15 is a partially enlarged view showing a characteristic configuration of the power semiconductor device 400 of the fourth embodiment. As shown in FIG. 15, in the power semiconductor device 400, a compression insulating plate 20 </ b> B in which a granular sealing resin is compressed into a thin plate shape is placed on the bottom surface of the lower mold LM. The main surface of the compression insulating plate 20B on the die pad 1a side is covered with a resin film RCT of a thermosetting resin, and the back surface of the die pad 1a is in contact with the resin film RCT. As described with reference to FIG. 10 in the second embodiment, the entire cavity constituted by the upper mold UM and the lower mold LM is filled with the sealing resins RS1 and RS2, and sealed in the cavity. The steps of curing the resins RS1 and RS2 to form a package, opening the mold and taking out the package are the same as in the second embodiment. The process of inserting the movable block 10 into the cavity immediately after the start of injection of the sealing resins RS1 and RS2 and extracting the movable block 10 after the resin injection is completed is the same.

圧縮絶縁板２０Ｂの厚さは、無機物粒子（フィラー）の最大粒径の４〜５倍に相当する厚さ、すなわち２２０〜２７５μｍ程度である。そして、圧縮絶縁板２０Ｂは、ダイパッド１ａの裏面から遠ざかるにつれてフィラー濃度が増加し、樹脂濃度が増加するフィラー分布を有する構成を採っている。   The thickness of the compression insulating plate 20B is a thickness corresponding to 4 to 5 times the maximum particle diameter of the inorganic particles (filler), that is, about 220 to 275 μm. And the compression insulating board 20B has taken the structure which has a filler distribution which a filler density | concentration increases and the resin density | concentration increases as it distances from the back surface of the die pad 1a.

このようなフィラー分布とするために、圧縮絶縁板２０Ｂは多層の樹脂層で構成されている。すなわちダイパッド１ａに接する樹脂層は、フィラー濃度が最も低く、７０〜８０ｗｔ％程度であり、樹脂濃度は２０〜３０ｗｔ％程度の樹脂層とし、ダイパッド１ａから離れるにつれてフィラー濃度が高く、樹脂濃度が低くなるように複数の樹脂層が積層された構成となっている。なお、最下層の樹脂層のフィラー濃度は８０〜９０ｗｔ％程度であり、樹脂濃度は１０〜２０ｗｔ％程度である。なお、何れの樹脂層も粒状の封止樹脂を圧縮して形成され、薄板状となっている。   In order to obtain such filler distribution, the compression insulating plate 20B is composed of multiple resin layers. That is, the resin layer in contact with the die pad 1a has the lowest filler concentration, which is about 70 to 80 wt%, and the resin concentration is about 20 to 30 wt%, and the filler concentration increases and becomes lower as the distance from the die pad 1a increases. In this way, a plurality of resin layers are laminated. The filler concentration of the lowermost resin layer is about 80 to 90 wt%, and the resin concentration is about 10 to 20 wt%. Each resin layer is formed by compressing granular sealing resin and has a thin plate shape.

ダイパッド１ａに接する樹脂層は、樹脂濃度が最も高いのでダイパッド１ａとの高い接着性を有し、また、パッケージの裏面に近づくにつれてフィラー濃度が高くなるので、放熱性が向上することとなる。   Since the resin layer in contact with the die pad 1a has the highest resin concentration, the resin layer has high adhesion to the die pad 1a, and the filler concentration increases as it approaches the back surface of the package, so that the heat dissipation is improved.

＜実施の形態５＞
次に、図１６〜図１８を用いて本発明に係る実施の形態５について説明する。なお、以下においては図１９および図２０を用いて説明した電力用半導体装置９０と同一の構成については同一の符号を付し、重複する説明は省略する。 <Embodiment 5>
Next, Embodiment 5 according to the present invention will be described with reference to FIGS. In the following, the same components as those of the power semiconductor device 90 described with reference to FIGS. 19 and 20 are denoted by the same reference numerals, and redundant description is omitted.

図１６は、図１に示したリードフレーム状態の電力用半導体装置を下金型ＬＭ内に載置した状態を示しており、下金型ＬＭの底面上には、エポキシ等の熱硬化性樹脂で構成される圧縮絶縁板３２を有する絶縁シート３が載置されている。絶縁シート３は金属板３１の上面に、粒状の封止樹脂を圧縮して薄板状にした圧縮絶縁板３２を有する構成となっており、圧縮絶縁板３２がダイパッド１ａ側となるように下金型ＬＭ内に搭載される。   FIG. 16 shows a state where the power semiconductor device in the lead frame state shown in FIG. 1 is placed in the lower mold LM, and a thermosetting resin such as epoxy is placed on the bottom surface of the lower mold LM. The insulating sheet 3 having the compression insulating plate 32 constituted by is placed. The insulating sheet 3 includes a compression insulating plate 32 formed by compressing granular sealing resin on the upper surface of the metal plate 31 to form a thin plate, and the lower metal plate so that the compression insulating plate 32 is on the die pad 1a side. Mounted in the mold LM.

圧縮絶縁板３２の厚さは、フィラーの最大粒径の４〜５倍に相当する厚さ、すなわち２２０〜２７５μｍ程度である。金属板３１は銅（Ｃｕ）またはアルミニウム（Ａｌ）で構成され、その厚さは３５〜３３００μｍ程度である。この厚さは一例であり、電解銅箔の最小厚さである３５μｍ程度から電力用半導体装置の定格に合わせて設定すれば良い。金属板３１の裏面はパッケージの裏面に露出するので、金属板３１を介してパッケージの外部に放熱され、放熱性をさらに高めることができる。   The thickness of the compression insulating plate 32 is about 4 to 5 times the maximum particle size of the filler, that is, about 220 to 275 μm. The metal plate 31 is made of copper (Cu) or aluminum (Al) and has a thickness of about 35 to 3300 μm. This thickness is merely an example, and may be set according to the rating of the power semiconductor device from about 35 μm, which is the minimum thickness of the electrolytic copper foil. Since the back surface of the metal plate 31 is exposed on the back surface of the package, the heat is radiated to the outside of the package through the metal plate 31, and the heat dissipation can be further improved.

図１７は、閉じた金型内に、注入ゲートＧＡ１およびＧＡ２を介して、それぞれ溶融した状態の２種類の封止樹脂ＲＳ１およびＲＳ２を注入する工程を示している。すなわち、上金型ＵＭと下金型ＬＭとで構成されるキャビティには、対向する２つの側面のうち、一方の側面から注入ゲートＧＡ１を介して溶融した状態の封止樹脂ＲＳ１が注入され、他方の側面から注入ゲートＧＡ２を介して溶融した状態の封止樹脂ＲＳ２が注入される。   FIG. 17 shows a process of injecting two kinds of molten sealing resins RS1 and RS2 into the closed mold through the injection gates GA1 and GA2, respectively. That is, in the cavity constituted by the upper mold UM and the lower mold LM, the sealing resin RS1 in a melted state is injected from one of the two side surfaces through the injection gate GA1, The molten sealing resin RS2 is injected from the other side surface through the injection gate GA2.

ここで、ＲＣ−ＩＧＢＴ５側のキャビティ側面に設けた注入ゲートＧＡ１から注入される封止樹脂ＲＳ１は、５０Ｐａ・ｓｅｃ以下の粘度を有し、ＩＣチップ６側のキャビティ側面に設けた注入ゲートＧＡ２から注入される封止樹脂ＲＳ２は、２０Ｐａ・ｓｅｃ以下の粘度を有している。なお、封止樹脂ＲＳ１およびＲＳ２を同じ樹脂とした場合は、フィラー量によって粘度を調整し、ＩＣチップ６側から注入される樹脂の粘度を、ＲＣ−ＩＧＢＴ５側から注入される樹脂の粘度よりも小さくする。これは、ＩＣチップ６に接続される細線ワイヤ８のワイヤの変形を抑制するためである。なお、封止樹脂ＲＳ２のフィラー量を、封止樹脂ＲＳ１のフィラー量よりも少なくすることで、封止樹脂ＲＳ２の接着力は封止樹脂ＲＳ１の接着力よりも強くなる。   Here, the sealing resin RS1 injected from the injection gate GA1 provided on the cavity side surface on the RC-IGBT5 side has a viscosity of 50 Pa · sec or less, and from the injection gate GA2 provided on the cavity side surface on the IC chip 6 side. The sealing resin RS2 to be injected has a viscosity of 20 Pa · sec or less. When the sealing resins RS1 and RS2 are the same resin, the viscosity is adjusted by the amount of filler, and the viscosity of the resin injected from the IC chip 6 side is higher than the viscosity of the resin injected from the RC-IGBT5 side. Make it smaller. This is to suppress the deformation of the thin wire 8 connected to the IC chip 6. In addition, the adhesive force of sealing resin RS2 becomes stronger than the adhesive force of sealing resin RS1 by making the filler amount of sealing resin RS2 smaller than the filler amount of sealing resin RS1.

また、封止樹脂ＲＳ１およびＲＳ２の注入は同時に行い、注入圧力などの注入条件も同じとする。なお、ＩＣチップ６側から注入する封止樹脂ＲＳ２の注入速度を封止樹脂ＲＳ１の注入速度よりも遅くすることで、細線ワイヤ８のワイヤの変形をさらに抑制することができる。   Further, the sealing resins RS1 and RS2 are injected at the same time, and the injection conditions such as the injection pressure are the same. In addition, the deformation | transformation of the wire of the fine wire 8 can further be suppressed by making the injection | pouring speed | velocity | rate of sealing resin RS2 inject | poured from the IC chip 6 side slower than the injection | pouring speed | velocity | rate of sealing resin RS1.

図１７に示されるように、上金型ＵＭと下金型ＬＭとで構成されるキャビティ内全体に封止樹脂ＲＳ１およびＲＳ２を充填し、キャビティ内で封止樹脂ＲＳ１およびＲＳ２を硬化させてパッケージを形成し、金型を開いてパッケージを取り出す。その後、ポストキュアなど追加硬化過程を経てパッケージの外形を加工し、また、パワーアウターリード１ｃおよび制御アウターリード１ｂをパッケージの裏面側に向けるように曲げ加工することで、図１８に示す電力用半導体装置５００が完成する。   As shown in FIG. 17, sealing resin RS1 and RS2 are filled in the entire cavity constituted by upper mold UM and lower mold LM, and the sealing resins RS1 and RS2 are cured in the cavity to package. And open the mold and take out the package. Thereafter, the external shape of the package is processed through an additional curing process such as post cure, and the power outer lead 1c and the control outer lead 1b are bent so as to face the back side of the package, whereby the power semiconductor shown in FIG. Device 500 is completed.

なお、電力用半導体装置５００の製造工程においては、封止樹脂ＲＳ１およびＲＳ２の注入開始直後に可動ブロック１０をキャビティ内に可動ブロック１０を挿入し、樹脂注入完了後に可動ブロック１０を抜き出す。可動ブロック１０を設けることによる効果は、実施の形態２において説明した効果と同じである。   In the manufacturing process of the power semiconductor device 500, the movable block 10 is inserted into the cavity immediately after the injection of the sealing resins RS1 and RS2 is started, and the movable block 10 is extracted after the resin injection is completed. The effect obtained by providing the movable block 10 is the same as the effect described in the second embodiment.

なお、以上説明した実施の形態１〜５においては、電力用デバイスとしてＲＣ−ＩＧＢＴを用いる例を示したが、これに限定されるものではなく、ＩＧＢＴとダイオードの組み合わせでも良く、ＭＯＳトランジスタとダイオードの組み合わせ等でも良い。また、ＲＣ−ＩＧＢＴ５とダイパッド１ａとの接合には、はんだ以外に導電性接着剤など導電性を有した接合材を用いても良い。   In the first to fifth embodiments described above, an example in which an RC-IGBT is used as a power device has been described. However, the present invention is not limited to this, and a combination of an IGBT and a diode may be used. A combination of these may be used. Moreover, you may use the joining material which has electroconductivity, such as a conductive adhesive other than solder, for joining RC-IGBT5 and the die pad 1a.

なお、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。   It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

１ａ ダイパッド、１ｂ 制御アウターリード、１ｃ パワーアウターリード、１ｄ 制御インナーリード、１ｅ パワーインナーリード、３ 絶縁シート、５ ＲＣ−ＩＧＢＴ、６ ＩＣチップ、２０，２０Ａ，２０Ｂ 圧縮絶縁板。   1a Die pad, 1b Control outer lead, 1c Power outer lead, 1d Control inner lead, 1e Power inner lead, 3 Insulating sheet, 5 RC-IGBT, 6 IC chip, 20, 20A, 20B Compression insulating plate.

Claims (7)

電力用デバイスが搭載されたダイパッドと、
前記ダイパッドに対向して配置され、制御用デバイスが搭載されたリードと、を有したリードフレームを樹脂で封止した電力用半導体装置であって、
前記電力用デバイスが搭載された主面とは反対側の前記ダイパッドの裏面に接するように設けられた、粒状樹脂の圧縮板で構成される圧縮絶縁板を備えた電力用半導体装置。 A die pad with a power device,
A power semiconductor device in which a lead frame having a control device mounted thereon and a lead frame disposed opposite to the die pad is sealed with a resin,
A power semiconductor device comprising a compression insulating plate made of a granular resin compression plate provided in contact with the back surface of the die pad opposite to the main surface on which the power device is mounted. 前記圧縮絶縁板は、
前記ダイパッドと接する主面を覆うように設けられた樹脂膜を有する、請求項１記載の電力用半導体装置。 The compression insulating plate is
The power semiconductor device according to claim 1, further comprising a resin film provided so as to cover a main surface in contact with the die pad. 前記リードフレームは、
前記電力用デバイスが搭載された領域と制御用デバイスが搭載された領域とで、異なる材質の樹脂で封止される、請求項１記載の電力用半導体装置。 The lead frame is
The power semiconductor device according to claim 1, wherein the region where the power device is mounted and the region where the control device is mounted are sealed with resin of different materials. 前記圧縮絶縁板は、
前記リードフレームの封止樹脂に含まれるフィラーの最大粒径の１〜４倍に相当する厚さを有する、請求項１記載の電力用半導体装置。 The compression insulating plate is
The power semiconductor device according to claim 1, wherein the power semiconductor device has a thickness corresponding to 1 to 4 times a maximum particle size of a filler contained in a sealing resin of the lead frame. 前記圧縮絶縁板は、
前記ダイパッドの前記裏面から遠ざかるにつれてフィラー濃度が増加し、樹脂濃度が減少するフィラー分布を有する、請求項１記載の電力用半導体装置。 The compression insulating plate is
The power semiconductor device according to claim 1, wherein the power semiconductor device has a filler distribution in which a filler concentration increases and a resin concentration decreases with increasing distance from the back surface of the die pad. 前記圧縮絶縁板は、金属板の上に搭載され、
前記圧縮絶縁板が搭載された主面とは反対側の全記金属板の裏面は、樹脂パッケージから露出する、請求項１記載の電力用半導体装置。 The compression insulating plate is mounted on a metal plate;
The power semiconductor device according to claim 1, wherein a back surface of the entire metal plate opposite to the main surface on which the compression insulating plate is mounted is exposed from the resin package. 電力用デバイスが搭載されたダイパッドと、
前記ダイパッドに対向して配置され、制御用デバイスが搭載されたリードと、を有したリードフレームを樹脂で封止した電力用半導体装置の製造方法であって、
（ａ）下金型の底面に粒状樹脂の圧縮板で構成される圧縮絶縁板を搭載し、前記電力用デバイスが搭載された主面とは反対側の前記ダイパッドの裏面が前記圧縮絶縁板に接するように前記リードフレームを前記下金型に搭載する工程と、
（ｂ）前記下金型上に上金型を被せ、前記下金型と前記上金型とで構成されるキャビティ内に、前記キャビティの対向する２つの側面のうち、前記電力用デバイス側となる一方の側面から溶融した状態の第１の封止樹脂を注入し、前記制御用デバイス側となる他方の側面から溶融した状態の第２の封止樹脂を注入する工程と、を備え、
前記工程（ｂ）は、
前記第２の封止樹脂として、前記第１の封止樹脂よりも粘度の小さい樹脂を準備する工程を含む、電力用半導体装置の製造方法。 A die pad with a power device,
A method of manufacturing a power semiconductor device in which a lead frame having a control device mounted thereon and a lead frame disposed opposite to the die pad is sealed with a resin,
(A) A compression insulating plate made of a granular resin compression plate is mounted on the bottom surface of the lower mold, and the back surface of the die pad opposite to the main surface on which the power device is mounted is the compression insulation plate. Mounting the lead frame on the lower mold so as to come into contact;
(B) An upper mold is put on the lower mold, and the power device side of the two opposing side surfaces of the cavity is formed in a cavity constituted by the lower mold and the upper mold. Injecting a first sealing resin in a molten state from one side surface, and injecting a second sealing resin in a molten state from the other side surface on the control device side,
The step (b)
The manufacturing method of the semiconductor device for electric power including the process of preparing resin with a viscosity smaller than said 1st sealing resin as said 2nd sealing resin.
JP2016161092A 2016-08-19 2016-08-19 Method for manufacturing power semiconductor device Active JP6667401B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2016161092A JP6667401B2 (en) 2016-08-19 2016-08-19 Method for manufacturing power semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016161092A JP6667401B2 (en) 2016-08-19 2016-08-19 Method for manufacturing power semiconductor device

Publications (2)

Publication Number Publication Date
JP2018029149A true JP2018029149A (en) 2018-02-22
JP6667401B2 JP6667401B2 (en) 2020-03-18

Family

ID=61249207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016161092A Active JP6667401B2 (en) 2016-08-19 2016-08-19 Method for manufacturing power semiconductor device

Country Status (1)

Country Link
JP (1) JP6667401B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11430707B2 (en) 2018-09-19 2022-08-30 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
CN115763381A (en) * 2022-11-17 2023-03-07 海信家电集团股份有限公司 Intelligent power module and device
WO2024103986A1 (en) * 2022-11-17 2024-05-23 海信家电集团股份有限公司 Power module and device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006210597A (en) * 2005-01-27 2006-08-10 Mitsubishi Electric Corp Insulating sheet and its manufacturing method, and power module using same
JP2006324401A (en) * 2005-05-18 2006-11-30 Mitsubishi Electric Corp Semiconductor device and its manufacturing method
WO2012046814A1 (en) * 2010-10-06 2012-04-12 日立化成工業株式会社 Multilayer resin sheet and process for production thereof, resin sheet laminate and process for production thereof, cured multilayer resin sheet, metal-foil-cladded multilayer resin sheet, and semiconductor device
JP2013138087A (en) * 2011-12-28 2013-07-11 Sanken Electric Co Ltd Semiconductor module and manufacturing method of the same
WO2015173906A1 (en) * 2014-05-14 2015-11-19 三菱電機株式会社 Method for manufacturing semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006210597A (en) * 2005-01-27 2006-08-10 Mitsubishi Electric Corp Insulating sheet and its manufacturing method, and power module using same
JP2006324401A (en) * 2005-05-18 2006-11-30 Mitsubishi Electric Corp Semiconductor device and its manufacturing method
WO2012046814A1 (en) * 2010-10-06 2012-04-12 日立化成工業株式会社 Multilayer resin sheet and process for production thereof, resin sheet laminate and process for production thereof, cured multilayer resin sheet, metal-foil-cladded multilayer resin sheet, and semiconductor device
JP2013138087A (en) * 2011-12-28 2013-07-11 Sanken Electric Co Ltd Semiconductor module and manufacturing method of the same
WO2015173906A1 (en) * 2014-05-14 2015-11-19 三菱電機株式会社 Method for manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11430707B2 (en) 2018-09-19 2022-08-30 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
CN115763381A (en) * 2022-11-17 2023-03-07 海信家电集团股份有限公司 Intelligent power module and device
WO2024103986A1 (en) * 2022-11-17 2024-05-23 海信家电集团股份有限公司 Power module and device

Also Published As

Publication number Publication date
JP6667401B2 (en) 2020-03-18

Similar Documents

Publication Publication Date Title
US9716072B2 (en) Power semiconductor device and method of manufacturing the same
JP6824913B2 (en) Power semiconductor devices and their manufacturing methods
US6979909B2 (en) Semiconductor device and method of manufacturing same
JP6115738B2 (en) Semiconductor device and manufacturing method thereof
JP5563918B2 (en) Circuit device manufacturing method
US10312178B2 (en) Semiconductor device
JP5563917B2 (en) Circuit device and manufacturing method thereof
JP6266168B2 (en) Semiconductor device
JP6183226B2 (en) Method for manufacturing power semiconductor device
JP2005191071A (en) Semiconductor device
JP6667401B2 (en) Method for manufacturing power semiconductor device
JP6469660B2 (en) Manufacturing method of semiconductor device
CN111095537B (en) Semiconductor device and power conversion device provided with same
US11152275B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP2017191807A (en) Power semiconductor device and manufacturing method of power semiconductor device
JP5607447B2 (en) Circuit equipment
JP6012531B2 (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20181030

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190618

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190620

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20190626

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190917

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200128

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200225

R150 Certificate of patent or registration of utility model

Ref document number: 6667401

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250