JP2018025686A - Method for manufacturing field effect transistor, positioning method, and exposure apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a field effect transistor, by which the position of an alignment mark can be detected with high accuracy.SOLUTION: The method for manufacturing a field effect transistor includes steps of: forming an oxide semiconductor layer and an alignment mark from the same material on a substrate; forming a metal film covering the oxide semiconductor layer and the alignment mark on the substrate; forming a photoresist on the metal film; irradiating the alignment mark with light and capturing an image of the light transmitted through the substrate, the alignment mark, the metal film and the photoresist and adjusting a relative positional relation between the alignment mark and a mask on which a pattern to be transferred to the photoresist is formed; exposing the photoresist through the mask and developing to pattern the photoresist; and etching the metal film by using the photoresist as a mask to form a source electrode and a drain electrode.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a method for manufacturing a field effect transistor, an alignment method, and an exposure apparatus.

In flat thin displays such as electronic paper, TFTs including field effect transistors using oxide semiconductor layers with high carrier mobility and small variation between elements in the channel formation region of the semiconductor layer are manufactured. Attention has been focused on technologies applied to the above. For example, a field effect transistor using zinc oxide (ZnO), indium oxide (In ₂ O ₃ ), In—Ga—Zn—O, or the like as an oxide semiconductor layer has been proposed.

  By the way, when a coating type oxide semiconductor is used for a semiconductor layer of a field effect transistor, it is necessary to bake a coating solution to be a semiconductor layer at a high temperature before forming a metal electrode having poor heat resistance. It is preferable to employ a field effect transistor having a top contact structure, and first form a semiconductor layer on the substrate. In this case, an alignment mark used for alignment with the upper layer is formed in the same layer as the semiconductor layer on the substrate.

  When manufacturing a field effect transistor having a top gate / top contact structure, a semiconductor layer and an alignment mark are formed on a base material, and then a metal film covering them is formed. A protrusion corresponding to the alignment mark is formed on a portion of the metal film that covers the alignment mark. Next, a photoresist is formed on the metal film, the photoresist is exposed and developed and patterned, and then the metal film is etched using the patterned photoresist as a mask to form a source electrode and a drain electrode.

  Before exposing and developing the photoresist, the alignment mark is used to detect the position of the exposure object, and the exposure mask and the exposure object are aligned. At this time, light is irradiated to the protrusion of the metal film through the photoresist, the reflected light from the protrusion is detected by the image sensor, and the position of the protrusion (that is, the position of the alignment mark) is detected by image processing. (For example, refer to Patent Document 1).

  By the way, the thinner the coated oxide semiconductor, the easier it is to control the amount of oxygen in the film. When the thickness is thicker, the amount of oxygen on the surface is different from the amount of oxygen in the semiconductor near the substrate and often exhibits unstable characteristics. For this reason, the semiconductor layer and the alignment mark are formed to a thickness of tens of nm or less. In this case, the step of the protrusion formed on the metal film corresponding to the alignment mark is also less than a dozen nm.

  However, it is difficult to accurately detect the position of the alignment mark because a step of less than 10 nm cannot be imaged with good contrast.

  An object of the present invention is to provide a method for manufacturing a field-effect transistor that can accurately detect the position of an alignment mark.

  The method for producing a field effect transistor is a method for producing a field effect transistor, comprising: forming an oxide semiconductor layer and an alignment mark in a predetermined region on a base material from the same material; and Forming a metal film covering the oxide semiconductor layer and the alignment mark; forming a photoresist on the metal film; and irradiating the alignment mark with light to form the base material and the alignment Imaging the light transmitted through the mark, the metal film, and the photoresist, and adjusting a relative positional relationship between the alignment mark and a mask on which a pattern to be transferred to the photoresist is formed; The photoresist is exposed and developed through a mask, and the photoresist is formed into a pattern corresponding to the mask. A step, by etching the metal film using the photoresist as a mask, a requirement to have the steps of forming a source electrode and a drain electrode.

  According to the disclosed technique, it is possible to provide a method of manufacturing a field effect transistor capable of accurately detecting the position of the alignment mark.

1 is a cross-sectional view illustrating a field effect transistor according to a first embodiment. It is a figure which illustrates the manufacturing process of the field effect transistor which concerns on 1st Embodiment. It is a figure which illustrates the exposure apparatus which concerns on 1st Embodiment. FIG. 4 is an enlarged view of the vicinity of an alignment illumination unit and an alignment detection unit in FIG. 3. It is a figure which illustrates the hardware block of the control part of FIG. It is a figure which illustrates the functional block of the control part of FIG. 3 is a flowchart illustrating a manufacturing process of a field effect transistor according to Example 1; 6 is a diagram (part 1) illustrating a manufacturing process of the field-effect transistor according to the first embodiment; FIG. 6 is a diagram (part 2) illustrating a manufacturing step of the field-effect transistor according to the first embodiment; FIG. It is a figure explaining the detection result of the alignment mark of Example 1 and Comparative Example 1. It is an enlarged view of the alignment illumination part and alignment detection part vicinity of the exposure apparatus which concerns on Example 2. FIG. It is the enlarged view (the 1) of the alignment illumination part of the exposure apparatus which concerns on Example 3, and the alignment detection part vicinity. It is the enlarged view (the 2) of the alignment illumination part and alignment detection part vicinity of the exposure apparatus which concerns on Example 3. FIG.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant description may be omitted.

<First Embodiment>
[Structure of field effect transistor]
FIG. 1 is a cross-sectional view illustrating a field effect transistor according to the first embodiment. Referring to FIG. 1, a field effect transistor 10 includes a top gate / top having a base material 11, a semiconductor layer 12, a source electrode 13, a drain electrode 14, a gate insulating layer 15, and a gate electrode 16. This is a contact-type field effect transistor. The field effect transistor 10 is a typical example of a semiconductor device according to the present invention.

  In the field effect transistor 10, a semiconductor layer 12 is formed on an insulating substrate 11, and a source electrode 13 and a drain electrode 14 are formed on the semiconductor layer 12. Further, a gate insulating layer 15 is formed so as to cover the semiconductor layer 12, the source electrode 13, and the drain electrode 14, and a gate electrode 16 is formed on the gate insulating layer 15. Hereinafter, each component of the field effect transistor 10 will be described in detail.

  In this embodiment, for convenience, the gate electrode 16 side is the upper side or one side, and the base material 11 side is the lower side or the other side. In addition, the surface on the gate electrode 16 side of each part is the upper surface or one surface, and the surface on the substrate 11 side is the lower surface or the other surface. However, the field effect transistor 10 can be used upside down, or can be arranged at an arbitrary angle. Moreover, planar view refers to viewing the object from the normal direction of the upper surface of the base material 11, and planar shape refers to the shape of the object viewed from the normal direction of the upper surface of the base material 11. .

  The base material 11 is an insulating member serving as a base on which the semiconductor layer 12 and the like are formed. There is no restriction | limiting in particular as a shape of the base material 11, a structure, and a magnitude | size, According to the objective, it can select suitably. The material of the substrate 11 is not particularly limited as long as it is a material that can transmit alignment light, and can be appropriately selected according to the purpose. For example, a glass substrate, a plastic substrate, or the like can be used. . There is no restriction | limiting in particular as a glass base material, Although it can select suitably according to the objective, For example, an alkali free glass, a silica glass, etc. are mentioned. Moreover, there is no restriction | limiting in particular as a plastic base material, Although it can select suitably according to the objective, For example, a polycarbonate (PC), a polyimide (PI), a polyethylene terephthalate (PET), a polyethylene naphthalate (PEN) etc. Is mentioned.

The semiconductor layer 12 is made of an oxide semiconductor and is formed in a predetermined region on the base material 11. As the oxide semiconductor that forms the semiconductor layer 12, for example, an n-type oxide semiconductor can be used. The n-type oxide semiconductor is not particularly limited and may be appropriately selected depending on the intended purpose, for _{example, ZnO, SnO 2, In 2} O 3, TiO 2, Ga 2 O 3 and the like.

  In addition, as an n-type oxide semiconductor, an In—Zn-based oxide, an In—Sn-based oxide, an In—Ga-based oxide, a Sn—Zn-based oxide, a Sn—Ga-based oxide, a Zn—Ga-based oxide, or the like can be used. In-Zn-Sn-based oxide, In-Ga-Zn-based oxide, In-Sn-Ga-based oxide, Sn-Ga-Zn-based oxide, In-Al-Zn-based oxide, Al-Ga- An oxide containing a plurality of metals such as a Zn-based oxide, a Sn-Al-Zn-based oxide, an In-Hf-Zn-based oxide, and an In-Al-Ga-Zn-based oxide can also be used.

  An n-type oxide semiconductor has at least one of indium, zinc, tin, gallium, and titanium, an alkaline earth metal, and a point from which high field effect mobility can be obtained and the electron carrier concentration can be easily controlled. It is preferable to contain, and it is more preferable to contain indium and an alkaline earth metal. Examples of the alkaline earth metal include beryllium, magnesium, calcium, strontium, barium, and radium.

Indium oxide has an electron carrier concentration of about 10 ¹⁸ cm ⁻³ to 10 ²⁰ cm ⁻³ depending on the amount of oxygen deficiency. However, indium oxide has a property that oxygen vacancies are easily generated, and in some cases, unintended oxygen vacancies may be generated in a subsequent step after the formation of the oxide semiconductor layer. Forming oxides from two metals, indium and an alkaline earth metal that is easier to bond with oxygen than indium, prevents unintentional oxygen vacancies and facilitates control of the composition. It is particularly preferable because it can be easily controlled.

  When the semiconductor layer 12 is formed using a vacuum film formation method such as sputtering, the average thickness of the semiconductor layer 12 is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably 1 nm to 200 nm. 2 nm to 100 nm is more preferable.

  On the other hand, when a coated oxide semiconductor is used, the thinner the coated oxide semiconductor, the easier it is to control the amount of oxygen in the film. When the coated oxide semiconductor is thicker, the amount of oxygen on the surface differs from the amount of oxygen in the semiconductor near the substrate. Often exhibits characteristics. Therefore, when using the coating type oxide semiconductor, the average thickness of the semiconductor layer 12 is preferably 0.5 nm to 100 nm, and more preferably 1 to 30 nm.

  Before forming a metal electrode with poor heat resistance, it is necessary to bake the coating solution that becomes the semiconductor layer at a high temperature. Therefore, a field effect transistor with a top gate / top contact structure is adopted, and the semiconductor layer is formed first. Is preferred.

  The material of the source electrode 13 and the drain electrode 14 is not particularly limited and can be appropriately selected according to the purpose. For example, Au, Cu, Al, Ti, Ag, Mo, Pd, Nb, Ta, Cr And metals such as these and alloys thereof. There is no restriction | limiting in particular as average thickness of the source electrode 13 and the drain electrode 14, Although it can select suitably according to the objective, 30 nm-2 micrometers are preferable and 50 nm-500 nm are more preferable.

  In the source electrode 13 and the drain electrode 14, the transmittance of alignment light (for example, visible light) is preferably 0.1% or more, and more preferably 1% or more. If the transmittance of the alignment light is 0.1% or more, as shown in Example 1 or the like, the alignment light is irradiated from the back surface side of the base material 11 and transmitted light transmitted to the front surface side of the base material 11 is used. It is possible to accurately detect the pattern edge of the alignment mark.

  The gate insulating layer 15 is provided between the semiconductor layer 12 and the gate electrode 16 so as to cover the source electrode 13 and the drain electrode 14. The gate insulating layer 15 is a layer for insulating the source electrode 13 and the drain electrode 14 from the gate electrode 16. There is no restriction | limiting in particular as a material of the gate insulating layer 15, Although it can select suitably according to the objective, For example, an inorganic insulating material, an organic insulating material, etc. are mentioned.

  Examples of the inorganic insulating material include silicon oxide, aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, lanthanum oxide, hafnium oxide, zirconium oxide, silicon nitride, aluminum nitride, and a mixture thereof. Examples of the organic insulating material include polyimide, polyamide, polyacrylate, polyvinyl alcohol, and novolak resin. There is no restriction | limiting in particular as average thickness of the gate insulating layer 15, Although it can select suitably according to the objective, 50 nm-1000 nm are preferable and 100 nm-500 nm are more preferable.

  The gate electrode 16 is formed in a predetermined region on the gate insulating layer 15. The gate electrode 16 is an electrode for applying a gate voltage. The material for the gate electrode 16 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, platinum, palladium, gold, silver, copper, zinc, aluminum, nickel, chromium, tantalum, molybdenum, titanium And the like, alloys thereof, mixtures of these metals, and the like.

Also, indium oxide, zinc oxide, tin oxide, gallium oxide, niobium oxide, In ₂ O ₃ (ITO) to which tin (Sn) is added, ZnO to which gallium (Ga) is added, and aluminum (Al) are added. Examples thereof include conductive oxides such as ZnO and SnO ₂ to which antimony (Sb) is added, composite compounds thereof, mixtures thereof, and the like. There is no restriction | limiting in particular as average thickness of the gate electrode 16, Although it can select suitably according to the objective, 10 nm-200 nm are preferable and 50 nm-100 nm are more preferable.

[Method for Manufacturing Field Effect Transistor]
Next, a method for manufacturing the field effect transistor shown in FIG. 1 will be described. FIG. 2 is a diagram illustrating a manufacturing process of the field effect transistor according to the first embodiment.

  First, in the step shown in FIG. 2A, a base material 11 made of a glass base material or the like is prepared, and a semiconductor layer 12 is formed in a predetermined region on the base material 11. The material and thickness of the base material 11 can be appropriately selected as described above. Further, from the viewpoint of cleaning the surface of the substrate 11 and improving adhesion, it is preferable to perform a pretreatment such as oxygen plasma, UV ozone, UV irradiation cleaning.

  The manufacturing method of the semiconductor layer 12 is not particularly limited and can be appropriately selected according to the purpose. For example, the sputtering method, the pulse laser deposition (PLD) method, the chemical vapor deposition (CVD) method, the atomic layer deposition After forming a film by a vacuum process such as the (ALD) method or a solution process such as dip coating, spin coating, or die coating, the desired shape is directly formed by a patterning method using photolithography, a printing method such as inkjet, nanoimprinting, or gravure. Examples include a film forming method.

  As will be described later, an alignment mark is formed on the substrate 11 with the same material as the semiconductor layer 12 simultaneously with the formation of the semiconductor layer 12. For example, the alignment marks can be formed one by one on the outer edges of the substrate 11 that face each other. The alignment mark may have an arbitrary planar shape, but may be a cross shape, for example.

  2B, a metal film is formed on the base material 11 and the semiconductor layer 12, and the metal film is patterned by etching to form the source electrode 13 and the drain electrode. There is no restriction | limiting in particular as a method of forming a metal film, According to the objective, it can select suitably, For example, a sputtering method, a vacuum evaporation method, a dip coating method, a spin coat method, a die coating method etc. are mentioned. The material of the metal film to be the source electrode 13 and the drain electrode 14 and the thickness of the source electrode 13 and the drain electrode 14 can be appropriately selected as described above. Before the metal film is etched, alignment is performed using a predetermined exposure apparatus, which will be described later.

  Next, in the step shown in FIG. 2C, a gate insulating layer 15 that covers the source electrode 13 and the drain electrode 14 is formed on the semiconductor layer 12. There is no restriction | limiting in particular as a manufacturing method of the gate insulating layer 15, According to the objective, it can select suitably, For example, (i) Sputtering method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD) After film formation by solution process such as vacuum process such as atomic layer deposition (ALD) method, dip coating method, spin coating method, die coating method, etc., patterning by photolithography, (ii) inkjet, nanoimprint, gravure, etc. Examples include a step of directly forming a desired shape by a printing process. The material and thickness of the gate insulating layer 15 can be appropriately selected as described above.

  Note that a part of the gate insulating layer 15 over the source electrode 13 and the drain electrode 14 is removed by etching or the like to expose a part of the source electrode 13 and the drain electrode 14 and current can be extracted from the field effect transistor 10. it can.

  Next, in the step shown in FIG. 2D, the gate electrode 16 is formed on the gate insulating layer 15. The method for forming the gate electrode 16 is not particularly limited and may be appropriately selected depending on the purpose. For example, (i) by sputtering, vacuum deposition, dip coating, spin coating, die coating, or the like. Examples include a method of patterning by photolithography after film formation, and (ii) a method of directly forming a desired shape by a printing process such as ink jet, nanoimprint, and gravure. The material and thickness of the gate electrode 16 can be appropriately selected as described above.

  Through the above steps, the top-gate / top-contact field effect transistor 10 can be manufactured.

[Exposure equipment]
FIG. 3 is a diagram illustrating an exposure apparatus according to the first embodiment. FIG. 4 is an enlarged view of the vicinity of the alignment illumination unit and the alignment detection unit in FIG. FIG. 5 is a diagram illustrating hardware blocks of the control unit in FIG. FIG. 6 is a diagram illustrating functional blocks of the control unit in FIG.

  Referring to FIG. 3, the exposure apparatus 100 includes an exposure light source 110, an illumination optical unit 120, a mask stage 130, a mask transport unit 140, a substrate stage 150, a substrate transport unit 160, and an alignment illumination unit 170. , An alignment detection unit 180 and a control unit 190.

  Referring to FIG. 5, the control unit 190 includes a CPU 191, a ROM 192, a RAM 193, an I / F 194, and a bus line 195. The CPU 191, ROM 192, RAM 193, and I / F 194 are connected to each other via a bus line 195.

  The CPU 191 controls each function of the control unit 190. A ROM 192 serving as a storage unit stores programs executed by the CPU 191 for controlling each function of the control unit 190 and various types of information. A RAM 193 serving as a storage unit is used as a work area of the CPU 191 or the like. The RAM 193 can temporarily store predetermined information. The I / F 194 is an interface for connecting to other devices, and is connected to, for example, an external network.

In the exposure apparatus 100, an exposure light source 110 is a light source for emitting exposure light _{L 1.} The exposure light source 110 can be appropriately selected according to the sensitivity of the exposed photoresist. For example, when the exposed photoresist has sensitivity to light having a wavelength of 436 nm called g-line or light having a wavelength of 365 nm called i-line, the exposure light source 110 is an ultraviolet ray that emits these lights. A high-pressure mercury lamp that is a light source can be used. The emission timing of the exposure light source 110 can be controlled by the exposure light source control means 190A of the control unit 190.

  A mask 210 on which a pattern to be transferred to a photoresist is formed is held on the mask stage 130. An exposure object 220 is held on a substrate stage 150 that is a placement unit on which the exposure object is placed.

The exposure light L ₁ emitted from the exposure light source 110 is adjusted to a predetermined projection magnification by the illumination optical unit 120, and is then held on the substrate stage 150 via the mask 210 held on the mask stage 130. Guided to the object 220. A photoresist is formed in advance on the exposure object 220, and the surface of the photoresist becomes the exposed surface. A projected image of the pattern of the mask 210 is formed on the exposed surface of the photoresist. On the exposed surface of the photoresist, an area where a projection image is formed becomes an exposure area.

  The illumination optical unit 120 can be composed of a plurality of optical elements including, for example, lenses and mirrors. The illumination optical unit 120 may include a movable lens whose position and posture can be adjusted from the outside by a lens control system.

  The mask 210 is carried onto the mask stage 130 when necessary by the mask carrying unit 140 controlled by the mask carrying unit 190B of the control unit 190, and then carried out from the mask stage 130. The exposure object 220 is carried onto the substrate stage 150 when necessary by the substrate carrying unit 160 controlled by the substrate carrying unit 190C of the control unit 190, and then carried out from the substrate stage 150.

  Here, consider an XYZ coordinate system in which the coordinate axis parallel to the optical axis of the illumination optical unit 120 is the Z axis. The substrate stage 150 can be adjusted in position with six degrees of freedom under the control of the stage position control means 190D of the control unit 190. Specifically, the substrate stage 150 is movable on the XY plane. That is, movement in the X-axis direction, movement in the Y-axis direction, and movement in the θz-axis direction (rotation around the Z-axis) are possible. The substrate stage 150 can move in the Z-axis direction, move in the θx direction (rotation around the X axis), and move in θy (rotation around the Y axis).

  The relative movement between the mask 210 held on the mask stage 130 and the exposure object 220 held on the substrate stage 150 is controlled by the stage position control unit 190D of the control unit 190. The positional relationship is adjusted. An alignment mark is formed on the exposure object 220 held on the substrate stage 150, and the alignment mark is used for adjusting the relative positional relationship between the mask 210 and the exposure object 220.

In exposure apparatus 100, from the back side of the substrate stage 150 (the side that does not hold the object of exposure) is irradiated with alignment light L ₂ to the alignment marks by alignment illumination unit 170. Then, a transmission image of the alignment mark is detected by the alignment detection unit 180 arranged on the front surface side (mask stage 130 side) of the substrate stage 150 to perform alignment.

  With reference to FIG. 4, the alignment illumination part 170 and the alignment detection part 180 are demonstrated in detail. FIG. 4 shows a state in which an exposure object 220 in which an alignment mark 221 is formed on the substrate 11 and a metal film 230 and a photoresist 250 are stacked on the alignment mark 221 is held on the substrate stage 150. Yes.

  The alignment illumination unit 170 can be configured by, for example, an alignment light source 171, an optical filter 172, a condenser lens 173, and a projection lens 174. On the other hand, the alignment detection unit 180 can be configured by a mirror 181, a condenser lens 182, and an image sensor 183.

  For example, a halogen lamp or the like can be used as the alignment light source 171. The optical filter 172 has a function of blocking an unnecessary wavelength region of light emitted from the alignment light source 171 and transmitting a necessary wavelength region.

The condenser lens 173 has a function of causing the alignment light L ₂ whose wavelength region is limited by the optical filter 172 to enter the projection lens 174 more. The projection lens 174 has a function of irradiating the alignment mark 221 with uniform light. The alignment illumination unit 170 can perform Koehler illumination perpendicularly to the alignment mark 221 formed on the exposure target 220 via the substrate stage 150.

The alignment light L _{2 that} has passed through the projection lens 174 passes through the substrate stage 150 formed of glass or the like, illuminates the alignment mark 221, and passes through the exposure object 220. Then, the light is reflected by the mirror 181, condensed by the condenser lens 182, and enters the image sensor 183, and the transmission image of the alignment mark 221 is detected by the image sensor 183. As the image sensor 183, for example, a charge coupled device (CCD), a complementary metal oxide semiconductor (CMOS), or the like can be used.

  Note that the emission timing of the alignment light source 171 can be controlled by the alignment light source control means 190E of the control unit 190. Further, the transmission image of the alignment mark 221 detected by the image sensor 183 is subjected to image processing by the image processing means 190F of the control unit 190, and the coordinates of the alignment mark 221 are calculated.

The stage position control unit 190D of the control unit 190 moves the substrate stage 150 based on the coordinates of the alignment mark 221 calculated by the image processing unit 190F, and the mask 210 and the alignment mark 221 held on the mask stage 130. Adjust the relative position of. Thus, the mask 210 held on the mask stage 130 and the exposure object 220 held on the substrate stage 150 can be aligned. As a result, the exposure light L ₁ can be irradiated to a desired position on the exposed surface of the photoresist 250.

  During exposure, the mask stage 130 moves in the Y-axis direction in synchronization with the substrate stage 150. The entire pattern of the mask 210 can be transferred onto the photoresist 250 by synchronously scanning the mask stage 130 and the substrate stage 150 in the Y-axis direction according to the projection magnification of the illumination optical unit 120.

<Example 1>
In Example 1, the top gate / top contact type field effect transistor 10 shown in FIG. The first embodiment will be described with reference to FIGS. 7 to 9 as appropriate.

(Formation of semiconductor layer 12)
First, a semiconductor layer 12 having a predetermined shape was formed on the substrate 11. Specifically, first, 3.55 g of indium nitrate (In (NO ₃ ) ₃ .3H ₂ O) and 0.139 g of strontium chloride (SrCl ₂ .6H ₂ O) were weighed in a beaker. -40 mL of propanediol, 40 mL of ethylene glycol monomethyl ether and 120 mL of methyl alcohol were added and mixed and dissolved at room temperature to prepare a coating solution for forming an oxide semiconductor layer used in Example 1.

  Then, a non-alkali glass is used as the base material 11, the oxide semiconductor layer forming coating solution is applied onto the base material 11 rotated by a spinner, and the base material is heated at 120 ° C. for 10 minutes. After drying, baking was performed at 400 ° C. for 1 hour in an air atmosphere to form an In—Sr-based oxide film. After that, photolithography and etching were performed on the In—Sr-based oxide semiconductor layer to form a semiconductor layer 12 having a predetermined shape with a thickness of 10 nm. Simultaneously with the formation of the semiconductor layer 12, an alignment mark 221 was formed on the outer edge portion of the base material 11 using the same material as the semiconductor layer 12 (see FIG. 8A).

(Formation of source electrode 13 and drain electrode 14)
Next, as shown in step S301 of FIG. 7 and FIG. 8A, an Au film having a thickness of 100 nm is formed as a metal film 230 on the base material 11, the semiconductor layer 12, and the alignment mark 221 by sputtering. Formed.

  Next, as shown in step S302 of FIG. 7 and FIG. 8B, a photoresist was applied to the entire surface of the metal film 230 with a spinner to form a uniform resist film of about 1.6 μm. Then, the resist film was dried in an oven at 100 ° C. for 30 minutes to obtain a photoresist 250.

  Next, as shown in step S <b> 303 of FIG. 7 and FIG. 8C, the structure shown in FIG. 8B serving as an exposure target was transferred onto the substrate stage 150. The transfer was performed by the substrate transfer unit 160 controlled by the substrate transfer means 190C of the control unit 190. In Example 1, the substrate stage 150 made of glass was used.

Next, alignment was performed as shown in step S304 of FIG. 7 and FIG. 9A. Specifically, the alignment light L ₂ was illuminated onto the alignment mark 221 formed on the exposure object via the substrate stage 150, and a transmission image of the alignment mark 221 was detected by the image sensor 183. In Example 1, using a halogen lamp as an alignment light source 171, and the visible light cut wavelength below 500nm by an optical filter 172 and alignment light _{L 2.}

  Then, the transmission image of the alignment mark 221 detected by the image sensor 183 was subjected to image processing by the image processing unit 190F of the control unit 190, and the coordinates of the alignment mark 221 were calculated.

  Further, the stage position control unit 190D of the control unit 190 moves the substrate stage 150 based on the coordinates of the alignment mark 221 calculated by the image processing unit 190F, and aligns the mask 210 held on the mask stage 130 with the alignment. The relative positional relationship with the mark 221 was adjusted.

  Next, as shown in step S305 of FIG. 7, the pattern of the mask 210 was transferred onto the photoresist 250 by exposure. Then, as shown in step S306 and FIG. 9B, the exposed portion of the photoresist 250 was melted by development, so that the photoresist 250 was formed into a desired pattern.

  Next, as shown in step S307 of FIG. 7 and FIG. 9C, the metal film 230 is etched using the patterned photoresist 250 as a mask, and the source electrode 13 and the drain electrode 14 are formed on the substrate 11 and the semiconductor layer 12. Formed. Thereafter, the photoresist 250 was removed.

(Formation of gate insulating layer 15)
Next, a gate insulating layer 15 was formed by depositing SiO ₂ to a thickness of 200 nm by plasma CVD.

(Formation of the gate electrode 16)
Next, an Al film was formed on the gate insulating layer 15 by a sputtering method. Then, photolithography and etching were performed on the Al film to form a gate electrode 16 having a predetermined shape. Thus, the top gate / top contact type field effect transistor shown in FIG. 1 was manufactured.

<Comparative example 1>
In Comparative Example 1, Example 1 is performed except that the alignment mark 221 is illuminated from above the substrate stage 150 (on the mask stage 130 side) and the reflected image of the alignment mark 221 is detected by the image sensor 183. And the same.

<Comparison between Example 1 and Comparative Example 1>
In the first embodiment, the transmitted light intensity of the alignment mark 221 detected by the image sensor 183 during the alignment described with reference to step S304 of FIG. 7 and FIG. 9A is schematically illustrated in FIG. It was shown to. In FIG. 10A, a region A having a relatively low transmitted light intensity (dark) corresponds to the alignment mark 221.

  As shown in FIG. 10A, in Example 1, an alignment mark having a thickness of 10 nm was detected with good contrast. As a result, it was possible to adjust the relative positional relationship between the mask 210 held on the mask stage 130 and the alignment mark 221 with an alignment deviation amount of 0.9 μm.

This is because in the region where the alignment mark 221 is formed, a part of the alignment light L ₂ is absorbed by the alignment mark 221 and the transmitted light intensity is lower than that in the surrounding region, and the imaging element 183 can capture an image with good contrast. Conceivable.

  On the other hand, the reflected light intensity in the region where the alignment mark 221 detected by the image sensor 183 was formed during the alignment in Comparative Example 1 is schematically shown in FIG. In FIG. 10B, the region B corresponds to the region where the alignment mark 221 is formed, but the edge portion of the region where the alignment mark 221 is formed cannot be clearly detected and cannot be aligned. It was.

  This is because the reflectance of the metal film 230 is high, and the reflected light of the metal film 230 is dominant in the detection by the image sensor 183. However, since only a very small step (G portion in FIG. 9A) corresponding to the thickness of the alignment mark 221 is formed on the metal film 230, it is considered that the imaging element 183 could not capture an image with good contrast. .

  As described above, even when there is only a slight level difference in the film that is the upper layer of the alignment mark 221 and the contrast cannot be obtained by detecting the reflected light, the alignment mark 221 is irradiated with the alignment light from the back side of the substrate 11 and transmitted. It was confirmed that the position of the alignment mark can be accurately detected by detecting the light intensity.

  The alignment method of detecting the transmitted light intensity by irradiating the alignment mark 221 with the alignment light 221 from the back surface side of the base material 11 makes the alignment mark 221 thin (several tens of nm) as in the case of using a coating type oxide semiconductor. This is particularly effective when formed. However, the alignment method of detecting the transmitted light intensity by irradiating the alignment mark 221 from the back surface side of the substrate 11 can be used even when the alignment mark 221 is thick.

<Example 2>
In Example 2, similarly to Example 1, the exposure apparatus 100 was used to manufacture the top gate / top contact type field effect transistor 10 shown in FIG.

However, using an opaque substrate stage 150 which is made of metal in the second embodiment, in a through-hole 150x portion that irradiates an alignment light L ₂ as shown in FIG. 11, the lower side of the alignment light L ₂ is the substrate stage 150 So that it can pass through the through hole 150x upward.

  In Example 2, it was confirmed that alignment can be performed with the same accuracy as in Example 1.

<Example 3>
In Example 3, the top gate / top contact type field effect transistor 10 shown in FIG. 1 was fabricated using the exposure apparatus 100 as in Example 1.

However, using an opaque substrate stage 150 which is made of metal in Example 3, the grooves 150y toward the side surface of the substrate stage 150 inwardly in a portion irradiated with alignment light L ₂ as shown in FIGS. 12 and 13 The glass 270 was fitted into the groove 150y. Thus, the alignment light L ₂ can be transmitted from the lower side to the upper side through the glass 270. FIG. 13 is a plan view of FIG. 12, and only shows the vicinity of the groove 150y of the substrate stage 150. FIG.

  In Example 3, it was confirmed that alignment can be performed with the same accuracy as in Example 1.

  The preferred embodiments and the like have been described in detail above, but the present invention is not limited to the above-described embodiments and the like, and various modifications can be made to the above-described embodiments and the like without departing from the scope described in the claims. Variations and substitutions can be added.

For example, in the exposure apparatus 100, the arrangement of the alignment illumination unit 170 and the alignment detection unit 180 may be upside down. In other words, the alignment light L ₂ may be irradiated to the exposure object from the alignment illumination unit 170 disposed on the mask stage 130 side, and the transmitted light may be detected by the alignment detection unit 180 disposed below the substrate stage 150.

DESCRIPTION OF SYMBOLS 10 Field effect transistor 11 Base material 12 Semiconductor layer 13 Source electrode 14 Drain electrode 15 Gate insulating layer 16 Gate electrode 100 Exposure apparatus 110 Exposure light source 120 Illumination optical part 130 Mask stage 140 Mask conveyance part 150 Substrate stage 150x Through-hole 150y Groove 160 Substrate transport unit 170 Alignment illumination unit 171 Alignment light source 172 Optical filter 173 Condensing lens 174 Projection lens 180 Alignment detection unit 181 Mirror 182 Condensing lens 183 Imaging element 190 Control unit 190A Exposure light source control unit 190B Mask transport unit 190C Substrate transport unit 190D Stage position control means 190E Alignment light source control means 190F Image processing means 191 CPU
192 ROM
193 RAM
194 I / F
195 Bus line 220 Exposure object 221 Alignment mark 230 Metal film 250 Photoresist 270 Glass

JP 2012-084616 A

Claims (7)

A method of manufacturing a field effect transistor,
A step of forming the oxide semiconductor layer and the alignment mark with the same material in a predetermined region on the substrate;
Forming a metal film covering the oxide semiconductor layer and the alignment mark on the substrate;
Forming a photoresist on the metal film;
The alignment mark is irradiated with light, the light is transmitted through the base material, the alignment mark, the metal film, and the photoresist, and a mask on which a pattern to be transferred to the photoresist is formed and the alignment Adjusting the relative positional relationship with the mark;
Exposing and developing the photoresist through the mask and forming the photoresist in a pattern corresponding to the mask;
Etching the metal film using the photoresist as a mask to form a source electrode and a drain electrode, and a method for manufacturing a field effect transistor. The step of forming the oxide semiconductor layer and the alignment mark includes:
Applying a coating liquid for forming an oxide semiconductor layer on the substrate;
The method for producing a field effect transistor according to claim 1, further comprising a step of baking the coating liquid for forming an oxide semiconductor layer applied on the base material. The structure in which the photoresist is formed is disposed on a stage formed from a light shielding member before the step of adjusting the relative positional relationship.
3. The field effect type according to claim 1, wherein, in the step of adjusting the relative positional relationship, the light is irradiated to the structure side through a through hole formed in the stage. A method for manufacturing a transistor. The structure in which the photoresist is formed is disposed on a stage formed from a light shielding member before the step of adjusting the relative positional relationship.
The step of adjusting the relative positional relationship includes irradiating the light to the structure side via a light transmitting member provided in a part of the stage. A method of manufacturing a field effect transistor.   5. The method of manufacturing a field effect transistor according to claim 1, wherein the light is visible light emitted from a halogen lamp.   An alignment method for irradiating an alignment mark with light and adjusting a relative positional relationship between the alignment mark and a mask on which a pattern to be transferred to a photoresist is formed, based on the light transmitted through the alignment mark. A placement unit on which an exposure object on which an alignment mark is formed is placed; and
A light illumination unit for irradiating the alignment mark with light;
A light detection unit for detecting the light transmitted through the alignment mark,
The exposure apparatus in which the light illumination unit and the light detection unit are disposed at positions facing each other with the placement unit interposed therebetween.

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