JP2018019339A - Capacitance type transducer and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simply perform a step of thinning a substrate thickness for suppressing reflection of ultrasonic waves by the substrate in a manufacturing method of a CMUT while suppressing a change of stress characteristics, etc. of a vibrating film.SOLUTION: The method of manufacturing a CMUT includes steps of: forming a support by raising a height in a stacking direction of a region outside a region where a gap is provided than a height in the stacking direction of the region where the gap is provided; and thinning a substrate thickness in the stacking direction by using the support.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a capacitive transducer and a method for manufacturing the same.

  In recent years, research on transducers using micromachining has been actively conducted. In particular, capacitive transducers are devices that transmit or receive elastic waves such as ultrasonic waves using a lightweight vibrating membrane, and can easily obtain broadband characteristics in liquids and in the air. Ultrasonic diagnosis with higher accuracy than modality is attracting attention as a promising technology. A capacitive transducer (capacitive micromachined ultrasonic transducer) may be hereinafter referred to as a CMUT. CMUT detects an inspection object by detecting a photoacoustic wave generated by irradiating the inspection object with light and an acoustic wave (ultrasonic wave) generated by irradiating the inspection object with ultrasonic waves. It is used for the photoacoustic apparatus which acquires the information of this, an ultrasonic probe, or a probe provided with both.

  The CMUT includes an element (element) in which a plurality of cells each having a gap (hereinafter referred to as a cavity) are formed between a substrate and a thin film that is a vibration film, and the cells are electrically connected to each other.

  Here, when receiving ultrasonic waves in the CMUT, the ultrasonic waves that are transmitted through the vibration film and reflected by the substrate may become noise. In Patent Document 1, in order to suppress the noise generated in this way, it is disclosed that the frequency of the ultrasonic wave reflected by the substrate is made larger than the frequency band of the ultrasonic wave received by the CMUT by thinning the substrate. There is. Noise can be suppressed by shifting the frequency of the reflected ultrasonic wave from the reception frequency band of the CMUT.

  On the other hand, in Patent Document 2, in a junction type CMUT, in order to detect a signal for each element, a part of the back surface of the surface on which the vibration film is formed is removed by cutting, polishing, etching, or the like to form a recess. There is disclosure of performing trench processing.

US Patent Application Publication No. 2003-0103412 JP 2010-35156 A

  Here, Patent Document 1 does not disclose a specific method of the process of thinning the back surface of the substrate.

  In Patent Document 2, trenching is performed by fixing a handling member to a CMUT diaphragm. For this reason, when the handling member is pressed against the vibration film during the trench processing, there is a possibility that stress characteristics of the vibration film and the like are changed.

  The method of manufacturing a capacitive transducer according to the present invention includes a step of providing a lower electrode layer in a stacking direction of a substrate, a step of providing a sacrificial layer in the stacking direction on the lower electrode layer, Forming a first membrane layer in the laminating direction, providing an upper electrode layer in the laminating direction on the first membrane layer, and providing an etching hole in the first membrane layer; And removing the sacrificial layer through the etching hole to form a void, and a method of manufacturing a capacitive transducer, wherein the stacking direction of the region where the void is provided Forming a support column by increasing the height in the stacking direction in at least a part of the region outside the region, and using the support column, A step of reducing the thickness of the stacking direction of.

  According to the CMUT manufacturing method of the present invention, the step of reducing the thickness of the substrate for suppressing the reflection of the ultrasonic wave by the substrate is simply performed while suppressing the change in the stress characteristics and the like of the vibrating membrane. be able to.

It is a figure for demonstrating each process of the manufacturing method of the capacitive transducer which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the structure of the electrostatic capacitance type transducer which concerns on Embodiment 2 of this invention.

  Although the manufacturing method of CMUT which concerns on embodiment of this invention is demonstrated, this invention is not limited to them.

  In the CMUT manufacturing method according to the present embodiment, a CMUT cell that transmits and receives ultrasonic waves and a structure that serves as a support for thinning the substrate constituting the cell are integrally formed on the main surface of the substrate. In this embodiment, the CMUT cell includes a substrate, a first electrode protective layer, a lower electrode layer, a first wiring layer, a second electrode protective layer, a sacrificial layer, a first membrane layer, an upper electrode layer, a second A membrane layer, a third membrane layer, and a second wiring layer are formed in this order. The support column is formed by at least one of a step of forming a lower electrode layer, a step of forming a sacrificial layer, a step of forming a first membrane layer, and a step of forming an upper electrode layer. Specifically, the height in the stacking direction in at least a part of the region outside the cell region is higher than the height in the stacking direction of the cell region. As a result, pillars are formed outside the cell region. Here, the height of the cell region in the stacking direction is the height (height h1 in the cell region β of FIG. 1 (13) described later). The height h2 (FIG. 1 (13)) in the stacking direction in at least a part of the area outside the cell area is higher than h1. Hereinafter, at least a part of the area outside the cell area may be simply abbreviated as outside the cell area.

  Next, the formed support column is fixed to the stage, and the thickness of the substrate in the stacking direction is reduced. In this way, since the cell is formed and the support is formed, and the material constituting the cell is used as the support, the support can be easily formed without increasing the number of processes. In addition, since the support is provided outside the cell region, a change in the stress characteristics of the vibrating membrane of the cell can be suppressed when the CMUT that is a stacked body is fixed using the support. Here, there are roughly two methods for forming the support columns. One is a method in which a certain layer remains only outside the cell region. In this case, a layer may be provided once inside and outside the cell region, and the layer inside the cell region may be removed, or a layer only outside the cell region may be formed. Once a certain layer is formed only outside the cell region, even if another layer is formed thereafter, a relatively high portion is formed outside the cell region, which becomes a support column. This method has an advantage that the thickness at the time of providing each layer can be made constant and the process becomes simple. In this method, it is preferable that the layer only outside the cell region is not only a function as a support but also a layer necessary for driving the CMUT. For example, as a layer only outside the cell region, a layer of wiring connected to an electrode can be given.

  Another method for forming the support is a method in which, in the step of providing a certain layer, the layer thickness of the layer provided outside the cell region is thicker than the layer thickness of the layer provided in the cell region. Note that the layer thickness provided outside the cell region may be thicker than the layer thickness provided inside the cell region in a plurality of steps as well as in one step.

Note that the lower electrode layer, the upper electrode layer, and the sacrificial layer are desirably formed in a narrower region in a plane perpendicular to the stacking direction than the first and second electrode protective layers. When the end surfaces of the lower electrode layer, the upper electrode layer, and the sacrificial layer are exposed on the surface of the support column, etching can be suppressed.
Further, the step of thinning the substrate may be performed during the CMUT formation. It is only necessary that the column is formed higher in at least a part of the region outside the cell region than in the cell region at the time of performing the step of thinning the substrate.
You may arrange | position a support | pillar in the clearance gap between cells. You may arrange | position the support | pillar of a large area outside a cell area | region.

The CMUT manufacturing method according to the present embodiment only needs to include at least the following steps.
(A) A step of providing a lower electrode layer in the stacking direction of the substrates.
(B) A step of providing a sacrificial layer on the lower electrode layer.
(C) forming a first membrane layer on the sacrificial layer.
(D) A step of providing an upper electrode layer on the first membrane layer.
(E) A step of providing an etching hole in the first membrane layer.
(F) The process of forming a space | gap part by removing a sacrificial layer through an etching hole.
Each of these layers is provided in the stacking direction.

  And the support | pillar is formed by making the height of the lamination direction in the at least one part area | region outside a cell area higher than the height of the cell area in which the space | gap part was provided.

  And the thickness of the lamination direction of a board | substrate is made thin using the formed support | pillar.

  Note that the method for manufacturing a capacitive transducer according to this embodiment may further include the step of providing the following coating layer on the uppermost layer of the capacitive transducer manufactured in the above-described steps. good. The covering layer in the present embodiment is a layer in which an adhesive layer, an acoustic matching layer, a light reflecting layer support layer, and a light reflecting layer are laminated in this order from the side closest to the uppermost layer. Note that layers other than those listed above may be included as appropriate. The light reflection layer is a light reflection layer that includes, for example, gold or the like and reflects light incident from the outside to the inspection object. The light reflection layer support layer is, for example, a layer that includes polyethylene terephthalate (PET) and generally supports a light reflection layer having a small thickness. The acoustic matching layer includes, for example, fluorine-substituted polydimethylsiloxane, and has an intermediate value between the acoustic impedance value of the light reflection layer and the acoustic impedance value of the uppermost layer described above. Sonic) reflection is suppressed. The adhesive layer contains, for example, polydimethylsiloxane without fluorine substitution, and is provided to improve the adhesiveness between the acoustic matching layer and the uppermost layer.

  Here, in order to make it difficult for bubbles to enter when an adhesive layer is provided on the uppermost layer, the difference between the height in the stacking direction of the cell region in which the void is provided and the height of the support column is smaller. Is preferred. The difference between the height in the stacking direction of the cell region provided with the void and the height of the support is preferably 1000 nm or less, more preferably 500 nm or less, and particularly preferably 100 nm or less.

On the other hand, if the difference between the height in the stacking direction of the cell region in which the void is provided and the height of the support column is too small, the stage used when thinning the substrate is likely to come into contact with the vibrating membrane, etc. There must be a difference. From such a viewpoint, the difference between the height in the stacking direction of the cell region provided with the void and the height of the support is preferably 20 nm or more, preferably 30 nm or more, and particularly preferably 50 nm or more.
Therefore, the difference between the height in the stacking direction of the region in which the void portion is provided and the height in the stacking direction of the columns is preferably 20 nm or more and 1000 nm or less, and more preferably 50 nm or more and 100 nm or less.

In addition, in Embodiment 1 and 2 mentioned later, although the coating layer is not specifically described, the above-mentioned content is applied.
(Embodiment 1: Manufacturing method of CMUT)
Hereafter, each process of the manufacturing method of CMUT which concerns on this Embodiment 1 is demonstrated in detail using FIG.

(1-1) Step of providing a substrate (FIG. 1 (1))
In this embodiment, first, the substrate 101 is provided. For the substrate, a material excellent in smoothness and heat resistance is used. For example, as the substrate 101, a silicon or glass substrate having a thickness of 100 μm to 1000 μm can be used.

(1-2) Step of providing a first electrode protective layer (FIG. 1 (1))
Next, the first electrode protective layer 102 is formed in the stacking direction α on the main surface of the substrate 101. In the present embodiment, the first electrode protective layer 102 is made of a material having high electrical insulation and low surface roughness. The first electrode protective layer 102 is provided by a film formation method with high coverage and few defects. From such a viewpoint, for the first electrode protective layer, an insulating film such as silicon oxide, silicon nitride, or glass can be used, and a film formation method such as CVD or PVD can be used. When the substrate 101 is a silicon substrate, the first electrode protective layer 102 is preferably a thermal oxide film because it can be easily formed.
Note that when the substrate is made of a material such as highly insulating glass, the first electrode protective layer is not necessarily formed.

  In the following FIGS. 1 (2) to (14), each layer and each member provided on the substrate are provided in the above-described stacking direction α unless otherwise specified.

(2) Step of providing a first wiring layer (FIG. 1 (2))
Next, a first wiring layer 103 that is electrically connected to the lower electrode layer is provided. The first wiring layer 103 is provided on a region of the substrate from which the first electrode protective layer 102 has been partially removed. A first wiring layer 103 ′ is provided on the first electrode protective layer 102 from which the lower electrode protective layer 102 has not been removed. 103 and 103 ′ are preferably provided by the same process and method, but may be provided by different processes and methods.

(3) Step of providing a lower electrode layer (FIG. 1 (3))
Next, the lower electrode layer 104 is provided on the first wiring layer 103 and the first electrode protective layer 102. Then, a lower electrode layer 104 ′ is provided on the first wiring layer 103 ′. 104 and 104 ′ are preferably provided by the same process and method, but may be provided by different processes and methods.

  Note that in the case where the substrate 101 is insulative, the lower electrode layer 104 may be formed directly on the surface of the substrate 101. The lower electrode layers 104 and 104 'are made of a material having a small surface roughness, excellent heat resistance, and low electrical resistance.

  For the lower electrode layers 104 and 104 ′, a film formation method with high coverage and few defects is used. From this point of view, the lower electrode layers 104 and 104 'are formed by etching, for example, by forming titanium, tungsten, or aluminum as a single layer or multiple layers by CVD, PVD, or the like to a thickness of 30 nm to 1000 nm. To do. The material constituting these lower electrode layers may be an alloy. The lower electrode layer 104 ′ is preferably formed simultaneously with the same material as the lower electrode layer 104. The lower electrode layer 104 ′ has a diameter of 1 μm or more and 100 μm or less, for example, and may be provided between the cells, or may be provided on the entire blank space in the outer periphery of the cell group.

(4) Step of providing a second electrode protective layer (FIG. 1 (4))
Next, a second electrode protective layer 105 that protects the lower electrode layer is provided on the lower electrode layer 104. A second electrode protective layer 105 ′ is provided on the lower electrode layer 104 ′. 105 and 105 ′ are preferably provided by the same process and method, but may be provided by different processes and methods. The second electrode protective layers 105 and 105 ′ are made of a material having a high polar electrical insulation and a small surface roughness. For the second electrode protective layers 105 and 105 ′, a film formation method in which the electrode protective layer has high coverage and few defects is used. From such a viewpoint, the second electrode protective layers 105 and 105 ′ can be made of a material such as silicon oxide, silicon nitride, or glass, and can be formed using a film formation method such as CVD or PVD. In particular, the silicon oxide 105 is preferably made of a material having a high potential potential at the interface with the lower electrode layer in order to make it difficult to be charged during pull-in. Therefore, it is preferable to use silicon oxide as the first membrane layer.

(5) Step of providing a sacrificial layer (FIG. 1 (5))
Next, a sacrificial layer 106 is provided over the second electrode protective layer 105. Then, a sacrificial layer 106 ′ is provided on the second electrode protective layer 105 ′. 106 and 106 ′ are preferably provided by the same process and method, but may be provided by different processes and methods. The sacrificial layers 106 and 106 ′ are formed in order to remove the sacrificial layer by a sacrificial layer etching in a process after the formation of the first membrane layer, which will be described later, and form a void in the cell.

For the sacrificial layers 106 and 106 ′, a material having a small surface roughness, high heat resistance, and a material that can be selectively etched with a material around the sacrificial layer is used. From such a viewpoint, for example, amorphous silicon, polysilicon, chromium, titanium, tungsten, morbden, or an alloy material thereof can be used for the sacrificial layers 106 and 106 ′, and a film formation method such as CVD or PVD is used. be able to. For the sacrificial layer etching, an etching solution containing XeF ₂ , a mixed acid, and a hydrogen peroxide solution as a main solution according to the material of the sacrificial layer can be used.

(6) Step of providing the first membrane layer (FIG. 1 (6))
Next, a first membrane layer 107 is provided in the stacking direction α on the sacrificial layer 106. Then, a first membrane layer 107 ′ is provided in the stacking direction α on the sacrificial layer 106 ′. 107 and 107 ′ are preferably provided by the same process and method, but may be provided by different processes and methods. The first membrane layers 107 and 107 ′ are made of a material having high electrical insulation and low surface roughness.

  For the first membrane layers 107 and 107 ′, a film forming method having excellent coverage and stress controllability is used. From such a viewpoint, the first membrane layer can be made of a material such as silicon oxide, silicon nitride, or silicon carbide, and a film forming method such as CVD or PVD can be used. The first membrane layer 107 functions as a vibrating membrane when receiving and transmitting ultrasonic waves. Therefore, it is preferable to use silicon nitride having an appropriate tensile stress as the first membrane layer.

(7) Step of providing the upper electrode layer (FIG. 1 (7))
Next, the upper electrode layer 108 is provided in the stacking direction on the first membrane layer. An upper electrode layer 108 ′ is provided on the first membrane layer 107 ′. 108 and 108 'are preferably provided in the same process and method, but may be provided in different processes and methods.

  The upper electrode layer is made of a material having a small surface roughness, high heat resistance, and low electrical resistance.

  For the upper electrode layer, a film forming method with high coverage and few defects is used.

  The upper electrode layer is formed by etching, for example, by depositing titanium, tungsten, aluminum, or neodymium as a single layer or a plurality of layers with a film thickness of 30 nm to 1000 nm by CVD, PVD, or the like. The material constituting these upper electrode layers may be an alloy.

(8) Step of providing the second membrane layer (FIG. 1 (8))
Next, a second membrane layer 109 is provided in the stacking direction on the upper electrode layer. A second membrane layer 109 ′ is provided on the upper electrode layer 108 ′. 109 and 109 ′ are preferably provided by the same process and method, but may be provided by different processes and methods. The second membrane layers 109 and 109 ′ are made of a material having high electrical insulation and low surface roughness. For the second membrane layers 109 and 109 ′, a film forming method having excellent coverage and stress controllability is used. From such a viewpoint, for example, a material such as silicon oxide, silicon nitride, or silicon carbide can be used for the second membrane layer, and a film forming method such as CVD or PVD can be used. The second membrane layer 109 functions as a vibration film when receiving and transmitting ultrasonic waves. Therefore, it is preferable to use silicon nitride having an appropriate tensile stress as the second membrane layer. In the case where the first membrane layer and the second membrane layer are provided so as to be in contact with each other, the second membrane layer and the first membrane layer are preferably made of the same material.

(9) Process of providing an etching hole (FIG. 1 (9))
The etching hole 110 is provided to process a part of the first membrane layer 107, the second membrane layer 109, and the upper electrode layer 108 to expose the sacrificial layer. Note that when the second membrane layer 109 is not provided, the etching hole 110 is provided in the first membrane layer 107 and the upper electrode layer 108. In addition, when the area where the upper electrode layer 108 is formed is narrower than the area where the first membrane layer is formed, the etching hole 110 is provided in the first membrane layer. The etching hole 110 is formed by a processing method with high processing accuracy.

  The etching hole can be formed by etching, for example.

(10) Step of providing a void (FIG. 1 (10))
The gap 111 is provided by etching the sacrificial layer 110 through the etching hole. When the gap 111 is provided by performing sacrificial layer etching using a liquid, the gap 111 is dried after being replaced with a chemical having a low surface tension.

For example, an etching gas or an etchant containing XeF ₂ , a mixed acid, or a hydrogen peroxide solution as a main solution can be used for the gap portion according to the material of the sacrificial layer. Of carbon dioxide can be used. In the case where amorphous silicon or polysilicon is used as the material of the sacrificial layer, etching is performed using XeF ₂₋ after removing hydrofluoric acid to remove silicon oxide on the surface of the amorphous silicon and polysilicon.

(11) Step of providing a third membrane layer (FIG. 1 (11))
A third membrane layer 112 is provided in the stacking direction on the second membrane layer. The third membrane layer 112 is formed at least on the etching hole 110. In addition, the third membrane layer 112 is preferably formed so as to seal the gap 110 described above. A third membrane layer 112 ′ is provided on the second membrane layer 109 ′. 112 and 112 ′ are preferably provided by the same process and method, but may be provided by different processes and methods.

The third membrane layers 112 and 112 ′ are made of a material having high electrical insulation. For the third membrane layers 112 and 112 ′, a film forming method having excellent coverage and stress controllability is used. From this perspective,
For the third membrane layers 112 and 112 ′, for example, a material such as silicon oxide, silicon nitride, or silicon carbide can be used, and a film formation method such as CVD or PVD can be used. The third membrane layer 112 functions as a vibration film when receiving and transmitting ultrasonic waves. Therefore, it is preferable to use silicon nitride having an appropriate tensile stress as the third membrane layer 112. When the third membrane layer and the second membrane layer are provided so as to be in contact with each other, it is preferable that the third membrane layer and the second membrane layer are made of the same material.

(12) Step of providing a contact hole (FIG. 1 (12))
A first contact hole 113 is provided in the stacking direction on the second membrane layer 109 and the third membrane layer 112 to expose the upper electrode layer 108 and connect a wiring. Also, a hole is formed in the first membrane layer 107, the second membrane layer 109, the third membrane layer 112, and the second electrode protective layer 105, and the lower electrode layer 104 is exposed to connect the wiring. A second contact hole 113 ′ is provided. The contact holes 113 and 113 ′ can be formed by an etching method.

(13) Step of providing second and third wirings (FIG. 1 (13))
The second wiring 114 is provided in the lower electrode layer 104. The second wiring 114 ′ is provided on the third membrane layer 112.

  A third wiring 115 is provided for electrical connection with the upper electrode layer 108. 114, 114 ', and 115 are preferably provided by the same process and method, but may be provided by different processes and methods.

  The second wiring 114 and the third wiring 115 are provided so that electric signals can be input / output from the outside of the capacitive transducer when ultrasonic waves are transmitted and received.

  At least one of the above-mentioned (3) a step of providing a lower electrode layer, (5) a step of providing a sacrificial layer, (6) a step of providing a first membrane layer, and (7) a step of providing an upper electrode layer The support is formed by the process. Specifically, the height h2 in the stacking direction outside the region β is set higher than the height h1 in the stacking direction of the region β in which the gap is provided. As a result, the support column 120 is formed.

(14) Step of reducing the thickness of the substrate (FIG. 1 (14))
The support column 120 is fixed to the stage 130, and the substrate 101 is thinned using a grinding wheel or the like. As described above, the strut 120 can be formed simultaneously with the transducer forming process, and no additional process is required. For this reason, it is possible to easily provide a support and thin the substrate. Moreover, the support | pillar is provided outside the area | region in which the space | gap part was provided, ie, the area | region where a vibration film vibrates, when transmitting / receiving an ultrasonic wave. Therefore, it is possible to suppress changes in the stress characteristics of the vibrating membrane.
Further, the substrate may be thinned by plasma etching. The etching gas is ionized in a vacuum state, and the substrate is etched using fluorine radicals or chlorine radicals. At this time, since the support is in contact with the chuck surface or tray of the etching apparatus, application of a load to the vibration film can be suppressed.

(Embodiment 2: CMUT)
The configuration of the CMUT according to the present embodiment will be described with reference to a cross-sectional view (FIG. 2) of the CMUT. In the CMUT according to the present embodiment, the first electrode, the insulating film, and the vibration film are arranged in this order from the substrate side in the stacking direction on the substrate, and the insulating film and the vibration film. With a gap between them. The vibrating membrane is configured such that the first membrane and the second electrode are positioned on the gap portion side. And the height of the said lamination direction in the at least one part area | region outside a area | region is provided rather than the height of the lamination direction of the area | region in which the space | gap part was provided.

Hereinafter, an example of a specific configuration will be described.
The CMUT 201 according to this embodiment has a cell structure 202. The CMUT may constitute an element having a plurality of cell structures 202. Furthermore, there may be a plurality of elements. Examples of the shape of the cell structure include a circle, a quadrangle, and a hexagon.

The cell structure 201 includes a substrate 211, a first electrode protective layer (first insulating film) 212 formed on the substrate, a first electrode layer 213 formed on the first electrode protective layer, a first A second electrode protective layer (second insulating film) 214 is provided on the electrode layer. Further, the cell structure 202 has a vibration film including a first membrane layer 216, a second membrane layer 218, a second electrode layer 219, and a third membrane layer 222. The first membrane layer 216, the second membrane layer 218, and the third membrane layer 222 are insulating films containing, for example, silicon nitride. The vibrating membrane is supported by the membrane support portion 217, and is disposed with a cavity 220 as a gap therebetween. As shown in FIG. 2, a portion higher than the height in the stacking direction of the region 202 in which the cavity 220 is provided is provided outside the region 202. This can also be called a column as in the first embodiment. As shown in FIG. 2, the support column may include a sacrificial layer 221 that is stacked in the process of providing the cavity 220.
The first electrode layer 213 and the second electrode layer 219 are opposed to each other, and a voltage is applied between the first electrode layer 213 and the second electrode layer 219 by a voltage application unit (not shown). The

  Further, by using the lead wiring 225, an electric signal can be drawn from the second electrode layer 219. In addition, an electrical signal can be extracted from the first electrode layer 213 by using the extraction wiring 215. Instead of the lead wiring, an electrical signal may be drawn using a through wiring or the like.

  Note that the first electrode layer 213 may be a common electrode, and the second electrode layer may be arranged for each element, whereby an electrical signal may be extracted from the second electrode layer 219, or the reverse configuration may be employed. Absent. That is, the second electrode layer 219 may be used as a common electrode, and the first electrode layer 213 may be arranged for each element, thereby extracting an electrical signal for each element.

  The drive principle of CMUT will be described. When receiving ultrasonic waves by CMUT, a DC voltage is applied to the first electrode layer 213 by a voltage application unit (not shown) so that a potential difference is generated between the first electrode layer and the second electrode layer. deep. When the ultrasonic wave is received, the vibration film having the second electrode layer 219 bends, so the distance between the second electrode layer 219 and the first electrode layer 213 (the distance in the depth direction of the cavity 220) changes. The capacitance changes. This capacitance change causes a current to flow through the lead-out wiring (not shown).

  This current is converted into a voltage by a current-voltage conversion element (not shown) to obtain an ultrasonic reception signal. As described above, by changing the configuration of the lead wiring, a DC voltage may be applied to the second electrode layer 219 and an electrical signal may be drawn from the first electrode layer 213 for each element.

  When transmitting ultrasonic waves, a DC voltage can be applied to the first electrode layer, an AC voltage can be applied to the second electrode layer, and the vibrating membrane can be vibrated by electrostatic force. Ultrasound can be transmitted by this vibration. Also in the case of transmitting an ultrasonic wave, the vibration film may be vibrated by applying a DC voltage to the second electrode layer and an AC voltage to the first electrode layer by changing the configuration of the lead wiring. Further, it is possible to apply a DC voltage and an AC voltage to the first electrode layer or the second electrode layer, and to vibrate the vibrating membrane by electrostatic force. The CMUT according to the present embodiment includes a portion in which the height in the stacking direction in at least a part of the region outside the region is higher than the height in the stacking direction of the region in which the gap is provided. It becomes an obstacle and makes it difficult for an external object to contact the vibrating membrane. As a result, it is possible to reduce the possibility of changing the stress characteristics and the like of the diaphragm when actually used.

DESCRIPTION OF SYMBOLS 101 Board | substrate 102 1st electrode protective layer 103 1st wiring layer 104 Lower electrode layer 105 2nd electrode protective layer 106 Sacrificial layer 107 1st membrane layer 108 Upper electrode layer 109 2nd membrane layer 110 Etching hole 111 Space | gap Portion 112 Third membrane layer 113 First contact hole 114 Second wiring layer 115 Third wiring layer 120 Post 130 Stage

Claims (14)

Providing a lower electrode layer in the stacking direction of the substrates;
Providing a sacrificial layer in the stacking direction on the lower electrode layer;
Forming a first membrane layer in the stacking direction on the sacrificial layer;
Providing an upper electrode layer in the stacking direction on the first membrane layer;
Providing an etching hole in the first membrane layer;
Removing the sacrificial layer through the etching hole to form a void;
A method of manufacturing a capacitive transducer having
The method further includes the step of forming the column by increasing the height in the stacking direction in at least a part of the region outside the region than the height in the stacking direction of the region in which the gap is provided. ,
Using the support pillars to reduce the thickness of the substrate in the stacking direction,
A method for manufacturing a capacitive transducer.   The method of manufacturing a capacitive transducer according to claim 1, wherein the step of forming the support includes a step of forming a layer only outside the region.   The step of forming the support column includes a step of forming a layer so that a layer thickness of a layer provided outside the region is larger than a layer thickness of a layer provided in the region. A method for producing the capacitive transducer according to claim 1. Before the step of providing the lower electrode layer, the step of providing a first electrode protective layer for protecting the lower electrode layer in the stacking direction on the substrate,
The method for manufacturing a capacitive transducer according to any one of claims 1 to 3. After the step of providing the first electrode protective layer and before the step of providing the lower electrode layer, a step of partially removing the first electrode protective layer, and the removal of the first electrode protective layer Providing a first wiring for electrically connecting to the lower electrode layer on the region of the substrate and on the first electrode protective layer,
A method for manufacturing the capacitive transducer according to claim 4. Before the step of providing the sacrificial layer, including a step of providing a second electrode protective layer for protecting the lower electrode layer in the stacking direction on the lower electrode layer.
A method for manufacturing a capacitive transducer according to claim 1. After the step of providing the first membrane layer, the step of forming a second membrane layer in the stacking direction on the first membrane layer,
A method for manufacturing the capacitive transducer according to claim 1. After the step of forming the second membrane layer, the step of forming a third membrane layer in the stacking direction on the second membrane layer,
A method for manufacturing a capacitive transducer according to any one of claims 1 to 7.   The method for manufacturing a capacitive transducer according to any one of claims 1 to 8, wherein the first membrane layer, the second membrane layer, and the third membrane layer are made of the same material. .   The electrostatic discharge according to any one of claims 1 to 9, wherein a difference between the height in the stacking direction of the region in which the gap is provided and the height in the stacking direction of the support column is 20 nm or more and 1000 nm or less. Manufacturing method of capacitive transducer.   The electrostatic discharge according to any one of claims 1 to 10, wherein a difference between the height in the stacking direction of the region in which the gap is provided and the height in the stacking direction of the support columns is 50 nm or more and 100 nm or less. Manufacturing method of capacitive transducer. A capacitive transducer comprising a substrate, a first electrode, an insulating film, and a vibrating film in this order from the substrate side in the stacking direction on the substrate, and the insulating film and the vibration in this order. The vibrating membrane includes a first membrane and a second electrode, and the first membrane is positioned on the gap side. And
An electrostatic capacitance type transducer comprising a portion in which the height in the stacking direction in at least a part of the region outside the region is higher than the height in the stacking direction of the region in which the gap is provided.   The capacitive transducer according to claim 12, wherein a difference between the height in the stacking direction of the region where the gap is provided and the height in the stacking direction of the portion is 20 nm or more and 1000 nm or less.   14. The capacitive transducer according to claim 12, wherein a difference between the height in the stacking direction of the region in which the gap portion is provided and the height in the stacking direction of the portion is 50 nm or more and 100 nm or less.

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