JP2018014878A - Sampling synchronization device of protection relay system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a protection relay device capable of satisfying necessity of dedicated hardware because information exchange is performed in an optical fiber transmission path and sampling synchronization is taken.SOLUTION: The protection relay includes: a hub configured to take time synchronization with a PTP protocol stipulated by IEEE1588; synchronization timing generation means. The synchronization timing generation means is configured to generate a frequency signal corresponding to a frequency of a power system as a result of time synchronization being taken with a PTP protocol stipulated by IEEE1588 and a frequency signal obtained by multiplying a power system frequency.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a sampling synchronizer, and more particularly to a sampling synchronizer for a system that transmits and receives sampling information of a protective relay device that constitutes an IP network using a hub.

  Sampling synchronization in the protective relay system is used, for example, in the PCM current differential relay shown in FIG. As a sampling synchronization method, there is a method of measuring the passage timing of a synchronization frame passing through each device with high accuracy and using the intermediate point as a sampling synchronization point. In the PCM current differential relay shown in FIG. 16 (a), a synchronization frame is flowed from the master station MS to the remote station RS-0 → RS-1 → RS-2 → RS-3 → RS-4 in this order, and the remote station RS− Return at 4 to return to the master station MS. As shown in FIG. 16B, an intermediate point between the uplink and downlink synchronization frame passage times is a synchronization point.

  In the protection relay system as shown in FIG. 16, IEEE 1588, which is a time synchronization protocol that can be used in Ethernet (registered trademark), is being actually used in the system.

  IEEE1588 makes it possible to realize time synchronization with Ethernet microsecond accuracy, which was impossible until now, based on propagation delay time measurement data between nodes. As a result, simultaneous processing among a plurality of devices becomes possible with Ethernet, which is widely used as a basic technology. In PCM current differential protection relay devices, protection relay devices that monitor and protect the amount of electricity over a wide range of systems, such as system stabilization devices, and system stabilization devices, they are placed at different electrical locations. It is important to acquire the amount of electricity of current information and voltage information at a timing synchronized with high accuracy between the devices.

  In the protection calculation in the protection relay device, it is necessary to use sampling data of the amount of electricity acquired at the same time, so the accuracy of the sampling timing is important. As the sampling timing signal, 600 Hz / 720 Hz which is 12 times the system frequency 50 Hz / 60 Hz and 96 times 4.8 KHz / 5.76 KHz are mainly used. The timing error of each sampling frequency obtained by multiplying the frequency of these power systems must be managed in about 20 μs seconds. Hereinafter, the error management is described as 20 μs, but the management accuracy is defined, and the error management may be 10 μs. As an example, the description will be continued with 20 μs.

  Time synchronization by IEEE1588 is a time synchronization function by PTP (Precision Time Protocol) via a LAN or WAN. Patent Documents 1 and 2 are publicly known as those using IEEE 1588 communication technology for a protective relay device.

JP 2000-78740 A JP 2011-200100 A

  In Patent Document 1, as a sampling synchronization circuit, the sampling synchronization of each protection relay device is managed by a sampling time synchronized with the absolute time, and each device does not impair the performance of the distributed protection relay sampling signal. It describes the effective use of measurement data. As a method of synchronization, the PCM current differential relay device and the ring system protection relay device take sampling synchronization by exchanging information of the time division multiplex transmission device in the optical fiber transmission line.

  In the optical fiber transmission line, a dedicated time division multiplex transmission device, an optical signal terminal device, and the like are required. In addition, there is a device in which the protective relay device has a time division multiplexing function directly and lays a dedicated optical fiber transmission line connecting each point, but in any case, the optical fiber transmission line and the time division multiplexing transmission The frame configuration requires the construction of an optical fiber transmission line, dedicated hardware that constitutes a time division multiplex transmission frame, or an optical signal terminal device, etc. It has become a challenge.

  The protection relay system described in Patent Document 2 is a method of managing packet transmission timing by time division of an electrical angle within a sampling period synchronized by IEEE1588. Information is divided into a system current information packet by multiple packets and IEEE1588 time management. Packets are split. The sampling synchronization method based on IEEE1588 time synchronization is a new concept, but for example, when operating in a wide area between remote electrical stations such as 200 km, there is a monitoring method to guarantee the performance applied to the protective relay device Not listed.

  An object of the present invention is to provide a sampling synchronization device that does not require a dedicated device or hardware and has a guaranteed performance.

The present invention connects a plurality of protective relay devices to an electric power system, samples each predetermined electrical angle at each protective relay device, takes in an AC electric quantity, and acquires AC electric quantity information with other protective relay apparatuses. In the protection relay system exchanged by IP communication,
Each protection relay device is provided with a hub configured to synchronize with the PTP protocol defined by IEEE 1588, and a synchronization timing generation means,
The synchronization timing generation means is configured to generate a frequency signal corresponding to the frequency of the power system and a frequency signal obtained by multiplying the power system frequency by time synchronization according to the PTP protocol defined by IEEE1588 of the hub. .

According to claim 2 of the present invention, the synchronization timing generating means latches a count signal from a time counter according to IEEE 1588;
A comparator that inputs the time count signal according to IEEE1588 and converts it into a time counter signal corresponding to the system frequency,
A phase comparison circuit that inputs a signal from the comparator and generates a periodic timing signal corresponding to a system frequency; and
A phase difference detection circuit for detecting a phase difference signal by inputting a signal from the comparator and a free-running pulse signal of a DPLL by an encoder;
A DPLL decoding circuit for generating a control signal by inputting a phase timing signal from the phase comparison circuit and a phase difference signal from the phase difference detection circuit;
A counter circuit that inputs a synchronization timing control signal from the decode circuit and outputs a count signal for DPLL corresponding to the power system frequency;
A sampling signal of a frequency obtained by multiplying a power system frequency from a count signal by the counter circuit, and an encoder that generates a pulse signal for self-running by means of a synchronous timing generation unit of a frequency corresponding to the power system frequency;
It is equipped with.

  According to a third aspect of the present invention, when the phase difference signal from the phase difference detection circuit is within a preset phase difference range, the decoding circuit selects a signal selected from +1, 0, -1 control signals. Is output, and when it is out of the range of the phase difference, a control signal of + α, −α (α is an arbitrary value greater than 1) is selectively output to accelerate the dependency synchronization performance.

According to claim 4 of the present invention, the synchronization timing generating means includes a counter circuit that divides the frequency according to the phase control signal using the oscillation pulse of the crystal oscillator as a clock,
A decode circuit that inputs a count signal divided by a counter circuit and generates a pulse signal a having a frequency corresponding to the frequency of the power system, a pulse signal b obtained by multiplying the frequency of the power system, and a pulse signal c having a frequency of 1 Hz;
A phase comparison circuit for obtaining a differential time pulse e by inputting a 1 Hz signal c generated by a decoding circuit and a 1 Hz signal d of PTP defined by IEEE1588 of the hub;
The obtained differential time pulse e is input, a phase correction amount region for subordinate synchronization set in advance according to the differential time pulse amount is selected, and phase correction signals f1 to fn corresponding to the region are output. A difference amount test circuit for 1 Hz that varies the division ratio of the counter circuit;
It is equipped with.

  According to claim 5 of the present invention, the difference amount test circuit for 1 Hz uses a sampling timing error of 20 μs and a time phase difference within ± 20 μs as a synchronization region with respect to a 1 Hz signal of PTP defined by IEEE1588 of the hub. Outside the synchronization region of the synchronization region ± 20 μs, the phase correction amount for the subordinate synchronization of a plurality of stages obtained by multiplying the time phase difference by 20 μs is output.

According to claim 6 of the present invention, the synchronization timing generating means inputs the pulse signal b obtained by multiplying the power system frequency generated by the decoding circuit and the 1 Hz signal d of the PTP protocol defined by IEEE1588 of the hub, A phase comparison circuit for multiplying free-running that obtains a phase difference amount h between the PTP signal and the self-running count signal of the synchronization timing generating means itself that has multiplied the power system frequency;
The phase difference amount h obtained by the phase comparison circuit for self-running multiplication is input, it is determined whether the phase difference amount is fast or slow with respect to a predetermined time set in advance, and a PTP signal according to the inside or outside of the predetermined time Output the phase correction amounts i1 to i5 of the differential time with variable timing signals from the output to the counter circuit, and outputs the reset signal j to the decode circuit when the phase difference amount h is within a predetermined time. A difference test circuit for running, and
It is provided.

According to claim 7 of the present invention, the phase comparison circuit for multiplication self-running starts with a logical product change of the phase correction signal f from the 1 Hz difference amount test circuit and the 1 Hz signal d of the PTP. ,
Count the time difference until the stop due to the change in the logical product of the PTP signal d and the DPLL free-running count signal b multiplied by the power system frequency,
The phase difference amount h is output to the multiplication self-running difference amount test circuit.

According to the eighth aspect of the present invention, a differential pulse in which a time corresponding to a half cycle of the frequency b obtained by multiplying the power system frequency is fixedly set as a phase adjustment time width on the output side of the phase comparison circuit for multiplication self-running. A number calculation circuit is provided,
The difference pulse number calculation circuit divides the input difference time signal h by the time of the set phase adjustment width, calculates the quotient m for the number of phase corrections and the correction time n for the remainder, and calculates the difference for multiplication self-running. Output to the quantity test circuit,
The differential amount test circuit for multiplication self-running outputs the phase control signal k for the number m of input phase corrections to the counter circuit, and the time corresponding to the remainder correction time n is added to the phase control signal k. Output.

According to claim 9 of the present invention, the synchronization timing generation means includes a counter circuit that divides frequency according to a phase control signal using an oscillation pulse of a crystal oscillator as a clock,
A decoding circuit for inputting a count signal divided by a counter circuit and generating a pulse signal a corresponding to the frequency of the power system;
A phase comparison circuit which obtains a differential time pulse e by inputting the frequency signal d and the frequency signal a generated by the decoding circuit as a frequency signal d corresponding to the frequency of the power system as a PTP signal acquired from the hub;
A difference amount test circuit for inputting the obtained difference time pulse e and obtaining a phase correction signal f corresponding to the difference time;
A phase comparison circuit that compares the phase correction signal f and the PTP signal and outputs a differential time signal h by performing phase comparison for dependent synchronization pull-in in a higher frequency region than the PTP signal d divided by the counter circuit;
A phase difference amount test circuit that generates a phase control signal by changing a correction amount corresponding to the difference time signal h and outputs the phase control signal to the counter circuit;
It is equipped with.

  According to the tenth aspect of the present invention, the difference amount test circuit performs phase correction when the phase difference between the pulse signal a decoded by the decoding circuit and the PTP signal d acquired from the hub is equal to or greater than a synchronous error region. The signal f is activated to correct the phase, and then the pulse signal a from the decoding circuit is set once at the timing of the PTP signal d.

  As described above, according to the present invention, the construction of the optical fiber transmission line, the dedicated hardware constituting the time-division multiplexed frame, or the hardware such as the optical signal terminal device becomes unnecessary. In addition, by combining a PTP synchronization circuit installed on the transmission board of the protective relay device with a simultaneous synchronization (PTP) compatible hub with IEEE1588 functionality, this is the performance that the protective relay device must have. Time synchronization performance can be compensated by a hub that is a network device.

The connection diagram of the protection relay system using the hub which shows embodiment of this invention. The block diagram of the PTP synchronous timing generation circuit of this invention. The schematic block diagram of the protection relay apparatus of this invention. The block diagram of a frequency divider circuit. Frequency division conceptual diagram. The block diagram of the synchronous timing generation circuit by the other Example of this invention. FIG. 6 is an explanatory diagram of phase correction for dependent synchronization. The block diagram of the synchronous timing generation circuit by the other Example of this invention. Explanatory drawing of the phase correction of dependent synchronization. Explanatory drawing of phase-synchronization correction | amendment. The block diagram of the synchronous timing generation circuit by the other Example of this invention. Frequency division conceptual diagram. The block diagram of the synchronous timing generation circuit by the other Example of this invention. Explanatory drawing of phase-synchronization correction | amendment. Explanatory drawing of phase-synchronization correction | amendment. In the conventional PCM current differential relay, (a) is a block diagram, (b) is a sampling explanatory drawing.

  FIG. 1 shows a schematic configuration diagram of a protection relay system according to the present invention. An IP network configuration using a plurality of protection relay devices (relay panels) each using an IEEE1588-compliant hub (HUB). It has become. In a protection relay system that exchanges information via each hub (HUB), time synchronization of all protection relay devices is required. Each protection relay device receives a signal that is output in time synchronization from the hub, and performs DPLL (digital type phase-locked loop) control that synchronizes the signal output to the relay operation with the signal. With such conditions, the common use of sampling data (instantaneous values) serving as system electrical information of each protection relay device is intended and will be described in detail with reference to the drawings.

  FIG. 2 shows a PTP synchronization timing generation circuit according to the IEEE 1588 of the present invention. Here, the relay panel shown in FIG. 1 is called a protective relay device. Hereinafter, for example, description will be made with an example of 50 Hz. When the system frequency is 60 Hz, it may be 60 Hz.

  1 is a counter circuit of PTP according to IEEE 1588, and 8 is a latch circuit of a time count signal k by counter circuit 1 according to IEEE 1588, and outputs a latched absolute time counter signal i. The count signal k from the time counter circuit 1 is an IEEE 1588 absolute time count value, and this count value is also output here to the comparator 2 of 50 Hz (60 Hz when the system frequency is 60 Hz). The time to be synchronized with 50 Hz of the counter circuit 1 according to IEEE 1588 is set in the 50 Hz comparator 2 in order to generate a timing signal to be synchronized in advance. As a result, a 50 Hz synchronization signal a synchronized with IEEE1588 is obtained.

  3 is a phase comparison circuit having a period of 50 Hz, and 4 is a phase difference detection circuit. The phase difference detection circuit 4 includes a 50 Hz synchronization signal a output from the comparator 2 and a timing signal from the encoder 7 (free-running 50 Hz). The time phase difference signal d (Δt) is detected. 5 is a 50 Hz DPLL control decoding circuit which outputs signals e1 to e5. For each signal, e1 performs + α control, e2 performs +1 control, e3 performs 0 control, e4 performs −1 control, and e5 performs −α control.

  Reference numeral 6 denotes a 50 Hz DPLL counter circuit which outputs a count signal f to the encoder 7 and the decoding circuit 5. In addition to the 50 Hz pulse signal b, the encoder 7 outputs a free-running 600 Hz sampling signal g1 using a 50 Hz DPLL and a free-running 4.8 kHz sampling signal g2 using a 50 Hz DPLL.

  The PTP synchronization timing generation circuit shown in FIG. 2 is provided in the protective relay device. For example, the timing signal b is 50 Hz generated from the DPLL circuit, g1 is a 600 Hz pulse generated from the DPLL circuit, and g2 is a 4.8 kHz sampling signal generated from the DPLL circuit, but the frequency to be synchronized is 60 Hz. In this case, b is 60 Hz generated from the DPLL circuit, g 1 is a 720 Hz pulse, and g 2 is a 5.76 kHz sampling signal.

  A frequency of 50 Hz to be synchronized with the comparator 2 is set, and the counter circuit 6 uses the obtained timing signal 50 Hz synchronized with IEEE 1588, and uses a 50 Hz DPLL to obtain a sampling signal that can run freely. The clock of the counter circuit 6 of the 50 Hz DPLL may be controlled with an accuracy of about microseconds in consideration of fluctuations allowed by the sampling synchronization signal. For example, a 20,000 counter circuit that operates with a 1 MHz clock can be incremented by 50 Hz. By using the 50 Hz DPLL counter circuit 6 as the DPLL control decoding circuit 5, a self-running 600 Hz pulse g1 by the 50 Hz DPLL and a free running 4.8 kHz sampling signal g2 by the 50 Hz DPLL are obtained. Can do.

  In each remote protection relay device (or system stabilization device, etc.) shown in FIG. 1, 4.8 capable of self-running by the 50 Hz DPLL obtained by the timing generation circuit by the time synchronization circuit by IEEE1588 between each device. As the kHz sampling signal g2, a sampling signal that compensates for the simultaneity of the instantaneous value of the analog signal of the protection relay system and the system voltage current information can be obtained.

The operation of the timing generation circuit for time synchronization according to IEEE1588 will be described.
The phase difference detection circuit 4 performs phase comparison by inputting two signals: a 50 Hz pulse b capable of self-running by a 50 Hz DPLL and a 50 Hz pulse a generated by the comparator 2 which is a time count signal by IEEE 1588. While doing DPLL operation. The phase comparison circuit 3 having a period of 50 Hz determines the phase advance or phase delay of the input signal a and outputs the phase comparison signal c to the decode circuit 5.

  The phase difference detection circuit 4 determines whether or not the phase difference between the input signals a and b is equal to or smaller than a preset phase difference Δt, and outputs the signal d in the following cases. In this case, the magnitude of the phase difference between the input signals a and b can be seen, and the DPLL follow-up performance can be set in two stages above or below the phase difference Δt. If it is within the range, the DPLL control decode circuit 5 outputs +1 control (e2), 0 control (e3), and -1 control (e4) signals.

  The decode circuit 5 outputs a signal for + α control (e1) and −α control (e5) if the time difference is other than the time difference of the phase difference Δt. With this operation, if the phase difference becomes large, the tracking performance is improved with the α clock, and if the phase difference is in the controlled region of Δt, dependent synchronization of +1, 0, −1 is taken and the DPLL is locked. It becomes a state. That is, it becomes possible to be in a synchronized state. Here, α is an arbitrary value greater than 1. If α is 6, for example, it is possible to pull in 6 times faster.

  The timing generation circuit configured as described above is mounted on the protective relay device together with the hub (HUB in FIG. 1) to share the synchronization performance between the devices. If the hub is equipped with the IEEE1588 function and the synchronization performance is guaranteed by the network equipment, the interface with the protection relay device is generated in the protection relay device based on the timing signal after time synchronization. do it.

  According to this embodiment, it is not necessary to construct an optical fiber transmission line, dedicated hardware constituting a time division multiplexed frame, or hardware such as an optical signal terminal device. In addition, by adopting a standard IP communication method that will expand in the future, system construction with these dedicated devices will be able to solve the equipment cost and technical succession issues.

  FIG. 3 shows a configuration diagram of a timing generation unit of a protective relay device in which the PTP timing signal generation circuit having the IEEE 1588 function shown in FIG. 2 is combined with a hub. The hub 10 generates a PTP (1PPS) timing signal by a PTP protocol having a time counter 11 according to IEEE 1588 and a latch circuit 12 of the time counter 11. 1PPS is a pulse signal with a period of 1 second. Further, the hub 10 generates a failure status and a synchronization status and sends them to the PTP synchronization circuit 20 provided on the transmission board 30.

  The PTP synchronization circuit 20 includes a synchronization monitoring unit 25 for the DPLL 21, a status verification unit 23 that inputs a failure status and a synchronization status and performs status verification, and a logical product that obtains a logical product of the status verification signal and the PTP (1PTP) signal. A circuit 24 is provided. Reference numeral 22 denotes a state monitoring unit for the status verification unit 23.

  The PTP synchronization circuit 20 receives the PTP (1PPS) signal from the hub 10 and inputs the PTP (1PPS) timing signal, the synchronization status, and the failure status three signals, which are necessary for the protection calculation of the protective relay device. A timing signal is generated, and signals SYNC1 (600 Hz or 720 Hz) and SYNC4 (50 Hz or 60 Hz) for performing transmission processing and operating are output to the protection arithmetic unit (not shown) and the transmission CPU 40. Further, the PHY 34 and the LAN controller 33 are connected to the transmission board 30 between the hub 10 and the transmission CPU 40, and Ethernet transmission / reception is executed with a clock by the crystal oscillator 32. Reference numeral 50 denotes a main CPU.

FIG. 4 shows an example of a frequency dividing circuit provided in the PTP synchronizing circuit 20, which divides the clock of the crystal oscillator 31 and outputs SYNC1 and SYNC4. For example, when the output frequency of the crystal oscillator 31 is 1.8432 MHz,
SYNC4 = 60Hz → SYNC1 = 720Hz 1 period 0.1388ms (2560 counts)
SYNC4 = 50Hz → SYNC1 = 600Hz 1 period 0.1666ms (3072 count)
Can be calculated.
FIG. 5 is a conceptual diagram of frequency division.

The PTP synchronization circuit 20 performs phase correction so that SYNC1 and SYNC4 are in phase with the PTP (1PPS) signal. Since an error from the PPS signal is generated depending on the accuracy of the crystal oscillator 31, the error can be dependent-synchronized every time a PTP (1PPS) signal from the hub 10 is received. Dependent synchronization is performed by changing the division ratio when the SYNC1 and SYNC4 are divided from the free-running count signal. However, in the following cases (1) to (3), the dependent synchronization of the free-running count signal is not performed.
(1) A state where the hub 10 is asynchronous according to the IEEE 1588 PTP protocol. Asynchronous is determined by a “synchronization status signal” from the hub 10.
(2) Dependent synchronization is performed when dependent synchronization control is possible in other inter-signal monitoring.
(3) Although synchronization is established between hubs, if the PPS signal output from the hub performs dependent synchronization within the range of ± 20μs with a tolerance of ± 20μs from the free-running count signal as the synchronization region, forward protection An asynchronous state is detected by detecting loss of synchronization due to the continuous number of times.

  In addition, in (1) and (2), the dependent synchronization control is possible, and if the phase is pulled in by the phase comparison operation, the synchronization is pulled in by the continuous number of times of backward protection. As for out-of-synchronization, out-of-synchronization determination is performed based on the number of consecutive times of forward protection. The timing generation circuit is configured so that these operation states can be confirmed by display on the status LED 35 or register access from the transmission CPU 40.

  According to this embodiment, the PTP synchronization circuit 20 installed on the transmission board of the protective relay device is combined with the simultaneous synchronization (PTP) compatible hub 10 having the function of IEEE 1588. The time synchronization performance, which is a performance that must be provided, can be compensated by the hub 10 that is a network device. Thereby, the sharing of the duty of time synchronization by the transmission board 30 and the hub 10 becomes clear. Other effects are the same as those of the first embodiment.

  FIG. 6 shows a circuit configuration of the DPLL 21 (subordinate synchronization counter), and is a DPLL synchronization circuit diagram in which the phase difference amount between the PTP signal and the free-running count signal is varied stepwise. In FIG. 6, 211 is a 1 Hz counter (frequency divider) circuit, 212 is a decode circuit, 213 is a phase comparison circuit, and 214 is a difference amount test circuit. The counter circuit 211 uses the oscillation pulse of the free-running counter crystal oscillator 31 as a clock, and generates a dependent synchronization count signal of 1 s according to the phase correction signal f generated from the comparison result by the difference amount test circuit 214.

  The decode circuit 212 decodes the signal from the counter circuit 211 to obtain predetermined synchronization pulses a, b, and c. Here, the pulse a is, for example, 50 Hz, the pulse b is, for example, 600 Hz, and the pulse c is, for example, 1 Hz (self-running count signal). The decode circuit 212 outputs the decoded 1 Hz pulse c as a comparison input c to the phase comparison circuit 213. The phase comparison circuit 213 receives the PTP signal d from the hub 10 and performs a phase comparison between c and d, and the difference time pulse e is input to the difference amount test circuit 214.

  FIG. 7 is an explanatory diagram of phase control for subordinate synchronization performed in the difference amount test circuit 214 of FIG. The phase correction amount f is determined from the phase difference amount e for subordinate synchronization according to the difference time between the PTP signal and the free-running counter, and the synchronization pull-in is varied stepwise. When the oscillation frequency of the crystal oscillator 31 is, for example, 1.8432 MHz, the DPLL operation of the oscillation circuit is 1 / 1.432 MHz≈542.53 ns for 1 clk time, so control of about 1 μs performs phase control for 2 counts. . In order to realize the following (11) to (16), the phase correction amount f is output for the phase difference e, and the frequency division ratio is changed.

  As a result of the phase comparison in the phase comparison circuit 213, if the time difference between the free-running count signal c and the PTP signal d is in the range of ± F shown in FIG. 7, the phase correction amount is set to 100 ms (184320 counts). Perform preset / reset. If it is from the F region for 1 PPS (1 second), ± 500 ms can be pulled in 5 seconds with a synchronous pulling capacity of 100 ms.

In the six-stage dependent synchronization shown in FIG. 7, the following phase control is performed.
(11) If the phase difference is 20 μs or less (phase difference is 36 counts or less), 1 μs (2 counts) of phase control f1 (area A) during 1 PPS.
(12) If the phase difference is 20 μs or more and 100 μs or less (36 counts or more and 184 counts or less), the phase control is performed at 20 μs (36 counts) f 2 during 1 PPS (region B).
(13) If the phase difference is 100 μs or more and 1 ms or less (184 counts or more and 1843 counts or less), the phase control of 100 μs (184 counts) f3 is performed during 1 PPS (region C).
(14) If the phase difference is 1 ms or more and 10 ms or less (1843 counts or more and 18432 counts or less), 1 ms (1843 counts) f4 phase control (area D) during 1 PPS.
(15) If the phase difference is 10 ms or more and 100 ms or less (18432 counts or more and 184320 counts or less), 10 ms (18432 counts) f5 phase control (area E) during 1 PPS.
(16) If the phase difference is 100 ms or more and 500 ms or less (184320 counts or more and 921600 counts or less), 100 ms (184320 counts) f6 phase control (area F) during 1 PPS.

  For example, assuming that the phase difference amount e is in the F region, adjustment is performed with a synchronization pulling capacity of 100 ms for 1 PPS (1 second), the maximum phase difference amount ± 500 ms is pulled in 5 seconds, and the phase difference enters the region E. . In region E, control is performed with a synchronization pulling capacity of 10 ms with respect to 1 PPS (1 second), the maximum phase difference amount ± 100 ms is pulled in 10 seconds, and the phase difference enters region D. Similarly, by performing synchronous pull-in over a maximum of 10 seconds in region D, a maximum of 10 seconds in region C, and a maximum of 5 seconds in region B, the phase difference enters region A (synchronization region).

  Therefore, according to the third embodiment, synchronous pull-in is performed in a maximum of 40 seconds (= 5 seconds + 10 seconds + 10 seconds + 10 seconds + 5 seconds).

  FIG. 8 shows a synchronous circuit diagram for performing DPLL control with the phase difference between the PTP signal d and the 600 Hz signal b in the DPLL 21 shown in FIG. In this embodiment, the synchronization pull-in time is shorter than the synchronization pull-in time by the subordinate sync counter method shown in FIG. 6, and the subordinate sync counter is constituted by a 600 Hz counter.

  The decode circuit 222 inputs the output signal of the 600 Hz counter circuit 221 to the decode circuit 222 and divides the frequency to obtain a predetermined pulse signal a of 600 Hz ÷ 12 = 50 Hz, a pulse signal b of 600 Hz ÷ 1 = 600 Hz, A pulse signal c of 600 Hz ÷ 600 = 1 Hz is obtained. The obtained 600 Hz signal b is output to the phase comparison circuit 223, and the difference amount e from the PTP signal d (1 Hz) from the hub 10 input to the phase comparison circuit 223 is calculated. In the difference amount test circuit 224, when the difference amount e is tested and the allowable difference is ± 20 μs, it is regarded as an asynchronous state if it is ± 20 μs or more. When asynchronous, the slave control signal f for executing phase correction is activated.

  Phase control is performed starting from the PTP signal d while the signal f is active. AND1 and AND2 output a free-running 600 Hz signal b and a PTP signal d by activating the signal f for performing phase correction. The phase comparison circuit 227 that compares the phases of the edge signals g1 and g2 from the edge extraction circuits 225 and 226 is started by a change in the logical product of the phase correction execution signal f and the PTP signal d, and the PTP signal d and the 600 Hz signal b. The time difference until the stop due to the change of the logical product is counted and output as the phase difference amount h.

  The output of AND3 becomes active at the timing when the 600 Hz signal b becomes active for the first time after the PTP signal d becomes active. Therefore, the difference time signal h output from the phase comparison circuit 227 is input to the phase difference amount test circuit 228 as a signal indicating a delay time of the 600 Hz signal b with respect to the PTP signal d. However, in the phase difference amount test circuit 228, the difference time signal h is a phase difference and will be described as the phase difference amount h. However, when the difference time signal h is 833 μs or more which is a half cycle of 600 Hz, the phase difference amount h−833 μs is obtained. It is recognized that the 600 Hz signal b is faster than the PTP signal d over time.

FIG. 9 is a conceptual diagram of phase correction for dependent synchronization according to this embodiment, and FIG. 10 is an explanatory diagram of phase synchronization correction. The phase difference amount test circuit 228 outputs a dependent control signal i so as to realize the following (21) to (23) according to the difference time of the phase difference amount h, and controls the reset timing of the 600 Hz counter to 600 Hz. Change the period.
(21) If the phase difference is 20 μs or less (the phase difference is 36 counts or less), ± 1 μs (2 counts) phase control i1 (A region) between 1 PPS.
(22) If the phase difference is 20 μs or more and 100 μs or less (36 counts or more and 184 counts or less), 20 μs (36 counts) phase control i2 (B region) between 1 PPS.
(23) If the phase difference is 100 μs or more and 833 μs or less (184 counts or more and 1536 counts or less), the phase control i3 (C region) is 100 μs (184 counts) between 1 PPS.

  If the time difference between the PTP signal d from the hub 10 and the free-running count value b from the decoding circuit 222 in the phase difference amount test circuit 228 is in the region c of FIG. 9, the phase correction amount is 100 μs (184 counts) and 600 Hz The counter circuit 221 is reset. When the phase difference is in the c region, 833 μs can be drawn in 8 seconds with a synchronous pulling ability of 100 μs for 1 PPS (1 second), and the phase difference enters the B region. When the phase difference is in the B region, the phase difference ± 20 μs can be drawn in 5 seconds with a synchronization pulling ability of 20 μs with respect to 1 PPS (1 second), and the phase difference enters the synchronous region which is the A region.

  Therefore, according to the fourth embodiment, the maximum phase difference 833 μs between the PTP signal d (1 Hz) and the 600 Hz signal b can be synchronously drawn in 13 seconds (= 5 seconds + 8 seconds). The position difference amount test circuit 228 determines that the difference time between the PTP signal d and the 600 Hz signal b is shorter than 20 μs from the phase difference amount h from the phase comparison circuit 227, and with the rise of the 600 Hz signal b by the decoding circuit 222. A reset signal j is output to the decoding circuit 222. As a result, by resetting the 50 Hz signal a, 600 Hz signal b, and 1 Hz signal c from the decoding circuit 222, the signals a, b, c synchronized with the PTP signal d from the hub 10 serving as a synchronization reference are obtained. It is done.

  FIG. 11 shows a fifth embodiment. The same reference numerals are given to the same or corresponding parts as those of the fourth embodiment shown in FIG. In this embodiment, the difference from FIG. 8 is that a differential pulse number calculation circuit 229 is provided on the output side of the phase comparison circuit 227, and the phase difference amount test circuit 228 receives the phase correction number signal from the differential pulse number calculation circuit 229. Based on this, the phase adjustment frequency signal is output. As a result, the synchronization pull-in speed is further increased than in the fourth embodiment.

  In FIG. 11, the decode circuit 222 inputs the output signal of the 600 Hz counter circuit 221 to the decode circuit 222 and divides the pulse signal a with a predetermined 600 Hz ÷ 12 = 50 Hz and 600 Hz ÷ 1 = 600 Hz. A pulse signal b and a pulse signal c of 600 Hz ÷ 600 = 1 Hz are obtained. The obtained 1 Hz signal c is output to the phase comparison circuit 223, and a difference amount e from the PTP signal d (1 Hz) from the hub 10 input to the phase comparison circuit 223 is calculated. In the difference amount test circuit 224, when the difference amount e is tested and the allowable difference is ± 20 μs, it is regarded as an asynchronous state if it is ± 20 μs or more. At the time of non-synchronization, the signal f for dependent control for executing phase correction is activated.

  In this embodiment, phase control is performed starting from the PTP signal d while the subordinate control signal f is active. AND1 and AND2 output a free-running 600 Hz signal b and a PTP signal d by activating the signal f for performing phase correction. Since the phase comparison with the edge signals g1 and g2 output from the edge extraction circuits 225 and 226 is performed, the phase comparison circuit 227 starts by a change in the logical product of the phase correction execution signal f and the PTP signal d, and the PTP signal d and 600 Hz. The time difference until the stop due to the change in the logical product of the signal b is counted and output as the phase difference amount h.

  The output signal of AND3 becomes active at the timing when the 600 Hz signal b becomes active for the first time after the PTP signal d becomes active. Therefore, the differential time signal h output from the phase comparison circuit 227 means a delay time of the 600 Hz signal b with respect to the PTP signal d, and this differential time signal h is input to the differential pulse number calculation circuit 229. When the input differential time signal h is 833 μs or more, which is a half cycle of 600 Hz, the differential pulse number calculation circuit 229 has a 600 Hz signal b faster than the PTP signal d by the time of the differential time signal h−833 μs. The phase adjustment width for phase adjustment will be described as 2.7 μs correction (5 counts), for example.

  In the differential pulse number calculation circuit 229, the differential time signal h is divided by the phase adjustment width 2.7 μs determined above, and the quotient is calculated as the number of phase corrections m, and the remainder is calculated as the remainder correction time n (n is 2.7 μs or less). And output to the position difference amount test circuit 228. The phase difference amount test circuit 228 outputs the phase control signal k5 (3072 ± 5 counts) corresponding to the number m of phase corrections to the 600 Hz counter circuit 221. The counter circuit 221 uses 3072 ± 5 counts as the 600 Hz signal. Output. Thereafter, at the end of the number of times of phase correction processing, the position difference amount test circuit 228 takes any one of the phase control signals k (k1 (± 1) to k4 (± 4) corresponding to the remainder correction time n. The counter circuit 221 performs phase correction according to the phase control signal k. As a result, ± 833 μs can be synchronously drawn in approximately 0.5 seconds (833 μs ÷ 2.7 μs × 1/600 Hz = 0.514 s).

  FIG. 12 is a specific explanatory diagram. For example, if the frequency of the crystal oscillator 31 is 1.8432 MHz, 1 count 1 / 1.84200 = 542.53 ns, and the 600 Hz counter circuit 221 applies one pulse of 600 Hz to the (1 /600)/(1/1.843200) = 3072 counts are output. The maximum phase difference h between the PTP signal d from the hub 10 and the 600 Hz signal b is 600 Hz half cycle (1/600 Hz) /2=0.833 ms. Therefore, the count value of the crystal oscillator 31 is 0.833 ms / 542.53 ns = 1536. This is an example in which the phase of the error is corrected in 0.5 s which is half of 1PPS.

  Since 600 Hz is 300 pulses at 0.5 s, the counter adjustment amount for one pulse of the 600 Hz counter circuit 221 is the number of corrections when it is drawn at half-phase count value / 0.5 s = 1536/300 = 5.12 ( ≒ 5) Count (542.53ns × 5count = 2.712267μs). In other words, by correcting the output ± 5 counts of the crystal oscillator 31, it is possible to pull in ± 0.833 ms within 0.5 s. When the phase correction is performed every 5 counts, a remainder of 4 counts or less is generated unless the error count of the PTP signal d and the 600 Hz signal b is a multiple of 5. The remainder is corrected and adjusted at the last timing of the 600 Hz period. For example, if the phase difference h by the phase comparison circuit 227 is ± 999 counts, ± 999/5 = ± 199 remainder is 4 counts, and the counter circuit 221 adjusts 3072 ± 5 counts for 199 times and ± 4 counts for the 200th time Make adjustments.

  After the difference time between the PTP signal d and the 600 Hz signal b becomes shorter than 20 μs, the reset signal j is output from the phase comparison circuit 227 as the 600 Hz signal b rises, and the 50 Hz signal a, 600 Hz signal b, and 1 Hz signal c are output. The respective signals a, b, and c synchronized with the PTP signal d from the hub 10 serving as the synchronization reference are obtained by resetting.

  In addition, if the 600 Hz signal fluctuates greatly, it causes overrun of the main CPU 50 that receives and operates the signal. According to this embodiment, while preventing overrun of the main CPU 50, the third embodiment and the implementation are performed. The synchronization can be pulled in faster than in Example 4.

  FIG. 13 shows an embodiment when the PTP signal is 50 Hz. The decode circuit 232 uses the oscillation pulse of the crystal oscillator 31 as a clock, inputs the output of the counter circuit 231 and divides the frequency to obtain a 50 Hz pulse signal a. The phase comparison circuit 233 compares the 50 Hz pulse signal a from the decoding circuit 232 with the 50 Hz PTP signal d serving as a synchronization reference from the hub 10 to obtain a difference amount e.

  The difference amount test circuit 234 activates the phase correction signal f when the phase difference between the pulse signal a and the PTP signal d is ± 20 μs or more. Since the signal f for executing the phase correction becomes active, the AND1, AND2, and AND3 perform the edge extraction circuit 235 based on the logical product of the PTP signal d serving as the synchronization reference and the 600 Hz pulse signal b from the counter circuit 231. , 236, the edge signals g1, g2 are output to the phase comparison circuit 237.

  The phase comparison circuit 237 performs phase comparison between the PTP signal d and the 600 Hz free-running count signal, generates a phase difference amount h, and outputs it to the phase difference amount test circuit 238. The phase difference amount test circuit 238 outputs a phase control signal i (i1 to i5) corresponding to the phase difference amount h to the counter circuit 231. The counter circuit 231 performs phase correction according to the phase control signal i, and outputs a pulse. When the phase difference between the signal a and the PTP signal d becomes ± 20 μs or less, a reset signal j is output to the decoding circuit 232 to obtain a synchronized signal a.

FIG. 14 is a diagram illustrating the phase difference between the PTP signal d and the 600 Hz free-running count signal, and FIG. 15 is a diagram illustrating the operation.
The phase difference amount test circuit 238 performs the following operations (31) to (34) according to the phase difference amount h.
(31) If the phase difference is 20 μs or less (phase difference +36 counts or less), −0.5 μs (−1 count) phase control i1 (region A−) in 20 ms.
(32) If the phase difference is -20 [mu] s or less (phase difference -36 counts or less), +0.5 [mu] s (+1 count) phase control i2 (region A +) in 20 ms.
(33) If the phase difference is +20 μs or more (phase difference +36 counts or more), the phase control i3 (region B−) is −39 μs (−72 counts) in 20 ms.
(34) If the phase difference is −20 μs or more (phase difference −36 counts or more), +39 μs (+72 counts) phase control i4 (region B +) in 20 ms.

  When performing synchronization pull-in, ± 39 μs adjustment is performed for 50 Hz pulse a. This can be realized by adjusting ± 3.25 μs 12 times for the 600 Hz pulse signal b (600 Hz = 50 Hz × 12 ± 39 μs / 12 = 2.25 μs). The 600 Hz pulse signal b and the 50 Hz pulse a have a frequency at which the main CPU 50 operates, and the main CPU 50 of the protective relay device performs processing determined for each 600 Hz pulse. When performing synchronization pull-in, the main CPU 50 overruns with the start of the next process before the process determined to be shorter is completed.

  In this embodiment, in order to prevent overrun, the adjustment width is reduced to ± 3.25 μs in the 600 Hz signal = 1.66 ms cycle. However, the smaller the phase adjustment width, the longer the phase adjustment takes. In this embodiment, as shown in FIG. 15, the 600 Hz pulse signal b is not adjusted until the 50 Hz pulse signal a is synchronized with the PTP signal d from the hub 10, but the 600 Hz pulse is applied to the PTP signal d. After the 12 times of the signal b are set to the same phase, the 50 Hz pulse signal a synchronized with the PTP signal d from the hub 10 at a high speed is set by setting the 50 Hz pulse once at the rising timing of the 600 Hz pulse signal b. Can be obtained.

Assuming that the phase difference is in the B + region or the B- region in FIG. 14, the maximum phase difference ± 10 ms is controlled by controlling the synchronous pull-in capability of 39 μs for 20 μs.
10ms / 39μs = 256 times (600Hz pulse)
Since 600Hz is 12 times 50Hz,
256/12 = 21.33 times (50Hz pulse)
Therefore, the maximum time required for phase correction from region B to region A in FIG.
21 times x 20μs = 420ms
Thus, 420 ms is the maximum phase correction time.

  Therefore, according to this embodiment, by finely adjusting the time width of 600 Hz at the time of synchronous pull-in, high-speed synchronous pull-in is possible, and overrun occurrence of the main CPU that is processed later is suppressed and stabilized. The main CPU can be operated. Others have the same effects as in the first to fifth embodiments.

DESCRIPTION OF SYMBOLS 10 ... Hub 20 ... PTP synchronous circuit 30 ... Transmission board 40 ... Transmission CPU
50 ... Main CPU
211, 221, 231 ... counter circuit 212, 222, 232 ... decoding circuit 213, 223, 233 ... phase comparison circuit 214, 224, 234 ... difference amount test circuit 227, 237 ... phase comparison circuit 228, 238 for free-running multiplication ... Multiple-running phase difference amount test circuit 229 ... Difference pulse number calculation circuit

Claims (10)

Connect multiple protective relay devices to the power system, sample each specified electrical angle at each protective relay device, capture AC electricity, and exchange AC electricity information with other protective relay devices via IP communication In the protective relay system
Each protection relay device is provided with a hub configured to synchronize with the PTP protocol defined by IEEE 1588, and a synchronization timing generation means,
The synchronization timing generation means is configured to generate a frequency signal corresponding to the frequency of the power system and a frequency signal obtained by multiplying the power system frequency by time synchronization according to the PTP protocol defined by IEEE1588 of the hub. A sampling synchronization device for a protective relay system. The synchronization timing generation means includes a latch circuit that latches a count signal from a time counter according to IEEE 1588, and
A comparator that inputs the time count signal according to IEEE1588 and converts it into a time counter signal corresponding to the system frequency,
A phase comparison circuit that inputs a signal from the comparator and generates a periodic timing signal corresponding to a system frequency; and
A phase difference detection circuit for detecting a phase difference signal by inputting a signal from the comparator and a free-running pulse signal of a DPLL by an encoder;
A DPLL decoding circuit for generating a control signal by inputting a phase timing signal from the phase comparison circuit and a phase difference signal from the phase difference detection circuit;
A counter circuit that inputs a synchronization timing control signal from the decode circuit and outputs a count signal for DPLL corresponding to the power system frequency;
A sampling signal of a frequency obtained by multiplying a power system frequency from a count signal by the counter circuit, and an encoder that generates a pulse signal for self-running by means of a synchronous timing generation unit of a frequency corresponding to the power system frequency;
The sampling synchronizer of the protective relay system according to claim 1, further comprising: When the phase difference signal from the phase difference detection circuit is within a preset phase difference range, the decoding circuit outputs a signal selected from the control signals of +1, 0, −1 to obtain subordinate synchronization, 3. The protection relay system according to claim 2, wherein when the phase difference is out of the range, the control signal of + α, −α (α is an arbitrary value greater than 1) is selectively output to accelerate the dependent synchronization performance. Sampling synchronizer. The synchronization timing generation means includes a counter circuit that divides frequency according to a phase control signal using an oscillation pulse of a crystal oscillator as a clock,
A decode circuit that inputs a count signal divided by a counter circuit and generates a pulse signal a having a frequency corresponding to the frequency of the power system, a pulse signal b obtained by multiplying the frequency of the power system, and a pulse signal c having a frequency of 1 Hz;
A phase comparison circuit for obtaining a differential time pulse e by inputting a 1 Hz signal c generated by a decoding circuit and a 1 Hz signal d of PTP defined by IEEE1588 of the hub;
The obtained differential time pulse e is input, a phase correction amount region for subordinate synchronization set in advance according to the differential time pulse amount is selected, and a phase correction signal f corresponding to the region is output to output the counter A differential amount test circuit for 1 Hz that varies the frequency division ratio of the circuit,
The sampling synchronizer of the protective relay system according to claim 1, further comprising: The differential amount test circuit for 1 Hz uses a sampling timing error of 20 μs as a synchronization region with a time phase difference within ± 20 μs with respect to the PTP 1 Hz signal specified by IEEE1588 of the hub, and is outside the synchronization region of the synchronization region ± 20 μs. 5. The sampling synchronization device for a protective relay system according to claim 4, wherein a phase correction amount for subordinate synchronization of a plurality of stages obtained by multiplying a time phase difference of 20 μs is output. The synchronization timing generation means inputs a pulse signal b obtained by multiplying the power system frequency generated by the decoding circuit and a 1 Hz signal d of the PTP protocol defined by IEEE1588 of the hub, and multiplies the PTP signal and the power system frequency. A phase comparison circuit for multiplying self-running to obtain a phase difference amount h from the self-running count signal of the synchronization timing generating means itself;
The phase difference amount h obtained by the phase comparison circuit for self-running multiplication is input, it is determined whether the phase difference amount is fast or slow with respect to a predetermined time set in advance, and a PTP signal according to the inside or outside of the predetermined time Output a phase correction amount i of a differential time with a variable timing signal from the counter circuit to the counter circuit, and output a reset signal j to the decode circuit when the phase difference amount h is within a predetermined time. A difference amount test circuit of
The sampling synchronization device for a protective relay system according to claim 4 or 5, further comprising: The multiplication self-running phase comparison circuit starts with a logical product change of the phase correction signal f from the 1 Hz difference amount test circuit and the 1 Hz signal d of the PTP,
Count the time difference until the stop due to the change in the logical product of the PTP signal d and the DPLL free-running count signal b multiplied by the power system frequency,
The sampling synchronization device for a protective relay system according to any one of claims 4 to 6, wherein the sampling synchronous device of the protection relay system according to any one of claims 4 to 6, wherein a phase difference amount h is output to the differential amount test circuit for self-running multiplication. Provided on the output side of the phase comparison circuit for self-running multiplication is a differential pulse number calculation circuit in which a time corresponding to a half cycle of the frequency b obtained by multiplying the power system frequency is fixedly set as a phase adjustment time width,
The difference pulse number calculation circuit divides the input difference time signal h by the time of the set phase adjustment width, calculates the quotient m for the number of phase corrections and the correction time n for the remainder, and calculates the difference for multiplication self-running. Output to the quantity test circuit,
The differential amount test circuit for multiplication self-running outputs the phase control signal k for the number m of input phase corrections to the counter circuit, and the time corresponding to the remainder correction time n is added to the phase control signal k. The sampling synchronization device of the protective relay system according to claim 7, wherein The synchronization timing generation means includes a counter circuit that divides frequency according to a phase control signal using an oscillation pulse of a crystal oscillator as a clock,
A decoding circuit for inputting a count signal divided by a counter circuit and generating a pulse signal a corresponding to the frequency of the power system;
A phase comparison circuit which obtains a differential time pulse e by inputting the frequency signal d and the frequency signal a generated by the decoding circuit as a frequency signal d corresponding to the frequency of the power system as a PTP signal acquired from the hub;
A difference amount test circuit for inputting the obtained difference time pulse e and obtaining a phase correction signal f corresponding to the difference time;
A phase comparison circuit that compares the phase correction signal f and the PTP signal and outputs a differential time signal h by performing phase comparison for dependent synchronization pull-in in a higher frequency region than the PTP signal d divided by the counter circuit;
A phase difference amount test circuit that generates a phase control signal by changing a correction amount corresponding to the difference time signal h and outputs the phase control signal to the counter circuit;
The sampling synchronizer of the protective relay system according to claim 1, further comprising: When the phase difference between the pulse signal a decoded by the decoding circuit and the PTP signal d acquired from the hub is equal to or greater than the synchronous error region, the difference amount test circuit activates the phase correction signal f to correct the phase. Thereafter, the pulse synchronization signal a from the decoding circuit is set once at the timing of the PTP signal d, and the sampling synchronizer of the protective relay system according to claim 9.

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