JP2018011236A - Transmission/reception system, transmitter, and receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmission/reception system, a transmitter, and a receiver that can reproduce a broadcast signal even if a terrestrial digital broadcast signal is deteriorated.SOLUTION: Each of transmitters (IP transmitters 10-1 and 10-2) includes demodulation means for demodulating a broadcast signal and transmission means for transmitting data obtained by the demodulation means to a communication network 150-1 or 150-2. A receiver (IP receiver 50) includes reception means for receiving data transmitted by the plurality of transmitters via the communication networks and synthesis/selection means for synthesizing or selecting the pieces of data from the transmitters received by the reception means.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a transmission / reception system, a transmission device, and a reception device.

  As a technique for transmitting terrestrial digital broadcasting or the like via an IP (Internet Protocol) communication network, for example, there is a technique disclosed in Patent Document 1.

  In the technique disclosed in Patent Document 1, the transmission apparatus uses the IQ data extraction unit to obtain in-phase component data (I data) and quadrature component data (Q data) for each carrier for each OFDM symbol from the RF signal of terrestrial digital broadcasting. The in-phase component data and the quadrature component data extracted by the IP output unit are converted into IP packets and output to the communication network. In the receiving apparatus, the IP receiving unit receives I data and Q data that have been converted into IP packets via a communication network, the OFDM signal generating unit extracts I data and Q data, and the extracted I data and Q data are extracted. An inverse Fourier transform is performed to generate an OFDM signal, and an RF signal generation unit frequency-converts the generated OFDM signal and outputs it as an RF signal.

  According to such a technique, it is possible to reduce a necessary transmission band when transmitting terrestrial digital broadcasting or the like via a communication network.

JP 2011-114469 A

  By the way, the technique disclosed in Patent Document 1 has a problem that when the terrestrial digital broadcast signal received on the transmission side is deteriorated, it is difficult to reproduce the broadcast signal on the reception side.

  The present invention has been made in view of the above points, and an object thereof is to provide a transmission / reception system, a transmission device, and a reception device that can reproduce a broadcast signal even when the terrestrial digital broadcast signal is deteriorated. It is said.

In order to solve the above-described problems, the present invention provides a plurality of transmission apparatuses that transmit broadcast signals to a communication network, and reception that receives the broadcast signals transmitted from the plurality of transmission apparatuses via the communication network. In the transmission / reception system, the transmission device includes a demodulation unit that demodulates the broadcast signal, and a transmission unit that transmits data obtained by the demodulation unit to the communication network. An apparatus comprises: a receiving unit that receives the data transmitted from the plurality of transmitting devices via the communication network; and a combining / selecting unit that combines or selects the data from the plurality of transmitting devices received by the receiving unit. And selecting means.
According to such a configuration, the broadcast signal can be reproduced even when the terrestrial digital broadcast signal is deteriorated.

Further, the present invention is characterized in that the transmission means transmits information indicating the reception state of the broadcast signal received by the transmission device, added to the data.
According to such a configuration, the reception apparatus can know the reception state by referring to the information indicating the reception state.

Further, the present invention is characterized in that the combining / selecting means selects data from the transmitting device according to information indicating the reception state.
According to such a configuration, it is possible to reproduce the broadcast signal even when the reception state of some of the transmission devices is poor by selecting data from the transmission device with the best reception state.

Further, the present invention is characterized in that the synthesis / selection unit synthesizes the data or a modulated signal thereof by weighting according to information indicating the reception state.
According to such a configuration, more probable data can be obtained by weighting and combining a plurality of data.

Further, the present invention is characterized in that the information indicating the reception state of the broadcast signal is a MER (Modulation Error Ratio).
According to such a configuration, the reception state can be accurately determined by using the MER.

Further, in the present invention, when the value indicating the reception state of the broadcast signal is equal to or less than a predetermined threshold, the transmission unit transmits data being demodulated by the demodulation unit, and the value indicating the reception state of the broadcast signal When the value exceeds a predetermined threshold value, the data demodulated by the demodulating means is transmitted.
According to such a configuration, correct data restoration can be performed more reliably by transmitting data being demodulated.

Further, the present invention is characterized in that the combining / selecting unit combines or selects the data being demodulated after completing the demodulation process.
According to such a configuration, by transmitting data that is being demodulated, correct data can be more reliably restored and the configuration can be simplified.

Also, the present invention is characterized in that the synthesizing / selecting means demodulates and demodulates the data being demodulated after synthesizing or selecting.
According to such a configuration, by transmitting data that is being demodulated, correct data can be more reliably restored and the configuration can be simplified.

According to the present invention, the transmission device includes an orthogonal demodulation circuit, the transmission means transmits the data in synchronization with a local signal of the orthogonal demodulation circuit, and the reception device orthogonally modulates the data. It has a quadrature modulation circuit, and adjusts the frequency of the local oscillation signal of the quadrature modulation circuit in accordance with the reception timing of the data by the receiving means.
According to such a configuration, it is possible to prevent the occurrence of an error based on the mismatch of the local signals in the transmission device and the reception device.

In addition, the present invention provides a plurality of transmission devices that transmit broadcast signals of terrestrial digital broadcasting to a communication network, and a reception device that receives the broadcast signals transmitted from the plurality of transmission devices via the communication network; The transmission apparatus of the transmission / reception system comprising: a demodulation unit that demodulates the broadcast signal; and a transmission unit that transmits the data obtained by the demodulation unit to the communication network. When the reception state of the broadcast signal is bad, the data being demodulated by the demodulation means is transmitted to the communication network, and when the reception state of the broadcast signal is good, the data demodulated by the demodulation means is sent to the communication network. It transmits to a communication network, It is characterized by the above-mentioned.
According to such a configuration, the broadcast signal can be reproduced even when the terrestrial digital broadcast signal is deteriorated.

In addition, the present invention provides a plurality of transmission devices that transmit broadcast signals of terrestrial digital broadcasting to a communication network, and a reception device that receives the broadcast signals transmitted from the plurality of transmission devices via the communication network; And receiving or receiving the data transmitted from the plurality of transmitting devices via the communication network, and combining or selecting the plurality of data received by the receiving unit. Combining / selecting means, wherein the receiving means receives data in the middle of demodulation transmitted from the transmitting device when the broadcast signal is in poor reception, and the broadcast signal is in good reception Receives the demodulated data transmitted from the transmitter, and the combining / selecting means receives the demodulated data received by the receiving means. The synthesized or selected data after data or demodulation, characterized in that.
According to such a configuration, the broadcast signal can be reproduced even when the terrestrial digital broadcast signal is deteriorated.

  According to the present invention, it is possible to provide a transmission / reception system, a transmission device, and a reception device capable of reproducing a broadcast signal even when the terrestrial digital broadcast signal is deteriorated.

It is a figure which shows the structural example of the transmission / reception system which concerns on 1st Embodiment of this invention. It is a figure which shows the detailed structural example of the IP transmitter of 1st Embodiment. It is a figure which shows the detailed structural example of the IP receiver of 1st Embodiment. It is a figure which shows the detailed structural example of the IP receiver of 2nd Embodiment. It is a figure which shows the detailed structural example of the IP transmitter of 3rd Embodiment. It is a figure which shows the detailed structural example of the IP receiver of 3rd Embodiment. It is a flowchart explaining operation | movement of the IP transmitter of 3rd Embodiment. It is a flowchart explaining operation | movement of the IP receiver of 3rd Embodiment. It is a figure which shows the detailed structural example of the IP transmitter of 4th Embodiment. It is a flowchart explaining operation | movement of the IP receiver of 4th Embodiment. It is a figure which shows the detailed structural example of the IP transmitter of 5th Embodiment. It is a figure which shows the detailed structural example of the IP receiver of 5th Embodiment.

  Next, an embodiment of the present invention will be described.

(A) Description of Configuration of First Embodiment of the Present Invention FIG. 1 is a diagram illustrating a configuration example of a transmission / reception system according to the first embodiment of the present invention. As shown in FIG. 1, the transmission / reception system according to the first embodiment of the present invention includes IP transmission apparatuses 10-1 and 10-2, an IP reception apparatus 50, and a television receiver 90- disposed in each home. 1 to 90-3.

  Here, the IP transmitters 10-1 and 10-2 receive terrestrial digital broadcasts transmitted from a radio tower (not shown) to form IP packets, and the IP receivers via the communication networks 150-1 and 150-2, respectively. 50.

  The IP receiver 50 receives the IP packets transmitted from the IP transmitters 10-1 and 10-2 via the communication networks 150-1 and 150-2, and performs, for example, diversity processing, and then performs the coaxial cable 190. It distributes to television receivers 90-1 to 90-3 arranged in each home via -1 to 190-3.

  FIG. 2 is a diagram illustrating a detailed configuration example of the IP transmission devices 10-1 and 10-2 illustrated in FIG. Since IP transmitting apparatuses 10-1 and 10-2 have the same configuration, these will be described as IP transmitting apparatus 10 below.

  The IP transmitter 10 includes an antenna 11, a tuner 12, a local oscillator signal generator 13, multipliers 14 and 15, a local oscillator signal generator 16, a phase shifter 17, and A / D (Analog to Digital) conversion circuits 18 and 19. FFT (Fast Fourier Transform) circuit 20, remapping circuit 21, MER (Modulation Error Ratio) detection circuit 22, P / S (Parallel to Serial) conversion circuit 23, IP (Internet Protocol) encoding circuit 24, and E A / O (Electrical Optical) conversion circuit 25 is provided.

  Here, the antenna 11 receives, for example, terrestrial digital broadcast radio waves transmitted from a radio tower (not shown) and supplies them to the tuner 12.

  The tuner 12 selects a broadcast signal of a desired channel from the radio wave received by the antenna 11, converts it to an IF (Intermediate Frequency) signal by the local signal supplied from the local signal generator 13, and outputs it. .

  The multipliers 14 and 15 generate I and Q signals by multiplying the IF signal output from the tuner 12 by the local signal output from the local signal generator 16 and output the signals. More specifically, the multiplier 14 extracts the in-phase I (In-phase) component by multiplying the IF signal output from the tuner 12 by the local signal output from the local signal generator 16. And output as an I signal. Further, the multiplier 15 multiplies the IF signal output from the tuner 12 by a local signal whose phase is shifted by π / 2 by the phase shifter 17, thereby extracting a quadrature Q (Quadrature) component. And output as a Q signal.

  The A / D conversion circuits 18 and 19 convert the I and Q signals (analog signals) output from the multipliers 14 and 15 into corresponding digital data and output them.

  The FFT circuit 20 performs FFT processing on the digital data supplied from the A / D conversion circuits 18 and 19 to generate and output OFDM (Orthogonal Frequency Division Multiplexing) symbols.

  The remapping circuit 21 determines the assigned code based on the amplitude and phase information of each carrier included in the data supplied from the FFT circuit 20.

  The MER detection circuit 22 detects the modulation error ratio by comparing the data before and after the remapping by the remapping circuit 21, and information on the detected MER (for example, the MER value itself or information obtained by encoding the MER value, etc.) ) Is supplied to the IP encoding circuit 24.

  The P / S conversion circuit 23 converts the parallel signal output from the remapping circuit 21 into a serial signal and outputs the serial signal.

  The IP encoding circuit 24 adds information on the MER supplied from the MER detection circuit 22 to the serial signal supplied from the P / S conversion circuit 23 to form an IP packet, and supplies the IP packet to the E / O conversion circuit 25.

  The E / O conversion circuit 25 converts the IP packet supplied from the IP encoding circuit 24 into a corresponding optical signal and outputs it to the communication network 150-1 or the communication network 150-2.

  FIG. 3 is a diagram illustrating a detailed configuration example of the IP reception device 50 illustrated in FIG. 1. As shown in FIG. 3, the IP receiver 50 includes O / E (Electrical Optical) conversion circuits 51-1 and 51-2, IP decoding circuits 52-1 and 52-2, and S / P (Serial to Parallel) conversion. Circuits 53-1, 53-2, MER detection circuit 54, selection circuit 55, IFFT (Inverse FFT) circuit 56, IQ modulation circuit 57, local oscillation signal generator 58, multiplier 59, and local oscillation signal generator 60 have.

  Here, the O / E conversion circuits 51-1 and 51-2 receive the optical signals transmitted from the IP transmission devices 10-1 and 10-2, convert them into corresponding electrical signals, and output them.

  The IP decoding circuits 52-1 and 52-2 decode the IP packet expressed by the electrical signal supplied from the O / E conversion circuits 51-1 and 51-2 and extract data included in the IP packet. And output.

  S / P conversion circuits 53-1 and 53-2 convert serial signals supplied from IP decoding circuits 52-1 and 52-2 into parallel signals and output the parallel signals.

  The MER detection circuit 54 detects information about the MER included in the data decoded by the IP decoding circuits 52-1, 52-2, and controls the selection circuit 55 based on the detected information about the MER.

  The selection circuit 55 selectively selects and outputs the parallel signals output from the S / P conversion circuits 53-1 and 53-2 under the control of the MER detection circuit 54.

  The IFFT circuit 56 performs IFFT processing on the data output from the selection circuit 55 to generate and output an OFDM signal.

  The IQ modulation circuit 57 performs IQ modulation on the OFDM signal output from the IFFT circuit 56 by the local signal supplied from the local signal generator 58 and outputs the result.

  The multiplier 59 up-converts the signal subjected to the IQ modulation to a predetermined frequency by the local signal supplied from the local signal generator 60 and outputs the signal.

(B) Description of Operation of First Embodiment of the Invention Next, operation of the first embodiment will be described. In the following, first, the outline of the operation of the first embodiment will be described, and then the detailed operation will be described with reference to FIGS.

  Terrestrial digital broadcasts transmitted from a radio tower (not shown) (one or a plurality of radio towers) are received by antennas arranged in the IP transmitters 10-1 and 10-2. Since the IP transmitters 10-1 and 10-2 are arranged in different places and the geographical situation with the radio tower is different, the state of the broadcast signal of the received terrestrial digital broadcast is also determined by the IP transmitter 10 -1 and 10-2 may differ.

  Therefore, in the first embodiment, the IP transmission devices 10-1 and 10-2 detect MER including information indicating the reception state, and encode information related to the detected MER (for example, the MER value itself or the MER value). Information) is added to the IP packet and transmitted via the communication networks 150-1 and 150-2.

  In the IP receiver 50, the MER detection circuit 54 extracts information about the MER added to the IP packets transmitted from the IP transmitters 10-1 and 10-2. The MER detection circuit 54 refers to information on the MER, selects an IP packet received from the side having a good reception state among the IP transmission devices 10-1 and 10-2 by the selection circuit 55, and converts it into an OFDM signal. To the television receivers 90-1 to 90-3. According to such an operation, the OFDM signal transmitted from the IP receiver 50 to the television receivers 90-1 to 90-3 is received by the terrestrial digital received by the IP transmitters 10-1 and 10-2. Since one of the broadcasts is generated based on a signal with a good signal state, even if one of the terrestrial digital broadcast signals received by the IP transmission devices 10-1 and 10-2 is degraded, By selecting the broadcast signal, the television receivers 90-1 to 90-3 can reproduce the broadcast signal.

  Next, the detailed operation of the first embodiment will be described with reference to FIGS. Terrestrial digital broadcast signals transmitted from a radio tower (not shown) are received by the antennas 11 of the IP transmitters 10-1 and 10-2.

  The tuners 12 of the IP transmitters 10-1 and 10-2 select a desired channel from the terrestrial digital broadcast signal received by the antenna 11, and convert it into an IF signal by the local signal supplied from the local signal generator 13. Convert and output.

  The IF signal output from the tuner 12 is supplied to the multipliers 14 and 15. The multipliers 14 and 15 extract I and Q components from the IF signal output from the tuner 12 and supply them to the A / D conversion circuits 18 and 19.

  The A / D conversion circuits 18 and 19 convert the I and Q signals into digital data and output them. The FFT circuit 20 performs FFT processing on the digital data output from the A / D conversion circuits 18 and 19 and outputs the obtained data.

  The remapping circuit 21 determines the assigned code from the data output from the FFT circuit 20 based on the amplitude and phase information of each carrier. More specifically, the remapping circuit 21 separates 64QAM, 16QAM and accompanying signals (pilot signal, TMCC, etc.) from I and Q data for each carrier, and maps the I and Q data to 7-bit data.

  The MER detection circuit 22 detects the MER indicating the ratio of the vector amount from the ideal symbol position of the constellation such as 64QAM or 16QAM to the received symbol in decibel values, and supplies the MER to the IP encoding circuit 24.

  The P / S conversion circuit 23 converts the parallel signal output from the remapping circuit 21 into a serial signal and supplies the serial signal to the IP encoding circuit 24. The IP encoding circuit 24 adds information on the MER detected by the MER detection circuit 22 to the serial signal supplied from the P / S conversion circuit 23, and then converts the information into an IP packet to convert it into an E / O conversion circuit. 25.

  The E / O conversion circuit 25 converts the IP packet supplied from the IP encoding circuit 24 into an optical signal and outputs the optical signal.

  Through the above processing, IP packets to which information on MER is added are transmitted from the IP transmission devices 10-1 and 10-2.

  The IP receiver 50 receives IP packets transmitted from the IP transmitters 10-1 and 10-2 via the communication networks 150-1 and 150-2. More specifically, the O / E conversion circuit 51-1 receives the IP packet transmitted from the IP transmission device 10-1, converts it into a corresponding electrical signal, and outputs it. Similarly, the O / E conversion circuit 51-2 receives the IP packet transmitted from the IP transmission device 10-2, converts it into a corresponding electrical signal, and outputs it.

  The IP decoding circuits 52-1 and 52-2 decode the IP packets supplied from the O / E conversion circuits 51-1 and 51-2, extract data included in the IP packets, and perform S / P conversion. The signals are supplied to the circuits 53-1 and 53-2, respectively. S / P conversion circuits 53-1 and 53-2 convert serial signals supplied from IP decoding circuits 52-1 and 52-2 into parallel signals and output the parallel signals.

  The selection circuit 55 selects one output of the S / P conversion circuit 53-1 and the S / P conversion circuit 53-2 based on the control of the MER detection circuit 54, and supplies the selected output to the IFFT circuit 56. More specifically, when the reception state of the IP transmission device 10-1 is better than the reception state of the IP transmission device 10-2, more specifically, for example, the MER of the IP transmission device 10-1 Since the value is larger than the value related to the MER of the IP transmission device 10-2, the MER detection circuit 54 detects that the value related to the MER of the IP transmission device 10-1 is larger, and the selection circuit 55 To select the output of the S / P conversion circuit 53-1. As a result, data from the IP transmission device 10-1 having a good reception state is selected and supplied to the IFFT circuit 56. On the other hand, when the reception state of the IP transmission device 10-2 is better than the reception state of the IP transmission device 10-1, the MER detection circuit 54 controls the selection circuit 55 to perform S / P conversion. The output of the circuit 53-2 is selected. When the reception state of the IP transmission device 10-1 and the reception state of the IP transmission device 10-2 are both good, the MER detection circuit 54 determines the predetermined one (for example, the IP transmission device 10- 1) may be selected.

  The IFFT circuit 56 performs IFFT processing on the data supplied from the selection circuit 55 and supplies the obtained OFDM data to the IQ modulation circuit 57. The IQ modulation circuit 57 IQ-modulates the data supplied from the IFFT circuit 56 with the local oscillation signal of a predetermined frequency supplied from the local oscillation signal generator 58 and outputs the data. The multiplier 59 up-converts the data supplied from the local signal generator 60, and receives television receivers 90-1 to 90- arranged in each home via coaxial cables 190-1 to 190-3. Deliver to 3.

  According to the above operation, one of the terrestrial digital broadcast signals received by the IP transmitters 10-1 and 10-2 having a better reception state is selected and is sent to the television receivers 90-1 to 90-3. Since the other is selected even if the reception state of one of the IP transmitters 10-1 and 10-2 is poor, the terrestrial digital broadcast is reproduced by the television receivers 90-1 to 90-3. I can do it.

(C) Description of Configuration of Second Embodiment of the Invention Next, a second embodiment will be described. In the second embodiment, the configuration of the IP receiver 50 in the configuration shown in FIG. 1 is different from that in the first embodiment. Therefore, the second embodiment will be described below with reference to FIG.

  FIG. 4 is a diagram illustrating a configuration example of the IP reception device 50 according to the second embodiment. In FIG. 4, parts corresponding to those in FIG.

  In the configuration example of FIG. 4, the selection circuit 55 is replaced with a synthesis circuit 63 as compared with FIG. 3. In FIG. 3, the IFFT circuit 56, the IQ modulation circuit 57, and the local oscillation signal generator 58 arranged at the subsequent stage of the selection circuit 55 are connected to the IFFT circuits 56-1 and 56-at the previous stage of the synthesis circuit 63. 2 are arranged as IQ modulation circuits 57-1 and 57-2 and local signal generators 58-1 and 58-2. Further, phase circuits 61-1 and 61-2 and coefficient multipliers 62-1 and 62-2 are added after the IQ modulation circuits 57-1 and 57-2. In addition, the MER detection circuit 54 is configured to control the coefficient multipliers 62-1 and 62-2 in accordance with information related to MER. The rest is the same as in FIG.

(D) Description of Operation of Second Embodiment of the Invention Next, the operation of the second embodiment will be described. Note that the second embodiment is different from the first embodiment only in the operation of the IP receiving device 50. Therefore, the following description focuses on the operation of the IP receiving device 50.

  The O / E conversion circuits 51-1 and 51-2 receive the optical signals transmitted from the IP transmission devices 10-1 and 10-2, convert them into corresponding electrical signals, and convert the IP decoding circuits 52-1 and 52-2. -2. The IP decoding circuits 52-1 and 52-2 decode the IP packets supplied from the O / E conversion circuits 51-1 and 51-2, extract data included in the IP packets, and perform S / P conversion. This is supplied to the circuits 53-1 and 53-2.

  S / P conversion circuits 53-1 and 53-2 convert serial signals supplied from IP decoding circuits 52-1 and 52-2 into parallel signals and output the parallel signals. The IFFT circuits 56-1 and 56-2 perform IFFT processing on the data supplied from the S / P conversion circuits 53-1 and 53-2, and the obtained OFDM data is converted into IQ modulation circuits 57-1 and 57-. 2 is supplied.

  The IQ modulation circuits 57-1 and 57-2 IQ-modulate the data supplied from the IFFT circuits 56-1 and 56-2 by the local signal supplied from the local signal generators 58-1 and 58-2. And output. The phase circuits 61-1 and 61-2 adjust the signals output from the IQ modulation circuits 57-1 and 57-2 so as to match and synthesize the signals.

  The coefficient multipliers 62-1 and 62-2 multiply the signals output from the phase circuits 61-1 and 61-2, supplied from the MER detection circuit 54, and output the result. More specifically, the MER detection circuit 54 supplies the coefficient multipliers 62-1 and 62-2 with coefficients determined based on information on the MER detected by the IP decoding circuits 52-1 and 52-2. Specifically, for example, when the MER of the IP transmission device 10-1 detected by the MER detection circuit 54 is X and the MER of the IP transmission device 10-2 is Y, the coefficient multiplier 62-1 includes X / Y (or X / (X + Y)) is supplied as a coefficient, and Y / X (or Y / (X + Y)) is supplied as a coefficient to the coefficient multiplier 62-2. As a result, the coefficients of the coefficient multipliers 62-1 and 62-2 are set to a large value when the reception state of the IP transmitters 10-1 and 10-2 is good, and when the reception state is not good. Since a small value is set, a signal on the good reception state side is output with a larger value.

  The combining circuit 63 combines (for example, adds) the signals output from the coefficient multipliers 62-1 and 62-2, and supplies the combined signal to the multiplier 59. The multiplier 59 up-converts the signal output from the synthesizing circuit 63 with the local signal supplied from the local signal generator 60, and arranges the signal in each home via the coaxial cables 190-1 to 190-3. Distributed to the television receivers 90-1 to 90-3.

  According to the second embodiment described above, after the signals supplied from the phase circuits 61-1 and 61-2 are multiplied by the coefficient corresponding to the value related to MER by the coefficient multipliers 62-1 and 62-2. The synthesis is performed by the synthesis circuit 63. For this reason, when either one of the IP transmitters 10-1 and 10-2 has a bad reception state, the other signal having a good reception state can be synthesized with an increased specific gravity. If both reception states are not good, the data transmitted from the IP transmitters 10-1 and 10-2 are averaged by combining them, and more reliable information is obtained from the television receivers 90-1 to 90-90. -3.

(E) Description of Configuration of Third Embodiment of the Invention Next, a third embodiment of the invention will be described with reference to FIGS. 5 and 6. In the third embodiment, the configurations of the IP transmission devices 10-1 and 10-2 and the IP reception device 50 are different from the configuration shown in FIG. Other configurations are the same as those in FIG.

  FIG. 5 is a diagram illustrating a configuration example of the IP transmission device 10 according to the third embodiment. In FIG. 5, parts corresponding to those in FIG. Compared with FIG. 2, in FIG. 5, a check code check circuit 31, switches 32 and 33 are added, the P / S conversion circuit 23 is replaced with a P / S conversion circuit 23-1, and a P / S conversion circuit 23-2. Has been added. Other configurations are the same as those in FIG.

  Here, the check code check circuit 31 checks whether there is an error in a check code such as TMCC (Transmission and Multiplexing Configuration and Control), and controls the switch 33 based on the check result.

  The switch 32 is controlled by the MER detection circuit 22 and selects one of the output of the FFT circuit 20 and the output of the remapping circuit 21 and supplies it to the P / S conversion circuit 23-1.

  The P / S conversion circuit 23-1 converts the parallel signal output from the switch 32 into a serial signal and supplies it to the switch 33. The P / S conversion circuit 23-2 converts the parallel signal output from the A / D conversion circuits 18 and 19 into a serial signal and supplies it to the switch 33.

  The switch 33 is controlled by the check code check circuit 31, and selects and outputs one of the outputs of the P / S conversion circuits 23-1 and 23-2.

  FIG. 6 is a diagram illustrating a configuration example of the IP receiving device 50 according to the third embodiment. In FIG. 6, parts corresponding to those in FIG. In FIG. 6, compared with FIG. 3, FFT circuits 71-1 and 71-2, a control circuit 72, remapping circuits 73-1 and 73-2, and switches 74-1 and 74-2 are added. Other configurations are the same as those in FIG.

  Here, the FFT circuits 71-1 and 71-2 are supplied from the IP decoding circuits 52-1 and 52-2 via the switches 74-1 and 74-2, similarly to the FFT circuit 20 included in the IP transmission device 10. The processed data is subjected to FFT processing and output.

  The control circuit 72 controls the switches 74-1 and 74-2 and the selection circuit 55 based on the OFDM symbol length output from the IP decoding circuits 52-1 and 52-2.

  The remapping circuits 73-1 and 73-2 are supplied from the IP decoding circuits 52-1 and 52-2 via the switches 74-1 and 74-2, similarly to the remapping circuit 21 included in the IP transmission device 10. Remap the data to be output.

(F) Description of Operation of Third Embodiment of the Invention Next, the operation of the third embodiment will be described. In the following, the outline of the operation of the third embodiment will be described with reference to FIGS. 5 and 6, and then the detailed operation will be described with reference to FIGS. 7 and 8.

  In the third embodiment, the IP transmitters 10-1 and 10-2 select a predetermined pattern from the following three operation patterns according to the state of the check code and the state of the MER.

(1) When there is no error in the check code and the MER is a predetermined value (for example, 20 dB) or more, IQ data is encoded with 7 bits or less per symbol and transmitted.
(2) When there is no error in the check code and the MER is less than a predetermined value (for example, 20 dB), IQ data is encoded with 14 bits or less per symbol and transmitted.
(3) When there is an error in the check code, the baseband IQ time axis waveform is encoded with 28 bits or less per sample and transmitted.

  That is, when the check code check circuit 31 determines that there is no error in the check code, and the MER detection circuit 22 determines that the MER is equal to or greater than a predetermined value (for example, 20 dB) (in the case of (1) described above). The check code check circuit 31 controls the switch 33 to select the output of the P / S conversion circuit 23-1, and the MER detection circuit 22 controls the switch 32 to select the output of the remapping circuit 21. As a result, the output of the remapping circuit 21 is selected, and IQ data is encoded with 7 bits or less per symbol and transmitted.

  When the check code check circuit 31 determines that there is no error in the check code, and the MER detection circuit 22 determines that the MER is less than a predetermined value (for example, 20 dB) (in the case of (2) described above). The check code check circuit 31 controls the switch 33 to select the output of the P / S conversion circuit 23-1, and the MER detection circuit 22 controls the switch 32 to select the output of the FFT circuit 20. As a result, the output of the FFT circuit 20 is selected, and IQ data is encoded with 14 bits or less per symbol and transmitted.

  Further, when the check code check circuit 31 determines that there is an error in the check code (in the case of (3) described above), the check code check circuit 31 controls the switch 33 to control the P / S conversion circuit 23-. 2 output is selected. As a result, the outputs of the A / D conversion circuits 18 and 19 are selected, and the time axis waveform of the baseband IQ is encoded with 28 bits or less per sample and transmitted.

  In the IP receiver 50, the control circuit 72 switches the connection of the switches 74-1 and 74-2 according to the bit length of the data output from the IP decoding circuits 52-1 and 52-2. For example, when the bit length of the data output from the IP decoding circuit 52-1 is 7 bits, the control circuit 72 causes the switch 74-1 to select the S / P conversion circuit 53-1. As a result, the data output from the IP decoding circuit 52-1 is supplied to the S / P conversion circuit 53-1. When the bit length of the data output from the IP decoding circuit 52-1 is 14 bits, the control circuit 72 causes the switch 74-1 to select the remapping circuit 73-1. As a result, the data output from the IP decoding circuit 52-1 is supplied to the remapping circuit 73-1. Furthermore, when the bit length of the data output from the IP decoding circuit 52-1 is 28 bits, the control circuit 72 causes the FFT circuit 71-1 to be selected by the switch 74-1. As a result, the data output from the IP decoding circuit 52-1 is supplied to the FFT circuit 71-1. The switch 74-2 is also controlled in the same way as the switch 74-1.

  Next, the control circuit 72 compares the bit lengths of the data output from the IP decoding circuits 52-1 and 52-2, and selects the shorter one of the S / P conversion circuits 53-1 and 53-2. The selection circuit 55 is made to select the corresponding one. For example, when the bit length of the output data of the IP decoding circuit 52-1 is 7 bits and the bit length of the output data of the IP decoding circuit 52-1 is 14 bits, the control circuit 72 controls the selection circuit 55. Thus, the output of the S / P conversion circuit 53-1 is selected. If the bit lengths of the data output from the IP decoding circuits 52-1 and 52-2 are equal, the control circuit 72 may control the selection circuit 55 to select the predetermined one. Good.

  According to the above operation, data having a bit length corresponding to the reception state of the IP transmission devices 10-1 and 10-2 is transmitted, and the IP reception device 50 selects data having a short bit length, whereby the reception state is Good data can be selected.

  Next, an example of processing executed in the IP transmission device 10 will be described with reference to FIG. When the process shown in FIG. 7 is started, the following steps are executed.

  In step S <b> 10, the MER detection circuit 22 detects MER by comparing the input and output of the remapping circuit 21.

  In step S11, the check code check circuit 31 refers to the output of the remapping circuit 21 and detects the check code.

  In step S12, the check code check circuit 31 determines whether or not there is an error in the check code detected in step S11. If there is an error (step S12: Y), the check code check circuit 31 proceeds to step S13. In (Step S12: N), the process proceeds to Step S14.

  In step S13, the check code check circuit 31 controls the switch 33 to select the output of the P / S conversion circuit 23-2. As a result, the data output from the A / D conversion circuits 18 and 19 is supplied to the IP encoding circuit 24.

  In step S14, the check code check circuit 31 controls the switch 33 to select the output of the P / S conversion circuit 23-1.

  In step S15, the MER detection circuit 22 determines whether or not the MER detected in step S10 is equal to or greater than a predetermined threshold Th (for example, 20 dB), and determines that the MER is equal to or greater than the predetermined threshold Th (step S15). : Y), the process proceeds to step S16, and otherwise (step S15: N), the process proceeds to step S17.

  In step S <b> 16, the MER detection circuit 22 controls the switch 32 to select the output of the remapping circuit 21. As a result, the data output from the remapping circuit 21 is supplied to the IP encoding circuit 24.

  In step S <b> 17, the MER detection circuit 22 controls the switch 32 to select the output of the FFT circuit 20. As a result, the data output from the FFT circuit 20 is supplied to the IP encoding circuit 24.

  In step S18, the MER detection circuit 22 determines whether or not to continue the process. If it is determined that the process is to be continued (step S18: Y), the process returns to step S10 and the same process as described above is repeated. In other cases (step S18: N), the process ends.

  Next, with reference to FIG. 8, processing executed in the IP receiving device 50 will be described. When the flowchart shown in FIG. 8 is started, the following steps are executed.

  In step S30, the control circuit 72 acquires data output from the IP decryption circuit 52-1.

  In step S31, the control circuit 72 determines whether or not one symbol of the IQ data acquired in step S30 is configured with 7 bits or less, and determines that it is configured with 7 bits or less (step S31: In step Y, the process proceeds to step S32. In other cases (step S31: N), the process proceeds to step S33.

  In step S32, the control circuit 72 controls the switch 74-1 to select the input of the FFT circuit 71-1. As a result, the data output from the IP decoding circuit 52-1 is supplied to the FFT circuit 71-1 via the switch 74-1.

  In step S33, the control circuit 72 determines whether or not one symbol of the IQ data acquired in step S30 is configured with 14 bits or less, and determines that it is configured with 14 bits or less (step S33: In Y), the process proceeds to step S34, and in other cases (step S33: N), the process proceeds to step S35.

  In step S34, the control circuit 72 controls the switch 74-1 to select the input of the remapping circuit 73-1. As a result, the data output from the IP decoding circuit 52-1 is supplied to the remapping circuit 73-1 via the switch 74-1.

  In step S35, the control circuit 72 controls the switch 74-1 to select the input of the S / P conversion circuit 53-1. As a result, the data output from the IP decoding circuit 52-1 is supplied to the S / P conversion circuit 53-1 via the switch 74-1.

  In step S36, the control circuit 72 acquires data output from the IP decryption circuit 52-2.

  In step S37, the control circuit 72 determines whether or not one symbol of the IQ data acquired in step S36 is composed of 7 bits or less, and determines that it is composed of 7 bits or less (step S37: In step S38, the process proceeds to step S38. In other cases (step S37: N), the process proceeds to step S39.

  In step S38, the control circuit 72 controls the switch 74-2 to select the input of the FFT circuit 71-2. As a result, the data output from the IP decoding circuit 52-2 is supplied to the FFT circuit 71-2 via the switch 74-2.

  In step S39, the control circuit 72 determines whether or not one symbol of the IQ data acquired in step S36 is composed of 14 bits or less, and determines that it is composed of 14 bits or less (step S39: In step S40, the process proceeds to step S40. In other cases (step S39: N), the process proceeds to step S41.

  In step S40, the control circuit 72 controls the switch 74-2 to select the input of the remapping circuit 73-2. As a result, the data output from the IP decoding circuit 52-2 is supplied to the remapping circuit 73-2 via the switch 74-2.

  In step S41, the control circuit 72 controls the switch 74-2 to select the input of the S / P conversion circuit 53-2. As a result, the data output from the IP decoding circuit 52-2 is supplied to the S / P conversion circuit 53-2 via the switch 74-2.

  In step S42, the control circuit 72 refers to the data output from the IP decoding circuits 52-1, 52-2 and selects the S / P conversion circuits 53-1, 53-2 corresponding to the one with the smaller number of bits. The selection is made by the circuit 55. For example, when the output of the IP decoding circuit 52-1 is 7 bits and the output of the IP decoding circuit 52-2 is 14 bits, the control circuit 72 controls the selection circuit 55 to control the S / P conversion circuit 53-. 1 output is selected. Conversely, when the output of the IP decoding circuit 52-1 is 14 bits and the output of the IP decoding circuit 52-2 is 7 bits, the control circuit 72 controls the selection circuit 55 to control the S / P conversion circuit 53. -2 output is selected. In addition, when the number of output bits of the IP decoding circuit 52-1 and the IP decoding circuit 52-2 is the same, the selection circuit 55 selects either one (for example, a predetermined one).

  In step S43, the control circuit 72 determines whether or not to continue the process. If it is determined to continue the process (step S43: Y), the control circuit 72 returns to step S30 and repeats the same process as described above. In other cases (step S43: N), the process ends.

  As described above, in the third embodiment of the present invention, the IP transmission device 10 refers to the MER and the check code, and when the reception state is good, transmits the demodulated data. When it is not good, the data being demodulated is transmitted. In addition, the IP receiver 50 switches the switches 74-1 and 74-2 in accordance with the number of bits of the received data, and requires the FFT circuits 71-1 and 71-2 and the remapping circuits 73-1 and 73-2. It was made to go through according to it. The selection circuit 55 selects and outputs the one with the smaller number of bits. For this reason, it is possible to select one of the IP transmission apparatuses 10-1 and 10-2 that has a better reception state and receive data. In addition, when the reception state is not good, the data being demodulated is transmitted. Therefore, by monitoring the state of the signal in the IP reception device 50, the IP transmission devices 10-1 and 10- in the remote place are monitored. 2 reception status can be known.

(G) Description of Configuration of Fourth Embodiment of the Invention Next, the configuration of the fourth embodiment of the present invention will be described. In the fourth embodiment, the IP transmission device 10 has the same configuration as that shown in FIG. 5, and the IP reception device 50 has the configuration shown in FIG. Therefore, the configuration of the IP receiving device 50 will be described in detail below with reference to FIG.

  9, parts corresponding to those in FIG. 6 are given the same reference numerals and explanation thereof is omitted. In FIG. 9, compared to FIG. 6, a switch 81, a synthesis circuit 82, and a switch 83 are added. Also, the FFT circuits 71-1 and 71-2 are excluded and the FFT circuit 71 is added, the remapping circuits 73-1 and 73-2 are excluded and the remapping circuit 73 is added, and the switches 74-1 and 74. -2 is excluded, a switch 74 is added, and the control circuit 72 is replaced with a control circuit 84. Further, the selection circuit 55 is excluded. Except for these, it is the same as the case of FIG.

  Here, the switch 81 supplies the output of the IP decoding circuits 52-1 and 52-2 to one of the synthesis circuit 82 and the switch 83 in accordance with the control of the control circuit 84.

  The combining circuit 82 combines the data output from the IP decoding circuits 52-1, 52-2 and outputs the combined data.

  The switch 83 is controlled by the control circuit 84, and selects and outputs one of the data output from the IP decoding circuits 52-1, 52-2.

  The control circuit 84 controls the switch 81, the synthesis circuit 82, the switch 83, and the switch 74 based on the bit length of the data output from the IP decoding circuits 52-1, 52-2.

(H) Description of Operation of Fourth Embodiment of the Invention Next, the operation of the fourth embodiment will be described. Since the operation of the IP transmission device 10 is the same as that of the third embodiment, the operation of the IP reception device 50 will be mainly described below.

  As described above, in the fourth embodiment, the operation of the IP transmission device 10 is the same as that of the third embodiment, and the bit length of one symbol depends on the reception state of the IP transmission devices 10-1 and 10-2. Send data with different numbers.

  In the IP receiving device 50, the control circuit 84 refers to the bit length of one symbol of IQ data output from the IP decoding circuits 52-1, 52-2, and the two bit lengths are equal (IP transmitting device). 10-1 and 10-2 are in the same reception state), the switch 81 is controlled to supply the data output from the IP decoding circuits 52-1 and 52-2 to the synthesis circuit 82. When the reception states of the IP transmitters 10-1 and 10-2 are different), the data output from the IP decoding circuits 52-1 and 52-2 is supplied to the switch 33.

  When the bit lengths for one symbol of IQ data output from the IP decoding circuits 52-1 and 52-2 are equal, the data output from the IP decoding circuits 52-1 and 52-2 is supplied to the combining circuit 82, Therefore, these data (data having the same number of bits) are synthesized. As a synthesis method, for example, it can be obtained by calculating an average value of two data. When there are three or more IP decoding circuits, the majority process may be executed based on three or more data.

  Data output from the synthesis circuit 82 is supplied to the switch 74. The control circuit 84 switches the switch 74 based on the bit length for one symbol of IQ data output from the IP decoding circuits 52-1 and 52-2. More specifically, when the bit length for one symbol is 28 bits, the control circuit 84 controls the switch 74 to select the input of the FFT circuit 71 so that the bit length for one symbol is 14 bits. The input of the remapping circuit 73 is selected, and when the bit length for one symbol is 7 bits, the input of the S / P conversion circuit 53 is selected.

  With the above operation, when the reception states of the IP transmission devices 10-1 and 10-2 are the same, after the data output from the IP decoding circuits 52-1 and 52-2 are combined in the combining circuit 82, the bit is Depending on the number, it is input to any of the FFT circuit 71, the remapping circuit 73, and the S / P conversion circuit 53. As a result, when the reception state is the same, more likely data can be reproduced by combining the data.

  On the other hand, when the reception states of the IP transmitters 10-1 and 10-2 are different, the data output from the IP decoding circuits 52-1 and 52-2 is supplied to the switch 83 via the switch 81. The control circuit 84 controls the switch 83 to select the shorter one of the data output from the IP decoding circuits 52-1 and 52-2. As a result, for example, when the bit length of the data output from the IP decoding circuit 52-1 is shorter than the data output from the IP decoding circuit 52-2, the control circuit 84 controls the switch 83. Thus, the data output from the IP decoding circuit 52-1 is selected. As a result, the data received by the better receiving state of the IP transmitting apparatuses 10-1 and 10-2 is supplied to the switch 74 via the switch 83.

  The control circuit 84 switches the switch 74 based on the bit length of the data having the shorter bit length among the IQ data output from the IP decoding circuits 52-1 and 52-2. More specifically, when the bit length for one shorter symbol is 28 bits, the control circuit 84 controls the switch 74 to select the input of the FFT circuit 71 and the bit length for one symbol is 14. In the case of bits, the input of the remapping circuit 73 is selected, and when the bit length for one symbol is 7 bits, the input of the S / P conversion circuit 53 is selected.

  When the reception states of the IP transmitters 10-1 and 10-2 are different by the above operation, after the data with the better reception state is selected, the FFT circuit 71, remapping is performed according to the number of bits. The signal is input to either the circuit 73 or the S / P conversion circuit 53. As a result, if the reception state is different, more reliable data can be reproduced by selecting the better reception state.

  Next, an example of processing executed in the IP reception device 50 of the fourth embodiment will be described with reference to FIG. When the processing of the flowchart shown in FIG. 10 is started, the following steps are executed.

  In step S50, the control circuit 84 substitutes the variable A for the bit length of one symbol of the IQ data output from the IP decoding circuit 52-1.

  In step S51, the control circuit 84 substitutes the variable B for the bit length of one symbol of the IQ data output from the IP decoding circuit 52-2.

  In step S52, the control circuit 84 compares the bit lengths stored in the variable A and the variable B, and if these are equal (step S52: Y), the process proceeds to step S53, and otherwise (step S52: N). ) Proceeds to step S54.

  In step S53, the control circuit 84 controls the switch 81 to select the input of the synthesis circuit 82.

  In step S54, the control circuit 84 controls the switch 81 to select the input of the switch 83.

  In step S55, the control circuit 84 selects the shorter bit length of the bit lengths stored in the variables A and B and stores them in the variable C. Note that min (A, B) is a function that selects the smaller value among the values in parentheses (values stored in variables). If the values are equal, the value is selected.

  In step S56, the control circuit 84 determines whether or not the bit length stored in the variable C is 7 bits or less. If the bit length is 7 bits or less (step S56: Y), the process proceeds to step S57. In other cases (step S56: N), the process proceeds to step S58.

  In step S57, the control circuit 84 controls the switch 74 to select the input of the S / P conversion circuit 53.

  In step S58, the control circuit 84 determines whether or not the bit length stored in the variable C is 14 bits or less. If the bit length is 14 bits or less (step S58: Y), the process proceeds to step S59. In other cases (step S58: N), the process proceeds to step S60.

  In step S59, the control circuit 84 controls the switch 74 to select the input of the remapping circuit 73.

  In step S60, the control circuit 84 controls the switch 74 to select the input of the FFT circuit 71.

  In step S61, the control circuit 84 determines whether or not to continue the process. If it is determined to continue the process (step S61: Y), the control circuit 84 returns to step S50 and repeats the same process as described above. In other cases (step S61: N), the process ends.

  As described above, in the fourth embodiment of the present invention, when the reception states of the IP transmitters 10-1 and 10-2 are the same, the received data is combined by the combining circuit 82. More reliable data can be reproduced. In addition, when the reception states of the IP transmitters 10-1 and 10-2 are different, better received data is selected by the switch 83, so that more likely data can be reproduced.

  In the fourth embodiment, since the FFT circuit 71, the remapping circuit 73, and the switch 74 have a common configuration, the configuration of the apparatus can be simplified.

(I) Description of Configuration of Fifth Embodiment of the Invention Next, a fifth embodiment of the invention will be described. FIG. 11 is a configuration example of the IP transmission device 10 of the fifth embodiment. FIG. 12 is a diagram illustrating a configuration example of the IP reception device 50 according to the fifth embodiment.

  In FIG. 11, parts corresponding to those in FIG. In FIG. 11, a timing generation circuit 35 is added as compared with FIG. The other configuration is the same as that of FIG. Here, the timing generation circuit 35 generates and outputs a timing signal for transmitting an IP packet in synchronization with the local oscillation signal output from the local oscillation signal generator 16.

  12, parts corresponding to those in FIG. 4 are given the same reference numerals and explanation thereof is omitted. In FIG. 12, compared with FIG. 4, frequency control circuits 85-1 and 85-2 are added. Other configurations are the same as those in FIG. Here, the frequency control circuit 85-1 adjusts the oscillation frequency of the local signal generator 58-1 based on the reception timing of the IP packet by the IP decoding circuit 52-1. The frequency control circuit 85-2 adjusts the oscillation frequency of the local oscillation signal generator 58-2 based on the reception timing of the IP packet by the IP decoding circuit 52-2.

(J) Description of Operation of Fifth Embodiment of the Invention Next, the operation of the fifth embodiment will be described. In the fifth embodiment, the IP encoding circuit 24 of the IP transmitters 10-1 and 10-2 generates and outputs an IP packet in synchronization with the local signal output from the local signal generator 16. .

  In this way, IP packets transmitted at a constant cycle are transmitted to the IP receiver 50 via the communication networks 150-1 and 150-2.

  In the IP receiver 50, the IP packet is converted into an electric signal by the O / E conversion circuits 51-1 and 51-2 and supplied to the IP decoding circuits 52-1 and 52-2. The IP decoding circuits 52-1 and 52-2 decode the IP packets supplied from the O / E conversion circuits 51-1 and 51-2 and supply the decoded IP packets to the S / P conversion circuits 53-1 and 53-2. The frequency control circuits 85-1 and 85-2 synchronize with the timing at which IP packets are received by the IP decoding circuits 52-1 and 52-2, and the oscillation frequencies of the local signal generators 58-1 and 58-2. To control. More specifically, since the transmission timing of the IP packet by the IP encoding circuit 24 is synchronized with the local signal of the local signal generator 16, reception of the IP packet by the IP decoding circuits 52-1, 52-2. Is synchronized with the local signal of the local signal generator 16. For this reason, the local signal generated by the local signal generators 58-1 and 58-2 is adjusted by adjusting the local signal generators 58-1 and 58-2 according to the reception timing of the IP packet. It is possible to synchronize with the local oscillator signal generator 16 included in each of the IP transmitters 10-1 and 10-2. As a result, for example, even when the frequency of the local oscillator signal generator 16 deviates or fluctuates from the reference value, the receiving side can also reliably receive data by adjusting to the same frequency.

(K) Description of Modified Embodiment Each of the above embodiments is an example, and it is needless to say that the present invention is not limited to the case described above. For example, in the first embodiment, a value related to MER may be added to an IP packet and transmitted, and instead of MER, another index value indicating a reception state, for example, BER (Bit Error Rate) may be used.

  In the third embodiment, the IP transmission device 10 shown in FIG. 5 selects and transmits one of the output signals of the A / D conversion circuits 18 and 19, the FFT circuit 20, or the remapping circuit 21. However, either the output signal of the FFT circuit 20 or the remapping circuit 21 may be selected and transmitted.

  In the third embodiment, the selection circuit 55 is switched according to the bit length of the data received by the IP decoding circuits 52-1 and 52-2. Information indicating the reception state (for example, information related to MER or BER) may be added and transmitted, and the IP reception device 50 may switch the selection circuit 55 with reference to the information indicating the reception state. According to such control, for example, when the bit lengths of the data received by the IP decoding circuits 52-1 and 52-2 are the same, the data with the better reception state based on the magnitude comparison of the values Therefore, it is possible to select data having a better reception state.

  Further, in the third embodiment, as shown in FIG. 6, in the IP receiver 50, the demodulated data is selected by the selection circuit 55. For example, the demodulated data is synthesized as shown in FIG. You may make it synthesize | combine.

  Also in the case of the fourth embodiment, as in the case described above, the IP transmitter 10 transmits information indicating the reception state (for example, information on MER or BER) to the IP packet and transmits the IP packet. The switch 81 may be switched with reference to the information indicating the reception state.

  In the fifth embodiment, the IP transmission device 10 synchronizes the encoding timing of the IP encoding circuit 24 with the local signal generated by the local signal generator 16, and the IP reception device 50. Controls the oscillation frequency of the local signal generators 58-1 and 58-2 based on the decoding timing of the IP decoding circuits 52-1 and 52-2. However, the IP transmitter 10 synchronizes the conversion timing of the E / O converter circuit 25 with the local signal generated by the local signal generator 16, and the IP receiver 50 performs the O / E conversion. The oscillation frequencies of the local signal generators 58-1 and 58-2 may be controlled based on the conversion timing of the circuits 51-1 and 51-2.

  Further, in each of the embodiments described above, as the IP transmission devices 10-1 and 10-2 and the IP reception device 50, the configuration example in which the broadcast signal for one channel is transmitted and received is shown, but the same configuration is added. Thus, broadcast signals for a plurality of channels may be transmitted and received.

  Further, in each of the above embodiments, the case where the two IP transmission devices 10-1 and 10-2 are provided has been described as an example, but a configuration including three or more IP transmission devices may be employed. In the case of using three or more configurations, the IP receiving device 50 may add a circuit configuration according to the number of IP transmitting devices. The television receivers 90-1 to 90-3 may also be four or more or two or less.

  Further, in each of the above embodiments, the IP receiver 50 and the television receivers 90-1 to 90-3 are connected by the coaxial cables 190-1 to 190-3. You may make it connect. For example, the output of the IP receiving device 50 may be transmitted as a radio wave, and may function as a gap filler that distributes the radio wave to an area where a radio wave of terrestrial digital broadcasting cannot be directly received, such as a mountainous area, a high-rise building, or an underground mall.

  Further, in each of the above embodiments, the IP receiving device 50 is configured to receive IP packets from the IP transmitting devices 10-1 and 10-2 and perform OFDM modulation to transmit the IP packets. In addition, a storage device (for example, an HDD (Hard Disk Drive) or the like) may be provided to store data included in the IP packet. According to such a configuration, by analyzing the stored data, it is possible to analyze the reception states of the IP transmission apparatuses 10-1 and 10-2 existing at remote locations in one place. In the third and fourth embodiments, since the IP transmitters 10-1 and 10-2 transmit data being demodulated, the reception state is analyzed more accurately by analyzing the data being demodulated. Can do. In addition, since it is transmitted with a small bit length in a good reception state that does not require analysis, it is possible to allocate a limited communication capacity for transmission of information reflecting a bad reception state that is more important in analysis. Become.

10-1, 10-2 IP transmitter (transmitter)
DESCRIPTION OF SYMBOLS 11 Antenna 12 Tuner 13,16 Local signal generator 14,15 Multiplier 17 Phase shifter 18,19 A / D conversion circuit 20,71-1,71-2 FFT circuit (demodulation means)
21, 73-1, 73-2 Remapping circuit (demodulation means)
22 MER detection circuit 23 P / S conversion circuit 24 IP encoding circuit (transmission means)
25 E / O conversion circuit (transmission means)
31 Check code detection circuit 32, 33 Switch 35 Timing generation circuit 50 IP receiver circuit (receiver)
51-1, 51-2 O / E conversion circuit (receiving means)
52-1, 52-2 IP decoding circuit (receiving means)
53-1, 53-2 S / P conversion circuit 54 MER detection circuit 55 selection circuit (selection / combination means)
56 IFFT circuit 57 IQ modulation circuit 58, 60 Local signal generator 59 Multiplier 61-1, 61-2 Phase circuit 62-1, 62-2 Coefficient multiplier 63, 82 Synthesis circuit (selection / synthesis unit)
72, 84 Control circuit 74-1, 74-2, 81 switch 83 switch (selection / combination means)
85-1, 85-2 Frequency control circuit 150-1, 150-2 Communication network 190-1 to 190-3 Coaxial cable

Claims (11)

In a transmission / reception system having a plurality of transmission devices that transmit broadcast signals to a communication network and a reception device that receives the broadcast signals transmitted from the plurality of transmission devices via the communication network,
The transmitter is
Demodulation means for demodulating the broadcast signal;
Transmitting means for transmitting the data obtained by the demodulation means to the communication network,
The receiving device is:
Receiving means for receiving the data transmitted from the plurality of transmitting devices via the communication network;
Combining / selecting means for combining or selecting the data from the plurality of transmission devices received by the receiving means;
A transmission / reception system characterized by that. The transmission means adds information indicating a reception state of the broadcast signal received by the transmission device to the data and transmits the data.
The transmission / reception system according to claim 1. The synthesizing / selecting means selects data from the transmitting device according to information indicating the reception state;
The transmission / reception system according to claim 2. The synthesizing / selecting unit performs weighting according to information indicating the reception state, and synthesizes the data or a modulated signal thereof;
The transmission / reception system according to claim 2.   5. The transmission / reception system according to claim 2, wherein the information indicating the reception state of the broadcast signal is MER (Modulation Error Ratio). The transmission means transmits data being demodulated by the demodulation means when the value indicating the reception state of the broadcast signal is equal to or less than a predetermined threshold, and the value indicating the reception state of the broadcast signal exceeds a predetermined threshold In this case, data demodulated by the demodulator is transmitted.
The transmission / reception system according to claim 1.   7. The transmission / reception system according to claim 6, wherein the synthesizing / selecting unit synthesizes or selects the data being demodulated after completing demodulation processing.     7. The transmission / reception system according to claim 6, wherein the synthesizing / selecting unit demodulates and demodulates the data being demodulated after synthesizing or selecting the data. The transmitter has an orthogonal demodulation circuit, and the transmission means transmits the data in synchronization with a local signal of the orthogonal demodulation circuit,
The receiving apparatus includes an orthogonal modulation circuit that orthogonally modulates the data, and adjusts a frequency of a local oscillation signal of the orthogonal modulation circuit according to a timing of reception of the data by the reception unit.
The transmission / reception system according to claim 1. The transmission / reception system comprising: a plurality of transmission devices that transmit a terrestrial digital broadcast broadcast signal to a communication network; and a reception device that receives the broadcast signal transmitted from the plurality of transmission devices via the communication network. In the transmission device,
Demodulation means for demodulating the broadcast signal;
Transmitting means for transmitting the data obtained by the demodulation means to the communication network,
The transmission means transmits data being demodulated by the demodulation means to the communication network when the reception state of the broadcast signal is poor, and demodulates by the demodulation means when the reception state of the broadcast signal is good. Sending later data to the communication network;
A transmission apparatus characterized by the above. The transmission / reception system comprising: a plurality of transmission devices that transmit a terrestrial digital broadcast broadcast signal to a communication network; and a reception device that receives the broadcast signal transmitted from the plurality of transmission devices via the communication network. In the receiving device,
Receiving means for receiving the data transmitted from the plurality of transmitting devices via the communication network;
Combining / selecting means for combining or selecting a plurality of the data received by the receiving means,
The receiving means receives data in the middle of demodulation transmitted from the transmission device when the reception state of the broadcast signal is bad, and is demodulated from the transmission device when the reception state of the broadcast signal is good. Receive later data,
The synthesizing / selecting means synthesizes or selects data being demodulated or demodulated data received by the receiving means;
A receiving apparatus.

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