JP2018007422A - Insulating synchronous rectification type dc/dc converter, protection method thereof, power source adapter and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DC/DC converter improved in reliability.SOLUTION: A feedback circuit 206 drives a light-emitting element of a photocoupler 204 so that a detection voltage Vnears a target voltage according to an output voltage Vof a DC/DC converter 200. A primary-side controller 202 is connected to the light-receiving element of the photocoupler 204, and switches a switching transistor M1 according to a feedback signal V. A synchronous rectification controller 300 has a gate (GATE) pin connected to a gate electrode of a synchronous rectification transistor M2, and drives the synchronous rectification transistor M2. A gate open detection circuit 350 is provided outside the synchronous rectification controller 300, and connected to the gate electrode of the synchronous rectification transistor M2. The gate open detection circuit judges no pulse appearing on the gate electrode as a gate open abnormality in which the gate pin of the synchronous rectification controller 300 is electrically open.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an isolated synchronous rectification type DC / DC converter.

  Flyback DC / DC converters are used in various power supply circuits including AC / DC converters. 1A is a circuit diagram of a diode rectification type flyback converter 200R, and FIG. 1B is a circuit diagram of a synchronous rectification type flyback converter 200S.

The flyback converter 200R of FIG. 1A receives the input voltage _VIN of the input terminal P1, generates a DC output voltage _VOUT stabilized to a predetermined target voltage, and outputs the output terminal P2 and the ground terminal P3. A load (not shown) connected between them is supplied. A switching transistor M1 is connected to the primary winding W1 of the transformer T1, and a diode D1 is connected to the secondary winding W2. The output capacitor C1 is connected to the output terminal P2.

The feedback circuit 206 drives the light emitting element of the photocoupler 204 with a current corresponding to an error between the output voltage _VOUT and the target voltage _{VOUT (REF)} . A feedback current _IFB corresponding to the error flows through the light receiving element of the photocoupler 204. Primary controller (Primary Controller) The 202 FB (feedback) pin, the feedback signal _{V FB} is generated in response to the feedback current _{I FB,} the duty ratio primary controller 202 in response to the feedback signal _{V FB} (or frequency) Is generated to drive the switching transistor M1.

In a flyback converter diode rectification type in FIG. 1 (a), in the diode D1, the power loss of the Vf × _{I OUT} occurs. Vf is a forward voltage, and _IOUT is a load current. If Vf = 0.5V and I _OUT = 10A, the power loss is 5W. Therefore, in many applications, a heat sink or a heat sink for cooling the diode D1 is required.

  A flyback converter 200S in FIG. 1B includes a synchronous rectification transistor M2 and a synchronous rectification controller (also referred to as a synchronous rectification IC) 300S instead of the diode D1 in FIG. The synchronous rectification controller 300S switches the synchronous rectification transistor M2 in synchronization with the switching of the primary side switching transistor M1.

In the synchronous rectification type flyback converter, the loss of the synchronous rectification transistor M2 is R _ON × I _OUT ² . R _ON is the on-resistance of the synchronous rectification transistor M2, and when R _ON = 5 mΩ and I _OUT = 10 A, the loss is 0.5 W, which is greatly reduced compared to the diode rectification type. Therefore, theoretically, in the synchronous rectification type, a heat sink and a heat sink are unnecessary or can be simplified.

JP 2009-159721 A

  As a result of studying the synchronous rectification type converter of FIG. 1B, the present inventors have recognized the following problems.

  If there is a mounting failure in the synchronous rectification controller 300S and peripheral circuit elements and the gate and source of the switching transistor M2 are short-circuited, a failure mode in which switching of the switching transistor M1 becomes impossible may occur.

  For example, the gate electrode and the source electrode of the synchronous rectification transistor M2 are pulled down via a resistor. When the solder between the gate (GATE) pin of the synchronous rectification controller 300 and the mounting board is removed, the gate and the source of the synchronous rectification transistor M2 are short-circuited, so that the synchronous rectification transistor M2 is fixed in the off state. Note that a switching pulse is generated at the GATE pin at this time.

At this time, the DC / DC converter 200s operates in the diode rectification mode by replacing the body diode D2 of the synchronous rectification transistor M2 with the diode D1 of FIG. At this time, an appropriate output voltage _VOUT continues to be supplied to the load, but a power loss of 5 W occurs in the body diode D2.

  If a current continues to flow through the body diode D2 of the synchronous rectification transistor M2, there is a problem that the synchronous rectification transistor M2 generates abnormal heat. Further, the heat generated by the synchronous rectification transistor M2 may reduce the reliability of the synchronous rectification transistor M2 itself or peripheral circuit elements.

  For this measure, it is necessary to take a measure such as connecting a diode element (not shown) having a capacity larger than that of the body diode D2 in antiparallel with the synchronous rectification transistor M2, which increases the cost and increases the mounting area. .

  The present invention has been made in view of such a problem, and one of exemplary purposes of an embodiment thereof is to provide a DC / DC converter with improved reliability.

  One embodiment of the present invention relates to an isolated synchronous rectification type DC / DC converter. The DC / DC converter includes a transformer having a primary winding and a secondary winding, a switching transistor connected to the primary winding of the transformer, a synchronous rectification transistor connected to the secondary winding of the transformer, a light emitting element, and A photocoupler including a light receiving element, a feedback input circuit having a control input pin for receiving a detection voltage corresponding to the output voltage of the DC / DC converter, and driving the light emitting element of the photocoupler so that the detection voltage approaches the target voltage; A primary-side controller that is connected to the light-receiving element of the photocoupler and switches the switching transistor according to a feedback signal from the light-receiving element, and has a gate pin connected to the gate electrode of the synchronous rectification transistor, and drives the synchronous rectification transistor Synchronous rectification controller and external to synchronous rectification controller A gate open detection circuit that is connected to the gate electrode of the synchronous rectification transistor and determines that the gate pin of the synchronous rectification controller is electrically open when a pulse is not generated in the gate electrode, the gate open abnormality being Prepare.

  According to this aspect, by mounting the gate pin open detection circuit outside the synchronous rectification controller, it is possible to take appropriate protection measures when a gate pin open abnormality occurs. As a result, the DC / DC converter can be prevented from continuing to operate in the diode rectification mode, and the reliability can be improved.

The DC / DC converter may include an overvoltage protection circuit that stops switching of the switching transistor when the output voltage exceeds an overvoltage threshold. The gate open detection circuit may forcibly reduce the detection voltage when no pulse is generated in the gate electrode.
When the gate open abnormality occurs and the detection voltage is forcibly lowered, the duty ratio of the primary side switching transistor increases and the output voltage rises. When the output voltage exceeds the overvoltage threshold, the switching transistor is stopped. This can protect the circuit.

  The overvoltage protection circuit may resume switching of the switching transistor when the output voltage falls below the release threshold. In this case, when a gate open abnormality occurs, an intermittent operation is performed in which the operation period and the stop period are alternately repeated. By setting the stop period to the same time scale as the relaxation time during which the heat of the synchronous rectification transistor decreases, the temperature increase of the synchronous rectification transistor can be suppressed.

The gate open detection circuit may not reduce the detection voltage in a light load state of the DC / DC converter.
The load power of the DC / DC converter is proportional to the current flowing through the synchronous rectification transistor. Therefore, since the current of the synchronous rectification transistor is small when the load power is small, there may be no problem even if it operates in the diode rectification mode. According to this aspect, when the load power is smaller than a certain level, the power can be continuously supplied to the load.

  The gate open detection circuit may not reduce the detection voltage when the low level time of the periodic signal generated at the drain electrode of the synchronous rectification transistor is short. In the light load state, the low level time of the periodic signal is shortened, so that the load power can be estimated.

The gate open detection circuit includes a capacitor, a first path for charging the capacitor with the voltage of the gate electrode, and a second path for charging and discharging the capacitor with the voltage of the drain electrode of the synchronous rectification transistor. Accordingly, the detection voltage may be changed.
The voltage of the capacitor is high when a pulse is generated in the gate electrode, and is low when no pulse is generated. Furthermore, even when no pulse is generated in the gate electrode, the capacitor is charged and discharged by a periodic signal. However, in a light load state, the low level time is short, so the amount of charge discharged from the capacitor is reduced. The voltage increases. Therefore, the detection voltage can be changed as desired by appropriately setting the charging speed and discharging speed of the first path and the second path.

  The first path may include a first diode arranged such that the cathode is on the capacitor side. The second path may include a second diode arranged in a direction in which the cathode is on the drain electrode side, and a resistor connected in parallel with the second diode.

  The gate open detection circuit may further include a third diode provided between the capacitor and the control input pin so that the cathode faces the capacitor. Thereby, the voltage of the control input pin can be lowered according to the voltage of the capacitor.

  The gate open detection circuit may include a peak hold circuit for peak-holding the signal of the gate electrode, and may change the detection voltage based on the output voltage of the peak hold circuit. The gate open detection circuit may correct the output voltage of the peak hold circuit based on the duty ratio of the periodic signal generated at the drain electrode of the synchronous rectification transistor.

  The DC / DC converter may be a flyback converter. The DC / DC converter may be an LLC converter.

  Another embodiment of the present invention relates to an electronic device. Electronic equipment includes a load, a diode rectifier circuit that full-wave rectifies the commercial AC voltage, a smoothing capacitor that generates a DC input voltage by smoothing the output voltage of the diode rectifier circuit, and steps down the DC input voltage and supplies it to the load Any of the above-described DC / DC converters may be provided.

  Another aspect of the present invention relates to a power adapter. The power adapter includes a diode rectifier circuit that full-wave rectifies a commercial AC voltage, a smoothing capacitor that generates a DC input voltage by smoothing an output voltage of the diode rectifier circuit, and supplies the load by stepping down the DC input voltage. Any one of the DC / DC converters may be provided.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, heat generation of the DC / DC converter can be suppressed.

1A is a circuit diagram of a diode rectification type flyback converter, and FIG. 1B is a circuit diagram of a synchronous rectification type flyback converter. It is a circuit diagram of the insulation type DC / DC converter which concerns on embodiment. FIG. 3 is an operation waveform diagram of the DC / DC converter of FIG. 2. It is a circuit diagram of the structural example of a DC / DC converter. FIGS. 5A and 5B are operation waveform diagrams of the DC / DC converter at the time of heavy load and light load. It is a circuit diagram of an AC / DC converter provided with a DC / DC converter. It is a figure which shows an AC adapter provided with an AC / DC converter. FIGS. 8A and 8B are diagrams illustrating an electronic device including an AC / DC converter.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through other members that do not affect the state or inhibit the function is also included.

  Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. This includes cases where the connection is indirectly made through other members that do not affect the connection state or inhibit the function.

FIG. 2 is a circuit diagram of an insulation type DC / DC converter 200 according to the embodiment. The DC / DC converter 200 is a flyback converter, receives the input voltage _VIN of the input terminal P1, generates a DC output voltage _VOUT stabilized at a predetermined target voltage, and outputs the output terminal P2 and the ground terminal P3. To a load (not shown) connected between the two.

The transformer T1 has a primary winding W1, a secondary winding W2, and an auxiliary winding W3. One end of the primary winding W1 is connected to the input terminal P1 and receives a DC input voltage _VIN . The drain of the switching transistor M1 is connected to the other end of the primary winding W1 of the transformer T1. A sense resistor _RCS for current detection is inserted between the source of the switching transistor M1 and the ground line.

  The synchronous rectification transistor M2 and the secondary winding W2 of the transformer T1 are provided in series between the output terminal P2 and the ground terminal P3. The output capacitor C1 is connected between the output terminal P2 and the ground terminal P3.

Photocoupler 204 includes a light emitting element and a light receiving element. The light emitting element is biased by resistors R ₂₁ and R ₂₂ . The feedback circuit 206 drives the light emitting element of the photocoupler 204 so that the output voltage _VOUT of the DC / DC converter 200 approaches the target voltage _{VOUT (REF)} . For example, the feedback circuit 206 receives a detection voltage V _OUTS obtained by dividing the output voltage _VOUT by the resistors R ₁₁ and R _{12 at} its control input (SH_IN) pin, and a current corresponding to an error between the detection voltage V _OUTS and the target voltage. The light emitting element of the photocoupler 204 is driven by _IERR . For example, the feedback circuit 206 may include a shunt regulator or an error amplifier.

The primary controller 202 is connected to the light receiving element of the photocoupler 204. A feedback signal V _FB corresponding to a feedback current I _FB flowing through the light receiving element of the photocoupler 204 is generated at the feedback (FB) pin of the primary controller 202. The current detection (CS) terminal of the primary-side controller 202, the current detection signal _{V CS} generated in the sense resistor _{R CS} is input.

The primary-side controller 202 generates a pulse signal having a duty ratio (or frequency) corresponding to the feedback signal V _FB and outputs it from the output (OUT) terminal to drive the switching transistor M1. The configuration and control method of the primary controller 202 are not particularly limited. For example, the primary controller 202 may be a current mode modulator. In this case, the duty ratio of the pulse signal is adjusted according to the current detection signal _VCS .

The auxiliary winding W3 of the transformer T1 forms a self power supply circuit 208 together with the diode D3 and the capacitor C3. Supply voltage _{V CC} to self-powered circuit 208 is generated is supplied to the power supply of the primary controller 202 (VCC) terminal.

The synchronous rectification controller 300 controls the synchronous rectification transistor M2. The diode D2 is a body diode of the synchronous rectification transistor M2. For example, the synchronous rectification controller 300 generates a control pulse based on the drain-source voltage _VDS2 of the synchronous rectification transistor M2, and supplies a gate pulse corresponding to the control pulse to the gate of the synchronous rectification transistor M2.

  The synchronous rectification controller 300 is housed in one package and has at least a drain (DRAIN) pin, a source (SOURCE) pin, and a gate (GATE) pin. The SOURCE pin is a ground terminal of the synchronous rectification controller 300.

The synchronous rectification controller 300 drives the synchronous rectification transistor M2 based on the voltage V _{D2 of the} DRAIN pin (drain-source voltage V _{DS2 of} the synchronous rectification transistor M2).

  The gate open detection circuit 350 is provided outside the synchronous rectification controller 300 and is connected to the gate electrode of the synchronous rectification transistor M2. The gate open detection circuit 350 determines that the GATE pin of the synchronous rectification controller 300 is electrically open (gate open abnormality) when no pulse is generated in the gate electrode.

  When detecting the gate open abnormality, the gate open detection circuit 350 acts on other circuits so that the switching of the switching transistor M1 by the primary controller 202 is stopped.

The DC / DC converter 200 includes an OVP (overvoltage protection) circuit 390 that stops switching of the switching transistor M1 when the output voltage _VOUT exceeds the overvoltage threshold value V _OVP1 . In FIG. 2, the OVP circuit 390 is built in the feedback circuit 206. The OVP circuit 390 may detect an overvoltage state based on the voltage V _OUTS of the SH_IN pin. A voltage corresponding to the output voltage _VOUT is generated at the output (SH_OUT) pin of the feedback circuit 206. Therefore, the OVP circuit 390 may detect an overvoltage state based on the voltage of the SH_OUT pin. The OVP circuit 390 strongly drives the light emitting element of the photocoupler 204 in the overvoltage state. As a result, the feedback current I _FB increases, the feedback signal V _FB decreases, and the switching of the switching transistor M1 stops.

When detecting a gate open abnormality, the gate open detection circuit 350 forcibly decreases the voltage (detection voltage V _OUTS ) of the SH_IN pin of the feedback circuit 206.

  The above is the configuration of the DC / DC converter 200. Next, the operation will be described. FIG. 3 is an operation waveform diagram of the DC / DC converter 200 of FIG.

In before time t _0, DC / DC converter 200 is normal, the pulse signal is generated in the gate electrode of the synchronous rectifier transistor M2. The detection voltage V _OUTS is stabilized to the reference voltage V _REF by feedback, and as a result, the output voltage V _OUT is stabilized to the target level V _{OUT (REF)} .

Gate open abnormality occurs at time t _0. Then, the pulse of the gate electrode of the synchronous rectification transistor M2 disappears and the low level is maintained. The gate open detection circuit 350 forcibly decreases the voltage V _{OUTS of the} SH_IN pin at time t ₁ after the elapse of a certain detection period. As a result, the current I _ERR flowing through the SH_OUT pin of the feedback circuit 206 decreases, the feedback signal V _FB increases, and the duty ratio of the switching transistor M1 increases. As a result, the output voltage _VOUT begins to rise.

When the output voltage _{V OUT} at time _{t 2} exceeds the overvoltage threshold _{V OVP1,} OVP circuit 390 supplies a current _{I OVP} to the light emitting element of the photocoupler 204. As a result, the feedback current I _FB increases, the feedback signal V _FB decreases, and the switching of the switching transistor M1 is stopped. In the stop period of the switching transistor M1, the secondary-side current _IS becomes zero, and the output voltage _VOUT decreases.

Further optionally, the OVP circuit 390 may resume switching of the switching transistor M1 when the output voltage V _OUT falls below a release threshold V _OVP2 that is defined lower than the overvoltage threshold V _OVP1 . Operation at this time is shown by a chain line, the time _{t 3} after, turned upward output voltage _{V OUT} again reaches the overvoltage threshold _{V OVP1,} again, DC / DC converter 200 is stopped. Thus, the DC / DC converter 200 alternately repeats the operation period and the stop period in a time division manner.

FIG. 3 shows a case where a gate open abnormality occurs at time t ₀ during the operation of the DC / DC converter 200, but there may also be a case where a gate open abnormality has occurred from the beginning when the DC / DC converter 200 is started. It is the same.

The above is the operation of the DC / DC converter 200.
According to the DC / DC converter 200, the gate open abnormality can be detected by monitoring the gate electrode by the OVP circuit 390. When the gate open abnormality is detected, the switching of the switching transistor M1 is stopped, so that the DC / DC converter 200 can be prevented from continuing to operate in the diode rectification mode, the heat generation can be suppressed, and the reliability can be improved.

  Further, the overvoltage protection function provided in the synchronous rectification controller 300, the feedback circuit 206 or the primary side controller 202 is used, and it is not necessary to change these circuits. That is, by adding the gate open detection circuit 350 as an external application (peripheral) circuit to the conventional chip, protection at the time of gate open becomes possible.

  The present invention is understood as the block diagram and circuit diagram of FIG. 2 or extends to various devices and circuits derived from the above description, and is not limited to a specific configuration. In the following, more specific configuration examples and examples will be described in order not to narrow the scope of the present invention but to help understanding and clarify the essence and circuit operation of the present invention.

FIG. 4 is a circuit diagram of a configuration example (200a) of the DC / DC converter 200. The synchronous rectification controller 300, the feedback circuit 206, and the OVP circuit 390 are accommodated in one package (referred to as a secondary side controller) 400. For example, the synchronous rectification controller 300 is integrated on the first chip 402, and the feedback circuit 206 and the OVP circuit 390 are integrated on the second chip 404. All may be integrated on the same chip. The power supply (VCC) pin is connected to the output line of the DC / DC converter 200a and receives the output voltage _VOUT as a DC power supply voltage.

The synchronous rectification controller 300 includes a driver 304 and a pulse generator 306. The pulse generator 306, based on the voltage _{V D2} of DRAIN pin, and generates a control pulse _{S 11.} The configuration and control method of the pulse generator 306 are not particularly limited, and a known technique may be used. For example a pulse generator 306, based on the voltage V _D2 of DRAIN pin, detects the turning off of the switching transistor M1, and a zero current which current I _S is substantially zero in the secondary winding W2, the switching transistor M1 turns off the control pulse S ₁₁ as a trigger to transition to on level of shifts the control pulse S ₁₁ off level as a trigger zero current.

When the voltage comparator detects that the voltage V _D2 and a predetermined negative first threshold voltage V _THA (for example, −150 mV) have crossed, it may be determined that the switching transistor M1 is turned off.

During the synchronization on period of the rectifying transistors M2, the current I _S flows from the source to the drain of a synchronous rectification transistors M2, the drain-source voltage _{V DS2 (V D2)} is negative voltage, the absolute value of the current I _S that It is proportional to the amount of current.
V _DS2 = I _S × R _ON2
R _ON2 is the on-resistance of the synchronous rectification transistor M2. Thus, the voltage comparator compares the drain voltage V _D2 with a negative second threshold voltage V _THB (for example, −10 mV) set near zero, and the drain voltage V _D2 is higher than the second threshold voltage V _THB. Then, it may be determined that the current is zero. The driver 304 drives the synchronous rectification transistor M2 based on the control pulse _{S 11.}

The feedback circuit 206 includes an error amplifier 340, a reference voltage source 342 and a transistor _{M 11.} The reference voltage source 342 generates a reference voltage _VREF . The error amplifier 340 amplifies an error between the detection voltage V _OUTS and the reference voltage V _REF . The transistor M ₁₁ is provided on the same current path as the light emitting element of the photocoupler 204, and its control terminal (gate) is connected to the output of the error amplifier 340. A current I _ERR corresponding to the error between the detection voltage V _OUTS and the reference voltage V _REF flows through the transistor M ₁₁ .

OVP circuit 390 includes an overvoltage detection circuit 392 and a transistor 394. The overvoltage detection circuit 392 asserts the overvoltage detection signal S _OVP (for example, high level) when the output voltage _VOUT exceeds the overvoltage threshold V _OVP1 . The configuration of the overvoltage detection method and detection circuit is not particularly limited. For example, the overvoltage detection circuit 392 may compare the detection voltage V _OUTS at the SH_IN pin with a threshold value corresponding to the overvoltage threshold value V _OVP1 . Or current _{I ERR} flowing to SH_OUT pin, the output voltage _{V OUT} becomes higher increase, the overvoltage detection circuit 392 may detect the overvoltage condition on the basis of the current _{I ERR} flowing through the transistor _{M 11.} The overvoltage detection circuit 392 may detect an overvoltage state based on the voltage of the SH_OUT pin or the voltage of the VCC pin.

The overvoltage detection circuit 392 may _negate (low level) the OVP signal S _OVP when V _OUT <V _OVP2 . In this case, the overvoltage detection circuit 392 may be configured with a hysteresis comparator.

Alternatively, the secondary-side controller 400 may include an unillustrated UVLO (Under Voltage Lock Out) circuit, and may reset all the registers in the secondary-side controller 400 when V _OUT <V _UVLO . In this case, the UVLO threshold value V _UVLO corresponds to the release threshold value V _OVP2 , and the OVP signal S _OVP is negated by resetting the register.

Transistor _{M 12} is provided in parallel with the transistor _{M 11,} it turns on when the OVP signal is asserted. As a result, the current I _OVP is supplied to the light emitting element of the photocoupler 204, and the switching of the primary side switching transistor M1 can be stopped.

  Next, the gate open detection circuit 350 will be described.

In FIG. 2, the operation of the DC / DC converter 200 is stopped when a gate open abnormality occurs regardless of the load power. However, in the light load region where the secondary-side current _IS is small, even if the DC / DC converter 200a operates in the diode rectification mode, the current flowing through the body diode D2 of the synchronous rectification transistor M2 is small, so heat generation is a problem. Don't be.

  There is also a DC / DC converter that intentionally operates in the diode rectification mode without switching the synchronous rectification transistor M2 in order to increase the efficiency in the light load region. The intentional diode rectification mode is also referred to as a sleep mode. In the sleep mode, no pulse is generated on the gate electrode of the synchronous rectification transistor M2.

For these reasons, in a light load state (a state where the output power is lower than a predetermined threshold value or a state included in a predetermined power range), switching of the switching transistor M1 is stopped even if a gate open abnormality occurs. It may be preferable not to do so. Therefore, the gate open detection circuit 350 in FIG. 4 is configured not to decrease the detection voltage V _OUTS of the SH_IN pin in the light load state. This makes it possible to achieve both sleep mode operation and protection in the event of an abnormal gate opening. Alternatively, even if the sleep mode is not supported, the operation of the DC / DC converter 200a can be continued within a range in which the heat generation of the synchronous rectification transistor M2 does not become a problem, so that power can be continuously supplied to the load.

In the light load state, the low level time of the periodic signal V _D2 generated at the drain electrode of the synchronous rectification transistor M2 is shortened. Therefore, the gate open detection circuit 350 is configured not to decrease the detection voltage V _OUTS of the SH_IN pin when the low level time of the periodic signal V _D2 is short.

The gate open detection circuit 350 includes a capacitor C ₃₁ , a first path 352, and a second path 354. The first path 352 charges the capacitor C1 with the voltage V _G2 of the gate electrode. The first path 352 includes a diode _{D 31.} The diode D ₃₁ and the capacitor C ₃₁ can be regarded as a peak hold circuit.

The second path 354 to charge and discharge the capacitor _{C 31} by the voltage _{V D2} of the drain electrode of the synchronous rectifier transistor M2. Diode D ₃₂ is to form a discharge path when the periodic signal V _D2 is at the low level, the resistor R ₃₁ to form a charging path when the periodic signal V _D2 is at a high level. Charging path, a may be provided resistor R ₃₂ in the path of the discharge path overlap. Due to the resistor R ₃₂ , the charging / discharging speed of the second path 354 becomes slower than the charging speed of the first path 352. Since the periodic signal V _D2 may exceed 100 V, a Zener diode ZD ₃₁ is provided for circuit protection. The resistor R ₃₃ is provided in parallel with the capacitor C ₃₁ and forms a discharge path to the ground.

The gate open detection circuit 350 changes the detection voltage V _OUTS according to the voltage V _C31 of the capacitor C ₃₁ . The cathode of the diode _{D 33} is connected to the capacitor _{C 31,} an anode is connected to SH_IN terminal. The gate open detection circuit 350 can be understood as a clamp circuit that limits the detection voltage V _OUTS of the SH_IN pin so as not to exceed an upper limit value (V _C31 + V _F ) determined according to the voltage V _C31 . V _F is the forward voltage of the diode D ₃₃ . Instead of the diode _{D 33,} it is provided a bipolar transistor or _FET, an emitter (source) connected to the SH_OUT pins may input voltage _{V C31} to the base (gate).

Next, the operation of the gate open detection circuit 350 will be described. For ease of understanding, the periodic explanation of the drain electrode is ignored. When a pulse to the gate of the synchronous rectification transistor M2 is generated, the capacitor C _31, the voltage V _C31 of the peak-hold gate pulse _(e.g., 3V) appears. When the reference voltage V _REF is 0.8 V, the voltage V _{OUTS of the} SH_IN pin is also stabilized in the vicinity thereof, and therefore V _OUTS <V _C31 + V _F is established. Therefore, the gate open detection circuit 350 is set to the detection voltage V _OUTS . It does not act on it.

When a pulse to the gate of the synchronous rectification transistor M2 is not generated, the capacitor C ₃₁ is no longer charged, the voltage V _C31 is reduced to near zero (0V). As a result, V _OUTS is clamped to the upper limit value V _F and forcibly lowered.

Subsequently, the relationship between the drain electrode periodic signal V _D2 and the voltage V _C31 of the capacitor C ₃₁ will be described. It should be noted that a periodic signal is generated in the drain electrode regardless of whether or not a gate open abnormality has occurred. Charging rate of the second route 354 is defined by the resistor R _31, the discharge rate is defined by the diode D _32, towards the discharge speed is faster.

FIGS. 5A and 5B are operation waveform diagrams of the DC / DC converter 200a at the time of heavy load and light load. The heavy load, in both the light load, the secondary side of the current I _{period S} is to flow, the periodic signal V _D2 becomes low. Capacitor C ₃₁ is the period in which current I _S of the secondary side periodic signal V _D2 without flow to the high level, the charging period of the periodic signal V _D2 flows a current I _S of the secondary side becomes the low level Discharged.

The low level time of the periodic signal V _D2 is shorter in the light load state than in the heavy load state, and the time ratio of the low level to the high level is smaller in the light load state than in the heavy load state. As a result, in the heavy load state of FIG. 5A, the discharge at the low level wins, so the second path 354 reduces the voltage V _C31 of the capacitor C ₃₁ . On the other hand, in the light load state of FIG. 5 (b), since the direction of charging by the high-level wins, second path 354, it does not lower the voltage _{V C31} of the capacitor _{C 31.}

It can be understood that the gate open detection circuit 350 in FIG. 4 corrects the output voltage V _C31 of the peak hold circuit including the first path 352 and the capacitor C ₃₁ based on the duty ratio of the periodic signal V _D2 .

In summary, the voltage V _C31 of the capacitor C ₃₁ behaves as follows.
(1) Gate In normal or heavy load conditions, the voltage _{V 31} is high.
(2) Gate In normal or light load condition, the voltage _{V 31} is high.
(3) In the gate-open fault-heavy load state, the voltage _{V 31} decreases.
(4) In the gate-open fault, the light load state, the voltage _{V 31} is high.

As described above, according to the gate open detection circuit 350 of FIG. 4, when the gate open abnormality occurs in a heavy load state, the detection voltage V _OUTS can be lowered to protect the circuit.

  Note that the second path 354 may be omitted when it is desired to protect the light load state when the gate open is abnormal.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
The protection process when the gate open abnormality is detected is not limited to stopping the switching of the switching transistor M1. For example, when an open abnormality is detected, the primary-side controller 202 may reduce the switching duty ratio of the switching transistor M1. Alternatively the secondary side may reduce the reference voltage V _REF of the error amplifier 340 and shunt regulator.

  Further, a fail pin may be provided in the synchronous rectification controller 300 to output an abnormality detection signal to the outside. For example, when a microcontroller is connected to the load of the DC / DC converter 200, it is possible to take appropriate measures for the entire system by supplying an abnormality detection signal to the microcontroller.

(Second modification)
The synchronous rectification transistor M2 may be provided on the higher potential side than the secondary winding W2.

(Third Modification)
Although the flyback converter is taken as an example in the embodiment, the present invention can also be applied to an LLC converter.

(Use)
Subsequently, the application of the DC / DC converter 200 described in the embodiment will be described. The DC / DC converter 200 can be used for the AC / DC converter 100. FIG. 6 is a circuit diagram of an AC / DC converter 100 including the DC / DC converter 200.

The AC / DC converter 100 includes a filter 102, a rectifier circuit 104, a smoothing capacitor 106, and a DC / DC converter 200. The filter 102 removes noise from the _AC voltage VAC. The rectifier circuit 104 is a diode bridge circuit that full-wave rectifies the _AC voltage VAC. The smoothing capacitor 106 smoothes the full-wave rectified voltage and generates a DC voltage _VIN . The DC / DC converter 200 receives the direct current voltage _VIN and generates an output voltage _VOUT .

FIG. 7 is a diagram illustrating an AC adapter 800 including the AC / DC converter 100. The AC adapter 800 includes a plug 802, a housing 804, and a connector 806. Plug 802 is subjected to a commercial AC voltage _{V AC} from the wall outlet (not shown). The AC / DC converter 100 is mounted in the housing 804. The DC output voltage V _OUT generated by the AC / DC converter 100 is supplied from the connector 806 to the electronic device 810. Examples of the electronic device 810 include a laptop computer, a digital camera, a digital video camera, a mobile phone, and a mobile audio player.

FIGS. 8A and 8B are diagrams showing an electronic device 900 including the AC / DC converter 100. FIG. 8A and 8B is a display device, but the type of the electronic device 900 is not particularly limited, and is a device including a power supply device such as an audio device, a refrigerator, a washing machine, or a vacuum cleaner. I just need it.
Plug 902 is subjected to a commercial AC voltage _{V AC} from the wall outlet (not shown). The AC / DC converter 100 is mounted in the housing 904. The DC output voltage V _OUT generated by the AC / DC converter 100 is applied to a load such as a microcomputer, a DSP (Digital Signal Processor), a power supply circuit, a lighting device, an analog circuit, or a digital circuit mounted in the same housing 904. Supplied.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

P1 ... input terminal, P2 ... output terminal, M1 ... switching transistor, M2 ... synchronous rectification transistor, C1 ... output capacitor, T1 ... transformer, W1 ... primary winding, W2 ... secondary winding, W3 ... auxiliary winding, D1 ... Diode, D2 ... Body diode, 100 ... AC / DC converter, 102 ... Filter, 104 ... Rectifier circuit, 106 ... Smoothing capacitor, 200 ... DC / DC converter, 202 ... Primary controller, 204 ... Photocoupler, 206 ... Feedback Circuit, 300 ... Synchronous rectification controller, 304 ... Driver, 306 ... Pulse generator, 310 ... Gate open detection circuit, 340 ... Error amplifier, 800 ... AC adapter, 802 ... Plug, 804 ... Housing, 806 ... Connector, 810, 900 ... electronic device, 902 ... plug, 904 ... housing

Claims (19)

An insulated synchronous rectification type DC / DC converter,
A transformer having a primary winding and a secondary winding;
A switching transistor connected to the primary winding of the transformer;
A synchronous rectification transistor connected to the secondary winding of the transformer;
A photocoupler including a light emitting element and a light receiving element;
A feedback input circuit having a control input pin for receiving a detection voltage corresponding to the output voltage of the DC / DC converter, and driving the light emitting element of the photocoupler so that the detection voltage approaches a target voltage;
A primary side controller connected to the light receiving element of the photocoupler and switching the switching transistor in response to a feedback signal from the light receiving element;
A synchronous rectification controller having a gate pin connected to the gate electrode of the synchronous rectification transistor and driving the synchronous rectification transistor;
A gate open abnormality that is provided outside the synchronous rectification controller, is connected to the gate electrode of the synchronous rectification transistor, and the gate pin of the synchronous rectification controller is electrically open when no pulse is generated in the gate electrode A gate open detection circuit for determining
A DC / DC converter comprising: An overvoltage protection circuit that stops switching of the switching transistor when the output voltage exceeds an overvoltage threshold;
2. The DC / DC converter according to claim 1, wherein the gate open detection circuit forcibly reduces the detection voltage when the pulse is not generated in the gate electrode.   The DC / DC converter according to claim 2, wherein the overvoltage protection circuit restarts switching of the switching transistor when the output voltage falls below a release threshold.   4. The DC / DC converter according to claim 2, wherein the gate open detection circuit does not decrease the detection voltage in a light load state of the DC / DC converter. 5.   4. The DC / DC converter according to claim 2, wherein the gate open detection circuit does not decrease the detection voltage when a low level time of a periodic signal generated at a drain electrode of the synchronous rectification transistor is short. The gate open detection circuit includes:
A capacitor;
A first path for charging the capacitor with the voltage of the gate electrode;
A second path for charging and discharging the capacitor by the voltage of the drain electrode of the synchronous rectification transistor;
The DC / DC converter according to claim 1, wherein the detection voltage is changed according to a voltage of the capacitor.   The DC / DC converter according to claim 6, wherein the first path includes a first diode arranged in a direction in which a cathode is on the capacitor side. The second route is
A second diode disposed in a direction in which the cathode is on the drain electrode side;
A resistor connected in parallel with the second diode;
The DC / DC converter according to claim 6 or 7, characterized by comprising:   The gate open detection circuit further includes a third diode provided between the capacitor and the control input pin in a direction in which a cathode is on the capacitor side. The DC / DC converter described.   6. The gate open detection circuit includes a peak hold circuit for peak holding a signal of the gate electrode, and changes the detection voltage based on an output voltage of the peak hold circuit. The DC / DC converter in any one.   11. The DC / DC converter according to claim 10, wherein the gate open detection circuit corrects the output voltage of the peak hold circuit based on a duty ratio of a periodic signal generated at a drain electrode of the synchronous rectification transistor. . An insulated synchronous rectification type DC / DC converter,
A transformer having a primary winding and a secondary winding;
A switching transistor connected to the primary winding of the transformer;
A synchronous rectification transistor connected to the secondary winding of the transformer;
A photocoupler including a light emitting element and a light receiving element;
A feedback input circuit having a control input pin for receiving a detection voltage corresponding to the output voltage of the DC / DC converter, and driving the light emitting element of the photocoupler so that the detection voltage approaches a target voltage;
A primary side controller connected to the light receiving element of the photocoupler and switching the switching transistor in response to a feedback signal from the light receiving element;
A synchronous rectification controller having a gate pin connected to the gate electrode of the synchronous rectification transistor and driving the synchronous rectification transistor;
A capacitor;
A first path for charging the capacitor with the voltage of the gate electrode;
With
The DC / DC converter, wherein the voltage of the control input pin is limited according to the voltage of the capacitor.   The DC / DC converter according to claim 12, further comprising a second path for charging and discharging the capacitor by a voltage of a drain electrode of the synchronous rectification transistor.   The DC / DC converter according to claim 1, wherein the DC / DC converter is a flyback converter.   14. The DC / DC converter according to claim 1, wherein the DC / DC converter is an LLC converter. Load,
A diode rectifier circuit for full-wave rectification of commercial AC voltage;
A smoothing capacitor that smoothes the output voltage of the diode rectifier circuit and generates a DC input voltage;
The DC / DC converter according to any one of claims 1 to 13, wherein the DC input voltage is stepped down and supplied to a load.
An electronic device comprising: A diode rectifier circuit for full-wave rectification of commercial AC voltage;
A smoothing capacitor that smoothes the output voltage of the diode rectifier circuit and generates a DC input voltage;
The DC / DC converter according to any one of claims 1 to 13, wherein the DC input voltage is stepped down and supplied to a load.
A power adapter comprising: An insulating synchronous rectification type DC / DC converter protection method comprising:
The DC / DC converter is
A transformer having a primary winding and a secondary winding;
A switching transistor connected to the primary winding of the transformer;
A synchronous rectification transistor connected to the secondary winding of the transformer;
A photocoupler including a light emitting element and a light receiving element;
A feedback input circuit having a control input pin for receiving a detection voltage corresponding to the output voltage of the DC / DC converter, and driving the light emitting element of the photocoupler so that the detection voltage approaches a target voltage;
A primary side controller connected to the light receiving element of the photocoupler and switching the switching transistor in response to a feedback signal from the light receiving element;
A synchronous rectification controller having a gate pin connected to the gate electrode of the synchronous rectification transistor and driving the synchronous rectification transistor;
With
The protection method is:
Charging the capacitor with the voltage of the gate electrode;
Limiting the voltage of the control input pin according to the voltage of the capacitor;
A protection method comprising:   The protection method according to claim 18, further comprising charging and discharging the capacitor with a voltage of a drain electrode of the synchronous rectification transistor.

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