JP2018005647A - Power supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply device including a state setting circuit which enables a circuit scale to be reduced and facilitates determination of FMEA.SOLUTION: A state setting circuit comprises: current generation circuits (OP1, MP0, Vref0) for generating current of a current value inversely proportional to a resistance value of a mode resistance Rmode by controlling voltage of a mode terminal 3, to which the mode resistance Rmode is connected, to become a reference voltage Vref0; transistors MP1-MP6 making current of the same current value with each other corresponding to the current value of the current generated in the current generation circuits flow individually; reference current sources Iref1-Iref6; inverters INV1-INV6 for comparing current values of drain current of the transistors MP1-MP6 and N pieces of the reference current sources Iref1-Iref6 individually.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power supply apparatus including a state setting circuit that sets a combination of operation modes (hereinafter also referred to as “state”) by setting an external mode resistance or the like.

  In a highly versatile power supply device, a plurality of operation modes can be set, and the user can select a combination of operation modes according to the application used from the plurality of operation modes. This type of technology is described in Patent Document 1, for example.

  For example, in the voltage conversion method, one of a switching power supply method and a series regulator method can be selected (first group). Moreover, in the overcurrent protection method, when the overcurrent reaches a predetermined value, a timer latch method that cuts off the output voltage after a predetermined time elapses, and when the overcurrent reaches a predetermined value, the output voltage is cut off for a certain time and a certain time thereafter. One of the hiccup (automatic return) methods that repeats returning the output voltage when it has elapsed can be selected (second group). Furthermore, as for the output voltage, one voltage can be selected from a plurality of voltages (third group).

  The number of combinations for selecting operation modes one by one from these first to third groups and combining them is extremely large. For example, when there are two operation modes in one group, eight combinations are possible. However, it is troublesome for the user to set a combination of these operation modes. Therefore, a state setting circuit for easily selecting one combination from a plurality of combinations of these operation modes is desired.

  FIG. 7 is a diagram illustrating an example of a state setting circuit, which is a circuit that allows one combination to be selected and set from seven combinations of operation modes. 1 is a power supply terminal, 2 is a ground terminal, 3 is a mode terminal, and 6 is a decoder.

  CP1 to CP6 are comparators, and reference voltage sources Vref1 to Vref6 (voltage values are in a relationship of Vref1> Vref2> Vref3> Vref4> Vref5> Vref6) are connected to inverting input terminals, respectively.

  The mode voltage Vmode applied to the mode terminal 3 is input to the non-inverting input terminals of the comparators CP1 to CP6. Further, the signals of the output terminals OUT1 to OUT6 of the comparators CP1 to CP6 are input to the decoder 6.

  The decoder 6 decodes the logic combination of the signals of the output terminals OUT1 to OUT6, and outputs, for example, a 3-bit state setting signal MODE that designates one of the seven combinations of operation modes.

  An example of the contents of the decoder 6 is shown in FIGS. By setting the mode voltage Vmode applied to the mode terminal 3 to a predetermined voltage value, one of the combination states MODE1 to MODE7 can be selected.

  FIG. 10 is an example of another state setting circuit. In this circuit, the current Iref0 flowing from the reference current source Iref0 is converted into a voltage by the resistance value of the mode resistor Rmode connected between the mode terminal 3 and the ground terminal 2, and input to the non-inverting input terminals of the comparators CP1 to CP6. doing. In this circuit, one of the combination states MODE1 to MODE7 can be selected by appropriately setting the resistance value of the mode resistance Rmode.

Japanese Patent No. 5511564

  However, since the state setting circuits shown in FIGS. 7 and 10 use the comparators CP1 to CP6, and these comparators need to be configured with many transistors, the circuit scale increases as the number of comparators increases. There is a problem that becomes large.

  Further, since the mode voltage Vmode applied between the mode terminal 3 and the ground terminal 2 is switched or the mode resistance Rmode is switched to select a combination of operation modes, the mode terminal 3 is in contact with an adjacent pin. When considering FMEA (Failure Mode and Effect Analysis) such as short circuit, ground fault in contact with the ground terminal 2, and power fault in contact with the power terminal 1, the voltage value of the mode voltage Vmode and the resistance value of the mode resistance Rmode It is necessary to consider each separately. For example, as shown in FIGS. 7 and 10, when six reference voltages Vref1 to Vref6 are used, the mode voltage Vmode and the mode resistance Rmode use seven voltage values and resistance values. Therefore, it is necessary to separately consider the seven cases, which is not realistic and only about three operation modes are selected. Therefore, for example, when selecting eight operation modes, three state setting circuits are required.

  An object of the present invention is to provide a power supply device including a state setting circuit that can reduce the circuit scale and facilitate the study of FMEA.

  In order to achieve the above object, a power supply device according to a first aspect of the present invention is a power supply device including a state setting circuit that sets a combination of operation modes by setting a resistance value of a mode resistor connected to a mode terminal. The state setting circuit generates a current having a current value inversely proportional to the resistance value of the mode resistor by performing feedback control so that the voltage of the mode terminal becomes a reference voltage, and the current generation circuit N current sources (N is an integer of 2 or more) that individually flow currents having the same current value corresponding to the current values of the currents generated in step N, N reference current sources having different current values, N current comparison means for individually comparing the current values of the N current sources and the current values of the N reference current sources, and by combining the logics of the output signals of the N current comparison means The operation mode of Wherein the combined was to be set.

  A power supply device according to a second aspect of the present invention is a power supply device including a state setting circuit that sets a combination of operation modes by setting a resistance value of a mode resistor connected to a mode terminal, and the state setting circuit includes: Feedback control is performed so that the voltage at the mode terminal becomes a reference voltage, and a current generation circuit that generates a current having a current value inversely proportional to the resistance value of the mode resistor, and a current value of the current generated by the current generation circuit. N-2 current sources (N is an integer greater than or equal to 2) that individually flow currents having the same current value, N-2 reference current sources having different current values, and N-2 N-2 current comparison means for individually comparing the current values of the current sources and the N-2 reference current sources, and a first voltage lower than the reference voltage applied to the inverting input terminal The non-inverting input terminal is connected to the mode terminal. A first comparator that is applied with a second voltage higher than the reference voltage at an inverting input terminal and a non-inverting input terminal connected to the mode terminal, and the N-2 current comparisons The combination of operation modes is set by a combination of logic of output signals of the means and output signals of the first and second comparators.

  According to a third aspect of the present invention, in the power supply device according to the first or second aspect, the current generating circuit includes one of an inverting input terminal and a non-inverting input terminal connected to the mode terminal, and the inverting input terminal and the non-inverting input terminal. An operational amplifier in which the reference voltage is input to the other of the inverting input terminals, and a reference that operates such that the gate is connected to the output terminal of the operational amplifier, the drain is connected to the mode terminal, and the voltage of the mode terminal matches the reference voltage. The current source is a current source transistor having the same conductivity type as that of the reference transistor and having a gate commonly connected to the reference transistor, and the current comparing means includes a current of the current source transistor It is comprised by the inverter which determines a logic by the polarity of the difference with the electric current of the said reference current source.

  According to a fourth aspect of the present invention, in the power supply device according to the first aspect, the N reference current sources are replaced with resistors having the same resistance value.

  According to a fifth aspect of the present invention, in the power supply device according to the second aspect, the N-2 reference current sources are replaced with resistors having the same resistance value.

  According to the present invention, since an inverter can be used, the circuit scale can be reduced. In addition, since the mode can be set without applying a voltage from the outside, it is easy to study FMEA.

It is a circuit diagram of the state setting circuit of 1st Example of this invention. FIG. 2 is an explanatory diagram of a content of a decoder of the state setting circuit of FIG. 1. It is explanatory drawing which shows the relationship between the reference electric current value of the state setting circuit of FIG. 1, and a combination. It is a circuit diagram of the state setting circuit of 2nd Example of this invention. FIG. 5 is an explanatory diagram of a content of a decoder of the state setting circuit of FIG. 4. It is explanatory drawing which shows the relationship between the reference current value of the state setting circuit of FIG. 5, and a reference voltage value, and a combination. It is a circuit diagram of an example of a state setting circuit. FIG. 8 is an explanatory diagram of contents of a decoder of the state setting circuit of FIG. 7. It is explanatory drawing which shows the relationship between the reference value of the state setting circuit of FIG. 7, and a mode. It is a circuit diagram of an example of another state setting circuit.

<First embodiment>
FIG. 1 shows a state setting circuit of the first embodiment. 1 is a power supply terminal, 2 is a ground terminal, 3 is a mode terminal, and 4 is a decoder. OP1 is an operational amplifier, the non-inverting input terminal is connected to the mode terminal 3, the reference voltage Vref0 of the reference voltage source Vref0 is input to the inverting input terminal, and the output terminal is connected to the gate of the PMOS transistor MP0.

  As a result, the transistor MP0 is feedback-controlled so that the voltage at the non-inverting input terminal of the operational amplifier OP1 matches the reference voltage Vref0 at the inverting input terminal. The drain voltage Vref0 of the transistor MP0 thus generated is applied to the mode resistor Rmode connected between the mode terminal 3 and the ground terminal 2, and the mode current Imode flows. This mode current Imode is also the drain current of the transistor MP0.

  The gates of the six MP transistors MP1 to MP6 having the same size ratio as the transistor MP0 are commonly connected to the gate of the transistor MP0. For this reason, the drain currents of the transistors MP1 to MP6 are also the same as the mode current Imode. Become.

  Reference current sources Iref1 to Iref6 (current values are in a relationship of Iref1 <Iref2 <Iref3 <Iref4 <Iref5 <Iref6) are connected between the drains of the transistors MP1 to MP6 and the ground terminal 2, respectively. The input terminals of the inverters INV1 to INV6 are connected to common connection points of the transistors MP1 to MP6 and the reference current sources Iref1 to Iref6, respectively. Output terminals OUT1 to OUT6 of the inverters INV1 to INV6 are connected to the decoder 4. For example, a 3-bit state setting signal MODE is output from the decoder 4 in accordance with the logic combination of the output terminals OUT1 to OUT6.

  The reference transistor described in the claims is a transistor MP0, and the current source transistors are transistors MP1 to MP6. The current generation circuit includes an operational amplifier OP1, a transistor MP0, a reference voltage source Vref0, and a mode resistor Rmode. The current comparing means is composed of inverters INV1 to INV6.

  From the above, by setting the resistance value of the mode resistance Rmode to R1, when Imode <Iref1, all of the input terminals of the inverters INV1 to INV6 are “L”, so that all of the output terminals OUT1 to OUT6 are “H”. (MODE1).

  Next, by setting the resistance value of the mode resistance Rmode to R2 (R2 <R1), when Iref1 <Imode <Iref2, the input terminal of the inverter INV1 becomes “H”, and the inputs of the remaining inverters INV2 to INV6 Since the terminal is “L”, OUT1 is “L” and OUT2 to OUT6 are all “H” (MODE2).

  Further, by setting the resistance value of the mode resistance Rmode to R3 (R3 <R2), when Iref2 <Imode <Iref3, the input terminals of the inverters INV1 and INV2 become “H”, and the remaining inverters INV3 to INV6 Since the input terminal is “L”, OUT1 and OUT2 are “L”, and OUT3 to OUT6 are “H” (MODE3).

  Further, by setting the resistance value of the mode resistance Rmode to R4 (R4 <R3), when Iref3 <Imode <Iref4, the input terminals of the inverters INV1 to INV3 become “H”, and the input terminals of the inverters INV4 to INV6 Becomes “L”, OUT1 to OUT3 become “L”, and OUT4 to OUT6 become “H” (MODE 4).

  Further, by setting the resistance value of the mode resistance Rmode to R5 (R5 <R4), when Iref4 <Imode <Iref5, the input terminals of the inverters INV1 to INV4 become “H”, and the input terminals of the inverters INV5 and INV6 Becomes “L”, OUT1 to OUT4 become “L”, and OUT5 and OUT6 become “H” (MODE5).

  Further, by setting the resistance value of the mode resistance Rmode to R6 (R6 <R5), when Iref5 <Imode <Iref6, the input terminals of the inverters INV1 to INV5 become “H” and the input terminal of the inverter INV6 is “ Since it becomes “L”, OUT1 to OUT5 become “L”, and OUT6 becomes “H” (MODE 6).

  Finally, by setting the resistance value of the mode resistance Rmode to R7 (R7 <R6), when Iref6 <Imode, all the input terminals of the inverters INV1 to INV6 become “H”, so that all of the OUT1 to OUT6 are “ L "(MODE 7).

  As a result, if one of the resistance values R1 to R7 of the mode resistance Rmode is selected, any one of the operation mode combinations MODE1 to MODE7 can be set as shown in FIGS. At this time, since the voltage of the mode terminal 3 does not change from the reference voltage Vref0, the FMEA such as the short circuit, the ground fault, and the power fault described above can be easily studied. Further, in order to create a plurality of voltages, the power supply voltage is divided. However, if the power supply voltage has a different rating from the power supply voltage for the state setting circuit, a different power supply voltage must be prepared. However, in this embodiment, it is not necessary to connect a voltage source to the mode terminal, so that there is no complication. Further, when the inverters INV1 to INV6 and the reference current sources Iref1 to Iref6 are configured, the number of elements is reduced as compared with the case where the comparators OP1 to OP6 of the state setting circuit described with reference to FIG. The circuit scale can be reduced.

<Second embodiment>
FIG. 4 shows a state setting circuit of the second embodiment. 1 is a power supply terminal, 2 is a ground terminal, 3 is a mode terminal, and 5 is a decoder. In the present embodiment, the operational amplifier OP1, the transistors MP0 to MP4, the inverters INV1 to INV4, the reference voltage source Vref0, the reference current sources Iref1 to Iref4, and the mode resistor Rmode described with reference to FIG. 1, the comparators CP1, CP2 , Reference voltage sources Vref1 and Vref2 and a second circuit portion portion based on the mode voltage Vmode are combined. The current value of the reference current source is set to have a relationship of Iref1 <Iref2 <Iref3 <Iref4. The voltage value of the reference voltage source is set to have a relationship of Vref2 <Vref0 <Vref1. The decoder 5 is connected to the output terminals OUT1 to OUT4 of the inverters INV1 to INV4 and the output terminals OUT5 and OUT6 of the comparators CP1 and CP2.

  In this embodiment, if the resistance value of the mode resistance Rmode is set to any one of R1 to R5, any one of MODE1 to MODE5 in FIG. 5 can be set. At this time, the output terminals OUT1 to OUT4 of the inverters INV1 to INV4 are the same as those in the first embodiment. However, since Vref1> Vref0, the output OUT5 of the comparator CP1 is “L”, and since Vref2 <Vref0, the output OUT6 of the comparator CP2 is “H”.

  Next, when the mode resistance Rmode between the mode terminal 3 and the ground terminal 2 is removed and the mode voltage Vmode is applied thereto, if Vref1 <Vmode is set, the output terminals OUT5 and OUT6 of the comparators CP1 and CP2 are “H”. At this time, since Vref0 <Vmode, the drain currents of the transistors MP1 to MP4 become small, the input terminals of the inverters INV1 to INV4 become “L”, and the output terminals OUT1 to OUT4 become “H”. At this time, MODE 6 in FIG. 5 is realized.

  Next, if Vmode <Vref2, the output terminals OUT5 and OUT6 of the comparators CP1 and CP2 become “L”. At this time, since Vmode <Vfer0, the drain currents of the transistors MP1 to MP4 increase, the input terminals of the inverters INV1 to INV4 become “H”, and the output terminals OUT1 to OUT4 become “L”. At this time, MODE 7 in FIG. 5 is realized.

  As a result, when setting any one of MODE1 to MODE5, one mode resistor Rmode selected from the resistance values R1 to R5 may be connected to the mode terminal 3, and either MODE6 or MODE7 is set. In some cases, a mode voltage Vmode higher than the voltage Vref1 or lower than the voltage Vref2 may be applied to the mode terminal 3.

  In the first embodiment, it is necessary to prepare six types of reference current sources Iref1 to Iref6, and it is necessary to provide a relatively large difference between these current values. Therefore, when the number of combinations of operation modes increases, current consumption increases. There is a concern that will increase. On the other hand, in the present embodiment, the state setting circuit is divided into the first circuit portion and the second circuit portion, and the number of reference current sources can be reduced in the first circuit portion, thereby suppressing an increase in current consumption. be able to. At this time, the comparators CP1 and CP2 are used for the second circuit portion, but since the number is two, there is little concern that the circuit scale will be large.

<Other examples>
In the above embodiment, the PMOS transistors MP0 to MP6 are used. However, these transistors can be replaced with NMOS transistors. In this case, the inverting input terminal of the operational amplifier OP1 may be connected to the mode terminal 3 and the reference voltage source Vref0 may be connected to the non-inverting input terminal. Further, the reference current sources Iref1 to Iref6 can be replaced with fixed resistors having the same resistance value. In addition, as the inverters INV1 to INV6, if an inverter provided with two thresholds and provided with hysteresis is used, stable current comparison can be performed.

1: power supply terminal, 2: ground terminal, 3: mode terminal, 4-6: decoder

Claims (5)

A power supply device including a state setting circuit that sets a combination of operation modes by setting a resistance value of a mode resistor connected to a mode terminal,
The state setting circuit generates a current having a current value inversely proportional to the resistance value of the mode resistor by feedback control so that the voltage of the mode terminal becomes a reference voltage, and the current setting circuit generates the current setting circuit. N current sources (N is an integer greater than or equal to 2) individually flowing currents having the same current value corresponding to the current values of the currents, N reference current sources having different current values, and the N N current comparison means for individually comparing the current values of the current sources and the current values of the N reference current sources,
The power supply apparatus according to claim 1, wherein the combination of operation modes is set by a combination of logics of output signals of the N current comparison means. A power supply device including a state setting circuit that sets a combination of operation modes by setting a resistance value of a mode resistor connected to a mode terminal,
The state setting circuit generates a current having a current value inversely proportional to the resistance value of the mode resistor by feedback control so that the voltage of the mode terminal becomes a reference voltage, and the current setting circuit generates the current setting circuit. N-2 current sources (N is an integer of 2 or more) and N-2 reference current sources having different current values that individually flow currents having the same current value corresponding to the current values of the currents N-2 current comparison means for individually comparing the current values of the N-2 current sources and the current values of the N-2 reference current sources, and an inverting input terminal than the reference voltage. A first comparator in which a low first voltage is applied and a non-inverting input terminal is connected to the mode terminal, and a second voltage higher than the reference voltage is applied to the inverting input terminal and a non-inverting input terminal is connected to the mode terminal A second comparator,
The power supply apparatus according to claim 1, wherein the combination of operation modes is set by a combination of logics of output signals of the N-2 current comparison means and output signals of the first and second comparators. The power supply device according to claim 1 or 2,
The current generation circuit includes an operational amplifier in which one of an inverting input terminal and a non-inverting input terminal is connected to the mode terminal, and the reference voltage is input to the other of the inverting input terminal and the non-inverting input terminal, and a gate of the operational amplifier A reference transistor connected to the output terminal and having a drain connected to the mode terminal and operating to match the voltage of the mode terminal with the reference voltage;
The current source includes a current source transistor having the same conductivity type as the reference transistor and having a gate commonly connected to the reference transistor,
The current comparing means is composed of an inverter that determines the logic according to the polarity of the difference between the current of the current source transistor and the current of the reference current source.
A power supply device characterized by that. The power supply device according to claim 1,
A power supply apparatus, wherein the N reference current sources are replaced with resistors having the same resistance value. The power supply device according to claim 2,
The power supply apparatus according to claim 1, wherein the N-2 reference current sources are replaced with resistors having the same resistance value.

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