JP2017536009A5 - - Google Patents

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JP2017536009A5
JP2017536009A5 JP2017517709A JP2017517709A JP2017536009A5 JP 2017536009 A5 JP2017536009 A5 JP 2017536009A5 JP 2017517709 A JP2017517709 A JP 2017517709A JP 2017517709 A JP2017517709 A JP 2017517709A JP 2017536009 A5 JP2017536009 A5 JP 2017536009A5
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slot
physical uplink
qpucch
subframe
control channel
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JP2017536009A (ja
JP6479972B2 (ja
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JP2017517709A 2014-10-03 2015-09-28 低レイテンシを用いたダウンリンクおよびアップリンクチャネル Active JP6479972B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201462059831P 2014-10-03 2014-10-03
US201462059726P 2014-10-03 2014-10-03
US62/059,726 2014-10-03
US62/059,831 2014-10-03
US14/866,465 US10064165B2 (en) 2014-10-03 2015-09-25 Downlink and uplink channel with low latency
US14/866,465 2015-09-25
PCT/US2015/052592 WO2016053844A1 (en) 2014-10-03 2015-09-28 Downlink and uplink channel with low latency

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JP2017536009A JP2017536009A (ja) 2017-11-30
JP2017536009A5 true JP2017536009A5 (cg-RX-API-DMAC7.html) 2018-11-08
JP6479972B2 JP6479972B2 (ja) 2019-03-06

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JP2019019866A Active JP6679775B2 (ja) 2014-10-03 2019-02-06 低レイテンシを用いたダウンリンクおよびアップリンクチャネル
JP2020047221A Active JP6953573B2 (ja) 2014-10-03 2020-03-18 低レイテンシを用いたダウンリンクおよびアップリンクチャネル

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JP2020047221A Active JP6953573B2 (ja) 2014-10-03 2020-03-18 低レイテンシを用いたダウンリンクおよびアップリンクチャネル

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US (3) US10064165B2 (cg-RX-API-DMAC7.html)
EP (2) EP3937582B1 (cg-RX-API-DMAC7.html)
JP (3) JP6479972B2 (cg-RX-API-DMAC7.html)
KR (2) KR102360109B1 (cg-RX-API-DMAC7.html)
CN (2) CN106797642B (cg-RX-API-DMAC7.html)
AU (3) AU2015324152B2 (cg-RX-API-DMAC7.html)
ES (1) ES2898499T3 (cg-RX-API-DMAC7.html)
WO (1) WO2016053844A1 (cg-RX-API-DMAC7.html)

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