JP2017530436A - 異種共有仮想メモリにおけるオンデマンド共有可能性変換 - Google Patents

異種共有仮想メモリにおけるオンデマンド共有可能性変換 Download PDF

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JP2017530436A
JP2017530436A JP2017501367A JP2017501367A JP2017530436A JP 2017530436 A JP2017530436 A JP 2017530436A JP 2017501367 A JP2017501367 A JP 2017501367A JP 2017501367 A JP2017501367 A JP 2017501367A JP 2017530436 A JP2017530436 A JP 2017530436A
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processor
virtual memory
memory page
page
outer domain
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JP2017530436A5 (enExample
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ボフスラフ・ライチリック
ジェイソン・エドワード・ポダイマ
アンドリュー・エヴァン・グルーバー
ズン・レン・ツェン
ジェンビアオ・マ
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1483—Protection against unauthorised use of memory or access to memory by checking the subject access rights using an access-table, e.g. matrix or list
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems
    • G06F3/0622—Securing storage systems in relation to access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0637—Permissions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/067—Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/152—Virtualized environment, e.g. logically partitioned system

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Computer Security & Cryptography (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
JP2017501367A 2014-07-18 2015-06-25 異種共有仮想メモリにおけるオンデマンド共有可能性変換 Pending JP2017530436A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201462026319P 2014-07-18 2014-07-18
US62/026,319 2014-07-18
US14/510,804 2014-10-09
US14/510,804 US20160019168A1 (en) 2014-07-18 2014-10-09 On-Demand Shareability Conversion In A Heterogeneous Shared Virtual Memory
PCT/US2015/037651 WO2016010704A1 (en) 2014-07-18 2015-06-25 On-demand shareability conversion in a heterogeneous shared virtual memory

Publications (2)

Publication Number Publication Date
JP2017530436A true JP2017530436A (ja) 2017-10-12
JP2017530436A5 JP2017530436A5 (enExample) 2018-07-26

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JP2017501367A Pending JP2017530436A (ja) 2014-07-18 2015-06-25 異種共有仮想メモリにおけるオンデマンド共有可能性変換

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Country Link
US (1) US20160019168A1 (enExample)
EP (1) EP3170086A1 (enExample)
JP (1) JP2017530436A (enExample)
KR (1) KR20170031697A (enExample)
CN (1) CN106575264A (enExample)
TW (1) TW201610680A (enExample)
WO (1) WO2016010704A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2025041465A (ja) * 2023-09-13 2025-03-26 株式会社日立製作所 保護制御システムおよび保護制御方法

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180011792A1 (en) 2016-07-06 2018-01-11 Intel Corporation Method and Apparatus for Shared Virtual Memory to Manage Data Coherency in a Heterogeneous Processing System
US10296074B2 (en) * 2016-08-12 2019-05-21 Qualcomm Incorporated Fine-grained power optimization for heterogeneous parallel constructs
US10439960B1 (en) * 2016-11-15 2019-10-08 Ampere Computing Llc Memory page request for optimizing memory page latency associated with network nodes
US10585412B2 (en) * 2017-02-13 2020-03-10 Rockwell Automation Technologies, Inc. Safety controller using hardware memory protection
US10592164B2 (en) 2017-11-14 2020-03-17 International Business Machines Corporation Portions of configuration state registers in-memory
US10496437B2 (en) 2017-11-14 2019-12-03 International Business Machines Corporation Context switch by changing memory pointers
US10761751B2 (en) 2017-11-14 2020-09-01 International Business Machines Corporation Configuration state registers grouped based on functional affinity
US10635602B2 (en) 2017-11-14 2020-04-28 International Business Machines Corporation Address translation prior to receiving a storage reference using the address to be translated
US10552070B2 (en) 2017-11-14 2020-02-04 International Business Machines Corporation Separation of memory-based configuration state registers based on groups
US10901738B2 (en) 2017-11-14 2021-01-26 International Business Machines Corporation Bulk store and load operations of configuration state registers
US10642757B2 (en) 2017-11-14 2020-05-05 International Business Machines Corporation Single call to perform pin and unpin operations
US10698686B2 (en) 2017-11-14 2020-06-30 International Business Machines Corporation Configurable architectural placement control
US10761983B2 (en) 2017-11-14 2020-09-01 International Business Machines Corporation Memory based configuration state registers
US10664181B2 (en) 2017-11-14 2020-05-26 International Business Machines Corporation Protecting in-memory configuration state registers
US10558366B2 (en) 2017-11-14 2020-02-11 International Business Machines Corporation Automatic pinning of units of memory
CN107861887B (zh) * 2017-11-30 2021-07-20 科大智能电气技术有限公司 一种串行易失性存储器的控制方法
US10599568B2 (en) * 2018-04-09 2020-03-24 Intel Corporation Management of coherent links and multi-level memory
US11307993B2 (en) * 2018-11-26 2022-04-19 Advanced Micro Devices, Inc. Dynamic remapping of virtual address ranges using remap vector
KR102648790B1 (ko) * 2018-12-19 2024-03-19 에스케이하이닉스 주식회사 데이터 저장 장치 및 그 동작 방법
US10969980B2 (en) * 2019-03-28 2021-04-06 Intel Corporation Enforcing unique page table permissions with shared page tables
CN112905243B (zh) * 2019-11-15 2022-05-13 成都鼎桥通信技术有限公司 一种同时运行双系统的方法和装置
US11782835B2 (en) 2020-11-30 2023-10-10 Electronics And Telecommunications Research Institute Host apparatus, heterogeneous system architecture device, and heterogeneous system based on unified virtual memory
US11593108B2 (en) * 2021-06-07 2023-02-28 International Business Machines Corporation Sharing instruction cache footprint between multiple threads
US11593109B2 (en) 2021-06-07 2023-02-28 International Business Machines Corporation Sharing instruction cache lines between multiple threads
CN113674133B (zh) * 2021-07-27 2023-09-05 阿里巴巴新加坡控股有限公司 Gpu集群共享显存系统、方法、装置及设备
GB2616643B (en) * 2022-03-16 2024-07-10 Advanced Risc Mach Ltd Read-as-X property for page of memory address space

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0458347A (ja) * 1990-06-27 1992-02-25 Nec Corp 共有アドレス空間管理方式
JPH08320796A (ja) * 1994-09-09 1996-12-03 Hitachi Ltd データ処理装置
JPH08320829A (ja) * 1994-09-09 1996-12-03 Hitachi Ltd データ処理装置
JP2004259298A (ja) * 2004-04-21 2004-09-16 Toshiba Corp 仮想記憶管理方法
JP2004334267A (ja) * 2003-04-30 2004-11-25 Fujitsu Ltd マイクロプロセッサ
US20110055515A1 (en) * 2009-09-02 2011-03-03 International Business Machines Corporation Reducing broadcasts in multiprocessors
JP2012088894A (ja) * 2010-10-19 2012-05-10 Renesas Electronics Corp データ処理装置
US20140049551A1 (en) * 2012-08-17 2014-02-20 Intel Corporation Shared virtual memory

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060070069A1 (en) * 2004-09-30 2006-03-30 International Business Machines Corporation System and method for sharing resources between real-time and virtualizing operating systems
US7734842B2 (en) * 2006-03-28 2010-06-08 International Business Machines Corporation Computer-implemented method, apparatus, and computer program product for managing DMA write page faults using a pool of substitute pages
US8954697B2 (en) * 2010-08-05 2015-02-10 Red Hat, Inc. Access to shared memory segments by multiple application processes
KR101671494B1 (ko) * 2010-10-08 2016-11-02 삼성전자주식회사 공유 가상 메모리를 이용한 멀티 프로세서 및 주소 변환 테이블 생성 방법
US20120233439A1 (en) * 2011-03-11 2012-09-13 Boris Ginzburg Implementing TLB Synchronization for Systems with Shared Virtual Memory Between Processing Devices
KR20130076973A (ko) * 2011-12-29 2013-07-09 삼성전자주식회사 응용 프로세서 및 이를 포함하는 시스템
US11487673B2 (en) * 2013-03-14 2022-11-01 Nvidia Corporation Fault buffer for tracking page faults in unified virtual memory system
US9424201B2 (en) * 2013-03-14 2016-08-23 Nvidia Corporation Migrating pages of different sizes between heterogeneous processors
US9754561B2 (en) * 2013-10-04 2017-09-05 Nvidia Corporation Managing memory regions to support sparse mappings

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0458347A (ja) * 1990-06-27 1992-02-25 Nec Corp 共有アドレス空間管理方式
JPH08320796A (ja) * 1994-09-09 1996-12-03 Hitachi Ltd データ処理装置
JPH08320829A (ja) * 1994-09-09 1996-12-03 Hitachi Ltd データ処理装置
US5835963A (en) * 1994-09-09 1998-11-10 Hitachi, Ltd. Processor with an addressable address translation buffer operative in associative and non-associative modes
KR100368197B1 (ko) * 1994-09-09 2003-04-10 가부시끼가이샤 히다치 세이사꾸쇼 데이타처리장치
KR100369923B1 (ko) * 1994-09-09 2003-05-12 가부시끼가이샤 히다치 세이사꾸쇼 데이타처리장치
JP2004334267A (ja) * 2003-04-30 2004-11-25 Fujitsu Ltd マイクロプロセッサ
JP2004259298A (ja) * 2004-04-21 2004-09-16 Toshiba Corp 仮想記憶管理方法
US20110055515A1 (en) * 2009-09-02 2011-03-03 International Business Machines Corporation Reducing broadcasts in multiprocessors
JP2012088894A (ja) * 2010-10-19 2012-05-10 Renesas Electronics Corp データ処理装置
US20140049551A1 (en) * 2012-08-17 2014-02-20 Intel Corporation Shared virtual memory
WO2014028120A1 (en) * 2012-08-17 2014-02-20 Intel Corporation Shared virtual memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2025041465A (ja) * 2023-09-13 2025-03-26 株式会社日立製作所 保護制御システムおよび保護制御方法

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EP3170086A1 (en) 2017-05-24
CN106575264A (zh) 2017-04-19
TW201610680A (zh) 2016-03-16
WO2016010704A1 (en) 2016-01-21
KR20170031697A (ko) 2017-03-21
US20160019168A1 (en) 2016-01-21

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