JP2017228575A - Semiconductor module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor module less susceptible to noise.SOLUTION: The semiconductor module includes: a base plate 50; wiring patterns 60 to 64; semiconductor chips 70, 71; a detection element 72; and semiconductor chip lead-out terminals 90 to 94. The semiconductor chip lead-out terminals 90 to 94 are erected with respect to the base plate 50. The wiring patterns 63, 64 electrically connected to electrodes of the detection element 72 extend as detection element lead-out terminals up to the end of the base plate 50.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor module.

  The power switching elements and wirings that constitute the power conversion device such as the inverter device are modularized, and the modularization is also performed including the elements for detecting the current flowing through each arm and the like. Yes. In this case, each terminal including the terminal of the current detection element is generally extended in the same direction (Patent Document 1, etc.).

JP2013-98425A

  However, if the terminals including the terminals of the current detection elements are aligned and extended in the same direction, the terminals of the current detection elements need to be arranged so as not to receive noise from other terminals. If the terminals of the current detection elements are arranged away from other terminals so as not to be received, an increase in size is caused.

  An object of the present invention is to provide a semiconductor module that is not easily affected by noise.

  According to the first aspect of the present invention, a base plate formed by forming an insulating layer on the upper surface of a metal plate, a wiring pattern formed on the insulating layer of the base plate, and electrodes on the base plate are electrically connected to the wiring pattern. A semiconductor chip mounted in a connected state, a detection element mounted in a state where an electrode is electrically connected to the wiring pattern on the base plate, and an electrical connection to the electrode of the semiconductor chip A semiconductor chip lead terminal, wherein the semiconductor chip lead terminal is erected with respect to the base plate, and the wiring pattern electrically connected to the electrode of the detection element extends to the end of the base plate. The gist of the present invention is that it is extended as a lead-out terminal.

  According to the first aspect of the present invention, the semiconductor chip lead terminal is erected with respect to the base plate, and the wiring pattern electrically connected to the electrode of the detection element extends to the end portion of the base plate. Since the signal of the detection element can be taken out without running in parallel with other signals, it is less susceptible to noise.

As described in claim 2, in the semiconductor module according to claim 1, the detection element may be arranged at a side or a corner of the base plate.
The semiconductor module according to claim 1 or 2, further comprising a resin frame disposed on the base plate in a state where the semiconductor chip and the detection element are located inside, The wiring pattern extended as a detection element lead-out terminal may pass through the resin frame.

As described in claim 4, in the semiconductor module according to any one of claims 1 to 3, the detection element may be a current detection element.
As described in claim 5, in the semiconductor module according to any one of claims 1 to 4, a substrate connected to the semiconductor chip lead terminal is disposed so as to overlap, and the detection element lead terminal is provided. A controller connected to the extended wiring pattern may be arranged adjacent to an end of the wiring pattern extended as the detection element lead-out terminal.

  According to the present invention, it is difficult to be affected by noise.

The perspective view which shows the components arrangement | positioning of the inverter apparatus in embodiment. The circuit diagram which shows the electric constitution of an inverter apparatus. (A) is a top view of a semiconductor module, (b) is a longitudinal cross-sectional view in the AA line of (a), (c) is a longitudinal cross-sectional view in the BB line of (a). (A) is a top view of a semiconductor module in a state without a substrate and a resin frame, (b) is a front view of the semiconductor module, and (c) is a right side view of the semiconductor module. (A) is a top view of the semiconductor module in the state without a board | substrate, a resin-made frame, and a terminal, (b) is a front view of a semiconductor module, (c) is a right view of a semiconductor module. (A) is a top view of the semiconductor module in a state without a board | substrate, a resin-made frame, a terminal, and an element, (b) is a front view of a semiconductor module, (c) is a right view of a semiconductor module.

Hereinafter, an embodiment in which the present invention is embodied in an inverter device will be described with reference to the drawings.
The inverter device of the present embodiment is a three-phase inverter device that supplies three-phase AC power to a motor, and converts DC power supplied from a battery into AC power. As shown in FIG. 1, the inverter device 10 includes a semiconductor module 20, a drive circuit 30, and a controller 40. The controller 40 and the drive circuit 30 are connected by a bus line.

  As shown in FIG. 2, the inverter device 10 has a positive electrode bus Lp and a negative electrode bus Ln. Positive bus Lp is connected to the positive electrode of the battery, and negative bus Ln is connected to the negative electrode of the battery. The inverter device 10 includes six switching elements Q1, Q2, Q3, Q4, Q5, and Q6. A power MOSFET is used for each switching element Q1, Q2, Q3, Q4, Q5, and Q6.

  The U-phase upper arm switching element Q1 and the lower arm switching element Q2 are connected in series between the positive electrode bus Lp and the negative electrode bus Ln. An intermediate point between both switching elements Q1, Q2 is connected to the U-phase terminal of the motor. Between the positive electrode bus Lp and the negative electrode bus Ln, the V-phase upper arm switching element Q3 and the lower arm switching element Q4 are connected in series. An intermediate point between both switching elements Q3 and Q4 is connected to the V-phase terminal of the motor. A W-phase upper arm switching element Q5 and a lower arm switching element Q6 are connected in series between the positive electrode bus Lp and the negative electrode bus Ln. An intermediate point between both switching elements Q5 and Q6 is connected to the W-phase terminal of the motor.

  The inverter device 10 includes three shunt resistors Ru, Rv, and Rw. A shunt resistor Ru is connected between the source electrode of the U-phase lower arm switching element Q2 and the negative bus Ln. A shunt resistor Rv is connected between the source electrode of the V-phase lower arm switching element Q4 and the negative bus Ln. A shunt resistor Rw is connected between the source electrode of the W-phase lower arm switching element Q6 and the negative electrode bus Ln. The current flowing through the shunt resistors Ru, Rv, Rw can be detected by measuring the voltage across the shunt resistors Ru, Rv, Rw.

The switching elements Q <b> 1 to Q <b> 6, the shunt resistors Ru, Rv, Rw and the wiring that connects them are modularized to constitute a semiconductor module 20.
The drive circuit 30 is connected to the gate connection terminals G1, G2, G3, G4, G5, and G6 of the semiconductor module 20. The controller 40 is connected to the drive circuit 30. The controller 40 outputs a drive signal to the drive circuit 30. With this drive signal, drive circuit 30 applies a pulse voltage to the gate electrodes of switching elements Q1-Q6 to turn on / off switching elements Q1-Q6.

  The controller 40 is connected to the current detection monitor terminals S1, S2, S3, S4, S5 and S6 of the semiconductor module 20. The controller 40 measures the voltage across the shunt resistor Ru and detects the U-phase current flowing through the shunt resistor Ru. The controller 40 measures the voltage across the shunt resistor Rv and detects the V-phase current flowing through the shunt resistor Rv. The controller 40 measures the voltage across the shunt resistor Rw and detects the W-phase current flowing through the shunt resistor Rw. Feedback control is performed based on the detected current value. Further, the quality of the switching elements Q1, Q2, Q3, Q4, Q5, Q6, etc. is inspected based on the detected current value.

  3A, 3B, and 3C show the semiconductor module 20. FIG. Here, only the part enclosed by the broken line in FIG. 2 is shown in FIG. 3 (a), (b), (c). That is, of U-phase, V-phase, and W-phase in FIG. 2, U-phase switching elements Q1 and Q2 and shunt resistor Ru are arranged, and V-phase and W-phase switching elements Q3, Q4, Q5. The arrangement portion of Q6 and shunt resistors Rv and Rw is omitted.

In the drawings, the horizontal plane is defined by the orthogonal X and Y directions, and the vertical direction is defined by the Z direction.
As shown in FIGS. 3A, 3 </ b> B, and 3 </ b> C, the semiconductor module 20 has a cubic shape, and a drive substrate 31 constituting the drive circuit 30 is disposed on the upper surface of the semiconductor module 20. Various electronic components are mounted on the drive substrate 31. From the upper surface of the semiconductor module 20, semiconductor chip lead terminals 93 and 94 constituting the gate connection terminals G1 and G2 in FIG. From one side surface of the semiconductor module 20, wiring patterns 63 and 64 as detection element lead terminals constituting the current detection monitor terminals S1 and S2 in FIG.

  6A, 6B, and 6C, the semiconductor module 20 is formed on a base plate 50 in which an insulating layer 52 is formed on the upper surface of the metal plate 51, and on the insulating layer 52 of the base plate 50. Wiring patterns 60, 61, 62, 63, 64 are provided. The metal plate 51 is rectangular and has a predetermined thickness. An insulating layer 52 is coated over the entire upper surface of the metal plate 51.

The wiring patterns 60, 61, 62, 63, 64 are made of metal (for example, made of copper, aluminum, etc.). On the insulating layer 52, wiring patterns 60, 61, 62, 63 and 64 are extended.
The wiring pattern 60 constitutes the positive electrode bus Lp in FIG. 2 and extends in the X direction. The wiring pattern 62 constitutes the negative electrode bus Ln in FIG. 2 and extends in the X direction. The wiring pattern 60 and the wiring pattern 62 are spaced apart from each other in the Y direction.

  The wiring pattern 61 constitutes a wiring L3 between the switching element Q1 and the switching element Q2 in FIG. 2, has a rectangular shape, and is disposed at a position close to the wiring pattern 60.

  The wiring pattern 63 forms a wiring L4 between the switching element Q2 and the shunt resistor Ru in FIG. 2, and also forms a wiring L1 between one end of the shunt resistor Ru and the current detection monitor terminal S1. The wiring pattern 63 has a strip shape extending linearly, one end of the wiring pattern 63 is disposed at a position close to the wiring pattern 61, and the other end extends in the Y direction.

  The wiring pattern 64 forms a wiring L2 between the other end of the shunt resistor Ru in FIG. 2 and the current detection monitor terminal S2. The wiring pattern 64 has a strip shape extending linearly, and the wiring pattern 64 extends in the Y direction in a state of being continuous from the end of the wiring pattern 62. The wiring pattern 63 and the wiring pattern 64 are arranged at positions close to each other.

The base plate 50 of the semiconductor module 20 is disposed on the upper surface of a heat sink (heat sink) (not shown).
As shown in FIGS. 5A, 5 </ b> B, and 5 </ b> C, the semiconductor module 20 includes semiconductor chips 70 and 71 and a detection element 72. The semiconductor chip 70 constitutes the switching element Q1 in FIG. The semiconductor chip 70 is a vertical MOSFET, and a drain electrode 74 is formed on the lower surface, and a source electrode (pad) 73 and a gate electrode (pad) 75 are formed on the upper surface. The semiconductor chip 71 constitutes the switching element Q2 in FIG. The semiconductor chip 71 is a vertical MOSFET, and a drain electrode 77 is formed on the lower surface, and a source electrode (pad) 76 and a gate electrode (pad) 78 are formed on the upper surface. The detection element 72 is a current detection element and constitutes the shunt resistor Ru in FIG. The detection element 72 has an electrode 79 formed at one end on the lower surface and an electrode 80 formed at the other end.

  The semiconductor chip 70 is mounted on the base plate 50 in a state where the drain electrode 74 on the lower surface is electrically connected to the wiring pattern 60 by soldering. The semiconductor chip 71 is mounted on the base plate 50 in a state where the drain electrode 77 on the lower surface is electrically connected to the wiring pattern 61 by soldering. The source electrode 73 of the semiconductor chip 70 and the wiring pattern 61 are electrically connected by a conductive plate 81. Specifically, the conductive plate 81 is formed by bending a metal strip at two locations. One end of the conductive plate 81 is soldered to the source electrode 73 of the semiconductor chip 70, and the other end is the wiring pattern 61. It is soldered. The source electrode 76 of the semiconductor chip 71 and the wiring pattern 63 are electrically connected by a conductive plate 82. Specifically, the conductive plate 82 is formed by bending a metal strip at two locations. One end of the conductive plate 82 is soldered to the source electrode 76 of the semiconductor chip 71 and the other end is the wiring pattern 63. It is soldered. The conductive plate 81 constitutes a wiring L3 between the switching element Q1 and the switching element Q2 in FIG. The conductive plate 82 constitutes a wiring L4 between the switching element Q2 and the shunt resistor Ru in FIG.

  The detection element 72 is disposed on the side or corner of the base plate 50. The detection element 72 is electrically connected to the base plate 50 by soldering one electrode 79 on the lower surface to the wiring pattern 63 and soldering the other electrode 80 on the lower surface to the wiring pattern 62. Implemented in state. In this way, the detection element 72 is mounted on the base plate 50 in a state where the electrodes 79 and 80 are electrically connected to the wiring patterns 62 and 63. A wiring pattern 64 branches from the wiring pattern 62, and the wiring pattern 63 and the wiring pattern 64 extend in parallel to each other in the Y direction.

  4A, 4B, and 4C, the semiconductor module 20 includes a source electrode 73, a drain electrode 74, a gate electrode 75 of the semiconductor chip 70, a source electrode 76 of the semiconductor chip 71, and a drain electrode 77. The semiconductor chip lead terminals 90, 91, 92, 93 and 94 are electrically connected to the gate electrode 78.

  Specifically, a semiconductor chip lead terminal 90 is erected on the wiring pattern 60, and the lower end of the semiconductor chip lead terminal 90 is soldered to the wiring pattern 60 (electrically connected to the drain electrode 74 of the semiconductor chip 70). It is connected). A semiconductor chip lead terminal 91 is erected on the wiring pattern 62, and the lower end of the semiconductor chip lead terminal 91 is soldered to the wiring pattern 62 (via the source electrode 76 of the semiconductor chip 71 and the detection element 72). Electrically connected). A semiconductor chip lead terminal 92 is erected on the wiring pattern 61, and the lower end of the semiconductor chip lead terminal 92 is soldered to the wiring pattern 61 (the source electrode 73 of the semiconductor chip 70 and the drain electrode of the semiconductor chip 71). 77). A semiconductor chip lead terminal 93 is erected on the gate electrode 75 of the semiconductor chip 70, and the lower end of the semiconductor chip lead terminal 93 is soldered to the gate electrode 75 of the semiconductor chip 70 (the gate electrode of the semiconductor chip 70). 75 and electrically connected). A semiconductor chip lead terminal 94 is erected on the gate electrode 78 of the semiconductor chip 71, and the lower end of the semiconductor chip lead terminal 94 is soldered to the gate electrode 78 of the semiconductor chip 71 (the gate electrode of the semiconductor chip 71). 78).

In this way, the semiconductor chip lead terminals 90, 91, 92, 93, 94 are erected with respect to the base plate 50.
Wiring patterns 63 and 64 electrically connected to the electrodes 79 and 80 of the detection element 72 extend in the Y direction and extend as detection element lead terminals to the end of the base plate 50.

  As shown in FIGS. 3A, 3B, and 3C, the semiconductor module 20 includes a resin frame 53 as a housing. The resin frame 53 has a rectangular frame shape, and the upper portion is covered with a flat plate portion 53a. The resin frame 53 is disposed on the base plate 50 with the semiconductor chips 70 and 71 and the detection element 72 positioned inward. The semiconductor chip lead terminals 90, 91, 92, 93, 94 extending in the vertical direction are integrally formed in the resin frame 53 so as to penetrate the flat plate portion 53 a extending in the horizontal direction in the resin frame 53. Yes (insert molded).

  The wiring patterns 63 and 64 extended as detection element lead terminals extending in the Y direction penetrate the resin frame 53, and the wiring patterns 63 and 64 protrude from the outer wall surface of the resin frame 53 to the outside. ing.

  In this way, the semiconductor module 20 has the semiconductor chip 70 by the resin frame 53 in a state in which the leading ends of the semiconductor chip lead terminals 90, 91, 92, 93, 94 and the leading ends of the wiring patterns 63, 64 are exposed. 71, detection element 72, and wiring material. Further, when configuring a power module with an inverter device or the like, parasitic elements can be reduced by using a wiring pattern or a conductive plate instead of a bonding wire (using a direct lead bonding structure).

  As shown in FIGS. 3A, 3 </ b> B, and 3 </ b> C, a drive circuit board 31 is disposed on the upper surface of the resin frame 53. The substrate 31 is electrically connected to the semiconductor chip lead terminals 93 and 94. The substrates 31 connected to the semiconductor chip lead terminals 93 and 94 are arranged to overlap each other. The controller 40 connected to the wiring patterns 63 and 64 extended as the detection element lead-out terminals is disposed adjacent to the ends of the wiring patterns 63 and 64 extended as the detection element lead-out terminals. The controller 40 is electrically connected to the detection element 72 via the wiring patterns 63 and 64.

  3A, 3B, and 3C show the U-phase semiconductor chip lead terminals 93 and 94, the V-phase and the W-phase have the same configuration, and the gate shown in FIG. The semiconductor chip lead terminals constituting the connection terminals G3, G4, G5, and G6 protrude from the upper surface of the semiconductor module 20 and are connected to the substrate 31. Further, FIG. 3 shows the wiring patterns 63 and 64 as the detection element lead terminals in the U phase, but the V phase and the W phase have the same configuration, and the wiring patterns as the detection element lead terminals are semiconductors. Projecting from one side of the module 20 is connected to the controller 40.

Next, the operation will be described.
In the inverter device 10, the switching elements Q <b> 1 to Q <b> 6 are controlled to be turned on / off, and the DC power supplied from the battery is converted into AC power to supply three-phase AC power to the motor. At this time, the current is monitored and feedback control is performed.

  The semiconductor module 20 is provided with semiconductor chips (power MOSFETs) constituting the switching elements Q1 to Q6, and is connected to the inside of the resin frame 53 by wiring patterns 60, 61, 63. The current is measured by drawing the wiring patterns 63 and 64 to the outside of the resin frame 53 without drawing the terminal extending from the current detection element 72 upward. By taking out the terminal extending from the current detection element 72 in this way, the terminal can be taken out without running in parallel with other extraction wirings other than the terminal extending from the current detection element 72.

As a result, the wiring extending from the current detection element 72 is not easily affected by noise in other wiring.
In addition, since the terminal extending from the current detection element 72 is not pulled out to the upper portion of the semiconductor module 20, the area of the substrate 31 can be effectively utilized when the substrate 31 is disposed on the upper portion of the semiconductor module 20.

  Further, the current detection element 72 is arranged near the side or near the corner of the base plate 50 (resin frame 53), so that the wiring extending from the current detection element 72 can be minimized. .

  Therefore, the current inside the semiconductor module 20 is measured while reducing the influence of noise or the like during current feedback or inspection. Specifically, signals at both ends of the shunt resistors Ru, Rv, and Rw are output from the side surface (lateral) of the semiconductor module 20, and the positive terminal, the negative terminal, and the gate terminal are taken out to the top of the semiconductor module 20.

  In this way, since the elements and wirings are arranged in the resin frame 53 in the semiconductor module 20, it is possible to confirm the operation of the entire module and the current Itotal (see FIG. 2). It becomes difficult to measure the currents Iu, Iv, and Iw (see FIG. 2) in the three individual circuits of the phase and the W phase. For this reason, when the current measurement is performed for each individual circuit, it is necessary to incorporate a current detection element in advance and extract the voltage to the outside to perform the measurement. When the current monitoring is performed in this way, when the number of monitors increases, the number of wirings also increases, and the number of wirings in the semiconductor module 20 increases. Therefore, the number of extraction electrodes increases. In addition, since it is necessary to dispose the monitor extraction electrode so as not to receive noise from the terminal (electrode) of the power line, miniaturization is hindered.

  In the present embodiment, since the current sensor signal can be extracted without running in parallel with other signals, it is less susceptible to noise such as crosstalk. In addition, the substrate can be effectively used when the substrate 31 is disposed on the semiconductor module 20.

  Note that the U-phase, V-phase, and W-phase three-phase output lines serve as noise sources, and the gate signal lines also serve as noise sources because high-frequency pulse signals are sent. Therefore, the current detection signal line is susceptible to noise due to crosstalk (coupling) caused by the three-phase output line and the gate signal line, but this can be avoided and the current can be measured with high accuracy.

According to the above embodiment, the following effects can be obtained.
(1) The configuration of the semiconductor module 20 includes a base plate 50, wiring patterns 60 to 64, semiconductor chips 70 and 71, a detection element 72, and semiconductor chip lead terminals 90 to 94. The semiconductor chip lead terminals 90 to 94 are erected with respect to the base plate 50, and the wiring patterns 63 and 64 electrically connected to the electrodes of the detection elements 72 extend as detection element lead terminals to the end of the base plate 50. Has been.

Therefore, since the signal of the detection element 72 can be taken out without running in parallel with other signals, it is less susceptible to noise. Thereby, current measurement can be performed with high accuracy.
(2) Since the detection element 72 is disposed on the side or corner of the base plate 50, the wiring of the detection element 72 can be shortened.

  (3) A wiring pattern 63, 64 provided with a resin frame 53 arranged on the base plate 50 in a state where the semiconductor chips 70, 71 and the detection element 72 are located on the inside, and extended as a detection element lead-out terminal, Since it penetrates the resin frame 53, it is practical.

(4) Since the detection element 72 is a current detection element, the current can be easily detected.
(5) On the semiconductor module 20, the substrate 31 connected to the lead terminal for semiconductor chip is disposed so as to overlap, and the controller 40 connected to the wiring patterns 63 and 64 extended as the lead terminal for detection element detects the semiconductor module 20. Since it is arranged adjacent to the end portions of the wiring patterns 63 and 64 extending as the element lead-out terminals, it is possible to reduce the size.

The embodiment is not limited to the above, and may be embodied as follows, for example.
-Even if the lead terminal for the semiconductor chip is directly extended from the electrode (pad) of the semiconductor chip (even if it is erected directly), it is connected to the wiring pattern from the electrode (pad) of the semiconductor chip through a conductive plate or the like. It may be connected and extended from the wiring pattern (may be erected). In short, it is only necessary that the lead terminal for the semiconductor chip is electrically connected to the electrode of the semiconductor chip.

The current detection element is composed of a shunt resistor, but may be composed of another element, for example, a Hall element.
-Although the detection element was a current detection element, it is not restricted to this. For example, the detection element may be a voltage detection element.

  -Although applied to an inverter device, it is not limited to this. For example, you may apply to a DC / DC converter, PFC (power factor improvement circuit), etc.

  DESCRIPTION OF SYMBOLS 20 ... Semiconductor module, 31 ... Board | substrate, 40 ... Controller, 50 ... Base plate, 51 ... Metal plate, 52 ... Insulating layer, 53 ... Resin frame, 60-64 ... Wiring pattern, 70, 71 ... Semiconductor chip, 72 ... Detection elements, 74, 76... Electrodes, 90 to 94.

Claims (5)

A base plate formed by forming an insulating layer on the upper surface of the metal plate;
A wiring pattern formed on the insulating layer of the base plate;
A semiconductor chip mounted on the base plate in a state where electrodes are electrically connected to the wiring pattern;
A detection element mounted on the base plate in a state where electrodes are electrically connected to the wiring pattern;
A semiconductor chip lead terminal electrically connected to the electrode of the semiconductor chip;
With
The semiconductor chip lead terminal is erected with respect to the base plate,
The semiconductor module, wherein the wiring pattern electrically connected to the electrode of the detection element extends as an extraction terminal for the detection element to an end of the base plate.   The semiconductor module according to claim 1, wherein the detection element is arranged on a side or a corner of the base plate. A resin frame disposed on the base plate in a state where the semiconductor chip and the detection element are located inward,
3. The semiconductor module according to claim 1, wherein the wiring pattern extended as the detection element lead-out terminal penetrates the resin frame. 4.   The semiconductor module according to claim 1, wherein the detection element is a current detection element. The substrates connected to the semiconductor chip lead terminals are arranged to overlap,
A controller connected to the wiring pattern extended as the detection element lead-out terminal is disposed adjacent to an end of the wiring pattern extended as the detection element lead-out terminal. The semiconductor module of any one of Claims 1-4.

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