JP2017224874A - Coding device, transmission device, and coding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a coding device or the like, capable of improving an error floor.SOLUTION: A coding device includes: a parity inspection matrix; a calculation part; a selection part; and a synthesis part. The parity inspection matrix includes: a parity arithmetic matrix including a matrix on a diagonal line and a circulant matrix which is set to one line below on the diagonal line and a predetermine line; and an information arithmetic matrix. The calculation part sets an initial value of all cases to a following bit stream of a predetermined line number of a parity bit used when calculating the parity bit stream with an operational expression designated by the parity arithmetic matrix and the information arithmetic matrix in the parity inspection matrix, and calculates the parity bit line in each initial value. The selection part selects the parity bit line of the initial value when the following bit line of the parity bit line in each initial value is matched to the initial value. The synthesis part outputs a coding language by combining the parity bit line to be selected and a message bit line.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an encoding device, a transmission device, and an encoding method.

In recent years, in a digital coherent receiver of an optical transmission system, for example, an LDPC (Low-Density Parity Check) which is a soft decision code having a higher error correction capability than a hard decision code such as a BCH code or an RS (Reed-Solomon) code. There is a code FEC (Forward Error Correction). FIG. 12 is an explanatory diagram showing an example of BER-SNR characteristics of error correction using an LDPC code and (LDPC code + hard decision code). The BER-SNR characteristic shown in FIG. 12 has a waterfall and an error floor. When the waterfall is steep and the error floor is at a position as low as possible, the error correction capability becomes high. However, with the BER-SNR characteristics of error correction using an LDPC code, the transmission quality (BER (Bit Error Rate) ≦ 1e ⁻¹⁵ ) required for an optical transmission system cannot be achieved, and an error floor occurs.

Therefore, by combining the LDPC code and the hard decision code, as shown in FIG. 12, the error floor can be suppressed and the transmission quality BER ≦ 1e ^-15 of the optical transmission system can be achieved. However, in addition to the LDPC code, an FEC of a hard decision code is also required, which increases the circuit scale and power consumption.

  FIG. 13 is an explanatory diagram illustrating an example of a parity check matrix having an LDPC code column weight of 2 or less. In the parity check matrix, as shown in FIG. 13, it is known that the position of the error floor becomes high when the column weight is 2 or less. Therefore, the error floor can often be suppressed by designing the parity check matrix so that there is no column having a column weight of 2 or less, and the slope of the waterfall becomes steep.

  An RA (Repeat Accumulate) code is known as an encoding method that is easy to design and implement an encoding device and has high error correction capability. FIG. 14 is an explanatory diagram illustrating an example of a parity check matrix H20 of the RA code. A parity check matrix H20 illustrated in FIG. 14 is a matrix that specifies an arithmetic expression for calculating a parity bit string. The parity check matrix H20 includes an information calculation matrix H21 used for an arithmetic expression when substituting a predetermined bit element of a message bit string and a parity used for an arithmetic expression when substituting a predetermined bit element of a bit string of parity bits. And an arithmetic matrix H22. The information calculation matrix H21 is a matrix close to a random structure, and is, for example, a matrix of 3 columns × 6 rows of D1 to D3. The parity calculation matrix H22 is a matrix of 6 columns × 6 rows of P1 to P6 having a structure in which “1” elements are regularly arranged in a matrix on a diagonal line and in a matrix one row below the diagonal line. However, since the RA code parity calculation matrix H22 has a configuration in which the column weight is 2 or less, the error floor becomes high. Therefore, there is a w3RA (Weight-3 Repeat Accumulate) code as a method of suppressing the error floor by setting the column weight of the parity calculation matrix H22 to 3 or more. FIG. 15 is an explanatory diagram of an example of the parity check matrix H30 of the w3RA code. A parity check matrix H30 of the w3RA code illustrated in FIG. 15 includes an information calculation matrix H31 and a parity calculation matrix H32. The parity calculation matrix H32 is a lower triangular matrix having a structure in which “1” elements are regularly arranged in a matrix on the diagonal line and a matrix on the first row below the diagonal line, in addition to a matrix on the third row below the diagonal line.

  FIG. 16 is an explanatory diagram illustrating an example of a calculation performed when a message is encoded using the parity check matrix H30 illustrated in FIG. The message u is composed of [u1, u2, u3], for example, [101]. The code word c combines [u1, u2, u3, p1, p2, p3, p4] by combining the data [u1, u2, u3] and the parity bit sequence [p1, p2, p3, p4, p5, p6]. , P5, p6]. Each parity bit in the parity bit string is sequentially calculated using 0 (mod 2) operation for each column of the parity check matrix H30.

  The first row of the parity check matrix H30 focuses on the element “1” and is an arithmetic expression for 0 (mod 2) calculation of D1 + D2 + P1 = 0. Then, the calculation formula substitutes u1 = 1 and u2 = 0 to set P1 = 1 when 1 + 0 + P1 = 0, and calculate p1 = 1 as the parity bit p1 corresponding to P1. The second row of the parity check matrix H30 pays attention to the element “1”, and is an arithmetic expression of 0 (mod 2) calculation of D1 + D3 + P1 + P2 = 0. Then, u1 = 1, u3 = 1 and P1 = 1 are substituted into the arithmetic expression, P + 1 is set to 1 + 1 + 1 + P2 = 0, and p2 = 1 is calculated as a parity bit p2 corresponding to P2.

  The third row of the parity check matrix H30 is an arithmetic expression for 0 (mod2) calculation with D3 + P2 + P3 = 0, focusing on the element “1”. Then, the calculation formula substitutes u3 = 1 and P2 = 1 to set P3 = 0 when 1 + 1 + P3 = 0, and calculate p3 = 0 as the parity bit p3 corresponding to P3. The fourth row of the parity check matrix H30 is an arithmetic expression for 0 (mod 2) calculation of D2 + P1 + P3 + P4 = 0, paying attention to the element “1”. Then, the calculation formula substitutes u2 = 0, P1 = 1, and P3 = 0, 0 + 1 + 0 + P4 = 0, P4 = 1, and P4 = 1 is calculated as the parity bit p4 corresponding to P4.

  The fifth row of the parity check matrix H30 is an arithmetic expression for 0 (mod 2) calculation of D1 + P2 + P4 + P5 = 0 with attention paid to the element “1”. Then, the calculation formula substitutes u1 = 1, P2 = 1 and P4 = 1, 1 + 1 + 1 + P5 = 0 and P5 = 1, and P5 = 1 is calculated as a parity bit p5 corresponding to P5. The sixth row of the parity check matrix H30 focuses on the element “1” and is an arithmetic expression for 0 (mod 2) calculation of D2 + D3 + P3 + P5 + P6 = 0. Then, u2 = 0, u3 = 1, P3 = 0 and P5 = 1 are substituted into the arithmetic expression, 0 + 1 + 0 + 1 + P6 = 0, P6 = 0, and P6 = 0 as the parity bit p6 corresponding to P6.

  As a result, the parity bit string [p1, p2, p3, p4, p5, p6] = [110110]. Then, the encoding device can output the codeword c [101110110] by combining the data [u1, u2, u3] = [101] and the parity bit string [110110].

Special table 2008-541496 gazette International Publication No. 2006/120844

  However, even when the w3RA code is adopted, the error floor cannot be improved because the column weights of P4, P5, and P6 of the parity calculation matrix H32 in the parity check matrix H30 are 2 or less as shown in FIG.

  An object of one aspect is to provide an encoding device, a transmission device, and an encoding method that can improve an error floor.

  In one aspect, the encoding apparatus includes a parity check matrix, a calculation unit, a selection unit, and a synthesis unit. The parity check matrix includes a matrix on a diagonal line, a parity operation matrix having a cyclic matrix on the diagonal line and one row below the predetermined line, and an information operation matrix. The calculation unit, in accordance with the input of the bit string of the message, sets all the initial bit strings in the rear bit string for a predetermined number of rows of parity bits to be used when calculating the parity bit string with an arithmetic expression specified by the parity arithmetic matrix and the information arithmetic matrix. A value is set and a parity bit string is calculated for each initial value. The selection unit selects the parity bit string of the initial value when the backward bit string of the parity bit string for each initial value matches the initial value. The combining unit combines the selected parity bit string and the message bit string and outputs a codeword.

  As one aspect, the error floor can be improved.

FIG. 1 is an explanatory diagram illustrating an example of the optical transmission apparatus according to the first embodiment. FIG. 2 is an explanatory diagram illustrating an example of a parity check matrix of the w3RA code according to the first embodiment. FIG. 3 is an explanatory diagram illustrating an example of an encoding unit. FIG. 4 is an explanatory diagram illustrating an example of an accumulator unit according to the first embodiment. FIG. 5 is an explanatory diagram illustrating an example of the processing operation of the encoding unit related to the first encoding process. FIG. 6 is an explanatory diagram illustrating an example of an accumulator unit according to the second embodiment. FIG. 7 is an explanatory diagram illustrating an example of the processing operation of the encoding unit related to the second encoding process. FIG. 8 is an explanatory diagram illustrating an example of an accumulator unit according to the third embodiment. FIG. 9 is an explanatory diagram illustrating an example of the processing operation of the encoding unit related to the third encoding process. FIG. 10 is an explanatory diagram illustrating an example of a parity check matrix of a spatially combined RA code according to the fourth embodiment. FIG. 11A is an explanatory diagram illustrating an example of a BER-SNR characteristic of error correction of a spatially-coupled RA code (no cyclic) to which the present invention is not applied. FIG. 11B is an explanatory diagram illustrating an example of a BER-SNR characteristic of error correction of the spatially-combined RA code (with circulation) according to the fourth embodiment. FIG. 12 is an explanatory diagram showing an example of BER-SNR characteristics of error correction using an LDPC code and (LDPC code + hard decision code). FIG. 13 is an explanatory diagram illustrating an example of a parity check matrix having an LDPC code column weight of 2 or less. FIG. 14 is an explanatory diagram illustrating an example of a parity check matrix of an RA code. FIG. 15 is an explanatory diagram illustrating an example of a parity check matrix of a w3RA code. FIG. 16 is an explanatory diagram illustrating an example of a method of generating a code word using a parity check matrix of the encoding unit.

  Hereinafter, embodiments of an encoding device, a transmission device, and an encoding method disclosed in the present application will be described in detail based on the drawings. The disclosed technology is not limited by the present embodiment. The following embodiments may be appropriately combined.

  FIG. 1 is an explanatory diagram illustrating an example of the optical transmission device 1 according to the first embodiment. The optical transmission apparatus 1 includes an OTU (Optical-channel Transport Unit) framer 11, a transmission processing unit 12, a DAC (Digital Analog Converter) 13, a first LD (Laser Diode) 14, and a transmission-side optical module 15. Have Further, the optical transmission device 1 includes a reception side optical module 16, a second LD 17, an ADC (Analog Digital Converter) 18, and a reception processing unit 19.

  The OTU framer 11 is, for example, a processing unit that converts a client signal into an OTU frame and extracts the client signal from the OTU frame. The transmission processing unit 12 includes an encoding unit 21 and a pre-equalization unit 22. The encoding unit 21 is an encoding device that encodes the OTU frame from the OTU framer 11 and outputs a codeword c. The pre-equalization unit 22 is a processing unit that executes various signal processing such as chromatic dispersion compensation, frequency offset compensation, and optical module input / output characteristic compensation. The DAC 13 is a processing unit that performs analog conversion of the OTU frame. The transmission-side optical module 15 is a processing unit that optically transmits an analog-converted OTU frame with an optical signal from the first LD 14.

  The receiving-side optical module 16 is a processing unit that receives an OTU frame with an optical signal from the second LD 17. The ADC 18 is a processing unit that digitally converts the OTU frame. The reception processing unit 19 includes an equalization unit 23, a restoration unit 24, and a decoding unit 25. The equalizing unit 23 is a processing unit that executes various signal processing such as chromatic dispersion compensation, frequency offset compensation, polarization mode dispersion compensation, and waveform distortion compensation. The restoration unit 24 is a processing unit that restores the carrier wave phase. The decoding unit 25 is a processing unit that decodes encoded data. The decoding unit 25 performs error correction by repeatedly decoding the codeword using the parity check matrix.

  The encoding unit 21 encodes data with the parity check matrix H of the w3RA code and outputs a codeword c. The encoding unit 21 encodes data by calculating data using the parity check matrix H of the w3RA code. The code word c is composed of a bit string [u1, u3, which is a combination of 3 bits of the information bit string [u1, u2, u3] and 6 bits of the parity bit string [p1, p2, p3, p4, p5, p6]. u2, u3, p1, p2, p3, p4, p5, p6].

  FIG. 2 is an explanatory diagram illustrating an example of the parity check matrix H of the w3RA code. The parity check matrix H illustrated in FIG. 2 is a matrix that specifies an arithmetic expression for calculating a parity bit string, and includes an information operation matrix H1 and a parity operation matrix H2. The information calculation matrix H1 is a matrix of 3 columns × 6 rows of D1, D2, and D3. The information calculation matrix H1 is, for example, a matrix used for an arithmetic expression when a predetermined bit element of a message bit string is substituted. The parity calculation matrix H2 is a matrix of 6 columns × 6 rows of P1 to P6. The parity calculation matrix H2 is, for example, a matrix used for an arithmetic expression when a predetermined bit element of a parity bit string is substituted.

  The parity calculation matrix H2 is a structure in which “1” elements are regularly arranged in a diagonal matrix, a cyclic matrix one row below the diagonal, and a predetermined number of rows from the diagonal, for example, a cyclic matrix three rows below. is there. The circulant matrix one row below the diagonal is the second row of column P1, the third row of column P2, the fourth row of column P3, the fifth row of column P4, the sixth row of column P5, and the first row of column P6. Place a “1” element in the eye. The circulant matrix three rows below the diagonal line is the fourth row of the P1 column, the fifth row of the P2 column, the sixth row of the P3 column, the first row of the P4 column, the second row of the P5 column, and the third row of the P6 column. Place a “1” element in the eye. As a result, in the parity calculation matrix H2, the column weights of all the columns P1 to P6 are 3 or more. Therefore, the error floor can be reduced.

  The first row of the parity check matrix H is an arithmetic expression for 0 (mod 2) operation of D1 + D2 + P1 + P4 + P6 = 0, and the second row of the parity check matrix H is an arithmetic expression of 0 (mod 2) operation of D1 + D3 + P1 + P2 + P5 = 0. The third row of the parity check matrix H is an arithmetic expression for 0 (mod 2) operation of D3 + P2 + P3 + P6 = 0, and the fourth row of the parity check matrix H is an arithmetic expression of 0 (mod 2) operation of D2 + P1 + P3 + P4 = 0. The fifth row of the parity check matrix H is an arithmetic expression for 0 (mod2) calculation of D1 + P2 + P4 + P5 = 0, and the sixth column of the parity check matrix H is an arithmetic expression for 0 (mod2) calculation of D2 + D3 + P3 + P5 + P6 = 0. Parity bit strings [p1, p2, p3, p4, p5, p6] are calculated using the arithmetic expression of each row in the parity check matrix H.

  FIG. 3 is an explanatory diagram illustrating an example of the encoding unit 21 according to the first embodiment. The encoding unit 21 illustrated in FIG. 3 includes a repeat unit 31, an interleaver unit 32, a combining unit 33, an accumulator unit 34, and a combining unit 35. The repeat unit 31 copies message bits according to the column weight of the information calculation matrix H1 in the parity check matrix H. Since the column weight of the information calculation matrix H1 shown in FIG. 2 is “3”, the repeat unit 31 copies the bit strings [u1, u2, u3] of three messages.

  The interleaver unit 32 rearranges the bit strings according to the arrangement status of “1” for each row of the information calculation matrix H1. For example, in the case of the first row, the interleaver unit 32 is [110] of [D1, D2, D3] and is [10] when the message is [101] because of [D1, D2]. . The combining unit 33 includes, for example, six EXORs (Exclusive-OR) 33A, and adds bits according to the row weight of the information calculation matrix H1. In the case of the first row, since the coupling unit 33 is [110] of [D1, D2, D3], D1 + D2. The repeat unit 31, the interleaver unit 32, and the combining unit 33 constitute an information calculation matrix H1, and the weight (1) of H1 corresponds to the circuit wiring as shown in FIG. For example, in the case of the first row, since [110] of [D1, D2, D3], the first row of the coupling unit 33 takes XOR of u1 and u2.

  The accumulator unit 34 calculates a parity bit string [p1, p2, p3, p4, p5, p6] based on the structure of the parity calculation matrix H2. The accumulator unit 34 is, for example, a w3RA code accumulator unit, and includes an EXOR 51, a first shift register 52, a second shift register 53, and a third shift register 54, which will be described later. The combining unit 35 combines the bit string [u1, u2, u3] of the message and the parity bit string [p1, p2, p3, p4, p5, p6] to generate the codeword [u1, u2, u3, p1, p2, p3, p4, p5, p6] are output.

  However, the first row of the parity check matrix H is an arithmetic expression of D1 + D2 + P1 + P4 + P5 = 0, and although D1 = 1 and D2 = 0 can substitute elements, P1, P4, and P5 are unknown. Therefore, each pattern of the parity bit string [p4, p5, p6] of P4, P5, and P6 corresponding to the predetermined row ψ = 3 is eight patterns from the first initial value to the eighth initial value. The first initial value is [000], the second initial value is [001], the third initial value is [010], the fourth initial value is [011], the fifth initial value is [100], The sixth initial value is “101”, the seventh initial value is [110], and the eighth initial value is [111]. Of all the patterns, only one correct answer is always [p4, p5, p6]. The predetermined row is 3 because it is a cyclic matrix below a predetermined row in the parity calculation matrix H2, that is, three rows below.

  FIG. 4 is an explanatory diagram illustrating an example of the accumulator unit 34 according to the first embodiment. The accumulator unit 34 shown in FIG. 4 includes 2 ^ (predetermined number of rows) = 2 ^ 3 = 8 accumulator units. The accumulator unit 34 includes a first accumulator unit 41A, a second accumulator unit 41B, a third accumulator unit 41C, a fourth accumulator unit 41D, and a fifth accumulator unit 41E. The accumulator unit 34 includes a sixth accumulator unit 41F, a seventh accumulator unit 41G, an eighth accumulator unit 41H, and a first selection unit 42.

  The first accumulator unit 41A includes an EXOR 51, a first shift register 52, a second shift register 53, and a third shift register 54. The second to eighth accumulator units 41B to 41H also have an EXOR 51 and first to third shift registers 52 to 54, similarly to the first accumulator unit 41A.

  The first accumulator unit 41A sets [p4, p5, p6] = first initial value [000], and generates a parity bit string [p1, p2, p3, p4, p5, p6] based on the setting result. calculate. The second accumulator unit 41B sets [p4, p5, p6] = second initial value [001], and generates a parity bit string [p1, p2, p3, p4, p5, p6] based on the setting result. calculate. The third accumulator unit 41C sets [p4, p5, p6] = third initial value [010], and generates a parity bit string [p1, p2, p3, p4, p5, p6] based on the setting result. calculate.

  The fourth accumulator unit 41D sets [p4, p5, p6] = fourth initial value [011], and generates a parity bit string [p1, p2, p3, p4, p5, p6] based on the setting result. calculate. The fifth accumulator unit 41E sets [p4, p5, p6] = fifth initial value [100], and generates a parity bit string [p1, p2, p3, p4, p5, p6] based on the setting result. calculate. The sixth accumulator unit 41F sets [p4, p5, p6] = sixth initial value [101], and generates a parity bit string [p1, p2, p3, p4, p5, p6] based on the setting result. calculate. The seventh accumulator unit 41G sets [p4, p5, p6] = seventh initial value [110], and generates a parity bit string [p1, p2, p3, p4, p5, p6] based on the setting result. calculate. The eighth accumulator unit 41H sets [p4, p5, p6] = eighth initial value [111], and generates a parity bit string [p1, p2, p3, p4, p5, p6] based on the setting result. calculate.

  The first selection unit 42 collects each parity bit string from the first to eighth accumulator units 41A to 41H, and whether or not the backward bit string [p4, p5, p6] of the parity bit string matches the set bit string. Determine whether. The backward bit string is a bit string corresponding to a predetermined row ψ. In the case of the parity bit string of the first accumulator unit 41A, the first selection unit 42 matches the rear bit string [p4, p5, p6] of the parity bit string with the first initial value [000] being set. It is determined whether or not. Further, in the case of the parity bit string of the second accumulator unit 41B, the first selection unit 42 sets the backward bit string [p4, p5, p6] of the parity bit string and the second initial value [001] being set as one. Determine whether you are doing it. In the case of the parity bit string of the third accumulator unit 41C, the first selection unit 42 matches the rear bit string [p4, p5, p6] of the parity bit string with the third initial value [010] being set. It is determined whether or not. Further, in the case of the parity bit string of the fourth accumulator unit 41D, the first selection unit 42 sets the backward bit string [p4, p5, p6] of the parity bit string and the fourth initial value [011] being set as one. Determine whether you are doing it. In the case of the parity bit string of the fifth accumulator unit 41E, the first selection unit 42 matches the rear bit string [p4, p5, p6] of the parity bit string with the fifth initial value [100] being set. It is determined whether or not. Further, in the case of the parity bit string of the sixth accumulator unit 41F, the first selection unit 42 sets the backward bit string [p4, p5, p6] of the parity bit string and the sixth initial value [101] being set as one. Determine whether you are doing it. In the case of the parity bit sequence of the seventh accumulator unit 41G, the first selection unit 42 matches the rear bit sequence [p4, p5, p6] of the parity bit sequence with the seventh initial value [110] being set. It is determined whether or not. Further, in the case of the parity bit string of the eighth accumulator unit 41H, the first selection unit 42 sets the backward bit string [p4, p5, p6] of the parity bit string and the eighth initial value [111] being set as one. Determine whether you are doing it.

  When the rear bit string [p4, p5, p6] of the parity bit string matches the initial value being set, the first selection unit 42 determines that the parity bit string is correct and the parity bit string determined to be correct Is output to the synthesis unit 35 as an output of the accumulator unit 34. The combining unit 35 combines the bit string [u1, u2, u3] of the message and the parity bit string [p1, p2, p3, p4, p5, p6] to generate the codeword [u1, u2, u3, p1, p2, p3, p4, p5, p6] are output.

  Next, the operation of the optical transmission device 1 according to the first embodiment will be described. FIG. 5 is a flowchart illustrating an example of the processing operation of the encoding unit 21 related to the first encoding process. In FIG. 5, the encoding unit 21 determines whether or not the bit string [u1, u2, u3] of the message is accumulated (step S11). When the encoding unit 21 has accumulated the bit string [u1, u2, u3] of the message (Yes at Step S11), the encoding unit 21 performs the repeat process of the repeat unit 31 (Step S12).

  After executing the repeat process, the encoding unit 21 performs the interleaver process in the interleaver unit 32 (step S13). The encoding unit 21 performs a combining process in the combining unit 33 (step S14). The encoding unit 21 executes the accumulation process for each initial value in parallel in the first accumulator unit 41A to the eighth accumulator unit 41H (step S15). The encoding unit 21 outputs a parity bit string for each initial value in the accumulation process of the first accumulator unit 41A to the eighth accumulator unit 41H (step S16).

  The encoding unit 21 compares the backward bit string [p4, p5, p6] in the parity bit string acquired for each initial value with the initial value being set (step S17), and the backward bit string and the initial value being set are determined. The matched parity bit string is selected (step S18). The encoding unit 21 combines the selected parity bit string and the message bit string to generate a code word c (step S19), outputs the generated code word c (step S20), and performs the processing operation shown in FIG. finish.

  The encoding unit 21 according to the first embodiment includes a matrix on the diagonal line of the parity calculation matrix H2 in the parity check matrix H, a cyclic matrix that is one row below the diagonal line, and a cyclic matrix that is a predetermined row, for example, three rows below the diagonal line. And all the columns have a parity check matrix H having a column weight of 3 or more, so that the error floor can be improved.

  The encoding unit 21 calculates a parity bit string for each initial value based on each initial value to be assigned to the information calculation matrix H1, the parity calculation matrix H2, and [p4, p5, p6] in the parity check matrix H. The backward bit string of is compared with the initial value being set. Then, a parity bit string in which the backward bit string matches the initial value is selected, and the parity bit string and the message bit string are combined to output a code word c. As a result, a parity bit string can be calculated even when a parity check matrix H having a column weight of 3 or more for all the columns is used.

  Moreover, the encoding unit 21 arranges the first to eighth accumulator units 41A to 41H for each initial value in parallel, and calculates the parity bit strings of all patterns [p4, p5, p6]. Furthermore, the encoding unit 21 compares the rear bit string of the parity bit string with the initial value being set, and selects a parity bit string whose post-bit string matches the initial value being set. As a result, a parity bit string can be calculated even when a parity check matrix H having a column weight of 3 or more for all the columns is used.

In the first embodiment, the same merit as the RA code can be used even in an optical transmission system that requires high transmission quality. In addition, since it is not necessary to use an error correction circuit for hard decision, an optical transmission system with reduced circuit scale and power consumption can be realized. That is, the reception BER ≦ 1e- ¹⁵ can be achieved without having a hard decision circuit.

  The accumulator unit 34 of the first embodiment exemplifies a case where the first to eighth accumulators 41A to 41H in which initial values of all patterns of the backward bit string [p4, p5, p6] of the parity bit string are set are arranged in parallel. . However, the present invention is not limited to such a configuration, and a single accumulator unit may be used. An embodiment in that case will be described below as Example 2. The same components as those of the optical transmission device 1 according to the first embodiment are denoted by the same reference numerals, and the description of the overlapping configuration and operation is omitted.

  The difference between the first embodiment and the second embodiment is that the initial values are sequentially updated by a single tenth accumulator unit 43 instead of arranging the first to eighth accumulator units 41A to 41H in parallel. Thus, the parity bit string of each pattern is sequentially output.

  FIG. 6 is an explanatory diagram illustrating an example of an accumulator unit 34A according to the second embodiment. The accumulator unit 34A illustrated in FIG. 6 includes a tenth accumulator unit 43 and a second selection unit 42A. The tenth accumulator unit 43 includes an EXOR 51, a first shift register 52, a second shift register 53, a third shift register 54, a pattern memory 55, and a setting unit 56. The pattern memory 55 is an area for storing all initial values of [p4, p5, p6]. The setting unit 56 sets each initial value in the pattern memory 55 in the first to third shift registers 52 to 54. The initial values are, for example, the first [000], the second [001], the third [010], the fourth [011], the fifth [100], the sixth “101”, Eight types of seventh [110] and eighth [111].

  The setting unit 56 reads the initial value from the pattern memory 55, updates the read initial value to the first to third shift registers 52 to 54, and sequentially outputs a parity bit string for each initial value. That is, the tenth accumulator unit 43 sequentially outputs a parity bit string for each initial value in accordance with the update of the initial value of the setting unit 56.

  The second selection unit 42A sequentially inputs the parity bit string of the initial value from the tenth accumulator unit 43, and compares the backward bit string [p4, p5, p6] of the input parity bit string with the initial value being set. . The second selection unit 42A outputs the parity bit string when the backward bit string matches the initial value being set. The second selection unit 42A discards the parity bit string when the backward bit string does not match the initial value being set. The setting unit 56 sequentially sets initial values until the rear bit string matches the initial value being set by the second selection unit 42A.

  Next, the operation of the optical transmission device 1 according to the second embodiment will be described. FIG. 7 is a flowchart illustrating an example of a processing operation of the encoding unit 21 related to the second encoding process according to the second embodiment. In FIG. 7, the encoding unit 21 sets the initial value in the tenth accumulator unit 43 after executing the combining process in step S14 (step S31). The encoding unit 21 performs an accumulation process based on the initial value of the tenth accumulator unit 43 (step S32).

  The encoding unit 21 acquires an initial value parity bit string by the accumulation process (step S33). The encoding unit 21 compares the backward bit string in the set parity bit string with the initial value currently set (step S34), and determines whether or not the backward bit string and the initial value currently set match (step S34). Step S35). When the backward bit string matches the initial value (Yes at Step S35), the encoding unit 21 selects the matched parity bit string (Step S36).

  The encoding unit 21 combines the selected parity bit string and the message bit string to generate a code word c (step S37), outputs the generated code word c (step S38), and performs the processing operation shown in FIG. finish. When the backward bit string does not match the initial value (No at Step S35), the encoding unit 21 sets an unset initial value in the tenth accumulator unit 43 (Step S39), and executes the accumulation process. Therefore, the process proceeds to step S32.

  The encoding unit 21 according to the second embodiment sequentially sets the initial value by the single tenth accumulator unit 43 to sequentially calculate the parity bit string for each initial value, and the rear bit string of the calculated parity bit string and the initial bit being set Compare the value. The encoding unit 21 outputs the parity bit sequence when the backward bit sequence matches the initial value being set. Further, the encoding unit 21 combines the parity bit string and the message bit string and outputs a codeword c. As a result, a parity bit string can be calculated even when a parity check matrix H having a column weight of 3 or more for all the columns is used.

  In addition, it is not limited to the structure of the accumulator part 34 (34A) of Example 1 and 2, You may be made into the accumulator part which used the parallel processing and the update process together, and it is referred to as Example 3 below about the embodiment. Explained. The same components as those of the optical transmission device 1 according to the first embodiment are denoted by the same reference numerals, and the description of the overlapping configuration and operation is omitted.

  The difference between the accumulator unit 34 of the first embodiment and the accumulator unit 34B of the third embodiment is the four units of the 11th to 14th accumulator units 44A to 44D, and each of the 11th to 14th accumulator units 44A to 44D. Two types of initial values can be set.

  FIG. 8 is an explanatory diagram illustrating an example of the accumulator unit 34B according to the third embodiment. The accumulator unit 34B shown in FIG. 8 includes an eleventh accumulator unit 44A, a twelfth accumulator unit 44B, a thirteenth accumulator unit 44C, a fourteenth accumulator unit 44D, and a third selection unit 42B. .

  The 11th to 14th accumulator units 44A to 44D include an EXOR 51, first to third shift register units 52 to 54, a pattern memory 55A, and a setting unit 56A.

  The pattern memory 55A of the eleventh accumulator unit 44A stores a first initial value [000] and a second initial value [001] as two types of initial values. The setting unit 56A of the eleventh accumulator unit 44A can set the first initial value [000] and the second initial value [001].

  The pattern memory 55A of the twelfth accumulator unit 44B stores a third initial value [010] and a fourth initial value [011] as two types of initial values. The setting unit 56A of the twelfth accumulator unit 44B can set the third initial value [010] and the fourth initial value [011].

  The pattern memory 55A of the thirteenth accumulator unit 44C stores a fifth initial value [100] and a sixth initial value [101] as two types of initial values. The setting unit 56A of the thirteenth accumulator unit 44C can set the fifth initial value [100] and the sixth initial value [101].

  The pattern memory 55A of the fourteenth accumulator unit 44D stores a seventh initial value [110] and an eighth initial value [111] as two types of initial values. The setting unit 56A of the fourteenth accumulator unit 44D can set the seventh initial value [110] and the eighth initial value [111].

  The third selection unit 42B inputs a parity bit string for each initial value in parallel from the first to fourteenth accumulator units 44A to 44D. The third selection unit 42B compares the backward bit string of the parity bit string of the initial value with the initial value being set, and determines whether or not the backward bit string matches the initial value being set. The third selection unit 42B selects and outputs the parity bit string when the backward bit string of the parity bit string matches the initial value being set. Further, the third selection unit 42B discards the parity bit string when the backward bit string of the parity bit string does not match the initial value.

  Next, the operation of the optical transmission device 1 according to the third embodiment will be described. FIG. 9 is a flowchart illustrating an example of the processing operation of the encoding unit 21 related to the third encoding process according to the third embodiment. In FIG. 9, the encoding unit 21 sets the initial value in the 11th to 14th accumulator units 44A to 44D after executing the combining process in step S14 (step S41). The encoding unit 21 performs an accumulation process based on the initial values of the 11th to 14th accumulator units 44A to 44D (step S42).

  The encoding unit 21 acquires an initial value parity bit string by the accumulation process (step S43). The encoding unit 21 compares the backward bit string in the set parity bit string with the currently set initial value (step S44), and determines whether or not the backward bit string matches the currently set initial value ( Step S45). When the backward bit string matches the initial value being set (Yes at Step S45), the encoding unit 21 selects the parity bit string having the matching initial value (Step S46).

  The encoding unit 21 combines the selected parity bit string and the message bit string to generate a codeword c (step S47), outputs the generated codeword (step S48), and ends the processing operation shown in FIG. To do. If the backward bit string does not match the initial value being set (No at Step S45), the encoding unit 21 sets an unset initial value in the 11th to 14th accumulator units 44A to 44D (Step S49). ), The process proceeds to step S42 to execute the accumulation process.

  The encoding unit 21 according to the third embodiment sequentially sets initial values in the first to fourteenth accumulator units 44A to 44D, sequentially calculates a parity bit string for each initial value, and is setting a backward bit string of the calculated parity bit string Compare the initial value of. The encoding unit 21 outputs the parity bit sequence when the backward bit sequence matches the initial value being set. Further, the encoding unit 21 combines the parity bit string and the message bit string and outputs a codeword c. As a result, a parity bit string can be calculated even when a parity check matrix H having a column weight of 3 or more for all the columns is used.

  In the first to third embodiments, the w3RA code is exemplified. However, the present invention is not limited to the w3RA code and can be applied to a spatially coupled RA code. Therefore, the embodiment will be described below as a fourth embodiment. To do. In addition, the same code | symbol is attached | subjected to the structure same as Example 1, and the description of the overlapping structure and operation | movement is abbreviate | omitted.

  In the spatially-coupled RA code, the information calculation matrix H11 of the RA code or the w3RA code is configured by a spatially-coupled LDPC, and each element matrix is regarded as a space and coupled. FIG. 10 is an explanatory diagram illustrating an example of the parity check matrix H10 of the spatially-coupled RA code.

  A parity check matrix H10 illustrated in FIG. 10 includes an information operation matrix H11 and a parity operation matrix H12. The parity calculation matrix H12 has a structure in which “1” elements are regularly arranged in a diagonal matrix, a cyclic matrix one row below the diagonal, and a cyclic matrix below the predetermined row, for example, four rows from the diagonal. . In this case, 16 set bit strings of all 16 patterns of a predetermined row in the parity calculation matrix H12, that is, a 4-digit backward bit string [p9, p10, p11, p12] are set in 16 accumulator units. The initial value is 2 ^ (predetermined number of rows) = 2 ^ 4 = 16. Assume that 16 accumulator units are arranged in parallel. As a result, the 16 accumulator units output 16 parity bit strings for each set bit string.

  Then, the first selection unit 42 determines whether or not the backward bit string [p9, p10, p11, p12] of the parity bit string matches the initial value being set, and the backward bit string and the initial value being set A parity bit string that matches is output to the synthesizer 35.

  FIG. 11A is an explanatory diagram illustrating an example of a BER-SNR characteristic of error correction of a spatially-coupled RA code (no cyclic) to which the present invention is not applied. In the example shown in FIG. 11A, an error floor occurs because a column having a column weight of 2 or less exists in the parity calculation matrix H12. In contrast, FIG. 11B is an explanatory diagram illustrating an example of a BER-SNR characteristic of error correction of the spatially-combined RA code (with cyclic) according to the fourth embodiment. In the example shown in FIG. 11B, the error floor is improved because the column weights of all the columns in the parity calculation matrix H12 are 3 or more.

  The encoding unit 21 according to the fourth embodiment includes a matrix on the diagonal line of the parity operation matrix H12 in the parity check matrix H10 of the spatially coupled RA code, a cyclic matrix one row below the diagonal line, and a cyclic matrix four rows below the diagonal line. And a parity check matrix H10 in which the column weights of all the columns are 3 or more. As a result, the error floor can be improved.

  The encoding unit 21 according to the fourth embodiment uses a parity bit string for each initial value based on each information calculation matrix H11, parity calculation matrix H12, and [p9, p10, p11, p12] in the parity check matrix H10. Is calculated. The encoding unit 21 compares the backward bit string of the parity bit string for each initial value with the initial value being set. Then, the encoding unit 21 outputs a parity bit string in which the backward bit string matches the initial value being set, combines the parity bit string and the bit string of the message, and outputs a code word c. As a result, a parity bit string can be calculated even when a parity check matrix H10 having a column weight of 3 or more for all the columns of the spatially coupled RA code is used.

  In addition, the encoding unit 21 according to the fourth embodiment arranges the accumulator unit 34 in parallel for each initial value, calculates parity bit sequences of all patterns [p9, p10, p11, p12], Compare the initial value being set. The encoding unit 21 outputs a parity bit string in which the backward bit string matches the initial value being set. As a result, a parity bit string can be calculated even when a parity check matrix H10 having a column weight of 3 or more for all the columns is used.

  In the fourth embodiment, by applying to the spatially coupled RA code, it is possible to achieve both a high error correction capability and a low error floor without excessively complicating the encoding process.

  In the first to third embodiments, the diagonal matrix in the parity calculation matrix H2, the cyclic matrix one row below the diagonal line, and the cyclic matrix three rows below the diagonal line are used. However, the configurations are limited to these configurations. Needless to say, it can be changed as appropriate. The predetermined line is not limited to three lines or four lines below the diagonal, and can be changed as appropriate.

  The encoding unit 21 according to the fourth embodiment has been described by applying the spatially coupled RA code to the accumulator unit 34 according to the first embodiment. However, the encoding unit 21 may be applied to the accumulator unit 34A according to the second embodiment or the accumulator unit 34B according to the third embodiment. It can be changed as appropriate.

  Moreover, although the encoding part 21 of the said Example was incorporated in the optical transmission apparatus 1, it is not limited to an optical signal, It is applicable also when encoding an electrical signal.

  In addition, each component of each part illustrated does not necessarily need to be physically configured as illustrated. In other words, the specific form of distribution / integration of each part is not limited to the one shown in the figure, and all or a part thereof may be functionally or physically distributed / integrated in arbitrary units according to various loads and usage conditions. Can be configured.

  Furthermore, various processing functions performed in each device are performed on a CPU (Central Processing Unit) (or a microcomputer such as an MPU (Micro Processing Unit), MCU (Micro Controller Unit), etc.) in whole or in part. You may make it perform. Various processing functions may be executed entirely or arbitrarily on a program that is analyzed and executed by a CPU (or a microcomputer such as an MPU or MCU) or hardware based on wired logic. Needless to say.

DESCRIPTION OF SYMBOLS 1 Optical transmission apparatus 21 Encoding part 34, 34A, 34B Accumulator part 41A-41H 1st-8th accumulator part 42 1st selection part 42A 2nd selection part 42B 3rd selection part 43 10th accumulator part 44A-44D 11th-14th accumulator part

Claims (8)

A parity check matrix having a matrix on a diagonal line, a parity operation matrix having a cyclic matrix one row below and a predetermined row below the diagonal line, and an information operation matrix;
Depending on the input of the bit string of the message, all the initial values in the rear bit string of the predetermined number of rows of the parity bits used when calculating the parity bit string with the arithmetic expression specified by the parity arithmetic matrix and the information arithmetic matrix And calculating a parity bit string for each initial value;
A selection unit that selects a parity bit string of the initial value when a backward bit string of the parity bit string for each initial value matches the initial value;
An encoding apparatus, comprising: a combining unit that combines the selected parity bit string and the bit string of the message to output a code word. The calculation unit includes:
2. The encoding apparatus according to claim 1, comprising 2 ^ (predetermined number of rows) accumulator units for calculating the parity bit string for each initial value, and arranging these accumulator units in parallel. The calculation unit includes:
A setting unit for setting the initial value;
The encoding apparatus according to claim 1, further comprising: an accumulator unit that calculates the parity bit string for each of the initial values set by the setting unit. The calculation unit includes:
A setting unit for setting the initial value;
The encoding apparatus according to claim 1, further comprising: a plurality of accumulator units that calculate the parity bit string for each of the initial values set by the setting unit, wherein the accumulator units are arranged in parallel. The parity check matrix is
5. The encoding apparatus according to claim 1, wherein the encoding apparatus is a parity check matrix of a weight-3 Repeat Accumulate code. The parity check matrix is
5. The encoding apparatus according to claim 1, wherein the encoding apparatus is a parity check matrix of a spatially coupled Repeat Accumulate code. A transmission device including a coding device that outputs a code word in response to input of a bit string of a message,
The encoding device includes:
A parity check matrix having a matrix on a diagonal line, a parity operation matrix having a cyclic matrix one row below and a predetermined row below the diagonal line, and an information operation matrix;
In accordance with the bit string input of the message, all the initial bit strings in the rear bit string corresponding to the predetermined number of rows of parity bits used when calculating the parity bit string by the arithmetic expression specified by the parity arithmetic matrix and the information arithmetic matrix A calculation unit for setting a value and calculating a parity bit string for each initial value;
A selection unit that selects a parity bit string of the initial value when a backward bit string of the parity bit string for each initial value matches the initial value;
A transmission apparatus comprising: a combining unit that combines the selected parity bit string and the bit string of the message to output a code word. A parity check matrix having a matrix on a diagonal line, a parity operation matrix having a cyclic matrix below and one row below the diagonal line, and an information operation matrix,
Depending on the input of the bit string of the message, all the initial values in the rear bit string of the predetermined number of rows of the parity bits used when calculating the parity bit string with the arithmetic expression specified by the parity arithmetic matrix and the information arithmetic matrix To calculate a parity bit string for each initial value,
When a backward bit string of the parity bit string for each initial value matches the initial value, the parity bit string of the initial value is selected,
An encoding method comprising: executing a process of combining the selected parity bit string and the bit string of the message to output a code word.

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