JP2017224089A5

JP2017224089A5 -

Info

Publication number: JP2017224089A5
Application number: JP2016117940A
Authority: JP
Filing date: 2016-06-14
Publication date: 2018-09-06
Anticipated expiration: 2036-06-14

Description

そして、データ転送部においては、システムバスからバス入力メモリにデータが入力され、バス入力メモリに入力されたデータは、複数のアレイメモリの間で転送される。アレイメモリを介して転送されたデータは、複数のプロセッサ入力メモリを経て対応する演算プロセッサにより直接読み込まれる。各演算プロセッサが処理したデータは、それぞれに対応するプロセッサ出力メモリに直接書き込まれると、バス出力メモリを介してシステムバスに出力される。 In the data transfer unit, data is input from the system bus to the bus input memory, and the data input to the bus input memory is transferred between the plurality of array memories. Data transferred through the array memory is directly read by a corresponding arithmetic processor via a plurality of processor input memories. When the data processed by each arithmetic processor is directly written to the corresponding processor output memory, it is output to the system bus via the bus output memory.

請求項２記載のデータ処理システムによれば、バス出力メモリをｍ個のプロセッサ出力メモリの１つとしても機能させる。このように、バス出力メモリを、例えばシステムバスに最も近い位置にある演算プロセッサに対応するプロセッサ出力メモリとしても機能させることでメモリデバイスの数を減らすことができ、データ転送をより効率的に行うことができる。 According to the data processing system of the second aspect , the bus output memory is caused to function as one of the m processor output memories. As described above, the number of memory devices can be reduced by making the bus output memory function also as a processor output memory corresponding to an arithmetic processor located closest to the system bus, for example, and data transfer is performed more efficiently. be able to.

請求項３記載のデータ処理システムによれば、プロセッサ入力メモリのそれぞれに直接接続されている複数のアレイメモリは、自身に接続されているプロセッサ入力メモリに処理待ちのデータが配置されていると、隣接するプロセッサ入力メモリに接続されているアレイメモリにデータを転送する。これより、より早期に処理を行うことが可能な演算プロセッサにデータを処理させることができるので、待ちを発生させることなく効率的に処理できる。
According to the data processing system of claim 3, the plurality of array memories directly connected to each of the processor input memories are arranged such that the data waiting for processing is arranged in the processor input memory connected to itself. Data is transferred to the array memory connected to the adjacent processor input memory. As a result, the data can be processed by an arithmetic processor capable of performing processing earlier, so that it can be processed efficiently without causing a wait.

Claims

A plurality of arithmetic processors (7) for processing the read data;
A data transfer unit (6, 32, 42) including a plurality of memory devices (11-15, 33, 43, 53, 54) for transferring data between the system bus (2) and the plurality of arithmetic processors. , 52, 62)
The data transfer unit includes a time stamp giving unit (22) for giving a time stamp to data input from the system bus;
A transfer time counter (23) that measures the time during which data is being transferred;
A processing time counter (23) for measuring the time during which data processing by the arithmetic processor is performed;
When outputting the data processed by the arithmetic processor to the system bus, determining the total elapsed time from the time when the time stamp was given, it is determined whether the total elapsed time is within a specified time, processing time determination unit that applies the determination result to the data and (25) possess,
The number of the arithmetic processors is m (m ≧ 2),
The data transfer unit includes a bus input memory (11, 33) to which data is input from a system bus,
In order to read data input to the bus input memory into any of the m arithmetic processors, m · n (n ≧ 1) array memories (12) to which the data is transferred;
M processor input memories (13) for receiving data transferred through the array memory and for directly reading the data by the m arithmetic processors,
M processor output memories (14) to which data outputted from the m arithmetic processors are directly written, respectively;
A bus output memory (15, 43, 54) for inputting data written to the processor output memory and outputting the data to the system bus;
The time stamp giving unit (22 (I)) is arranged in the bus input memory,
The transfer time timer (23 (A)) is arranged in each of the array memories,
The processing time timer (23 (I), 23 (O)) is disposed in the processor input memory and the processor output memory,
The processing time determination unit is a data processing system arranged in the bus output memory .

The bus output memory, the data processing system of claim 1 in which also serves as one of the m processors output memory.

The m array memories directly connected to each of the processor input memories are connected to adjacent processor input memories when data waiting for processing is arranged in the processor input memories connected thereto. data processing system according to claim 1 or 2, wherein transferring data to the array memory.

The data transfer unit transfers data input from the system bus with priority given to a processor input memory having a shortest data transfer path from the bus input memory,
Thereafter, data is sequentially transferred to (m−1) processor input memories adjacent to the processor input memory,
Wherein the conflict on the destination data between the array memory is generated, the data processing system of any at all according to claims 1 to 3 to perform transfer in favor of the array memory towards the path is short to the processor input memory.

The data transfer unit is in the same path between the bus input memory and the m processor input memories (33) and between the bus input memory and the processor input memory having the shortest data transfer path. An initial data transfer bus (34) for direct connection to each existing array memory;
The bus input memory transfers initial data, which is input after power is turned on, from the memory with the longest data transfer path to the memory with the shortest path sequentially via the initial data transfer bus. The data processing system according to any one of claims 1 to 4 .

6. The bus output memory according to any one of claims 1 to 5 , wherein when the total elapsed time exceeds the specified time, information indicating that the data is invalid is added to the corresponding data. Data processing system.

The bus output memory (43) is configured so that when the data becomes invalid and other data currently being processed becomes invalid, each memory and operation that holds the data currently being processed Inform the processor that it is invalid,
7. The data processing system according to claim 6 , wherein the memory and the arithmetic processor that have received the notification stop transferring the currently held data, and transfer data that is input via the bus input memory after that time.

The bus output memory (54) indicates that the data is output to the system bus when the data output to the system bus is input again to the bus input memory. )
The bus input memory measures the time from when the notification is received until the data is input again, compares the time measured with a specified time, determines whether the data is invalid, The data processing system according to any one of claims 1 to 7 , wherein if determined, the processing of the data is stopped.

An input selector (73) for switching between a path for inputting data to the bus input memory via the system bus and a path for inputting data without passing through the system bus;
And path for inputting data to said system bus from said bus output memory, any one of claims 1 to 8, wherein an output selector for switching between the paths to output the data without passing through the system bus (74) The data processing system described in 1.

The data according to any one of claims 1 to 9 , wherein the processing time determination unit (65) adds a margin time, which is a difference between the specified time and the total elapsed time, to data to be output to the system bus. Processing system.

A clock supply unit configured to supply an operation clock signal to the arithmetic processor and change a frequency of the operation clock signal;
Depending on the processing time determination notified margin time from the data processing system of claim 1 0, wherein and a processing time adjustment unit that adjusts to reduce the frequency (64).