JP2017216262A - Semiconductor element built-in substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element built-in substrate that can be reduced in size.SOLUTION: In a resin seal body 10, a first veer hole 14 is formed for grounding and a power source by using, as a bottom face, electrodes 12G, 12P for grounding and the power source, and a second veer hole 15 is formed for grounding and a power source by using, as a bottom face, the upper face of a semiconductor element positioning conductor 11. In the first and second veer holes 14, 15 for a second main face 10b and grounding, a wiring conductor 16 for grounding is formed. An external connection pad 13 for grounding is connected to the underside of the semiconductor element positioning conductor 11. In addition, in the first and second veer holes 14, 15 for a second main face 10b and a power source, a wiring conductor 16 for the power source is formed. An external connection pad 13 for the power source is connected to the underside of the semiconductor element positioning conductor 11.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor element built-in substrate that incorporates a semiconductor element.

FIG. 2 is a schematic cross-sectional view of a conventional substrate B with a built-in semiconductor element.
A conventional semiconductor element-embedded substrate B includes, for example, a resin sealing body 30, a semiconductor element positioning conductor 31, a semiconductor element 32, an external connection pad 33, first and second via holes 34 and 35, and a wiring conductor. 36.

The resin sealing body 30 has a semiconductor element buried region Y at the center of the lower surface.
The semiconductor element positioning conductor 31 is formed, for example, in a frame shape in a region outside the semiconductor element buried region Y.
The semiconductor element 32 has an electrode forming surface 32a on which a plurality of signal electrodes 32S, grounding electrodes 32G, and power supply electrodes 32P are formed, and an electrode non-forming surface 32b on which no electrodes are formed. The semiconductor element 32 is embedded in a state where the electrode non-formation surface 32b is exposed in the semiconductor element embedded region Y.
A plurality of external connection pads 33 are formed in a region outside the semiconductor element buried region Y on the lower surface of the resin sealing body 30. The external connection pad 33 is connected to an electrode of an external substrate (not shown) on which the semiconductor element built-in substrate B is mounted via solder.
The first via hole 34 is formed in the resin sealing body 30 with the grounding electrode 32G, the power supply electrode 32P, and the signal electrode 32S as bottom surfaces.
The second via hole 35 is formed in the resin sealing body 30 with a part of the external connection pad 33 as a bottom surface.
A wiring conductor 36 is formed on the surface and inside of the resin sealing body 30. The wiring conductor 36 formed in the surface of the resin sealing body 30 and in the first and second via holes 34 and 45 connects the grounding electrode 32G, the power supply electrode 32P, the signal electrode 32S, and the external connection pad 33. Electrically connected.

Incidentally, in recent years, as electronic devices typified by portable game machines and music players have been reduced in size, there has been an increasing demand for miniaturization of substrates with built-in semiconductor elements mounted on these electronic devices.
However, in the conventional semiconductor element-embedded substrate B, a region for forming the semiconductor element positioning conductor 31 is required in a region outside the semiconductor element buried region Y.
For this reason, the external connection pad 33 must be formed outside the semiconductor element positioning conductor 31, and there is a problem that it is difficult to reduce the size of the semiconductor element built-in substrate.

Japanese Patent Laid-Open No. 2005-236039

  It is an object of the present invention to provide a semiconductor element-embedded substrate that can be miniaturized by forming a part of the external connection pad at a position close to the semiconductor element buried region.

  A semiconductor element-embedded substrate in the present invention has a flat first main surface and a second main surface facing each other, and a resin sealing body having a semiconductor element embedded region on the first main surface side, and a semiconductor element A positioning conductor for a semiconductor element, which is formed along the outer periphery of the buried region, the bottom surface is exposed to the first main surface, and the top surface and the side surface are composed of a plurality of independent conductor patterns embedded in the resin sealing body; And an electrode forming surface on which a plurality of signal electrodes, grounding electrodes and power supply electrodes are formed, and an electrode non-forming surface on which no electrode is formed, and the electrode non-forming surface is exposed in the semiconductor element buried region A semiconductor element-embedded substrate comprising a semiconductor element embedded in a resin sealing body and a plurality of external connection pads formed on a first main surface, wherein the resin sealing body includes Is First via hole for grounding with an electrode for bottom surface, second via hole for grounding with the top surface of a positioning conductor for semiconductor elements as a bottom surface, and first via hole for power source and semiconductor with a power electrode as a bottom surface A power supply second via hole is formed with the upper surface of the element positioning conductor as the bottom surface. The grounding electrode and the semiconductor element are provided in the second main surface and the first and second via holes for grounding. A grounding wiring conductor for electrically connecting the positioning conductor is formed, and the external connection pad for grounding is connected to the lower surface of the positioning conductor for the semiconductor element so as to overlap at least a part of the positioning conductor for the semiconductor element. And a power supply for electrically connecting a power supply electrode and a semiconductor element positioning conductor in the second main surface and the first and second via holes for power supply. Wiring and conductors are formed, it is characterized in that the external connection pads for power supply to the lower surface of the semiconductor element positioning conductor is connected so as to overlap with at least a part of the positioning conductive semiconductor element.

According to the substrate with a built-in semiconductor element according to the present invention, the first via hole for grounding with the grounding electrode as the bottom surface, the second via hole for grounding with the top surface of the positioning conductor for the semiconductor element as the bottom surface, and the power supply electrode A first via hole for power supply having a bottom surface and a second via hole for power supply having a top surface of the positioning conductor for semiconductor element as a bottom surface are formed, and the second main surface and the first and second grounding surfaces are formed. In the via hole, a grounding wiring conductor for electrically connecting the grounding electrode and the semiconductor element positioning conductor is formed. An external connection pad for grounding is provided on the lower surface of the semiconductor element positioning conductor for the semiconductor element. It is connected so as to overlap with at least a part of the positioning conductor, and in the second main surface and the first and second via holes for the power supply, the power supply electrode and the semiconductor A wiring conductor for power supply that electrically connects the element positioning conductor is formed, and the external connection pad for power supply is connected to at least a part of the semiconductor element positioning conductor on the lower surface of the semiconductor element positioning conductor. Has been.
In this way, the second via hole for grounding and a part of the external connection pad for grounding, and the second via hole for power supply and a part of the external connection pad for power supply are located close to the semiconductor element buried region. Thus, it is possible to provide a substrate with a built-in semiconductor element that can be reduced in size.

FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor element built-in substrate according to the present invention. FIG. 2 is a schematic cross-sectional view showing an example of a conventional substrate with a built-in semiconductor element.

  First, an example of a semiconductor element built-in substrate according to the present invention will be described with reference to FIG.

  As shown in FIG. 1, a semiconductor element-embedded substrate A according to the present invention includes, for example, a resin sealing body 10, a semiconductor element positioning conductor 11, a semiconductor element 12, an external connection pad 13, and first and second elements. Via holes 14 and 15 and a wiring conductor 16.

The resin sealing body 10 is made of a thermosetting resin such as an epoxy resin or a polyurethane resin. The resin sealing body 10 has a flat first main surface 10a and a second main surface 10b facing each other. On the first main surface 10a side, a semiconductor element buried region X is provided. The resin sealing body 10 protects the semiconductor element 12 from the external environment.
The resin sealing body 10 is formed by placing a semiconductor element 12 with a semiconductor element positioning conductor 11 formed, for example, on a support plate by copper plating or the like as a guide, and then placing a mold surrounding the semiconductor element 12 to seal the semiconductor element 12. It is formed by pouring a stopping resin into a mold and curing it.

A plurality of semiconductor element positioning conductors 11 are formed along the outer periphery of the semiconductor element buried region X. The semiconductor element positioning conductor 11 has a lower surface exposed at the first main surface 10 a and an upper surface and side surfaces embedded in the resin sealing body 10.
The semiconductor element positioning conductor 11 functions as a guide for accurately arranging the semiconductor element 12 in the semiconductor element buried region X.
Each semiconductor element positioning conductor 11 is formed in, for example, a circular shape or a rectangular shape in a top view, and has a diameter or an outer dimension of about 100 to 200 μm and a thickness of about 30 to 50 μm.

  Examples of the semiconductor element 12 include a microprocessor and a semiconductor memory, and are made of silicon or germanium. The semiconductor element 12 has an electrode forming surface 12a on which a plurality of signal electrodes 12S, grounding electrodes 12G and power supply electrodes 12P are formed, and an electrode non-forming surface 12b on which no electrodes are formed. The semiconductor element 12 is embedded in the resin sealing body 10 such that the electrode non-forming surface 12b is exposed in the semiconductor element embedded region X. By exposing the electrode non-formation surface 12b from the resin sealing body 10, it is possible to efficiently dissipate heat to the outside when the semiconductor element 12 operates.

A plurality of external connection pads 13 are formed in a region outside the semiconductor element embedding region X using a well-known metal such as electroless copper plating and electrolytic copper plating using a known semi-additive method. The external connection pad 13 formed in the vicinity of the semiconductor element buried region X is formed so that at least a part thereof overlaps the semiconductor element positioning conductor 11.
The external connection pad 13 is connected to an electrode of an external substrate (not shown) on which the semiconductor element built-in substrate A is mounted via solder.

The first via hole 14 has a grounding electrode 12G, a power supply electrode 12P, and a signal electrode 12S as bottom surfaces.
The second via hole 15 uses the upper surface of the semiconductor element positioning conductor 11 or the upper surface of the external connection pad 13 as the bottom surface.
The first and second via holes 14 and 15 are formed by, for example, laser processing or blast processing. The opening diameters of the first and second via holes 14 and 15 are approximately 50 to 100 μm.

The wiring conductor 16 is formed on the surface and inside of the resin sealing body 10 by using a well-conductive metal such as electroless copper plating and electrolytic copper plating using a known semi-additive method, for example.
The second main surface 10b and the wiring conductor 16 formed in the first and second via holes 14, 15 electrically connect the ground electrode 12G, the power electrode 12P, the signal electrode 12S, and the external connection pad 13. Connected.

By the way, in the semiconductor element built-in substrate A according to the present invention, the second via hole 15 for grounding has the upper surface of the positioning conductor 11 for semiconductor element as the bottom surface. An external connection pad 13 for grounding is connected to the lower surface of the semiconductor element positioning conductor 11 so as to overlap the semiconductor element positioning conductor 11.
The second via hole 15 for power supply uses the upper surface of the semiconductor element positioning conductor 11 as the bottom surface. An external connection pad 13 for power supply is connected to the lower surface of the semiconductor element positioning conductor 11 so as to overlap the semiconductor element positioning conductor 11.
Thus, according to the semiconductor element-embedded substrate A according to the present invention, the grounding first via hole 14 having the grounding electrode 12G as the bottom surface and the grounding first via hole 14 having the top surface of the semiconductor element positioning conductor 11 as the bottom surface. The first via hole 14 for power supply having the bottom surface of the power supply electrode 12P and the second via hole 15 for power supply having the bottom surface of the upper surface of the positioning conductor 11 for semiconductor element are formed. The grounding wiring conductor 16 that electrically connects the grounding electrode 12G and the semiconductor element positioning conductor 11 is formed in the two main surfaces 10b and the first and second via holes 14 and 15 for grounding. An external connection pad 13 for grounding is connected to the lower surface of the semiconductor element positioning conductor 11 so as to overlap at least a part of the semiconductor element positioning conductor 11. That. Furthermore, a power supply wiring conductor 16 for electrically connecting the power supply electrode 12P and the semiconductor element positioning conductor 11 is provided in the second main surface 10b and the first and second via holes 14 and 15 for power supply. The power supply external connection pad 13 is connected to the lower surface of the semiconductor element positioning conductor 11 so as to overlap at least a part of the semiconductor element positioning conductor 11.
As described above, the second via hole 15 for grounding and a part of the external connection pad 13 for grounding, and the second via hole 15 for power supply and a part of the external connection pad 13 for power supply are formed in the semiconductor element buried region. It is possible to provide the semiconductor element-embedded substrate A that can be reduced in size by being formed at a position close to X.
The second via holes 15 for grounding and the second via holes 15 for power supply are preferably formed alternately along the outer periphery of the semiconductor element buried region X.
In this way, by arranging the second via holes 15 for grounding and the second via holes 15 for power supply alternately, the loop inductance of the semiconductor element built-in substrate A can be reduced and noise can be reduced. .

In addition, this invention is not limited to an example of above-mentioned embodiment, A various change is possible if it is a range which does not deviate from the summary of this invention. For example, in the example of the above-described embodiment, only one wiring conductor 16 is formed on the surface of the second main surface 10b of the resin sealing body 10, but insulating layers and wiring conductors are alternately stacked. A fan-out structure may be formed by forming a rewiring layer.
Moreover, although the example which did not form the soldering resist layer in the surface of the 1st main surface 10a and the 2nd main surface 10b was shown in the example of the above-mentioned embodiment, you may form a soldering resist layer. Absent.

DESCRIPTION OF SYMBOLS 10 Resin sealing body 10a 1st main surface 10b 2nd main surface 11 Positioning conductor 12 for semiconductor elements Semiconductor element 12a Electrode formation surface 12b Electrode non-formation surface 12G Grounding electrode 12P Power supply electrode 12S Signal electrode 13 External connection Pad 14 First via hole 15 Second via hole 16 Wiring conductor A Semiconductor element embedded substrate X Semiconductor element buried region

Claims (2)

A resin sealing body having a flat first main surface and a second main surface facing each other and having a semiconductor element embedded region on the first main surface side;
A semiconductor formed of a plurality of independent conductor patterns formed along the outer periphery of the semiconductor element embedded region, with a lower surface exposed at the first main surface, and an upper surface and side surfaces embedded in the resin sealing body. A positioning conductor for the element;
An electrode forming surface on which a plurality of signal electrodes, grounding electrodes and power supply electrodes are respectively formed; and an electrode non-forming surface on which no electrode is formed. A semiconductor element embedded in the resin sealing body so as to be exposed;
A plurality of external connection pads formed on the first main surface;
A substrate with a built-in semiconductor element comprising:
The resin sealing body includes a first via hole for grounding with the grounding electrode as a bottom surface, a second via hole for grounding with the top surface of the positioning conductor for semiconductor element as a bottom surface, and the power supply electrode. A first via hole for a power source as a bottom surface and a second via hole for a power source with a top surface of the positioning conductor for a semiconductor element as a bottom surface are formed, and the second main surface and the first and the grounding ground holes are formed. A ground wiring conductor for electrically connecting the grounding electrode and the semiconductor element positioning conductor is formed in the second via hole, and the external connection for grounding is formed on the lower surface of the semiconductor element positioning conductor. A pad is connected to overlap at least part of the positioning conductor for semiconductor element, and the first and second via holes for the second main surface and power source Includes a power supply wiring conductor that electrically connects the power supply electrode and the semiconductor element positioning conductor, and the external connection pad for power supply is provided on the lower surface of the semiconductor element positioning conductor. A semiconductor element-embedded substrate, wherein the substrate is connected so as to overlap at least a part of the positioning conductor for use.   2. The semiconductor element built-in according to claim 1, wherein the second via hole for grounding and the second via hole for power supply are alternately formed along an outer periphery of the semiconductor element buried region. substrate.

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