JP2017211906A - Data transfer system, electronic apparatus, and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to reduce a load on a processor due to log data storage processing.SOLUTION: A data transfer system according one embodiment comprises: a plurality of storage media in which log data is written by respective different processors; and a transfer control circuit that transfers the log data stored in the plurality of storage media to an external storage medium at each predetermined timing.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a data transfer system, an electronic apparatus, and an image forming apparatus.

  Conventionally, log data of a CPU is collected and stored in an external storage device for debugging a program executed by a CPU (Central Processing Unit). In a system including a plurality of CPUs, log data of each CPU is stored.

  As a method for storing log data of a plurality of CPUs, one CPU connected to an external storage device collects log data of other CPUs, and the collected log data and its own log data are stored in the external storage device. The method of writing to is known.

  However, the conventional method has a problem that the load of the CPU connected to the external storage device increases due to the log data saving process.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to reduce the load on the processor due to log data storage processing.

  A data transfer system according to an embodiment transfers a plurality of storage media into which log data is written from different processors and the log data stored in the plurality of storage media to an external storage medium at a predetermined timing, respectively. A transfer control circuit.

  According to each embodiment of the present invention, it is possible to reduce the load on the processor due to log data storage processing.

1 is a diagram illustrating an example of a hardware configuration of an electronic device according to a first embodiment. 6 is a flowchart illustrating an example of an operation of a CPU in a storage process according to the first embodiment. The figure which shows the specific example of a log buffer. 6 is a flowchart illustrating an example of an operation of a transfer control circuit in the storage process according to the first embodiment. The timing chart which shows the specific example of a preservation | save process. The flowchart which shows an example of operation | movement of CPU in the preservation | save process of 2nd Embodiment. FIG. 10 is a diagram illustrating an example of a hardware configuration of an image forming apparatus according to a third embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In addition, regarding the description of the specification and the drawings according to each embodiment, constituent elements having substantially the same functional configuration are denoted by the same reference numerals and overlapping description is omitted.

<First Embodiment>
The electronic device according to the first embodiment will be described with reference to FIGS. First, the configuration of the electronic device according to the present embodiment will be described. FIG. 1 is a diagram illustrating an example of a hardware configuration of an electronic device. 1 includes CPUs 1 and 2, log buffers 3 and 4, a transfer control circuit 5, and an external storage medium 6.

The CPU 1 is an example of a processor. Processor is MPU (Micro Processing)
Unit, DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), PLD (Programmable Logic Device), and the like.

  The CPU 1 executes a program stored in the memory and realizes a predetermined function in the electronic device. Further, the CPU 1 writes log data to the log buffer 3. The log data is data used for debugging (such as operation analysis) of a program executed by the CPU 1. Further, the CPU 1 transmits a transfer request to the transfer control circuit 5 at a predetermined timing. The transfer request transmitted by the CPU 1 is data including predetermined information for requesting the transfer control circuit 5 to transfer the log data of the CPU 1.

  The CPU 2 is an example of a processor. The processor may be an MPU, DSP, ASIC, FPGA, PLD, or the like.

  The CPU 2 executes a program stored in the memory and realizes a predetermined function in the electronic device. Further, the CPU 2 writes log data to the log buffer 4. The log data is data used for debugging (such as operation analysis) of a program executed by the CPU 2. Further, the CPU 2 transmits a transfer request to the transfer control circuit 5 at a predetermined timing. The transfer request transmitted by the CPU 2 is data including predetermined information for requesting the transfer control circuit 5 to transfer the log data of the CPU 2.

  In the example of FIG. 1, the electronic device includes two CPUs 1 and 2, but may include three or more CPUs (processors). In the present embodiment, the CPUs 1 and 2 operate independently of each other. That is, the CPUs 1 and 2 operate without synchronization.

  The log buffer 3 is a storage medium to which log data is written from the CPU 1. The log buffer 3 stores log data written from the CPU 1. Also, the log data stored in the log buffer 3 is read by the transfer control circuit 5. The log buffer 3 is, for example, a RAM (Random Access Memory) or a flash memory. The RAM is, for example, an SRAM (Static RAM) or a DRAM (Dynamic RAM).

  The log buffer 4 is a storage medium to which log data is written from the CPU 2. The log buffer 4 stores log data written from the CPU 2. The log buffer 4 is read by the transfer control circuit 5 for stored log data. The log buffer 4 is, for example, a RAM or a flash memory. The RAM is SRAM, DRAM, or the like.

  In the example of FIG. 1, the electronic device includes two log buffers 3 and 4, but may include three or more log buffers. In any case, each log buffer is written with log data from the corresponding processor, and the transfer control circuit 5 reads the log data.

  The transfer control circuit 5 transfers log data of the CPUs 1 and 2 to the external storage medium 6. The transfer of log data here refers to reading log data from the log buffers 3 and 4 and writing it to the external storage medium 6. The transfer control circuit 5 together with the log buffers 3 and 4 constitutes a data transfer system that transfers log data of the CPUs 1 and 2 to the external storage medium 6.

  The transfer control circuit 5 transfers the log data of the CPUs 1 and 2 at predetermined timings so that the transfer periods do not overlap. The transfer control circuit 5 includes a transfer circuit 51 and an adjustment circuit 52.

  The transfer circuit 51 receives a transfer instruction from the adjustment circuit 52. The transfer instruction is data including predetermined information for instructing the transfer circuit 51 to transfer log data. The transfer circuit 51 transfers the log data of the CPUs 1 and 2 according to the transfer instruction received from the adjustment circuit 52.

  Specifically, when receiving the log data transfer instruction from the CPU 1, the transfer circuit 51 reads the log data of the CPU 1 from the log buffer 3 and writes it to the external storage medium 6. Similarly, when the transfer circuit 51 receives a log data transfer instruction from the CPU 2, the transfer circuit 51 reads the log data of the CPU 2 from the log buffer 4 and writes it to the external storage medium 6.

  The adjustment circuit 52 receives a log data transfer request from the CPUs 1 and 2. The adjustment circuit 52 detects the transfer state of the log data by the transfer circuit 51. The adjustment circuit 52 transmits a transfer instruction to the transfer circuit 51 based on the transfer request received from the CPUs 1 and 2 and the detected transfer state of the log data. That is, the adjustment circuit 52 adjusts the log data transfer period of the CPUs 1 and 2 based on the transfer request and the transfer state.

  Specifically, when the transfer circuit 51 is not transferring the log data of the CPU 2 at the timing when the transfer request is received from the CPU 1, the adjustment circuit 52 transmits an instruction to transfer the log data of the CPU 1 to the transfer circuit 51. .

  On the other hand, when the transfer circuit 51 is transferring the log data of the CPU 2 at the timing when the transfer request is received from the CPU 1, the adjustment circuit 52 ends the transfer of the log data of the CPU 2 to the transfer circuit 51. Send log data transfer instructions.

  Further, when the transfer circuit 51 is not transferring the log data of the CPU 1 at the timing when the transfer request is received from the CPU 2, the adjustment circuit 52 transmits an instruction to transfer the log data of the CPU 2 to the transfer circuit 51.

  On the other hand, when the transfer circuit 51 is transferring the log data of the CPU 1 at the timing when the transfer request is received from the CPU 2, the adjustment circuit 52 ends the transfer of the log data of the CPU 1 to the transfer circuit 51. Send log data transfer instructions.

  When the adjustment circuit 52 transmits the transfer instruction as described above (adjusts the transfer period), the transfer circuit 51 transfers the log data of the CPUs 1 and 2 so that the transfer periods of the log data of the CPUs 1 and 2 do not overlap. Can be transferred.

  If the CPUs 1 and 2 are asynchronous, the log data transfer periods of the CPUs 1 and 2 may overlap if the transfer periods are not adjusted. However, the transfer circuit 51 cannot simultaneously write the log data of the CPUs 1 and 2 to the external storage medium 6. As a result, if the log data transfer periods of the CPUs 1 and 2 overlap, the log data may not be stored.

  In this embodiment, since the transfer period of the log data of the CPUs 1 and 2 can be adjusted by the adjustment circuit 52 so as not to overlap, the log data of the CPUs 1 and 2 is externally stored even when the CPUs 1 and 2 are asynchronous. It can be reliably stored in the medium 6.

  In the present embodiment, the transfer control circuit 5 may be configured by a processor. In this case, the functions of the transfer circuit 51 and the adjustment circuit 52 may be realized by the transfer control circuit 5 executing a predetermined program.

  When the electronic device includes three or more CPUs (processors), the adjustment circuit 52 may overlap the log data transfer periods of the CPUs so as not to overlap each other. That is, when the transfer circuit 51 is not transferring the log data of another CPU at the timing when the transfer request is received from a certain CPU, the adjustment circuit 52 may transmit a log data transfer instruction corresponding to the transfer request. Good. Further, when the transfer circuit 51 is transferring log data of another CPU at the timing when a transfer request is received from a certain CPU, the adjustment circuit 52 responds to the transfer request after the transfer of the log data is completed. A CPU log data transfer instruction may be transmitted.

  The external storage medium 6 is a rewritable nonvolatile memory in which log data of the CPUs 1 and 2 is written by the transfer control circuit 5. The external storage medium 6 is preferably removable from the electronic device. The external storage medium 6 is, for example, a flash memory (such as an SD card or a USB (Universal Serial Bus) memory), a magnetic disk, or an optical disk.

  Next, the operation of the electronic device according to the present embodiment will be described. Hereinafter, the processing for storing the log data of the CPUs 1 and 2 is referred to as storage processing. The storage process includes a writing process in which the CPUs 1 and 2 write log data to the log buffers 3 and 4 and a transfer process in which the transfer control circuit 5 transfers log data.

  FIG. 2 is a flowchart showing an example of the operation (write process) of the CPUs 1 and 2 in the storage process of the present embodiment. The operation of FIG. 2 is common to the CPUs 1 and 2. Hereinafter, the operation of FIG. 2 will be described using the CPU 1 as an example.

  When the log data saving process starts, the CPU 1 acquires log data to be saved at an arbitrary timing. The timing at which the CPU 1 acquires log data may be the timing at which the CPU 1 executes a predetermined process, the timing at which a predetermined signal is input to the CPU 1, the timing at which a predetermined change occurs in the signal monitored by the CPU 1, and the like. When the CPU 1 acquires log data to be saved (YES in step S101), the CPU 1 writes the acquired log data in the log buffer 3 (step S102).

  If the CPU 1 has not acquired the log data to be saved (NO in step S101), or after writing of the acquired log data has ended, the CPU 1 has determined whether a predetermined time has elapsed since the last transmission of the transfer request Determination is made (step S103).

  When the predetermined time has elapsed (YES in step S103), the CPU 1 transmits a log data transfer request to the adjustment circuit 52 (step S104). This transfer request includes the start address of the transfer source log buffer and the data amount of the transfer source log buffer. The transfer source log buffer is a storage area in the log buffer 3 that stores log data to be transferred. The transfer control circuit 5 can specify the transfer source log buffer based on the head address and the data amount included in the transfer request.

  Note that the timing at which the CPU 1 transmits the transfer request is not limited to this. For example, the CPU 1 transmits a transfer request when the amount of log data written to the log buffer 3 exceeds a predetermined value or when the number of times log data is written to the log buffer 3 exceeds a predetermined number. Also good.

  CPU1 repeats the process of step S101-S104 until a preservation | save process is complete | finished (NO of step S105). The saving process may be always executed during the operation of the CPUs 1 and 2, or may be executed only while the CPUs 1 and 2 are executing a predetermined process. Further, the storage process may be executed during the operation of both the CPUs 1 and 2 or may be executed during the operation of only one of the CPUs 1 and 2.

  FIG. 3 is a diagram illustrating a specific example of the log buffer. The log buffer of FIG. 3 has two storage areas (areas 1 and 2). For example, when the area 1 of the log buffer in FIG. 3 is the transfer source log buffer, the CPU 1 transmits a transfer request including the start address of the area 1 and the data amount to the transfer control circuit 5. Upon receiving this transfer request, the transfer control circuit 5 transfers the log data stored in the area 1 to the external storage medium 6.

  FIG. 4 is a flowchart showing an example of the operation (transfer process) of the transfer control circuit 5 in the storage process of the present embodiment. The adjustment circuit 52 determines whether a transfer request has been received from the CPUs 1 and 2 at an arbitrary timing (steps S201 and S206).

  When the adjustment circuit 52 receives a transfer request from the CPU 1 (YES in step S201), the adjustment circuit 52 detects the transfer state of the log data by the transfer circuit 51. The transfer request received from the CPU 1 includes the start address of the transfer source log buffer and the data amount in the log buffer 3.

  When the transfer circuit 51 is not transferring the log data of the CPU 2 (NO in step S202), the process proceeds to step S204. On the other hand, when the transfer circuit 51 is transferring the log data of the CPU 2 (YES in step S202), the adjustment circuit 52 waits until the transfer of the log data of the CPU 2 is completed (step S203).

  Subsequently, the adjustment circuit 52 transmits a log data transfer instruction of the CPU 1 to the transfer circuit 51 (step S204). The adjustment circuit 52 generates a transfer instruction based on the transfer request received from the CPU 1. The transfer instruction transmitted by the adjustment circuit 52 includes the start address of the transfer source log buffer and the data amount in the log buffer 3.

  When receiving the transfer instruction from the adjustment circuit 52, the transfer circuit 51 transfers the log data of the CPU 1 based on the received transfer instruction (step S205). That is, the transfer circuit 51 reads the transfer target log data from the transfer source log buffer of the log buffer 3 specified by the transfer instruction, and writes the read log data to the external storage medium 6. Thereby, the log data of the CPU 1 is stored in the external storage medium 6.

  On the other hand, when the adjustment circuit 52 receives a transfer request from the CPU 2 (YES in step S206), the adjustment circuit 52 detects the transfer state of the log data by the transfer circuit 51. The transfer request received from the CPU 2 includes the start address of the transfer source log buffer and the amount of data in the log buffer 4.

  When the transfer circuit 51 is not transferring the log data of the CPU 1 (NO in step S207), the process proceeds to step S209. On the other hand, when the transfer circuit 51 is transferring the log data of the CPU 1 (YES in step S207), the adjustment circuit 52 waits until the transfer of the log data of the CPU 1 is completed (step S208).

  Subsequently, the adjustment circuit 52 transmits a log data transfer instruction of the CPU 2 to the transfer circuit 51 (step S209). The adjustment circuit 52 generates a transfer instruction based on the transfer request received from the CPU 2. The transfer instruction transmitted by the adjustment circuit 52 includes the start address of the transfer source log buffer and the data amount in the log buffer 4.

  When receiving the transfer instruction from the adjustment circuit 52, the transfer circuit 51 transfers the log data of the CPU 2 based on the received transfer instruction (step S210). That is, the transfer circuit 51 reads the transfer target log data from the transfer source log buffer of the log buffer 4 specified by the transfer instruction, and writes the read log data to the external storage medium 6. Thereby, the log data of the CPU 2 is stored in the external storage medium 6.

  The transfer control circuit 5 repeats the processes of steps S201 to S210 until the storage process ends (NO in step S211).

  FIG. 5 is a timing chart showing a specific example of the storage process. In the example of FIG. 5, at time T1, the CPU 1 transmits a transfer request (step S104). When the adjustment circuit 52 receives this transfer request (YES in step S201), the adjustment circuit 52 detects the transfer state of the transfer circuit 51. At time T1, the transfer circuit 51 does not transfer log data (NO in step S202), and therefore the adjustment circuit 52 transmits a log data transfer instruction of the CPU 1 to the transfer circuit 51 (step S204). In accordance with this transfer instruction, the transfer circuit 51 transfers the log data of the CPU 1 to the external storage medium 6 (step S205).

  Next, at time T2, the CPU 2 transmits a transfer request (step S104). When the adjustment circuit 52 receives this transfer request (YES in step S206), the adjustment circuit 52 detects the transfer state of the transfer circuit 51. At time T2, since the transfer circuit 51 is not transferring log data (NO in step S207), the adjustment circuit 52 transmits a log data transfer instruction of the CPU 2 to the transfer circuit 51 (step S209). In accordance with this transfer instruction, the transfer circuit 51 transfers the log data of the CPU 2 to the external storage medium 6 (step S210).

  Subsequently, at time T3, the CPU 1 transmits a transfer request. When the adjustment circuit 52 receives this transfer request (YES in step S201), the adjustment circuit 52 detects the transfer state of the transfer circuit 51. At time T3, the transfer circuit 51 transfers the log data of the CPU 2 (YES in step S202). For this reason, the adjustment circuit 52 waits until the transfer of the log data is completed (step S203), and transmits a log data transfer instruction of the CPU 1 to the transfer circuit 51 at time T4 (step S204). In accordance with this transfer instruction, the transfer circuit 51 transfers the log data of the CPU 1 to the external storage medium 6 (step S205).

  As can be seen from FIG. 5, by adjusting the timing at which the adjustment circuit 52 transmits the transfer instruction, the transfer processing of the log data of the CPUs 1 and 2 is adjusted so as not to overlap.

  According to the conventional storage method, the CPUs 1 and 2 need to read log data of other CPUs or write log data of other CPUs to an external storage device in order to save log data. . On the other hand, according to the present embodiment, transfer of log data of the CPUs 1 and 2 is performed by the transfer control circuit 5. Therefore, according to the present embodiment, it is possible to reduce the load on the CPU (processor) due to the log data saving process, as compared with the conventional saving method.

  In the conventional storage method, the CPU connected to the external storage device needs to monitor the operation state of the other log data in order to read the log data of the other CPU. On the other hand, according to the present embodiment, the adjustment of the transfer period of the log data is performed by the adjustment circuit 52, so that the CPUs 1 and 2 do not need to monitor each other's operation state. Therefore, according to the present embodiment, it is possible to further reduce the load on the CPUs 1 and 2 in the storage process as compared with the conventional storage method.

Second Embodiment
An electronic apparatus according to the second embodiment will be described with reference to FIG. The configuration of the electronic device according to the present embodiment is the same as that of the first embodiment.

  FIG. 6 is a flowchart showing an example of the operation (write process) of the CPUs 1 and 2 in the storage process of the present embodiment. The operation of FIG. 6 is the same as that of FIG. 2 except for step S104. Hereinafter, the operation of FIG. 6 will be described using the CPU 1 as an example.

  In the present embodiment, the CPU 1 transmits a transfer request including the start address of the transfer source log buffer, the data amount of the transfer source log buffer, and the transfer request transmission time (step S104).

  The adjustment circuit 52 that has received this transfer request transmits to the transfer circuit 51 a transfer instruction including the start address, data amount, and transmission time included in the transfer request received from the CPU 1. The transfer circuit 51 that has received this transfer instruction writes the log data of the CPU 1 stored in the transfer source log buffer to the external storage medium 6 in association with the transmission time included in the transfer instruction.

  As described above, according to the present embodiment, the log data of the CPUs 1 and 2 is written to the external storage medium 6 in association with the transmission time of the transfer request. As a result, the time series of the log data stored in the external storage medium 6 can be easily grasped, and the debugging analysis man-hours can be reduced.

<Third Embodiment>
An electronic apparatus according to the third embodiment will be described with reference to FIG. In this embodiment, an image forming apparatus will be described as an example of an electronic apparatus. FIG. 7 is a diagram illustrating an example of a hardware configuration of the image forming apparatus according to the present embodiment.

  7 includes a developing device 11, a transfer device 12, a memory 13, a transport device 21, a fixing device 22, a memory 23, a controller 7, an operation panel 71, a communication device 72, And a memory 73. Other configurations are the same as those of the first embodiment.

  The CPU 1 serves as an engine control unit that controls part of the engine (device) of the image forming apparatus (the developing device 11 and the transfer device 12). The developing device 11 is a laser or toner supply device. The developing device 11 develops an image on the photosensitive drum by generating a latent image on the photosensitive drum with a laser and supplying toner to the latent image. The transfer device 12 is a photosensitive drum or the like. The transfer device 12 transfers the image developed on the photosensitive drum to a document. The memory 13 stores a program for the CPU 1 to control the developing device 11 and the transfer device 12, a program for executing log data saving processing, and the like.

  The CPU 2 serves as an engine control unit that controls part of the engine (device) of the image forming apparatus (the conveyance device 21 and the fixing device 22). The transport device 21 transports a document. The fixing device 22 is a toner fixing roller or the like. The fixing device 22 fixes the image transferred to the document. The memory 23 stores a program for the CPU 2 to control the conveyance device 21 and the fixing device 22 and a program for executing a log data saving process.

  The controller 7 is a processor that controls the entire image forming apparatus. The operation panel 71 is an input / output device of an image forming apparatus that includes a touch panel, push buttons, a display, and the like. Based on the information input from the operation panel 71, the controller 7 controls the image forming apparatus. The communication device 72 is a device for communicating with an external device by wire or wireless. The image forming apparatus communicates with an external server or the like via the communication device 72. The memory 73 stores a program executed by the controller 7 and the like.

  In the image forming apparatus according to this embodiment, the CPU 1 controls the developing device 11 and the transfer device 12, and the CPU 2 controls the transport device 21 and the fixing device 22, thereby printing an image on a document. When printing an image, the CPUs 1 and 2 operate asynchronously. During operation of the CPUs 1 and 2, the log data of the CPUs 1 and 2 are transferred to the external storage medium 6 by the transfer control system (log buffers 3 and 4 and the transfer control circuit 5).

  Therefore, the image forming apparatus according to the present embodiment can print an image on a document while reducing the load on the CPUs 1 and 2 due to log data storage processing. Further, based on the log data of the CPUs 1 and 2 stored in the external storage medium 6, it is possible to analyze the cause of a problem that has occurred during image printing.

  The electronic apparatus is not limited to the image forming apparatus, and can be any apparatus including a plurality of processors. For example, the electronic device may be a printer device, a scanner device, a fax device, an electronic information board, a digital camera, or the like.

  It should be noted that the present invention is not limited to the configuration shown here, such as a combination with other elements in the configuration described in the above embodiment. These points can be changed without departing from the spirit of the present invention, and can be appropriately determined according to the application form.

1, 2: CPU
3, 4: Log buffer 5: Transfer control circuit 6: External storage medium 7: Controller 11: Developing device 12: Transfer device 13: Memory 21: Transport device 22: Fixing device 23: Memory 51: Transfer circuit 52: Adjustment circuit 71 : Operation panel 72: Communication device 73: Memory

JP2013-134518A

Claims (7)

A plurality of storage media to which log data is written from different processors;
A transfer control circuit for transferring the log data stored in the plurality of storage media to an external storage medium at a predetermined timing;
A data transfer system comprising: The data transfer system according to claim 1, wherein the transfer control circuit transfers the log data so that transfer periods of the log data do not overlap. The data transfer system according to claim 1, wherein the transfer control circuit transfers the log data based on a transfer request from the processor. The data transfer system according to claim 3, wherein the transfer request includes a start address of a storage area where the log data is stored in the storage medium, and a data amount of the log data. The data transfer system according to claim 4, wherein the transfer control circuit writes the log data in the external storage medium in association with a transmission time of the transfer request. A plurality of the processors that respectively write the log data to the plurality of storage media;
The data transfer system according to any one of claims 1 to 5,
An electronic device comprising: A plurality of the processors that respectively write the log data to the plurality of storage media;
The data transfer system according to any one of claims 1 to 5,
An image forming apparatus comprising:

Images