JP2017200097A - Signal source - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal source which does not require a filter having steep characteristics in a high frequency band.SOLUTION: The signal source includes: an oscillator for outputting a signal of a frequency corresponding to a control signal; a first frequency conversion circuit for generating a first signal synchronously with a reference signal; a first mixer for inputting a plurality of signals synchronized with the reference signal, mixing the plurality of signals and performing frequency conversion of the mixed signal; a second mixer for mixing the signal frequency-converted by the first mixer with the signal outputted from the oscillator and performing frequency conversion of the mixed signal; a phase frequency comparator for detecting a phase difference between the first signal generated by the first frequency conversion circuit and the signal frequency-converted by the second mixer and outputting a signal corresponding to the phase difference; and a loop filter for suppressing spurious included in the signal outputted from the phase frequency comparator by using transmission characteristics of a closed loop together with the oscillator, the second mixer and the phase frequency comparator and outputting the spurious-suppressed signal to the oscillator as a control signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a signal source used in a radio communication apparatus or a radar system.

  The signal source is a circuit capable of generating a signal having an arbitrary signal waveform or an arbitrary frequency. For example, as shown in Patent Document 1, the signal source is configured using a PLL (Phase Locked Loop) circuit, a DDS (Direct Digital Synthesizer), or the like.

  The PLL circuit includes a voltage controlled oscillator (VCO: Voltage Controlled Oscillator), a frequency divider, an LF (Loop Filter), a phase frequency comparator (PFD: Phase Frequency Detector), a reference signal source, and an output of the divided VCO. The circuit compares the phase of the signal with the phase of the reference signal source and feeds back a current or voltage corresponding to the error to the VCO through the LF, thereby stabilizing the oscillation frequency of the VCO.

FIG. 12 is a configuration diagram showing the configuration of the signal source in Patent Document 1. In FIG.
The signal source of Patent Document 1 is provided with a mixer 108 in a feedback path of a PLL circuit in a DDS drive PLL in which a DDS 102 and a PLL circuit are connected in series in order to correspond to different reference signal frequencies, and a frequency divider 110 and a mixer The reference signal is frequency-converted by 111 to be a LO (Local Oscillator) wave of the mixer 108. Regardless of the output frequency of the reference signal source 101, this signal source can be any reference signal frequency by making the frequency of the output signal of the DDS 102 and the frequency of the output signal of the filter 112 substantially constant. A constant frequency fout is output.

  However, in the conventional signal source, the output signal of the mixer 111 that performs frequency conversion of the reference signal is in a high frequency band, and spurious is generated in the frequency near the desired signal due to frequency mixing. A steep characteristic is required in the band. In order to realize such a filter, there is a disadvantage that an excessive amount of hardware and an increase in cost are caused.

Japanese Patent No. 5523135

  As described above, the conventional signal source requires a filter having a steep characteristic in a high frequency band, and there is a problem that the amount of hardware and cost are excessively increased in order to realize such a filter. .

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a signal source that does not require a filter having steep characteristics in a high frequency band.

  The signal source of the present invention includes an oscillator that outputs a signal having a frequency according to a control signal, a first frequency conversion circuit that generates a first signal in synchronization with the reference signal, and a plurality of signals that are synchronized with the reference signal A first mixer that receives a signal, mixes a plurality of signals and performs frequency conversion, and mixes a frequency converted by the first mixer and a signal output from the oscillator to perform frequency conversion. A phase frequency comparator for detecting a phase difference between the first signal generated by the mixer and the first signal generated by the first frequency conversion circuit and the signal converted by the second mixer, and outputting a signal corresponding to the phase difference; In addition to the oscillator, the second mixer, and the phase frequency comparator, the spurious contained in the output signal of the phase frequency comparator is suppressed using the closed loop transfer characteristics, and the signal with the spurious suppressed is used as a control signal for the oscillator. Loop fill to output Provided with a door.

  According to the present invention, it is possible to provide a signal source that does not require a filter having a steep characteristic in a high frequency band.

It is a block diagram which shows one structural example of the signal source which concerns on Embodiment 1 of this invention. It is a block diagram which shows one structural example of the frequency converter circuit 2 which concerns on Embodiment 1 of this invention. It is a block diagram which shows one structural example of the frequency converter circuit 3 which concerns on Embodiment 1 of this invention. It is a block diagram which shows one structural example of the frequency converter circuit 4 which concerns on Embodiment 1 of this invention. It is a figure which shows the frequency spectrum of the output signal of the mixer 5 which concerns on Embodiment 1 of this invention. It is a figure which shows the frequency spectrum of the output signal of the mixer 9 which concerns on Embodiment 1 of this invention. It is a figure which shows the frequency spectrum of the output signal of the filter 10 which concerns on Embodiment 1 of this invention. It is a figure which shows the frequency spectrum of the output signal of PFD6 which concerns on Embodiment 1 of this invention. It is a figure which shows the frequency spectrum of the output signal of LF7 which concerns on Embodiment 1 of this invention. It is a block diagram which shows the other structural example of the signal source which concerns on Embodiment 1 of this invention. It is a block diagram which shows the other structural example of the signal source which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the signal source in patent document 1. FIG.

Embodiment 1.
1 is a block diagram showing an example of the configuration of a signal source according to Embodiment 1 of the present invention.
This signal source includes a reference signal source 1, a frequency conversion circuit 2 (an example of a first frequency conversion circuit), a frequency conversion circuit 3, a frequency conversion circuit 4, a mixer 5 (an example of a first mixer), and a PFD 6 (a phase). An example of a frequency comparator), LF7 (an example of a loop filter), a VCO 8 (an example of an oscillator), a mixer 9 (an example of a second mixer), and a filter 10. In FIG. 1, fCLK is the frequency of the reference signal output from the reference signal source 1, f1 is the frequency of the signal output from the frequency conversion circuit 2, and f2 is the frequency of the signal output from the frequency conversion circuit 3. , F3 is the frequency of the signal output from the frequency conversion circuit 4, and fout is the frequency of the signal output from the VCO 8.

  The reference signal source 1 is an oscillator that outputs a reference signal of this signal source. The output terminal of the reference signal source 1 is connected to the input terminal of the frequency conversion circuit 2, the input terminal of the frequency conversion circuit 3, and the input terminal of the frequency conversion circuit 4. The reference signal source 1 oscillates at fCLK and outputs the output signal to the frequency conversion circuit 2, the frequency conversion circuit 3, and the frequency conversion circuit 4. The reference signal source 1 may be an oscillator having any configuration as long as it is an oscillator that can output an accurate frequency. For example, the reference signal source 1 is a crystal oscillator or a PLL circuit that can output an accurate frequency.

  The frequency conversion circuit 2 is a frequency conversion circuit that generates a signal having a frequency f1 in synchronization with a reference signal input from the outside. The input terminal of the frequency conversion circuit 2 is connected to the output terminal of the reference signal source 1, and the output terminal of the frequency conversion circuit 2 is connected to the reference signal input terminal of the PFD 6. The frequency conversion circuit 2 generates a signal having a frequency f1 different from the reference signal in synchronization with the reference signal output from the reference signal source 1, and outputs the signal to the PFD 6. For example, the frequency conversion circuit 2 can be a DDS, a frequency divider, or a mixer. Furthermore, a DDS, a frequency divider, and a mixer may be used in combination, or a plurality of them may be used. When DDS is used for the frequency conversion circuit 2, frequency control data is input from the outside, and when a mixer is used, LO waves are input from the outside. Here, the frequency control data is digital data indicating the output frequency of the DDS. The frequency f1 may be the same as the frequency fCLK of the reference signal. In this case, the frequency conversion circuit 2 is a through line.

FIG. 2 is a block diagram showing a configuration example of the frequency conversion circuit 2 according to the first embodiment of the present invention.
In FIG. 2, the DDS 11 is used as the frequency conversion circuit 2.

  The DDS 11 is a circuit that generates a continuous signal of a sine wave having a frequency f1 using the reference signal output from the reference signal source 1 as a clock. For example, the DDS 11 includes an adder, a latch, a ROM, and a DAC. The clock terminal of the DDS 11 is connected to the output terminal of the reference signal source 1 through the input terminal of the frequency conversion circuit 2, and the output terminal of the DDS 11 is connected to the reference signal input terminal of the PFD 6 through the output terminal of the frequency conversion circuit 2. Connected. The DDS 11 generates a signal having a frequency f1 in synchronization with the clock signal from the reference signal source 1, and outputs the signal to the PFD 6.

  The output signal of the DDS 11 includes, in addition to the signal of the frequency f1, harmonics having a component that is an integral multiple of the frequency of f1, or spurious image waves of harmonics that are folded back in the first Nyquist zone. Although not shown in FIG. 2, a filter for suppressing spurious output from the DDS 11 may be provided between the output terminal of the DDS 11 and the reference signal input terminal of the PFD 6.

  The frequency conversion circuit 3 is a frequency conversion circuit that generates a signal having a frequency f2 in synchronization with a reference signal input from the outside. The input terminal of the frequency conversion circuit 3 is connected to the output terminal of the reference signal source 1, and the output terminal of the frequency conversion circuit 3 is connected to the first input terminal (LO terminal) of the mixer 5. The frequency conversion circuit 3 generates a signal having a frequency f 2 different from the reference signal in synchronization with the reference signal output from the reference signal source 1 and outputs the signal to the mixer 5. For example, the frequency conversion circuit 3 can be a DDS, a frequency divider, or a mixer. Furthermore, a DDS, a frequency divider, and a mixer may be used in combination, or a plurality of them may be used. When DDS is used for the frequency conversion circuit 3, frequency control data is input from the outside, and when a mixer is used, LO waves are input from the outside. The frequency f2 may be the same as the frequency fCLK of the reference signal. In this case, the frequency conversion circuit 3 is a through line.

FIG. 3 is a configuration diagram showing one configuration example of the frequency conversion circuit 3 according to the first embodiment of the present invention.
In FIG. 3, a frequency divider 21 is used as the frequency conversion circuit 3.

  The frequency divider 21 is a frequency divider that divides the frequency of the input signal by A and outputs the divided signal. A is an integer of 2 or more. The input terminal of the frequency divider 21 is connected to the output terminal of the reference signal source 1 via the input terminal of the frequency conversion circuit 3, and the output terminal of the frequency divider 21 is connected to the mixer via the output terminal of the frequency conversion circuit 3. 5 is connected to the first input terminal (LO terminal). For the frequency divider 21, for example, a field-programmable gate array (FPGA) that can perform high-speed digital signal processing can be used. The frequency divider 21 may have any configuration as long as it can output a signal having a frequency 1 / A of the frequency of the input signal, and may be a fixed frequency divider or a variable frequency divider. When the frequency divider 21 is a variable frequency divider, the frequency of the input signal is divided by A in accordance with a control signal indicating the frequency division number input from the outside.

  The frequency conversion circuit 4 is a frequency conversion circuit that generates a signal having a frequency f3 in synchronization with a reference signal input from the outside. The input terminal of the frequency conversion circuit 4 is connected to the output terminal of the reference signal source 1, and the output terminal of the frequency conversion circuit 4 is connected to the second input terminal (IF terminal) of the mixer 5. The frequency conversion circuit 4 generates a signal having a frequency f3 different from the reference signal in synchronization with the reference signal output from the reference signal source 1, and outputs the signal to the mixer 5. For example, the frequency conversion circuit 4 can be a DDS, a frequency divider, or a mixer. Furthermore, a DDS, a frequency divider, and a mixer may be used in combination, or a plurality of them may be used. When DDS is used for the frequency conversion circuit 4, frequency control data is input from the outside, and when a mixer is used, LO waves are input from the outside. The frequency f3 may be the same as the frequency fCLK of the reference signal. In this case, the frequency conversion circuit 4 is a through line.

FIG. 4 is a configuration diagram showing a configuration example of the frequency conversion circuit 4 according to the first embodiment of the present invention.
In FIG. 4, a frequency divider 31 is used as the frequency conversion circuit 4.

  The frequency divider 31 is a frequency divider that divides the frequency of the input signal by B and outputs the divided signal. B is an integer of 2 or more. The input terminal of the frequency divider 31 is connected to the output terminal of the reference signal source 1 via the input terminal of the frequency conversion circuit 4, and the output terminal of the frequency divider 31 is connected to the mixer via the output terminal of the frequency conversion circuit 4. 5 to the second input terminal (IF terminal). For the frequency divider 31, for example, an FPGA capable of performing digital signal arithmetic processing at high speed can be used. The frequency divider 31 may have any configuration as long as it can output a signal having a frequency 1 / B of the frequency of the input signal, and may be a fixed frequency divider or a variable frequency divider. When the frequency divider 31 is a variable frequency divider, the frequency of the input signal is divided according to a signal indicating the frequency division number input from the outside.

  The mixer 5 is a mixer that mixes two input signals and outputs the mixed signal. The first input terminal (LO terminal) of the mixer 5 is connected to the output terminal of the frequency conversion circuit 3, and the second input terminal (IF terminal) of the mixer 5 is connected to the output terminal of the frequency conversion circuit 4, and the mixer 5 The output terminal (RF terminal) 5 is connected to the first input terminal (RF terminal) of the mixer 9. The mixer 5 performs frequency conversion by mixing the signal output from the frequency conversion circuit 3 and the signal output from the frequency conversion circuit 4, and outputs the frequency-mixed mixed signal to the mixer 9. For example, the mixer 5 is a diode mixer that performs mixing using the nonlinearity of the diode.

  The PFD 6 is a PFD that compares the phases of two input signals and outputs a signal corresponding to the phase difference. The reference signal input terminal of the PFD 6 is connected to the output terminal of the frequency conversion circuit 2, the synchronization signal input terminal of the PFD 6 is connected to the output terminal of the filter 10, and the output terminal of the PFD 6 is connected to the input terminal of LF7. . For example, a mixer can be used for the PFD 6.

  The LF 7 is a filter that smoothes the signal output from the PFD 6 and outputs it to the VCO 8 as a control voltage. The input terminal of LF7 is connected to the output terminal of PFD6, and the output terminal of LF7 is connected to the input terminal of VCO8. For example, the LF 7 uses a low-pass filter composed of a capacitor and a resistor. The LF 7 may use a filter incorporating an operational amplifier in accordance with a required gain.

  The VCO 8 is an oscillator that controls the oscillation frequency by a control voltage. The input terminal of the VCO 8 is connected to the output terminal of the LF 7, and the output terminal of the VCO 8 is connected to the second input terminal (LO terminal) of the mixer 9 and the output terminal of this signal source. For the VCO 8, for example, an oscillator that changes the oscillation frequency with a variable capacitance diode is used. The variable capacitance diode changes its capacitance according to the applied voltage. As a result, the resonance frequency of the resonance circuit including the variable capacitance diode changes, and the oscillation frequency changes.

  The mixer 9 is a mixer that mixes two input signals and outputs the mixed signal. The first input terminal (RF terminal) of the mixer 9 is connected to the output terminal (RF terminal) of the mixer 5, and the second input terminal (LO terminal) of the mixer 9 is connected to the output terminal of the VCO 8, and the mixer The output terminal (IF terminal) 9 is connected to the input terminal of the filter 10. The mixer 9 performs frequency conversion by mixing the signal output from the VCO 8 and the signal output from the mixer 5, and outputs the frequency-converted mixed signal to the filter 10. For example, the mixer 9 is a diode mixer that performs mixing using the nonlinearity of the diode. The mixer 9 is for lowering the frequency of the signal output from the VCO 8, and therefore, instead of the mixer 9 or in the mixer 9 in the PLL feedback path from the output terminal of the VCO 8 to the input terminal of the filter 10. In addition, a frequency converter that further reduces the frequency may be provided. For example, a mixer or a frequency divider is used for the frequency converter.

  The filter 10 is a filter that has a predetermined pass band, passes signals that are within the pass band among input signals, and suppresses signals that are in a frequency band outside the pass band. The input terminal of the filter 10 is connected to the output terminal (IF terminal) of the mixer 9, and the output terminal of the filter 10 is connected to the synchronization signal input terminal of the PFD 6. For example, the filter 10 is mounted using a chip inductor, a chip capacitor, or the like. Further, the filter 10 may be configured using a microstrip resonator, a resonator such as a coaxial resonator, or the like according to a frequency band to be passed and a necessary suppression amount.

Next, the operation of the signal source according to Embodiment 1 of the present invention will be described.
First, the reference signal source 1 outputs a reference signal having a frequency fCLK to the frequency conversion circuit 2, the frequency conversion circuit 3, and the frequency conversion circuit 4, respectively.

  Since the frequency conversion circuit 2 is composed of the DDS 11, the DDS 11 is synchronized with the reference signal output from the reference signal source 1, and generates a signal of the frequency f1 based on the frequency control data input from the outside. , Output to PFD6. Therefore, the frequency f1 is substantially constant regardless of the frequency fCLK of the reference signal. The frequency f1 can be changed according to the frequency control data.

  Since the frequency conversion circuit 3 is composed of the frequency divider 21, the frequency of the reference signal output from the reference signal source 1 is divided by A to generate a signal of frequency fCLK / A and output to the mixer 5. Therefore, f2 = fCLK / A. A is generally an integer of 2 or more, but if A is 1, it is the same as bypassing the frequency divider 21.

  Since the frequency conversion circuit 4 is configured by the frequency divider 31, the frequency of the reference signal output from the reference signal source 1 is divided by B to generate a signal of frequency fCLK / B and output it to the mixer 5. Therefore, f3 = fCLK / B. Note that B is generally an integer equal to or greater than 2, but if B is 1, it is the same as bypassing the frequency divider 31.

  The mixer 5 mixes the signal of the frequency f2 output from the frequency conversion circuit 3 and the signal of the frequency f3 output from the frequency conversion circuit 4, and outputs the mixed signal to the mixer 9. Generally, if two frequencies input to the mixer are fin1 and fin2, the output frequency can be expressed by the following equations (1) and (2).

  Here, m and n are positive integers. In the mixer 5, the two input frequencies are f2 and f3, and the frequency of the desired signal is f2 + f3. However, from the equations (1) and (2), the output signal of the mixer 5 includes a number of spurious signals in addition to the desired signal. Hereinafter, in order to simplify the description, the spurious included in the output signal of the mixer 5 is a spurious represented by n = 1 or 2 and m = 1 in the equations (1) and (2).

FIG. 5 is a diagram showing the frequency spectrum of the output signal of the mixer 5 according to Embodiment 1 of the present invention.
The horizontal axis is frequency, and the vertical axis is power. In addition to a desired signal of frequency f2 + f3 (hereinafter referred to as an RF signal), the mixer 5 has a frequency | f2-f3 | (hereinafter referred to as SP1) and a frequency f2 + 2f3 (hereinafter referred to as SP2) as spurious. , Frequency | f2-2f3 | (hereinafter referred to as SP3) is output. The output signal of the mixer 5 is in a high frequency band, and spurious exists near the frequency of the desired signal.

  Note that the frequency of the output signal of the mixer 5 is substantially constant regardless of the frequency fCLK of the reference signal and is synchronized with the reference signal. Further, the frequency f2 + f3 of the output signal of the mixer 5 is different from the frequency fout of the output signal of the VCO 8.

  The mixer 9 mixes the signal of the frequency fout output from the VCO 8 and the output signal of the mixer 5 including spurious signals, and outputs the mixed signal to the filter 10. The output frequency of the mixer 9 can be expressed by using fin2 as the RF signal output from the mixer 5, the frequency of SP1, SP2, or SP3 and fin1 as fout in the equations (1) and (2). Similarly to the mixer 5, the mixer 9 also includes a large number of spurious signals in the output signal. Hereinafter, in order to simplify the description, the spurious included in the output signal of the mixer 9 is a spurious represented by n = m = 1 in the equation (2).

FIG. 6 is a diagram showing a frequency spectrum of the output signal of the mixer 9 according to Embodiment 1 of the present invention.
The horizontal axis is frequency, and the vertical axis is power. In addition to the desired signal of frequency | f2 + f3-fout | (hereinafter referred to as the desired signal of mixer 9), mixer 9 has a frequency || f2-f3 | -fout | (mixed signal of SP1 and fout) as spurious. ), Frequency | f2 + 2f3-fout | (mixed signal of SP2 and fout), || f2-2f3 | -fout | (mixed signal of SP3 and fout). The spurious output from the mixer 5 exists in the vicinity of the desired signal of the mixer 9 due to the mixing in the mixer 9.

  The filter 10 suppresses spurious signals existing outside the pass band of the filter 10 from the output signal of the mixer 9 and outputs the result to the PFD 6. The filter 10 is a low pass filter. Although omitted here for the sake of simplicity, the output signal of the mixer 9 includes many spurious signals over a wide band in addition to the spurious signal shown in FIG. The filter 10 is provided in order to prevent malfunction caused by inputting a large number of spurious signals to the PFD 6 and failure caused by inputting high power spurious signals. The filter 10 only needs to suppress a large number of spurious signals in the high-frequency band by allowing the low-frequency band signal to pass therethrough, so that a steep characteristic is not necessary.

FIG. 7 is a diagram showing the frequency spectrum of the output signal of the filter 10 according to Embodiment 1 of the present invention.
The horizontal axis is frequency, and the vertical axis is power. The output signal of the filter 10 includes a spurious signal having a frequency | f2 + 2f3-fout | (hereinafter referred to as SP4). Since the power level of SP4 is lower than that of the output signal of the filter 10, the PFD 6 Does not cause malfunction.

  The PFD 6 compares the phase of the signal of the frequency f1 output from the frequency conversion circuit 1 with the phase of the signal output from the filter 10, and outputs a control signal corresponding to the phase difference to the LF7. In the present embodiment, it is assumed that PFD 6 is a mixer. The output frequency of the PFD 6 can be expressed by using fin1 as f1 and fin2 as the output signal of the filter 10 or the frequency of SP4 in the equations (1) and (2). Hereinafter, in order to simplify the description, the spurious included in the output signal of the PFD 6 is a spurious represented by n = m = 1 in the equation (2).

FIG. 8 is a diagram showing a frequency spectrum of the output signal of the PFD 6 according to Embodiment 1 of the present invention.
The horizontal axis is frequency, and the vertical axis is power. When phase synchronization is established in the two signals input to the PFD 6, since the frequencies of the two signals are equal, the output signal of the PFD 6 has a frequency of 0 (DC). In addition, a spurious signal having a frequency of || f2 + 2f3-fout | -f1 | (hereinafter referred to as SP5), which is a mixed signal of f1 and SP4, is included. SP5 to be suppressed by the closed loop transfer characteristic is a spurious closest to DC.
In the signal source of the present embodiment, the path that returns from the PFD 6 to the PFD 6 via the LF 7, VCO 8, mixer 9, and filter 10 forms a PLL circuit. Here, the closed loop transfer function of the PLL circuit is expressed by the following equation (3).

Here, K _p is the detection sensitivity of the PFD6, the phase difference of the two input signals is an indicator indicating whether voltage or current degree varying output upon changing 1 rad. The unit is V / rad when the PFD 6 is a voltage output type PFD, and A / rad when the PFD 6 is a current output type PFD. F (s) is a transfer function of LF7, and s is a complex frequency. K _v is the tuning sensitivity of the VCO 8, the voltage input is an index indicating how much change the frequency to be output upon 1V changed. The unit is Hz / V. N is the frequency dividing number of the frequency divider in the feedback path of the PLL circuit. In the case of the configuration shown in FIG. 1, N = 1.

  From Equation (3), the closed-loop transfer function of the PLL circuit has a transfer characteristic equivalent to that of the low-pass filter. In the present embodiment, the spurious SP5 generated by the mixer 5 and frequency-converted by the mixer 9 and the PFD 6 is suppressed using the closed-loop transfer characteristic of the PLL circuit.

As a method of suppressing SP5 by the transfer function represented by Expression (3), for example, there is a method of making the 3 dB band of the transfer function represented by Expression (3) smaller than the frequency of SP5. The 3 dB band is a frequency bandwidth from a frequency at which the gain becomes the maximum value to a frequency at which the gain decreases by 3 dB. At this time, if the frequency of _SP5 is set to _fSP5 , the following formula (4) is established.

SP5 is suppressed by determining the detection sensitivity of PFD 6, the transfer function of LF 7 and the tuning sensitivity of VCO 8 so as to satisfy equation (4).

  The LF 7 smoothes the voltage signal (control voltage) output from the PFD 6 and outputs the voltage signal to the VCO 8. The VCO 8 oscillates at the frequency fout based on the voltage signal output from the LF 7, outputs it as an output signal from the output terminal, and outputs the output signal to the mixer 9.

FIG. 9 is a diagram showing a frequency spectrum of the output signal of the LF 7 according to Embodiment 1 of the present invention.
The horizontal axis is frequency, and the vertical axis is power. By making the 3 dB band of the closed loop transfer function of the PLL circuit lower than the frequency of the spurious SP5, SP5 can be suppressed.

  For example, when a low-pass filter including a capacitor and a resistor is used as LF7, the transfer function F (s) can be changed by changing the capacitance value, the resistance value, and the order of the filter. Similarly, when a mixer is used as the PFD 6, the detection sensitivity can be changed by changing the diode to be used, and the VCO 8 can change the tuning sensitivity by changing the variable capacitance diode. These can be easily performed without excessively increasing the amount of hardware. The characteristics of the loop filter are determined by characteristics required for the PLL circuit, such as the frequency switching time, and the closed-loop transfer characteristics are determined so that the spurious closest to DC can be suppressed.

  For example, in general, when a high-speed frequency switching time is realized, the cutoff frequency of the loop filter is increased. This is because the cutoff frequency and the time constant are in an inversely proportional relationship, so that the larger the cutoff frequency, the smaller the time constant and the shorter the time required for switching. When the switching time is shortened, the spurious frequency becomes smaller than the cut-off frequency of the loop filter, and the output signal includes spurious. Even in such a case, in this signal source, the closed-loop transfer characteristic is determined so that the spurious can be suppressed, so that both high-speed frequency switching time and low spurious can be achieved.

  As described above, according to the first embodiment, since the spurious included in the output signal of the mixer 5 is suppressed by the closed loop transmission characteristic of the PLL circuit, a steep characteristic in the high frequency band is provided between the mixer 5 and the mixer 9. There is no need to provide a band-pass filter. Thereby, it is possible to realize a signal source that does not cause an excessive increase in hardware amount and cost.

In the above description, the frequency f2 + f3 component of the output signal of the mixer 5 is the desired signal, but other frequency components generated by frequency mixing may be used as the desired signal.
Similarly, the component of frequency | f2 + f3-fout | of the output signal of mixer 9 is the desired signal, but other frequency components generated by frequency mixing may be used as the desired signal.

  Moreover, although the component of the frequency f1 is made into the desired signal among the outputs of DDS11, the other signal produced from DDS11 may be made into a desired signal, and you may make it provide the filter which passes a desired signal.

  The frequency conversion circuit 2, the frequency conversion circuit 3, and the frequency conversion circuit 4 use the output signal of the reference signal source 1 having the frequency fCLK as an input signal, but input a signal synchronized with the output signal of the reference signal source 1 from the outside. You may do it. Further, the output signal of the VCO 8 may be used as the input signal of the frequency conversion circuit 2.

FIG. 10 is a block diagram showing another configuration example of the signal source according to Embodiment 1 of the present invention.
Compared with FIG. 1, the frequency conversion circuit 4 is deleted, and the output signal (f1) of the frequency conversion circuit 2 is used instead of the output signal (f3) of the frequency conversion circuit 4. The mixer 5 performs frequency conversion by mixing the f1 signal obtained by frequency conversion of fCLK and the f2 signal, and outputs the frequency converted signal to the mixer 9. The operation after the mixer 9 is the same as in FIG. In the configuration of FIG. 10, compared with FIG. 1, the frequency conversion circuit 4 is not necessary, so that there is an effect that the size can be reduced and the power consumption can be reduced.

FIG. 11 is a block diagram showing another example of the signal source according to Embodiment 1 of the present invention. FIG. 11 shows a configuration in which a frequency divider 41 is inserted between the mixer 5 and the mixer 9 as compared with FIG.
The frequency divider 41 has an effect of lowering the level of spurious included in the input signal by 20 log ₁₀ (B), where B is a frequency division number (B is a positive natural number). That is, the frequency divider 41 reduces spurious without reducing the level of the desired signal. This is a reverse utilization of the characteristic that the phase noise and the spurious increase by 20 log ₁₀ (X) when the frequency is multiplied by X due to the frequency multiplication effect at the frequency near the desired signal. By providing the frequency divider 41, the level ratio between the desired signal and spurious can be improved by 20 log ₁₀ (B). Therefore, the level of spurious included in the output signal of the mixer 5 can be lowered, and a signal with reduced spurious can be input to the mixer 9. For this reason, in the PFD 6 to which the output signal of the mixer 9 is input, there is an effect that the spurious level of the output signal of the PFD 6 can be lowered.

1 reference signal source, 2 frequency conversion circuit, 3 frequency conversion circuit, 4 frequency conversion circuit, 5 mixer, 6 PFD, 7 LF, 8 VCO, 9 mixer, 10 filter, 11 DDS, 21 frequency divider, 31 frequency divider, 41 divider, 101 reference signal source, 102 DDS, 103 filter, 104 divider, 105 PFD, 106 LF, 107 VCO, 108 mixer, 109 filter, 110 divider, 111 mixer, 112 filter.

Claims (5)

An oscillator that outputs a signal having a frequency according to the control signal;
A first frequency conversion circuit that generates a first signal in synchronization with a reference signal;
A plurality of signals synchronized with the reference signal, a first mixer that mixes the plurality of signals and performs frequency conversion;
A second mixer that mixes the frequency-converted signal of the first mixer and the signal output from the oscillator and converts the frequency;
A phase frequency comparator that detects a phase difference between the first signal generated by the first frequency conversion circuit and a signal frequency-converted by the second mixer, and outputs a signal corresponding to the phase difference; ,
Together with the oscillator, the second mixer, and the phase frequency comparator, using a closed loop transfer characteristic, the spurious contained in the output signal of the phase frequency comparator is suppressed, and the signal with the spurious suppressed is A loop filter that outputs to the oscillator as a control signal;
A signal source comprising:   The signal source according to claim 1, wherein the spurious signal is a mixed signal of the first signal and an output signal of the second mixer.   3. The closed loop transfer characteristic is determined from a transfer function of the loop filter, a tuning sensitivity of the oscillator, and a detection sensitivity of the phase frequency comparator, and suppresses the spurious closest to DC. Signal source as described in Transfer function of the loop filter (F (s), s is a complex frequency), tuning sensitivity of the oscillator (K _v ), detection sensitivity of the phase frequency comparator (K _p ), and frequency of the spurious (f _sp5 ) And the closed loop transfer characteristic is
_{20log | 1 / ((f sp5} / (K p · F (f sp5) · K v)) + 1) | <3dB
The signal source according to claim 2, wherein:   The frequency divider which frequency-divides the signal which the said 1st mixer frequency-converted between the said 1st mixer and the said 2nd mixer was provided. Signal source.

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