JP2017192195A - Motor control device, image formation device, motor control method, and method of controlling image formation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the position of a motor with high accuracy even when a rotational speed of the motor is changed.SOLUTION: In a motor control device, a deviation counter update unit 823 updates the value of a deviation counter CT every time when a reference pulse signal Ps and an encoder pulse signal Pe are generated. A periodic recording unit 825 records data of a target period Tref in a case where the deviation counter CT represents a phase-delay state every time when the reference pulse signal Ps is generated, and records data of a measurement period Tenc in a case where the deviation counter CT represents a phase-advance state every time when the encoder pulse signal Pe is generated, in a FIFO buffer 820. A phase error calculation unit 826 calculates a phase error PHE on the basis of a phase error that is previously calculated, a period represented by data read out from the FIFO, and a period that is newly detected.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a motor control device, an image forming apparatus that controls a motor that drives an image carrier by the motor control device, a motor control method, and a control method for the image forming apparatus.

  In an electrophotographic image forming apparatus, the power supplied to a motor that drives a drum-shaped image carrier is adjusted, and thereby the rotational speed and position (orientation) of the image carrier are controlled.

  For example, it is known that the motor is controlled by feedback control that adjusts the supply power in a direction in which a difference between a target position of the motor and a measurement position (detection position) of the motor is reduced (for example, Patent Document 1). The target position is obtained by counting the edges of the reference pulse signal. The measurement position is obtained by counting the edges of the encoder pulse signal synchronized with the rotation of the motor. The encoder pulse signal is output by an encoder attached to the motor.

JP 2013-162694 A

  By the way, when the difference between the count numbers of the reference pulse signal and the encoder pulse signal is used as a deviation of the feedback control of the motor, the deviation of less than one pulse becomes a dead zone in the feedback control. In this case, it is difficult to maintain the deviation below 1 pulse, and the resolution of position measurement based on the encoder pulse signal becomes a limitation, and it is difficult to control the position of the motor with high accuracy.

  On the other hand, it is also conceivable that the difference between the generation periods of the two pulse signals is used as a deviation in the feedback control of the motor. In this case, when the deviation exceeds the generation period of one of the two pulse signals, information on the difference between the target position and the measurement position is lost. Therefore, if the difference between the target position and the measurement position becomes large when the speed of the motor is changed, such as when the motor is started and stopped, the position of the motor cannot be controlled.

  An object of the present invention is to provide a motor control device, an image forming apparatus, a motor control method, and an image forming apparatus control method capable of controlling the position of the motor with high accuracy even when the rotational speed of the motor is changed. It is in.

  A motor control device according to one aspect of the present invention includes a target cycle detection unit, a measurement cycle detection unit, a deviation counter update unit, a cycle recording unit, a phase error calculation unit, and a power adjustment unit. The target period detector detects a target period that is an elapsed time from the previous generation of the reference pulse signal every time a reference pulse signal is generated. The measurement cycle detector detects a measurement cycle that is an elapsed time from the previous generation of the encoder pulse signal every time an encoder pulse signal synchronized with the rotation of the motor is generated. The deviation counter updating unit updates the value of a deviation counter, which is a predetermined variable, to a value obtained by adding a predetermined unit value every time the reference pulse signal is generated, and the encoder pulse signal is generated. Each time, the value of the deviation counter is updated to a value obtained by subtracting the unit numerical value. The period recording unit, when the reference pulse signal occurs, when the value of the deviation counter represents a phase delay state in which the phase of the reference pulse signal is delayed with respect to the phase of the encoder pulse signal, The newly detected data of the target period is recorded in a FIFO buffer, and each time the encoder pulse signal is generated, the value of the deviation counter is changed so that the phase of the reference pulse signal is relative to the phase of the encoder pulse signal. When representing the advanced phase advance state, the data of the newly detected measurement cycle is recorded in the FIFO buffer. Whenever the encoder pulse signal is generated, the phase error calculation unit, when the value of the deviation counter represents the phase delay state, the previously calculated phase error and the period represented by the read data from the FIFO The phase error is calculated by applying the newly detected measurement period to a predetermined first calculation formula. Further, the phase error calculation unit, when the value of the deviation counter indicates the phase advance state every time the reference pulse signal is generated, the phase error calculated last time and the read data from the FIFO buffer. The phase error is calculated by applying the cycle represented by and the newly detected target cycle to a predetermined first calculation formula. The power adjusting unit adjusts the power supplied to the motor in a direction in which the phase error is reduced.

  An image forming apparatus according to another aspect of the present invention includes an image carrier, a motor that drives the image carrier, an encoder, and the motor control device. The encoder outputs an encoder pulse signal synchronized with the rotation of the motor. The motor control device adjusts electric power supplied to the motor.

  A motor control method according to another aspect of the present invention includes a plurality of steps shown below. One of the plurality of steps is a step of detecting a target period which is an elapsed time from the previous generation of the reference pulse signal every time the reference pulse signal is generated. Another one of the plurality of steps is a step of detecting a measurement cycle which is an elapsed time from the previous generation of the encoder pulse signal every time an encoder pulse signal synchronized with the rotation of the motor is generated. The other one of the plurality of steps updates the value of a deviation counter, which is a predetermined variable, to a value obtained by adding a predetermined unit value every time the reference pulse signal is generated, This is a step of updating the value of the deviation counter to a value obtained by subtracting the unit numerical value every time a signal is generated. Another one of the plurality of steps is a phase delay state in which the value of the deviation counter is delayed from the phase of the encoder pulse signal each time the reference pulse signal is generated. When the encoder pulse signal is generated, the value of the deviation counter is recorded with respect to the phase of the encoder pulse signal each time the encoder pulse signal is generated. This is a step of recording the newly detected data of the measurement cycle in the FIFO buffer in the case of representing a phase advance state in which the phase of the pulse signal is advanced. Another one of the plurality of steps is that each time the encoder pulse signal is generated, when the value of the deviation counter indicates the phase delay state, the previously calculated phase error and the read data from the FIFO Is a step of calculating the phase error by applying the cycle represented by the above and the newly detected measurement cycle to a predetermined first calculation formula. Another one of the plurality of steps is that each time the reference pulse signal is generated, when the value of the deviation counter indicates the phase advance state, the previously calculated phase error and the FIFO buffer In this step, the phase error is calculated by applying a cycle represented by read data and the newly detected target cycle to a predetermined second calculation formula. Another one of the plurality of steps is a step of adjusting the power supplied to the motor in a direction in which the phase error is reduced.

  According to another aspect of the present invention, there is provided a method for controlling an image forming apparatus, comprising: an image carrier; a motor that drives the image carrier; and an encoder that outputs an encoder pulse signal synchronized with the rotation of the motor. A method for controlling an apparatus. In this control method, the electric power supplied to the motor is adjusted by the motor control method.

  According to the present invention, it is possible to provide a motor control device, an image forming apparatus, a motor control method, and an image forming apparatus control method capable of controlling the position of the motor with high accuracy even when the rotational speed of the motor is changed. Is possible.

FIG. 1 is a configuration diagram of an image forming apparatus according to the first embodiment. FIG. 2 is a block diagram of the motor control device according to the first embodiment. FIG. 3 is a block diagram of a phase comparison unit in the motor control device according to the first embodiment. FIG. 4 is a diagram illustrating an example of a time chart of the reference pulse signal and the encoder pulse signal input by the phase comparison unit of the motor control device according to the first embodiment. FIG. 5A is a diagram illustrating an example of a memory map of the FIFO buffer when the first reference pulse signal in the time chart of FIG. 4 is input. FIG. 5B is a diagram illustrating an example of a memory map of the FIFO buffer when the second reference pulse signal in the time chart of FIG. 4 is input. FIG. 6A is a diagram illustrating an example of a memory map of the FIFO buffer when the third encoder pulse signal in the time chart of FIG. 4 is input. FIG. 6B is a diagram illustrating an example of a memory map of the FIFO buffer when the fourth encoder pulse signal in the time chart of FIG. 4 is input. FIG. 6C is a diagram illustrating an example of a memory map of the FIFO buffer when the fifth encoder pulse signal in the time chart of FIG. 4 is input. FIG. 7A is a diagram illustrating an example of a memory map of the FIFO buffer when the fourth reference pulse signal in the time chart of FIG. 4 is input. FIG. 7B is a diagram illustrating an example of a memory map of the FIFO buffer when the sixth encoder pulse signal in the time chart of FIG. 4 is input. FIG. 7C is a diagram illustrating an example of a memory map of the FIFO buffer when the fifth reference pulse signal in the time chart of FIG. 4 is input. FIG. 8 is a block diagram of a motor control device according to the second embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the following embodiment is an example which actualized this invention, Comprising: It does not have the character which limits the technical scope of this invention.

[First Embodiment]
The image forming apparatus 10 according to the first embodiment is an electrophotographic image forming apparatus. The image forming apparatus 10 is, for example, a printer, a copier, a facsimile machine, or a multifunction machine.

  As shown in FIG. 1, in the image forming apparatus 10, the sheet supply unit 2 sends out the sheets 9 one by one, and the sheet conveyance unit 3 moves the sheet 9 supplied from the sheet supply unit 2 along the conveyance path 30. Transport. The sheet 9 is a sheet-like image forming medium such as paper or an envelope.

  Further, in the image forming apparatus 10, the image forming unit 4 forms an image on the sheet 9 moving on the conveyance path 30. In the image forming unit 4, the photosensitive member 41 rotates, and the charging roller 421 of the charging unit 42 rotates opposite to the photosensitive member 41 to charge the photosensitive member 41. The photoconductor 41 is an example of an image carrier.

  Further, the optical scanning unit 5 writes an electrostatic latent image on the charged photoreceptor 41, and a developing roller 431 rotated by the developing unit 43 develops the electrostatic latent image as a toner image. Further, the transfer unit 45 transfers the toner image on the photoconductor 41 to the sheet 9 moving on the conveyance path 30. Further, the fixing unit 46 fixes the toner image on the sheet 9 by heating the toner image formed on the sheet 9.

  Rotating bodies such as the photoconductor 41, the charging roller 421, and the developing roller 431 are driven by a motor 40 connected through a gear mechanism 401.

  The motor 40 is a servo motor, for example, a DC motor such as a DC brushless motor. An encoder 400 is attached to the motor 40. The encoder 400 outputs an encoder pulse signal Pe that is a pulse signal synchronized with the rotation of the motor 40.

  The encoder pulse signal Pe is generated every time the motor 40 rotates by a unit angle. The unit angle is determined by the resolution of the encoder 400. The encoder pulse signal Pe is input to the control unit 8.

  The control unit 8 includes a motor control device 80 that controls the motor 40 and other control units that control devices other than the motor 40. The control unit 8 is configured by a combination of, for example, an MPU (Micro Processor Unit), other semiconductor devices, and other electronic circuits. The various operations executed by the control unit 8 are realized by the MPU executing a program stored in a non-temporary and computer-readable memory, or by hardware such as a logic operation circuit. It can be realized.

  The motor control device 80 controls the rotational speed and rotational position (orientation) of the motor 40 by adjusting the power supplied to the motor 40. That is, the motor control device 80 performs feedback control for adjusting the supplied power in a direction in which the difference between the target position of the motor 40 and the measurement position (detection position) of the motor 40 is reduced. The target position is given as a reference pulse signal Ps described later (for example, see FIG. 2).

  By the way, when the difference between the count numbers of the reference pulse signal Ps and the encoder pulse signal Pe is used as a deviation in feedback control of the motor 40, the deviation of less than one pulse becomes a dead zone in the feedback control. In this case, it is difficult to maintain the deviation below one pulse, and the resolution of position measurement based on the encoder pulse signal Pe is limited, and it is difficult to control the position of the motor 40 with high accuracy.

  On the other hand, it is also conceivable that the difference between the two pulse signals Ps and Pe is used as a deviation of the feedback control of the motor 40. In this case, when the deviation exceeds the generation period of one of the two pulse signals Ps and Pe, information on the difference between the target position and the measurement position is lost. Therefore, the position of the motor 40 cannot be controlled if the difference between the target position and the measurement position increases when the speed of the motor 40 is changed, such as when the motor 40 is started and stopped.

  On the other hand, the motor control device 80 can control the position of the motor 40 in the rotational direction with high accuracy even when the rotational speed of the motor 40 is changed.

[Details of motor control device 80]
As shown in FIG. 2, the motor control device 80 includes a reference pulse generation unit 81, a phase comparison unit 82, a motor power adjustment unit 83, and the like.

  The reference pulse generator 81 generates a reference pulse signal Ps that serves as a reference for the target position in the rotation direction of the motor 40. For example, the reference pulse generation unit 81 includes a target speed calculation unit 811, a low pass filter processing unit 812, and a voltage controlled oscillator 813. The target speed calculation unit 811 calculates a primary target speed Vx that is the rotational speed of the motor 40 necessary for operating the photoconductor 41 in accordance with a predetermined rule.

  The low-pass filter processing unit 812 performs low-pass filter processing on a signal having a level corresponding to the primary target speed Vx. The voltage controlled oscillator 813 generates a reference pulse signal Ps that is a pulse signal having a frequency corresponding to the signal of the secondary target speed Vy after the low-pass filter processing.

  The phase comparator 82 calculates a phase error PHE that is an integrated value of the phase difference between the reference pulse signal Ps and the encoder pulse signal Pe. Details of the phase comparator 82 will be described later.

  The motor power adjustment unit 83 adjusts the power supplied to the motor 40 in a direction in which the phase error PHE is reduced. For example, the motor power adjustment unit 83 includes a proportional element amplifier 831, an integrator 832, an integration element amplifier 833, an adder 834, a pulse width modulation unit 835, and a motor drive circuit 836. Note that the direction in which the phase error PHE decreases can be rephrased as the direction in which the phase error PHE converges to 0 or the direction in which the phase error PHE is eliminated.

  The proportional element amplifier 831 is an amplifier that generates a proportional control signal Xp reflecting the proportional element of the phase error PHE by amplifying a signal corresponding to the phase error PHE with a preset proportional gain.

  The integrator 832 performs integration processing on the signal corresponding to the phase error PHE. The integral element amplifier 833 is an amplifier that generates an integral control signal Xi reflecting the integral element of the phase error PHE by amplifying a signal corresponding to the integral value of the phase error PHE with a preset integral gain. is there.

  The adder 834 generates a power supply amount signal Xo representing the magnitude of power supplied to the motor 40 by adding the proportional control signal Xp and the integral control signal Xi. That is, the proportional element amplifier 831, the integrator 832, the integral element amplifier 833, and the adder 834 are control units that adjust the power supplied to the motor 40 by so-called PI control.

  The pulse width modulation unit 835 generates a pulse width modulation signal Pc whose pulse width is adjusted by a duty ratio corresponding to the level of the power supply amount signal Xo by performing pulse width modulation processing on the power supply amount signal Xo.

  The motor drive circuit 836 is a circuit that generates a drive pulse signal Pd that is a pulsed motor drive power signal synchronized with the pulse width modulation signal Pc. The drive pulse signal Pd is supplied to the motor 40.

  That is, the pulse width modulation unit 835 adjusts the duty ratio of the drive pulse signal Pd supplied to the motor 40 in accordance with the power supply amount signal Xo that is an input signal in which the proportional and integral elements of the phase error PHE are reflected. Thereby, the electric power supplied to the motor 40 is adjusted according to the phase error PHE.

  As described above, the motor power adjustment unit 83 executes a step of adjusting the power supplied to the motor 40 in a direction in which the phase error PHE is reduced. Further, in the step of adjusting the power supplied to the motor 40, the pulse width modulation unit 835 is supplied to the motor 40 according to a proportional control signal Xp that is an input signal that reflects at least a proportional element of the phase error PHE. A step of adjusting the duty ratio of the drive pulse signal Pd is executed.

[Phase comparison unit 82]
As shown in FIG. 3, the phase comparison unit 82 includes a FIFO buffer 820, a target cycle detection unit 821, a measurement cycle detection unit 822, a deviation counter update unit 823, a phase state determination unit 824, a cycle recording unit 825, and a phase error calculation. Part 826.

  The FIFO buffer 820 is a first-in / first-out data storage medium having a plurality of data storage units 8200 (see, for example, FIGS. 5A and 5B). For example, the FIFO buffer 820 can include at least three data storage units 8200.

  The period recording unit 825 records the latest data in the FIFO buffer 820, and the phase error calculation unit 826 reads the oldest data from the FIFO buffer 820. The oldest data read by the phase error calculation unit 826 is erased from the FIFO buffer 820.

  The oldest data is the first recorded data among the effective data stored in the FIFO buffer 820.

  In the example shown in FIGS. 5A, 5B, etc., the FIFO buffer 820 includes 16 data storage units 8200 with buffer numbers 0-15. In the memory maps shown in FIGS. 5A, 5B, etc., the data storage units 8200 with buffer numbers 4 to 14 are omitted.

  Note that a ring buffer that records and reads data using the FIFO method is also an example of the FIFO buffer 820.

  In the following description, the integers i, j, and k represent the number of the generated reference pulse signal Ps, the number of the generated encoder pulse signal Pe, and the number of the phase error PHE calculated sequentially.

  Each time the reference pulse signal Ps is generated, the target period detection unit 821 detects a target period Tref that is an elapsed time from the previous generation of the reference pulse signal Ps. That is, when the i-th reference pulse signal Ps is generated, the target cycle detection unit 821 is a target cycle Tref that is an elapsed time from the generation time point of the (i−1) -th (see FIG. 6) reference pulse signal Ps. (I) is detected.

  Each time the encoder pulse signal Pe is generated, the measurement period detector 822 detects a measurement period Tenc that is an elapsed time from the previous generation of the encoder pulse signal Pe. That is, when the j-th reference pulse signal Ps is generated, the measurement cycle detection unit 822 detects the measurement cycle Tenc (j) that is an elapsed time from the generation time point of the (j−1) -th encoder pulse signal Pe. To do.

  The step executed by the target cycle detection unit 821 is an example of a step of detecting the target cycle Tref. Moreover, the process performed by the measurement cycle detection unit 822 is an example of a process of detecting the measurement cycle Tenc.

  Note that the data of the target period Tref and the measurement period Tenc may be numerical data representing a count-up number of a predetermined clock signal, in addition to numerical data in units of time such as milliseconds. .

  Each time the reference pulse signal Ps is generated, the deviation counter updating unit 823 updates the value of the deviation counter CT, which is a predetermined variable, to a value obtained by adding a predetermined unit numerical value. Further, the deviation counter updating unit 823 updates the value of the deviation counter CT to a value obtained by subtracting the unit numerical value every time the encoder pulse signal Pe is generated.

  In this embodiment, the unit numerical value is 1. The unit numerical value may be another numerical value such as -1. The step executed by the deviation counter updating unit 823 is an example of a step of updating the value of the deviation counter CT.

  In the following description, a state where the phase of the reference pulse signal Ps is advanced with respect to the phase of the encoder pulse signal Pe is referred to as a phase advance state, and the phase of the reference pulse signal Ps is relative to the phase of the encoder pulse signal Pe. The state of being delayed is referred to as a phase delay state.

  The phase advance state and the phase delay state are an example of a relative relationship between the phase of the encoder pulse signal Pe and the phase of the reference pulse signal Ps.

  Although a state in which the encoder pulse signal Pe and the reference pulse signal Ps are completely synchronized is also conceivable, for the sake of convenience, it is assumed that the completely synchronized state is the phase advance state. It may be assumed that the state of complete synchronization is the phase delay state.

  Here, it is assumed that the initial value of the deviation counter CT is 0 and the initial state of the motor control device 80 is the phase advance state. In this case, every time the reference pulse signal Ps is generated, the value of the deviation counter CT updated by the deviation counter updating unit 823 being greater than 0 indicates the phase delay state, and the value is 0 or less. The phase advance state is represented.

  On the other hand, every time the encoder pulse signal Pe is generated, the value of the deviation counter CT updated by the deviation counter updating unit 823 being 0 or more indicates the phase delay state, and the value being less than 0 is the phase. Indicates the advance state.

  When the initial value of the deviation counter CT is 0 and the unit numerical value is −1, the updated value of the deviation counter CT every time the reference pulse signal Ps is generated is less than 0, or the encoder pulse signal Pe. The state where the value of the updated deviation counter CT for each occurrence is 0 or less is the phase delay state, and the other states are the phase advance state.

  The phase state determination unit 824 determines whether the value of the deviation counter CT represents the phase delay state or the phase advance state. For convenience, in FIG. 4, the determination result ST of the phase state determination unit 824 is expressed as 1 when the phase is delayed, and the determination result ST is expressed as 0 when it is the phase advance state.

  Specifically, the phase state determination unit 824 determines that the value of the deviation counter CT updated by the deviation counter updating unit 823 is greater than 0 every time the reference pulse signal Ps is generated, or whenever the encoder pulse signal Pe is generated. When the value of the deviation counter CT updated by the deviation counter updating unit 823 is 0 or more, it is determined that the phase delay state has occurred.

  On the other hand, the phase state determination unit 824 updates the deviation counter every time the value of the deviation counter CT updated by the deviation counter updating unit 823 is 0 or less every time the reference pulse signal Ps is generated, or every time the encoder pulse signal Pe is generated. When the value of the deviation counter CT updated by the unit 823 is less than 0, it is determined that the phase advance state has occurred.

  Whenever the reference pulse signal Ps is generated, the period recording unit 825 stores the data of the newly detected target period Tref in the FIFO buffer 820 when the determination result ST of the phase state determination unit 824 is the phase delay state. Record.

  Further, every time the encoder pulse signal Pe is generated, the period recording unit 825 stores the data of the newly detected measurement period Tenc in the FIFO buffer when the determination result ST of the phase state determination unit 824 is the phase advance state. Record at 820.

  The process executed by the periodic recording unit 825 is an example of a process of recording data in the FIFO buffer 820.

  The phase error calculation unit 826 reads data from the FIFO buffer 820 every time the encoder pulse signal Pe is generated, when the determination result ST of the phase state determination unit 824 is the phase delay state. The data to be read is the oldest data among the valid data stored in the FIFO buffer 820.

  Further, in the phase delay state, the phase error calculation unit 826 newly adds the previously calculated phase error PHE (k−1), the cycle Tout represented by the read data from the FIFO buffer 820, and the measurement cycle detection unit 822. The phase error PHE (k) is calculated by applying the detected measurement cycle Tenc (j) to the equation (1).

  The initial value of the phase error PHE is zero. In addition, (1) Formula is an example of the 1st calculation formula defined beforehand.

  Further, every time the reference pulse signal Ps is generated, the phase error calculation unit 826 reads data from the FIFO buffer 820 even when the determination result ST of the phase state determination unit 824 is the phase advance state. The data to be read is the oldest data among the valid data stored in the FIFO buffer 820.

  Further, in the phase advance state, the phase error calculation unit 826 newly adds the previously calculated phase error PHE (k−1), the cycle Tout represented by the read data from the FIFO buffer 820, and the target cycle detection unit 821. The phase error PHE (k) is calculated by applying the detected target cycle Tref (i) to the following equation (2). Equation (2) is an example of a predetermined second calculation equation.

  The above steps executed by the phase error calculation unit 826 are examples of steps for calculating the phase error PHE.

  Hereinafter, based on the example of the reference pulse signal Ps and the encoder pulse signal Pe shown in the time chart of FIG. 4, an example of specific processing of the phase comparison unit 82 will be described.

  In the example of FIG. 4, first (i = 1) reference pulse signal Ps is generated. At this time, the value of the deviation counter CT is counted up from the initial value 0 to 1. Since the updated deviation counter CT is larger than 0, the determination result ST of the phase state determination unit 824 becomes the phase delay state (= 1).

  Therefore, the period recording unit 825 records the newly detected data of the first target period Tref (1) in the FIFO buffer 820 (see FIG. 5A).

  Next, in the example of FIG. 4, the first (j = 1) encoder pulse signal Pe is generated. At this time, the value of the deviation counter CT is counted down from 1 to 0. Since the value of the updated deviation counter CT is 0 or more, the determination result ST of the phase state determination unit 824 is maintained in the phase delay state (= 1).

  Therefore, the phase error calculation unit 826 has the previous phase error PHE (0), the target period Tref (1) that is the period Tout represented by the read data from the FIFO buffer 820, and the newly detected first measurement period. The phase error PHE (1) is calculated by applying Tenc (1) to the equation (1). The FIFO buffer 820 after data is read becomes empty.

  Note that the arrow indicating the phase error PHE (i) pointing to the right in FIG. 6 indicates the phase delay state, and the arrow indicating the phase error PHE (i) is directed toward the sheet in FIG. Leftward direction represents the phase advance state.

  Next, in the example of FIG. 4, the second (i = 2) reference pulse signal Ps is generated. At this time, the value of the deviation counter CT is counted up from 0 to 1. Since the value of the updated deviation counter CT is larger than 0, the determination result ST of the phase state determination unit 824 is maintained in the phase delay state (= 1).

  Therefore, the period recording unit 825 records the newly detected data of the second target period Tref (2) in the FIFO buffer 820 (see FIG. 5B).

  Next, in the example of FIG. 4, the second (j = 2) encoder pulse signal Pe is generated. At this time, the value of the deviation counter CT is counted down from 1 to 0. Since the value of the updated deviation counter CT is 0 or more, the determination result ST of the phase state determination unit 824 is maintained in the phase delay state (= 1).

  Therefore, the phase error calculation unit 826 includes the previously calculated phase error PHE (1), the target period Tref (2) that is the period Tout represented by the read data from the FIFO buffer 820, and the newly detected second error. The phase error PHE (2) is calculated by applying the measurement cycle Tenc (2) to the equation (1). Further, the FIFO buffer 820 after data is read becomes empty.

  Next, in the example of FIG. 4, the third (j = 3) encoder pulse signal Pe is generated. At this time, the value of the deviation counter CT is counted down from 0 to -1. Since the value of the updated deviation counter CT is less than 0, the determination result ST of the phase state determination unit 824 becomes the phase advance state (= 0).

  Therefore, the period recording unit 825 records the data of the newly detected third measurement period Tenc (3) in the FIFO buffer 820 (see FIG. 6A).

  Next, in the example of FIG. 4, the third (i = 3) reference pulse signal Ps is generated. At this time, the value of the deviation counter CT is counted up from −1 to 0. Since the value of the updated deviation counter CT is 0 or less, the determination result ST of the phase state determination unit 824 is maintained in the phase advance state (= 0).

  Therefore, the phase error calculation unit 826 includes the previously calculated phase error PHE (2), the measurement period Tenc (3) that is the period Tout represented by the read data from the FIFO buffer 820, and the third detected newly. The phase error PHE (3) is calculated by applying the target period Tref (3) to the equation (2). Further, the FIFO buffer 820 after data is read becomes empty.

  Next, in the example of FIG. 4, the fourth (j = 4) encoder pulse signal Pe is generated. At this time, the value of the deviation counter CT is counted down from 0 to -1. Since the value of the updated deviation counter CT is less than 0, the determination result ST of the phase state determination unit 824 is maintained in the phase advance state (= 0).

  Therefore, the period recording unit 825 records the newly detected data of the fourth measurement period Tenc (4) in the FIFO buffer 820 (see FIG. 6B).

  Next, in the example of FIG. 4, the fifth (j = 5) encoder pulse signal Pe is generated. At this time, the value of the deviation counter CT is counted down from −1 to −2. Since the value of the updated deviation counter CT is less than 0, the determination result ST of the phase state determination unit 824 is maintained in the phase advance state (= 0).

  Therefore, the period recording unit 825 records the newly detected data of the fifth measurement period Tenc (5) in the FIFO buffer 820 (see FIG. 6C).

  Next, in the example of FIG. 4, the fourth (i = 4) reference pulse signal Ps is generated. At this time, the value of the deviation counter CT is counted up from -2 to -1. Since the value of the updated deviation counter CT is 0 or less, the determination result ST of the phase state determination unit 824 is maintained in the phase advance state (= 0).

  Therefore, the phase error calculation unit 826 includes the previously calculated phase error PHE (3), the measurement period Tenc (4) that is the period Tout represented by the read data from the FIFO buffer 820, and the newly detected fourth error. The phase error PHE (4) is calculated by applying the target period Tref (4) to the equation (2). Further, only the fifth measurement cycle Tenc (5) remains in the FIFO buffer 820 after the data is read (see FIG. 7A).

  Next, in the example of FIG. 4, the sixth (j = 6) encoder pulse signal Pe is generated. At this time, the value of the deviation counter CT is counted down from −1 to −2. Since the value of the updated deviation counter CT is less than 0, the determination result ST of the phase state determination unit 824 is maintained in the phase advance state (= 0).

  Therefore, the period recording unit 825 records the newly detected data of the sixth measurement period Tenc (6) in the FIFO buffer 820 (see FIG. 7B).

  Next, in the example of FIG. 4, the fifth (i = 5) reference pulse signal Ps is generated. At this time, the value of the deviation counter CT is counted up from -2 to -1. Since the value of the updated deviation counter CT is 0 or less, the determination result ST of the phase state determination unit 824 is maintained in the phase advance state (= 0).

  Therefore, the phase error calculation unit 826 includes the previously calculated phase error PHE (4), the measurement period Tenc (5) that is the period Tout represented by the read data from the FIFO buffer 820, and the newly detected fifth. The phase error PHE (5) is calculated by applying the target period Tref (5) to the equation (2). Further, only the sixth measurement cycle Tenc (6) remains in the FIFO buffer 820 after the data is read (see FIG. 7C).

  Next, in the example of FIG. 4, the sixth (i = 6) reference pulse signal Ps is generated. At this time, the value of the deviation counter CT is counted up from −1 to 0. Since the value of the updated deviation counter CT is 0 or less, the determination result ST of the phase state determination unit 824 is maintained in the phase advance state (= 0).

  Therefore, the phase error calculation unit 826 includes the previously calculated phase error PHE (5), the measurement period Tenc (6) that is the period Tout represented by the read data from the FIFO buffer 820, and the newly detected sixth. The phase error PHE (6) is calculated by applying the target period Tref (6) to the equation (2). Further, the FIFO buffer 820 after data is read becomes empty.

  Next, in the example of FIG. 4, the seventh (j = 7) encoder pulse signal Pe is generated. At this time, the value of the deviation counter CT is counted down from 0 to -1. Since the value of the updated deviation counter CT is less than 0, the determination result ST of the phase state determination unit 824 is maintained in the phase advance state (= 0).

  Therefore, the period recording unit 825 records the newly detected data of the seventh measurement period Tenc (7) in the FIFO buffer 820. Thereafter, the phase comparator 82 repeats the same processing according to the generation status of the reference pulse signal Ps and the encoder pulse signal Pe.

  Expressions (1) and (2) are expressions that integrate the differences between the target period Tref (i) and the measurement period Tenc (j) that are sequentially detected. In the phase delay state, the value of the phase error PHE (k) is 0 or more, and in the phase advance state, the value of the phase error PHE (k) is less than 0.

  The phase error PHE (k), which is an integrated value of the difference, corresponds to a measurement position error (position error) with respect to a target position in the rotation direction of the motor 40. Unlike a general phase difference that changes only within a range of less than one period of the reference pulse signal Ps, the phase error PHE can change within a range exceeding one period of the reference pulse signal Ps.

  Then, the latest phase error PHE (k) calculated sequentially is input to the motor power adjustment unit 83. Thereby, the motor power adjusting unit 83 adjusts the power supplied to the motor 40 in a direction in which the phase error PHE (k) is reduced. The process executed by the motor power adjustment unit 83 is an example of a process for adjusting the power supplied to the motor 40.

  If the motor control device 80 is employed, the phase error PHE that is an integrated value of the difference between the generation periods of the reference pulse signal Ps and the encoder pulse signal Pe is used as a deviation in feedback control of the motor 40. Therefore, even if the phase error PHE (deviation) is a time difference of less than one pulse, the power supplied to the motor 40 is adjusted in such a direction that the time difference disappears. Therefore, the resolution of position measurement based on the encoder pulse signal Pe does not become a restriction on the control performance, and the position of the motor 40 can be controlled with high accuracy.

  Furthermore, a plurality of data representing one of a plurality of target periods Tref or a plurality of measurement periods Tenc is stored in the FIFO buffer 820 in accordance with the expansion of the phase delay state or the phase advance state. Therefore, even if the phase difference (deviation) between the reference pulse signal Ps and the encoder pulse signal Pe exceeds the generation period of one of the two pulse signals Ps and Pe, the correct phase error PHE is calculated.

  Therefore, even when the speed of the motor 40 is changed relatively large, such as when the motor 40 is started and stopped, that is, even when the difference between the target position and the measurement position becomes large, the position of the motor 40 is correctly controlled. can do.

  Further, one data of the target cycle Tref and the measurement cycle Tenc is selectively stored in the FIFO buffer 820 depending on whether the deviation counter CT represents the phase delay state or the phase advance state. Therefore, the size of the buffer for storing the target period Tref and the measurement period Tenc can be reduced.

  Further, in the motor power adjustment unit 83, the pulse width modulation unit 835 has a duty ratio of the drive pulse signal Pd supplied to the motor 40 in accordance with the input signal (power supply amount signal Xo) reflecting the proportional element of the phase error PHE. Adjust. Such control is effective as control for quickly reducing the phase error PHE.

  In the present embodiment, the pulse width modulation unit 835 further adjusts the duty ratio of the drive pulse signal Pd supplied to the motor 40 in accordance with the input signal (power supply amount signal Xo) that also reflects the integral element of the phase error PHE. . Thereby, it is possible to prevent an offset from occurring in the position control of the motor 40.

[Second Embodiment]
Next, differences from the motor control device 80 in the motor control device 80A according to the second embodiment will be described with reference to FIG. In FIG. 8, the same components as those shown in FIG. 2 are given the same reference numerals.

  The motor control device 80A has a configuration in which a target speed detection unit 84, an actual measurement level detection unit 85, a subtractor 86, a speed feedback control amplifier 87, and a feedforward control amplifier 88 are added to the configuration of the motor control apparatus 80. ing.

  The target speed detector 84 detects (calculates) the target rotational speed of the motor 40 by calculating the reciprocal of the generation period of the reference pulse signal Ps. Similarly, the actual measurement degree detection unit 85 detects (calculates) the actual rotational speed of the motor 40 by calculating the reciprocal of the generation period of the encoder pulse signal Pe.

  The subtracter 86 calculates a speed deviation that is a difference between the target rotation speed and the actual rotation speed. The speed feedback control amplifier 87 is an amplifier that generates a speed control signal that reflects the speed deviation by amplifying a signal corresponding to the speed deviation with a preset gain.

  The feedforward control amplifier 88 is an amplifier that amplifies a signal corresponding to the target rotation speed with a preset gain to generate a feedforward control signal in which an element of the change in the target rotation speed is reflected. is there.

  The speed control signal and the feedforward control signal are added together with the proportional control signal Xp and the integral control signal Xi by the adder 834 and reflected in the power supply amount signal Xo.

  The image forming apparatus according to the second embodiment includes a configuration in which the motor control device 80 in the image forming device 10 is replaced with a motor control device 80A.

  As described above, the motor control device 80A performs feedback control and feedforward control based on the rotation speed of the motor 40 in parallel with feedback control based on the phase error PHE. Thereby, the phase error PHE can be reduced more quickly.

[Application example]
In the motor control devices 80 and 80A, the integrator 832 and the integral element amplifier 833 may not be omitted.

  The motor control device, the image forming apparatus, the motor control method, and the image forming apparatus according to the present invention can be freely combined within the scope of the invention described in each claim. Alternatively, the embodiment and application examples may be modified as appropriate, or may be configured by omitting a part thereof.

2: Sheet feeding unit 3: Sheet conveying unit 4: Image forming unit 5: Optical scanning unit 8: Control unit 9: Sheet 10: Image forming apparatus 30: Conveying path 40: Motor 41: Photoconductor 42: Charging unit 43: Development Unit 45: transfer unit 46: fixing unit 80, 80A: motor control device 81: reference pulse generation unit 82: phase comparison unit 83: motor power adjustment unit 84: target speed detection unit 85: measured degree detection unit 86: subtractor 87 : Speed feedback control amplifier 88: Feed forward control amplifier 400: Encoder 401: Gear mechanism 421: Charging roller 431: Development roller 811: Target speed calculation unit 812: Low pass filter processing unit 813: Voltage controlled oscillator 820: FIFO buffer 821 : Target period detection unit 822: Measurement period detection unit 823: Deviation counter update 824: Phase state determination unit 825: Period recording unit 826: Phase error calculation unit 831: Proportional element amplifier 832: Integrator 833: Integration element amplifier 834: Adder 835: Pulse width modulation unit 836: Motor drive circuit 8200: Data storage Part CT: Deviation counter PHE: Phase error Pc: Pulse width modulation signal Pd: Drive pulse signal Pe: Encoder pulse signal Ps: Reference pulse signal Tenc: Measurement cycle Tref: Target cycle

Claims (6)

A target period detection unit that detects a target period that is an elapsed time from the previous generation of the reference pulse signal each time a reference pulse signal is generated;
Each time an encoder pulse signal synchronized with the rotation of the motor is generated, a measurement cycle detection unit that detects a measurement cycle that is an elapsed time from the previous generation of the encoder pulse signal;
Each time the reference pulse signal is generated, the value of the deviation counter, which is a predetermined variable, is updated to a value obtained by adding a predetermined unit value, and each time the encoder pulse signal is generated, the deviation counter A deviation counter updating unit for updating the value to a value obtained by subtracting the unit numerical value;
Each time the reference pulse signal is generated, the value of the deviation counter is newly detected when the phase of the reference pulse signal is delayed with respect to the phase of the encoder pulse signal. Phase lead state in which the data of the target period is recorded in the FIFO buffer, and the value of the deviation counter is advanced with respect to the phase of the encoder pulse signal each time the encoder pulse signal is generated , A period recording unit that records data of the newly detected measurement period in the FIFO buffer;
Each time the encoder pulse signal is generated, when the value of the deviation counter represents the phase lag state, the previously calculated phase error, the period represented by the read data from the FIFO, and the newly detected When the phase error is calculated by applying a measurement period to a predetermined first calculation formula, and the value of the deviation counter represents the phase advance state every time the reference pulse signal is generated, The phase error is calculated by applying the calculated phase error, the period represented by the read data from the FIFO buffer, and the newly detected target period to a predetermined second calculation formula. A phase error calculator;
And a power control unit that adjusts power supplied to the motor in a direction in which the phase error is reduced.   The said power adjustment part has a pulse width modulation part which adjusts the duty ratio of the drive pulse signal supplied to the said motor according to the input signal in which the proportional factor of the said phase error is reflected at least. Motor control device. An image carrier;
A motor for driving the image carrier;
An encoder that outputs an encoder pulse signal synchronized with the rotation of the motor;
An image forming apparatus comprising: the motor control device according to claim 1, which adjusts electric power supplied to the motor. Each time a reference pulse signal is generated, detecting a target period that is an elapsed time from the previous generation of the reference pulse signal;
Each time an encoder pulse signal synchronized with the rotation of the motor is generated, a step of detecting a measurement cycle that is an elapsed time from the previous generation of the encoder pulse signal;
Each time the reference pulse signal is generated, the value of the deviation counter, which is a predetermined variable, is updated to a value obtained by adding a predetermined unit value, and each time the encoder pulse signal is generated, the deviation counter Updating the value to a value obtained by subtracting the unit numerical value;
Each time the reference pulse signal is generated, the value of the deviation counter is newly detected when the phase of the reference pulse signal is delayed with respect to the phase of the encoder pulse signal. Phase lead state in which the data of the target period is recorded in the FIFO buffer, and the value of the deviation counter is advanced with respect to the phase of the encoder pulse signal each time the encoder pulse signal is generated The step of recording the newly detected data of the measurement period in the FIFO buffer,
Each time the encoder pulse signal is generated, when the value of the deviation counter represents the phase lag state, the previously calculated phase error, the period represented by the read data from the FIFO, and the newly detected Calculating the phase error by applying a measurement period to a predetermined first calculation formula;
Each time the reference pulse signal is generated, when the value of the deviation counter indicates the phase advance state, the phase error calculated last time and the period represented by the read data from the FIFO buffer are newly detected. Calculating the phase error by applying the target period to a predetermined second calculation formula;
Adjusting the power supplied to the motor in a direction in which the phase error is reduced.   The step of adjusting the power supplied to the motor includes a step of adjusting a duty ratio of a drive pulse signal supplied to the motor in accordance with an input signal reflecting at least a proportional factor of the phase error. The motor control method as described in. An image forming apparatus comprising: an image carrier; a motor that drives the image carrier; and an encoder that outputs an encoder pulse signal synchronized with the rotation of the motor.
6. A method for controlling an image forming apparatus, wherein electric power supplied to the motor is adjusted by the motor control method according to claim 4 or 5.

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