JP5925403B1 - Motor control apparatus, image forming apparatus, motor control method, and image forming apparatus control method - Google Patents

Abstract

The target cycle recording unit (821) sequentially records the target cycle data (Tref) in the first ring buffer (824) every time the reference pulse signal (Ps) is generated. The measurement cycle recording unit (822) records measurement cycle data (Tenc) in the second ring buffer (825) every time the encoder pulse signal (Pe) is generated. The phase error calculation unit (823) calculates the phase error PHE by integrating the difference between the target cycle data (Tref) and the measurement cycle data (Tenc) of the data buffers corresponding to each other in the two ring buffers.

Description

  The present invention relates to a motor control device, an image forming apparatus that controls a motor that drives an image carrier by the motor control device, a motor control method, and a control method for the image forming apparatus.

  In an electrophotographic image forming apparatus, the power supplied to a motor that drives a drum-shaped image carrier is adjusted, and thereby the rotational speed and position (orientation) of the image carrier are controlled.

  For example, it is known that the motor is controlled by feedback control that adjusts the supplied power in a direction in which a difference between a target position of the motor and a measurement position (detection position) of the motor is reduced. The target position is obtained by counting the edges of the reference pulse signal. The measurement position is obtained by counting the edges of the encoder pulse signal synchronized with the rotation of the motor. The encoder pulse signal is output by an encoder attached to the motor.

JP 2013-162694 A

  By the way, when the difference between the count numbers of the reference pulse signal and the encoder pulse signal is used as a deviation of the feedback control of the motor, the deviation of less than one pulse becomes a dead zone in the motor control. In this case, it is difficult to maintain the deviation below 1 pulse, and the resolution of position measurement based on the encoder pulse signal becomes a limitation, and it is difficult to control the position of the motor with high accuracy.

  On the other hand, it is also conceivable that the difference between the generation periods of the two pulse signals is used as a deviation in the feedback control of the motor. In this case, when the deviation exceeds the generation period of one of the two pulse signals, information on the difference between the target position and the measurement position is lost. Therefore, if the difference between the target position and the measurement position becomes large when the speed of the motor is changed, such as when the motor is started and stopped, the position of the motor cannot be controlled.

  An object of the present invention is to provide a motor control device, an image forming apparatus, a motor control method, and an image forming apparatus control method capable of controlling the position of the motor with high accuracy even when the rotational speed of the motor is changed. It is in.

  A motor control device according to one aspect of the present invention includes a target cycle recording unit, a measurement cycle recording unit, a phase error calculation unit, and a power adjustment unit. The target cycle recording unit outputs target cycle data representing an elapsed time from the previous generation of the reference pulse signal each time a reference pulse signal is generated in a first ring buffer having three or more first data buffers. Recording is sequentially performed on each of the first data buffers. The measurement cycle recording unit has the same number of measurement cycle data as the number of the first data buffers, each representing an elapsed time from the previous generation of the encoder pulse signal each time an encoder pulse signal synchronized with the rotation of the motor is generated. Are sequentially recorded in each of the second data buffers in the second ring buffer having the second data buffer. The phase error calculation unit includes the target cycle data and the measurement cycle data that are sequentially recorded in the first data buffer and the second data buffer corresponding to each other in the first ring buffer and the second ring buffer, respectively. The phase error is calculated by integrating the differences. The power adjusting unit adjusts the power supplied to the motor in a direction in which the phase error is reduced.

  A motor control device according to another aspect of the present invention includes a target cycle recording unit, the measurement cycle recording unit, the phase error calculation unit, an error pulse count unit, a first power adjustment unit, and a second power. And an adjustment unit. The error pulse count unit counts error pulses of the encoder pulse signal with respect to the reference pulse signal. The first power adjustment unit adjusts the power supplied to the motor when the error pulse is less than the number of the first data buffers in a direction in which the phase error is reduced. The second power adjustment unit adjusts the power supplied to the motor when the error pulse is greater than or equal to the number of the first data buffers in a direction in which the error pulse decreases.

  An image forming apparatus according to another aspect of the present invention includes an image carrier, a motor that drives the image carrier, an encoder, and the motor control device. The encoder outputs an encoder pulse signal synchronized with the rotation of the motor. The motor control device adjusts electric power supplied to the motor.

  A motor control method according to another aspect of the present invention includes a target cycle recording step, a measurement cycle recording step, a phase error calculation step, and a power adjustment step. In the target cycle recording step, each time a reference pulse signal is generated, target cycle data representing an elapsed time from the previous generation of the reference pulse signal is stored in a first ring buffer having three or more first data buffers. The step of sequentially recording each of the first data buffers. In the measurement cycle recording step, every time an encoder pulse signal synchronized with the rotation of the motor is generated, measurement cycle data representing the elapsed time from the previous generation of the encoder pulse signal is the same as the number of the first data buffers. Recording in the second data buffer in the second ring buffer having the second data buffer. In the phase error calculation step, the target period data and the measurement period data sequentially recorded in the first data buffer and the second data buffer corresponding to each other in the first ring buffer and the second ring buffer, respectively. This is a step of calculating a phase error by integrating the differences. The power adjustment step is a step of adjusting the power supplied to the motor in a direction in which the phase error is reduced.

  The motor control method according to another aspect of the present invention includes the target cycle recording step, the measurement cycle recording step, the phase error calculation step, the error pulse count step, the first power adjustment step, and the second power. Adjusting step. The error pulse counting step is a step of counting error pulses of the encoder pulse signal with respect to the reference pulse signal. The first power adjustment step is a step of adjusting the power supplied to the motor in a direction in which the phase error is reduced when the error pulse is less than the number of the first data buffers. The second power adjustment step is a step of adjusting the power supplied to the motor in a direction in which the error pulse decreases when the error pulse is equal to or greater than the number of the first data buffers.

  According to another aspect of the present invention, there is provided a method for controlling an image forming apparatus, comprising: an image carrier; a motor that drives the image carrier; and an encoder that outputs an encoder pulse signal synchronized with the rotation of the motor. A method for controlling an apparatus. In this control method, the electric power supplied to the motor is adjusted by the motor control method.

  According to the present invention, it is possible to provide a motor control device, an image forming apparatus, a motor control method, and an image forming apparatus control method capable of controlling the position of the motor with high accuracy even when the rotational speed of the motor is changed. Is possible.

FIG. 1 is a configuration diagram of an image forming apparatus according to the first embodiment of the present invention. FIG. 2 is a block diagram of the motor control device according to the first embodiment of the present invention. FIG. 3 is a block diagram of the phase comparison unit in the motor control device according to the first embodiment of the present invention. FIG. 4 is a diagram illustrating a memory map of the first ring buffer in the phase comparison unit of the motor control device according to the first embodiment of the present invention. FIG. 5 is a diagram illustrating a memory map of the second ring buffer in the phase comparison unit of the motor control device according to the first embodiment of the present invention. FIG. 6 is a diagram illustrating an example of a time chart of the reference pulse signal and the encoder pulse signal input by the phase comparison unit of the motor control device according to the first embodiment of the present invention. FIG. 7 is a block diagram of a motor control device according to the second embodiment of the present invention. FIG. 8 is a block diagram of a motor control device according to the third embodiment of the present invention. FIG. 9 is a diagram illustrating a memory map of the first ring buffer in the phase comparison unit of the motor control device according to the third embodiment of the present invention. FIG. 10 is a diagram illustrating a memory map of the second ring buffer in the phase comparison unit of the motor control device according to the third embodiment of the present invention. FIG. 11 is a diagram illustrating an example of a time chart of the reference pulse signal and the encoder pulse signal input by the phase comparison unit of the motor control device according to the third embodiment of the present invention. FIG. 12 is a diagram illustrating an example of a time chart of the reference pulse signal and the encoder pulse signal when the control mode of the motor control device according to the third embodiment of the present invention is switched from the first mode to the second mode. FIG. 13 is a diagram illustrating an example of a time chart of the reference pulse signal and the encoder pulse signal when the control mode of the motor control device according to the third embodiment of the present invention is switched from the second mode to the first mode. FIG. 14 is a block diagram of a motor control device according to the fourth embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the following embodiment is an example which actualized this invention, Comprising: It does not have the character which limits the technical scope of this invention.

[First Embodiment]
First, the configuration of the image forming apparatus 10 according to the first embodiment of the present invention will be described with reference to FIG. The image forming apparatus 10 is an electrophotographic image forming apparatus. As shown in FIG. 1, the image forming apparatus 10 includes a sheet supply unit 2, a sheet conveying unit 3, an image forming unit 4, an optical scanning unit 5, a fixing device 6, and a control unit 8 in a casing 100.

  The image forming apparatus 10 is, for example, a printer, a copier, a facsimile machine, or a multifunction machine. The multifunction device is a device that has both the function of the printer and the function of the copier.

  The sheet supply unit 2 includes a sheet receiving unit 21 and a sheet sending unit 22. The sheet receiving portion 21 is configured to be able to stack a plurality of recording sheets 9. The recording sheet 9 is a sheet-like image forming medium such as paper, coated paper, postcard, envelope, and OHP sheet.

  The sheet feeding unit 22 rotates in contact with the recording sheet 9 to send the recording sheet 9 from the sheet receiving unit 21 toward the conveyance path 30.

  The sheet conveyance unit 3 includes a registration roller 31, a conveyance roller 32, a discharge roller 33, and the like. The registration roller 31 and the conveyance roller 32 convey the recording sheet 9 supplied from the sheet supply unit 2 toward the image forming unit 4. Further, the discharge roller 33 discharges the recording sheet 9 after image formation from the discharge port of the transport path 30 onto the discharge tray 101.

  The image forming unit 4 forms an image on the surface of the recording sheet 9 that is supplied from the sheet feeding unit 22 and is moving along the conveyance path 30. The image forming unit 4 includes a drum-shaped photoconductor 41, a charging unit 42, a developing unit 43, a transfer unit 45, a cleaning unit 47, a motor 40, a rotation driving mechanism 401, and the like. The photoreceptor 41 is an example of an image carrier.

  The photoconductor 41 rotates, and the charging unit 42 uniformly charges the surface of the photoconductor 41. In the charging unit 42, the charging roller 421 included in the charging unit 42 rotates to face the rotating photoconductor 41 to charge the photoconductor 41.

  The optical scanning unit 5 writes an electrostatic latent image on the photoconductor 41 by laser light irradiation. The developing unit 43 includes a developing roller 431 that develops the electrostatic latent image by supplying a developer to the photoreceptor 41.

  The transfer unit 45 transfers the image (developer) on the surface of the photoconductor 41 to the recording sheet 9 that is moving along the conveyance path 30. Finally, the cleaning unit 47 removes the developer remaining on the surface of the photoreceptor 41.

  The motor 40 drives the photosensitive member 41 and other rotating members disposed around the photosensitive member 41. For example, the motor 40 is a drive source that drives the photoconductor 41, the charging roller 421, the developing roller 431, and the like. The rotation drive mechanism 401 is a gear mechanism or the like interlocking with the motor 40, and transmits the rotational force of the motor 40 to the photosensitive member 41 and other rotating members around it.

  The motor 40 is a servo motor, for example, a DC motor such as a DC brushless motor. An encoder 400 is attached to the motor 40. The encoder 400 outputs an encoder pulse signal Pe (see FIG. 2) that is a pulse signal synchronized with the rotation of the motor 40.

  The encoder pulse signal Pe is generated every time the motor 40 rotates by a unit angle. The unit angle is determined by the resolution of the encoder 400. The encoder pulse signal is input to the control unit 8.

  In the fixing device 6, a heating roller 61 that encloses a heater 611 and a pressure roller 62 that faces the heater 611 send the recording sheet 9 on which an image is formed between them to a subsequent process. Accordingly, the fixing device 6 heats the developer on the recording sheet 9 and fixes the image on the recording sheet 9.

  The control unit 8 includes a motor control device 80 that controls the motor 40. The control unit 8 further includes an MPU (Micro Processor Unit) for controlling devices other than the motor 40 included in the image forming apparatus 10, a memory, a signal interface, and the like.

  The motor control device 80 controls the rotational speed and rotational position (orientation) of the motor 40 by adjusting the power supplied to the motor 40. That is, the motor control device 80 performs feedback control to adjust the supplied power in a direction in which the difference between the target position of the motor 40 and the measurement position (detection position) of the motor 40 is reduced. The target position is given as a reference pulse signal Ps (see FIG. 2) described later.

  When the difference between the count numbers of the reference pulse signal Ps and the encoder pulse signal Pe is used as a feedback control deviation of the motor 40, the deviation of less than one pulse becomes a dead zone in the motor control. In this case, it is difficult to maintain the deviation below one pulse, and the resolution of position measurement based on the encoder pulse signal is limited, and it is difficult to control the position of the motor 40 with high accuracy.

  It is also conceivable that the difference between the generation periods of two pulse signals (the reference pulse signal Ps and the encoder pulse signal Pe) is used as a deviation in the feedback control of the motor. In this case, when the deviation exceeds the generation period of one of the two pulse signals, information on the difference between the target position and the measurement position is lost. Therefore, if the difference between the target position and the measurement position becomes large when the speed of the motor 40 is changed when the motor 40 is started and stopped, the position of the motor cannot be controlled.

  On the other hand, the motor control device 80 according to the present embodiment has a configuration shown below, and controls the position of the motor 40 in the rotational direction with high accuracy even when the rotational speed of the motor 40 is changed. Can do.

[Details of motor control device]
Next, details of the motor control device 80 will be described with reference to FIGS. As shown in FIG. 2, the motor control device 80 includes a reference pulse generation unit 81, a phase comparison unit 82, and a motor power adjustment unit 83.

  The reference pulse generator 81 generates a reference pulse signal Ps that serves as a reference for a target position in the rotation direction of the motor 40. For example, the reference pulse generator 81 includes a target speed calculator 811, a low-pass filter processor 812, and a voltage controlled oscillator 813. The target speed calculation unit 811 calculates a primary target speed Vx that is a rotation speed of the motor 40 necessary for operating the photoconductor 41 in accordance with a predetermined rule.

  The low-pass filter processing unit 812 performs low-pass filter processing on a signal having a level corresponding to the primary target speed Vx. The voltage controlled oscillator 813 generates the reference pulse signal Ps which is a pulse signal having a frequency corresponding to the signal of the secondary target speed Vy after the low pass filter process.

  The phase comparator 82 calculates a phase error PHE that is an integrated value of the phase difference between the reference pulse signal Ps and the encoder pulse signal Pe. Details of the phase comparator 82 will be described later.

  The motor power adjustment unit 83 adjusts the power supplied to the motor 40 in a direction in which the phase error PHE is reduced. For example, the motor power adjustment unit 83 includes a proportional element amplifier 831, an integrator 832, an integration element amplifier 833, an adder 834, a pulse width modulation unit 835, and a motor drive circuit 836. The direction in which the phase error PHE is reduced can be said to be the direction in which the phase error PHE is converged to 0 or the direction in which the phase error PHE is eliminated.

  The proportional element amplifier 831 is an amplifier that generates a proportional control signal Xp reflecting the proportional element of the phase error PHE by amplifying a signal corresponding to the phase error PHE with a preset proportional gain.

  The integrator 832 performs an integration process on a signal corresponding to the phase error PHE. The integral element amplifier 833 generates an integral control signal Xi that reflects the integral element of the phase error PHE by amplifying a signal corresponding to the integral value of the phase error PHE with a preset integral gain. Amplifier.

  The adder 834 adds the proportional control signal Xp and the integral control signal Xi to generate a power supply amount signal Xo indicating the magnitude of power supplied to the motor 40. That is, the proportional element amplifier 831, the integrator 832, the integral element amplifier 833, and the adder 834 are control units that adjust the power supplied to the motor 40 by so-called PI control.

  The pulse width modulation unit 835 performs pulse width modulation processing on the power supply amount signal Xo to generate a pulse width modulation signal Pc whose pulse width is adjusted at a duty ratio corresponding to the level of the power supply amount signal Xo. .

  The motor drive circuit 836 is a circuit that generates a drive pulse signal Pd that is a pulsed motor drive power signal synchronized with the pulse width modulation signal Pc. The drive pulse signal Pd is supplied to the motor 40.

  In other words, the pulse width modulation unit 835 has a duty ratio of the drive pulse signal Pd supplied to the motor 40 in accordance with an input signal (the power supply amount signal Xo) in which a proportional element and an integral element of the phase error PHE are reflected. Adjust the ratio. Thereby, the electric power supplied to the motor 40 is adjusted according to the phase error PHE.

  The step of adjusting the power supplied to the motor 40 by the motor power adjustment unit 83 is an example of the power adjustment step. In addition, the step of adjusting the duty ratio of the drive pulse signal Pd by the pulse width modulation unit 835 is an example of the pulse width modulation step.

  For example, portions other than the motor drive circuit 836 in the motor control device 80 are configured by a combination of a microcomputer, an ASIC (Application Specific Integrated Circuit), other semiconductor devices, and other electronic circuits. The various operations shown below can be realized not only by the microcomputer executing a program stored in advance in a memory but also by hardware such as a logic operation circuit.

  As shown in FIG. 3, the phase comparison unit 82 includes a memory 820, a target cycle recording unit 821, a measurement cycle recording unit 822, and a phase error calculation unit 823. The memory 820 is a data storage medium accessed from each of the target cycle recording unit 821, the measurement cycle recording unit 822, and the phase error calculation unit 823. The data storage area of the memory 820 includes a first ring buffer 824 area and a second ring buffer 825 area.

  4 and 5 are diagrams illustrating examples of memory maps of the first ring buffer 824 and the second ring buffer 825. FIG. The first ring buffer 824 includes three or more data buffers. The second ring buffer 825 includes the same number of data buffers as the number of data buffers of the first ring buffer 824.

  In the following description, the data buffer included in the first ring buffer 824 is referred to as a first data buffer 8240. Similarly, the data buffer included in the second ring buffer 825 is referred to as a second data buffer 8250. FIG. 4 shows a memory map of the first ring buffer 824 having 16 first data buffers 8240 with buffer numbers 0-15. Similarly, FIG. 5 shows a memory map of the second ring buffer 825 having 16 second data buffers 8250 with buffer numbers 0-15. 4 and 5, the buffer numbers 3 to 12 are omitted.

  Hereinafter, the processing of the target cycle recording unit 821, the measurement cycle recording unit 822, and the phase error calculation unit 823 will be described in more detail with reference to the time chart of FIG. The example shown in FIG. 6 is an example in the case where the phase delay of the encoder pulse signal Pe with respect to the reference pulse signal Ps occurs.

  Further, in the example shown in FIG. 6 for convenience, the phase delay of the encoder pulse signal Pe with respect to the reference pulse signal Ps increases with time. However, in practice, the phase difference is reduced by the control of the motor control device 80.

  In the following description, integer variables i, j, and k are variables that are counted up one by one from the initial value 0 and circulate in the range of 0 to 15. That is, the variables i, j, and k return to 0 when they are counted up from 15. In other words, when i = 0, i-1 = 15.

  The target cycle recording unit 821 generates target cycle data Tref representing the elapsed time from the previous generation of the reference pulse signal Ps each time the reference pulse signal Ps is generated, in the first ring buffer 824. Data is sequentially recorded in each of the data buffers 8240. At this time, the target cycle recording unit 821 notifies the phase error calculation unit 823 of the number of the first data buffer 8240 in which the latest target cycle data Tref is recorded.

  The process in which the target period recording unit 821 calculates and records the target period data Tref is an example of the target period recording process.

  In the example of FIG. 6, at each of the rising edge timings t1, t3, t5, t6, t8, and t10 of the reference pulse signal Ps, the target period recording unit 821 uses the target period data Tref determined at that time Recording is performed in each of the first data buffers 8240 having buffer numbers 0 to 5. Further, at each of the timings t1, t3, t5, t6, t8, and t10, the target cycle recording unit 821 has the numbers 0, 1, 2, and 3 of the first data buffer 8240 that is the data recording destination at each time point. , 4, 5 are notified to the phase error calculation unit 823.

  The i-th target cycle data Tref (i) recorded when the i-th reference pulse signal Ps (i) is generated is the (i-1) -th reference pulse signal Ps (i-1). This is data representing the elapsed time from the time of occurrence to the time of generation of the i-th reference pulse signal Ps (i). However, the target cycle data Tref (0), which is the initial value of the target cycle data, is the elapsed time from the start of processing until the first (0th) reference pulse signal Ps (0) is generated. is there.

  The measurement cycle recording unit 822 generates measurement cycle data Tenc representing the elapsed time from the previous generation of the encoder pulse signal Pe every time the encoder pulse signal Pe is generated, in the second ring buffer 825. Data is sequentially recorded in each data buffer 8250. At this time, the measurement cycle recording unit 822 notifies the phase error calculation unit 823 of the number of the second data buffer 8250 in which the latest measurement cycle data Tenc is recorded.

  The process in which the measurement cycle recording unit 822 calculates and records the measurement cycle data Tenc is an example of the measurement cycle recording process.

  In the example of FIG. 6, at each of the rising edge timings t2, t4, t7, and t9 of the encoder pulse signal Pe, the measurement cycle recording unit 822 uses the buffer number 0 as the measurement cycle data Tenc determined at that time. To No. 3 to the second data buffer 8250. Further, at each of timings t2, t4, t7, and t9, the measurement cycle recording unit 822 sets the numbers 0, 1, 2, and 3 of the second data buffer 8250, which is the data recording destination at each time point, as the phase error. The calculation unit 823 is notified.

  The j-th measurement period data Tenc (j) recorded when the j-th encoder pulse signal Pe (j) is generated is the (j-1) -th encoder pulse signal Pe (j-1). This is data representing the elapsed time from the time of occurrence to the time of occurrence of the j-th encoder pulse signal Pe (j). However, the measurement cycle data Tenc (0), which is the initial value of the measurement cycle data, is the elapsed time from the start of processing until the first (0th) encoder pulse signal Pe (0) is generated. is there.

  In addition, the target cycle data Tref (i) and the measurement cycle data Tenc (j) are numeric data in units of time such as milliseconds, for example, and numeric data representing the count-up number of a predetermined clock signal. It can be considered that.

  The phase error calculation unit 823 is configured to sequentially record the target period data Tref recorded in the first data buffer 8240 and the second data buffer 8250 corresponding to each other in the first ring buffer 824 and the second ring buffer 825, respectively. The phase error PHE is calculated by integrating the difference between the measurement cycle data Tenc.

  The first data buffer 8240 and the second data buffer 8250 correspond to each other in the same order in which the target cycle data Tref and the measurement cycle data Tenc are recorded. In the above example, each of the 0th, 1st, 2nd... 15th first data buffers 8240 and each of the 0th, 1st, 2nd... 15th second data buffers 8250 and Are in a mutually corresponding relationship.

  The phase error calculator 823 calculates the phase error PHE every time data is recorded in both the first ring buffer 824 and the second ring buffer 825 corresponding to each other.

More specifically, each time data is recorded in both the k-th (0 to 15) first ring buffer 824 and the second ring buffer 825, the phase error calculation unit 823 performs the following (1 ) To calculate the (k + 1) -th phase error PHE (k + 1). However, the initial value of the phase error PHE (0) is zero.

  Equation (1) is an equation for accumulating the difference between the target cycle data Tref and the measurement cycle data Tenc that are sequentially recorded in the first data buffer 8240 and the second data buffer 8250 that correspond to each other. The phase error PHE that is an integrated value of the difference corresponds to an error (position error) of a measurement position with respect to a target position in the rotation direction of the motor 40. Unlike the general phase difference that changes only within a range of less than one period of the reference pulse signal Ps, the phase error PHE can change within a range exceeding one period of the reference pulse signal Ps.

  When the phase error PHE (k + 1) calculated by the equation (1) is 0, the phase of the reference pulse signal Ps and the phase of the encoder pulse signal Pe match. When the value of the phase error PHE (k + 1) calculated by the equation (1) is a positive value, the phase of the reference pulse signal Ps is ahead of the phase of the encoder pulse signal Pe. When the value of the phase error PHE (k + 1) calculated by the equation (1) is a negative value, the phase of the reference pulse signal Ps is delayed from the phase of the encoder pulse signal Pe.

  For example, when the phase of the reference pulse signal Ps is ahead of the phase of the encoder pulse signal Pe or both phases are the same, the phase error calculation unit 823 notifies the number j from the measurement cycle recording unit 822. Each time, k = j, the (k + 1) -th phase error PHE (k + 1) is calculated.

  On the other hand, when the phase of the reference pulse signal Ps is delayed from the phase of the encoder pulse signal Pe, the phase error calculation unit 823 receives the number i from the target period recording unit 821 and k = The (k + 1) -th phase error PHE (k + 1) is calculated as i.

  The step in which the phase error calculation unit 823 calculates the phase error PHE is an example of a phase error calculation step.

  In the example shown in FIG. 6, the data recording to both the 0th first data buffer 8240 and the 0th second data buffer 8250 corresponding thereto is completed at the timing t2. Therefore, the phase error calculation unit 823 applies the 0th target cycle data Tref (0) and the 0th measurement cycle data Tenc (0) to the equation (1) to thereby obtain the first phase error. PHE (1) is calculated.

  Similarly, the data recording to both the first first data buffer 8240 and the first second data buffer 8250 corresponding thereto is completed at the timing t4. Therefore, the phase error calculation unit 823 applies the first target cycle data Tref (1) and the first measurement cycle data Tenc (1) to the equation (1), so that the second phase error is calculated. PHE (2) is calculated.

  In addition, at each time point of timings t7 and t9, the phase error calculation unit 823 similarly calculates the third and fourth phase errors PHE (3) and PHE (4).

  The latest phase error PHE sequentially calculated as described above is input to the motor power adjustment unit 83. Accordingly, the motor power adjustment unit 83 adjusts the power supplied to the motor 40 in a direction in which the phase error PHE is reduced.

  If the motor control device 80 is employed, the phase error PHE that is an integrated value of the difference between the generation periods of the reference pulse signal Ps and the encoder pulse signal Pe is used as a deviation in feedback control of the motor 40. Therefore, even if the phase error PHE (deviation) is a time difference of less than one pulse, the power supplied to the motor 40 is adjusted in such a direction that the time difference disappears. Therefore, the resolution of position measurement based on the encoder pulse signal Pe does not become a restriction on control performance, and the position of the motor 40 can be controlled with high accuracy.

  Further, the three or more recent target cycle data Tref and the measurement cycle data Tenc are stored in two ring buffers. Therefore, even if the phase difference (deviation) between the reference pulse signal Ps and the encoder pulse signal Pe exceeds the generation period of one of the two pulse signals, the correct phase error PHE is calculated.

  That is, if each of the two ring buffers 824 and 825 has N data buffers, the phase difference between the two pulse signals is (N−1) times the generation period of one of the two pulse signals. Even if it becomes, the information on the difference between the target position of the motor 40 and the measurement position is not lost. Therefore, even when the speed of the motor 40 is changed relatively large, such as when the motor 40 is started and stopped, that is, even when the difference between the target position and the measurement position becomes large, the position of the motor 40 Can be controlled correctly.

  In the motor power adjustment unit 83, the pulse width modulation unit 835 is supplied to the motor 40 in accordance with an input signal (the power supply amount signal Xo) reflecting a proportional element of the phase error PHE. The duty ratio of the pulse signal Pd is adjusted. Such control is effective as control for quickly reducing the phase error PHE.

  In the present embodiment, the pulse width modulation unit 835 further includes the drive pulse signal Pd supplied to the motor 40 in accordance with an input signal (the power supply amount signal Xo) that also reflects an integral element of the phase error PHE. Adjust the duty ratio. Thereby, it is possible to prevent an offset from occurring in the position control of the motor 40.

[Second Embodiment]
Next, a motor control device 80A according to a second embodiment of the present invention will be described with reference to FIG. FIG. 7 is a block diagram of the motor control device 80A. In FIG. 7, the same components as those shown in FIG. 2 are given the same reference numerals. Hereinafter, differences of the motor control device 80A from the motor control device 80 will be described.

  The motor control device 80A has a configuration in which a target speed detection unit 84, an actual measurement level detection unit 85, a subtractor 86, a speed feedback control amplifier 87, and a feedforward control amplifier 88 are added to the configuration of the motor control device 80. Have.

  The target speed detector 84 detects (calculates) the target rotational speed of the motor 40 by calculating the reciprocal of the generation period of the reference pulse signal Ps. Similarly, the actual measurement degree detection unit 85 detects (calculates) the actual rotational speed of the motor 40 by calculating the reciprocal of the generation period of the encoder pulse signal Pe.

  The subtractor 86 calculates a speed deviation that is a difference between the target rotation speed and the actual rotation speed. The speed feedback control amplifier 87 is an amplifier that generates a speed control signal that reflects the speed deviation by amplifying a signal corresponding to the speed deviation with a preset gain.

  The feedforward control amplifier 88 is an amplifier that amplifies a signal corresponding to the target rotation speed with a preset gain to generate a feedforward control signal in which an element of the change in the target rotation speed is reflected. is there.

  The speed control signal and the feedforward control signal are added together with the proportional control signal Xp and the integral control signal Xi by the adder 834 and reflected in the power supply amount signal Xo.

  The image forming apparatus according to the second embodiment of the present invention has a configuration in which the motor control device 80 in the image forming device 10 is replaced with the motor control device 80A.

  As described above, the motor control device 80A performs feedback control and feedforward control based on the rotational speed of the motor 40 in parallel with feedback control based on the phase error PHE. Thereby, the phase error PHE can be reduced more quickly.

[Third Embodiment: Details of Motor Control Device]
Next, the details of the motor control device 80B according to the third embodiment will be described with reference to FIGS. In the present embodiment, the control unit 8 of the image forming apparatus 10 includes a motor control device 80 </ b> B that controls the motor 40 instead of the motor control device 80. As shown in FIG. 8, the motor control device 80B includes a reference pulse generation unit 81, a phase comparison unit 82, a first power adjustment unit 83, an error pulse count unit 84, a second power adjustment unit 85, a signal selection unit 86, A motor drive signal generation unit 87 is provided. Hereinafter, differences of the motor control device 80B from the motor control device 80 will be described.

  As described above, the reference pulse generator 81 generates the reference pulse signal Ps that serves as a reference for the target position in the rotation direction of the motor 40. Further, as described above, the phase comparator 82 calculates a phase error PHE that is a phase difference between the reference pulse signal Ps and the encoder pulse signal Pe (see FIG. 8).

  The first power adjustment unit 83 generates a first control signal X1 that is a control signal for adjusting the power supplied to the motor 40 in a direction in which the phase error PHE is reduced. For example, the first power adjustment unit 83 includes a proportional element amplifier 831, an integrator 832, an integral element amplifier 833, and an adder 834.

  The proportional element amplifier 831 is an amplifier that generates a proportional control signal Xp reflecting the proportional element of the phase error PHE by amplifying a signal corresponding to the phase error PHE with a preset proportional gain.

  The integrator 832 performs an integration process on a signal corresponding to the phase error PHE. The integral element amplifier 833 generates an integral control signal Xi that reflects the integral element of the phase error PHE by amplifying a signal corresponding to the integral value of the phase error PHE with a preset integral gain. Amplifier.

  The adder 834 generates a first control signal X1 representing the magnitude of power supplied to the motor 40 by adding the proportional control signal Xp and the integral control signal Xi.

  The first control signal X1 is a signal representing the magnitude of power supplied to the motor 40. The proportional element amplifier 831, the integrator 832, the integral element amplifier 833, and the adder 834 are control units that adjust the power supplied to the motor 40 by so-called PI control.

  The error pulse count unit 84 counts error pulses EP of the encoder pulse signal Pe with respect to the reference pulse signal Ps. The error pulse EP is a difference in the number of occurrences of the encoder pulse signal Pe with respect to the number of occurrences of the reference pulse signal Ps. The error pulse EP is input to the second power adjustment unit 85 and the signal selection unit 86. Further, it is conceivable that the error pulse EP is input to the phase comparator 82.

  The error pulse EP is a parameter representing the deviation of the measurement position with respect to the target position in the rotation direction of the motor 40 by the number of pulses. The error pulse EP is also referred to as a droop pulse or a deviation pulse. The process in which the error pulse counting unit 84 counts the error pulse EP is an example of an error pulse counting process.

  The second power adjustment unit 85 generates a second control signal X2 that is a control signal for adjusting the power supplied to the motor 40 in a direction in which the error pulse EP decreases. The second control signal X2 is a signal representing the magnitude of power supplied to the motor 40.

  For example, the second power adjustment unit 85 is an amplifier that generates the second control signal X2 by amplifying a signal corresponding to the error pulse EP with a preset proportional gain.

  The signal selection unit 86 selects one of the first control signal X1 and the second control signal X2 according to the magnitude of the error pulse EP, and sends the selected signal to the motor drive signal generation unit 87 in the subsequent stage. Output. Hereinafter, the signal selected by the signal selector 86 is referred to as a power supply amount signal Xo.

  It can be said that the signal selector 86 is a so-called signal switch. A method by which the signal selection unit 86 selects a control signal based on the error pulse EP will be described later.

  The motor drive signal generation unit 87 supplies power corresponding to the power supply amount signal Xo to the motor 40. For example, the motor drive signal generation unit 87 includes a low pass filter processing unit 871, a pulse width modulation unit 872, and a motor drive circuit 873.

  The low-pass filter processing unit 871 performs low-pass filter processing on the power supply amount signal Xo. The power supply amount signal Xo after the low-pass filter processing is input to the pulse width modulator 872. The low-pass filter processing unit 871 prevents a sudden change in the input signal of the pulse width modulation unit 872 when the selection state of the signal selection unit 86 changes.

  The pulse width modulation unit 872 performs pulse width modulation processing on the power supply amount signal Xo after the low-pass filter processing, and thereby the pulse width modulation whose pulse width is adjusted with a duty ratio corresponding to the level of the power supply amount signal Xo. A signal Pc is generated.

  The motor drive circuit 873 is a circuit that generates a drive pulse signal Pd that is a pulsed motor drive power signal synchronized with the pulse width modulation signal Pc. The drive pulse signal Pd is supplied to the motor 40.

  In the following description, the control mode of the motor control device 80B when the signal selection unit 86 selects the first control signal X1 is referred to as a first mode. The control mode of the motor control device 80B when the signal selection unit 86 selects the second control signal X2 is referred to as a second mode.

  When the control mode is the first mode, the pulse width modulator 872 causes the motor 40 to respond to an input signal (the first control signal X1) in which the proportional and integral elements of the phase error PHE are reflected. The duty ratio of the drive pulse signal Pd supplied to is adjusted. As a result, the power supplied to the motor 40 is adjusted in the direction in which the phase error PHE is reduced. Note that the step of adjusting the duty ratio of the drive pulse signal Pd by the pulse width modulator 872 is an example of the pulse width modulation step.

  On the other hand, when the control mode is the second mode, the pulse width modulation unit 872 causes the motor 40 to respond to an input signal (the second control signal X2) that reflects the magnitude of the error pulse EP. The duty ratio of the supplied drive pulse signal Pd is adjusted. As a result, the power supplied to the motor 40 is adjusted so that the error pulse EP decreases.

  For example, a portion other than the motor drive circuit 872 in the motor control device 80B is configured by a combination of a microcomputer, an ASIC (Application Specific Integrated Circuit), other semiconductor devices, and other electronic circuits. The various operations shown below can be realized not only by the microcomputer executing a program stored in advance in a memory but also by hardware such as a logic operation circuit.

  As shown in FIG. 3, the phase comparison unit 82 includes a memory 820, a target cycle recording unit 821, a measurement cycle recording unit 822, and a phase error calculation unit 823. The memory 820 is a data storage medium accessed from each of the target cycle recording unit 821, the measurement cycle recording unit 822, and the phase error calculation unit 823. The data storage area of the memory 820 includes a first ring buffer 824 area and a second ring buffer 825 area.

  FIGS. 9 and 10 are diagrams showing examples of memory maps of the first ring buffer 824 and the second ring buffer 825, respectively. The first ring buffer 824 includes three or more data buffers. The second ring buffer 825 includes the same number of data buffers as the number of data buffers of the first ring buffer 824.

  In the following description, the data buffer included in the first ring buffer 824 is referred to as a first data buffer 8240. Similarly, the data buffer included in the second ring buffer 825 is referred to as a second data buffer 8250. FIG. 9 shows a memory map of the first ring buffer 824 having four first data buffers 8240 with buffer numbers 0-3. Similarly, FIG. 10 shows a memory map of the second ring buffer 825 having four second data buffers 8250 with buffer numbers 0 to 3.

  Hereinafter, the processes of the target cycle recording unit 821, the measurement cycle recording unit 822, and the phase error calculation unit 823 will be described more specifically with reference to the time chart of FIG. The example shown in FIG. 11 is an example in the case where a phase delay of the encoder pulse signal Pe with respect to the reference pulse signal Ps occurs.

  For convenience, in the example shown in FIG. 11, the phase delay of the encoder pulse signal Pe with respect to the reference pulse signal Ps increases with time. However, in practice, the phase difference is reduced by the control of the motor control device 80B.

  In the following description, integer variables i, j, and k are variables that are counted up one by one from the initial value 0 and circulate in the range of 0 to 3. That is, the variables i, j, and k return to 0 when they are counted up from 3. In other words, when i = 0, i-1 = 3.

  The target cycle recording unit 821 generates target cycle data Tref representing the elapsed time from the previous generation of the reference pulse signal Ps each time the reference pulse signal Ps is generated, in the first ring buffer 824. Data is sequentially recorded in each of the data buffers 8240. At this time, the target cycle recording unit 821 notifies the phase error calculation unit 823 of the number of the first data buffer 8240 in which the latest target cycle data Tref is recorded.

  The process in which the target period recording unit 821 calculates and records the target period data Tref is an example of the target period recording process.

  In the example of FIG. 11, at each of the rising edge timings t1, t3, t5, t6, t8, and t10 of the reference pulse signal Ps, the target cycle recording unit 821 uses the target cycle data Tref determined at that time as the The data is recorded in each of the first data buffers 8240 with buffer numbers 0, 1, 2, 3, 0, and 1. Further, at each of the timings t1, t3, t5, t6, t8, and t10, the target cycle recording unit 821 has the numbers 0, 1, 2, and 3 of the first data buffer 8240 that is the data recording destination at each time point. , 0, 1 are notified to the phase error calculator 823.

  The i-th target cycle data Tref (i) recorded when the i-th reference pulse signal Ps (i) is generated is the (i-1) -th reference pulse signal Ps (i-1). This is data representing the elapsed time from the time of occurrence to the time of generation of the i-th reference pulse signal Ps (i). However, the target cycle data Tref (0), which is the initial value of the target cycle data, is the elapsed time from the start of processing until the first (0th) reference pulse signal Ps (0) is generated. is there.

  The measurement cycle recording unit 822 generates measurement cycle data Tenc representing the elapsed time from the previous generation of the encoder pulse signal Pe every time the encoder pulse signal Pe is generated, in the second ring buffer 825. Data is sequentially recorded in each data buffer 8250. At this time, the measurement cycle recording unit 822 notifies the phase error calculation unit 823 of the number of the second data buffer 8250 in which the latest measurement cycle data Tenc is recorded.

  The process in which the measurement cycle recording unit 822 calculates and records the measurement cycle data Tenc is an example of the measurement cycle recording process.

  In the example of FIG. 11, at each of the rising edge timings t2, t4, t7, and t9 of the encoder pulse signal Pe, the measurement cycle recording unit 822 uses the buffer number 0 as the measurement cycle data Tenc determined at that time. To No. 3 to the second data buffer 8250. Further, at each of timings t2, t4, t7, and t9, the measurement cycle recording unit 822 sets the numbers 0, 1, 2, and 3 of the second data buffer 8250, which is the data recording destination at each time point, as the phase error. The calculation unit 823 is notified.

  The j-th measurement period data Tenc (j) recorded when the j-th encoder pulse signal Pe (j) is generated is the (j-1) -th encoder pulse signal Pe (j-1). This is data representing the elapsed time from the time of occurrence to the time of occurrence of the j-th encoder pulse signal Pe (j). However, the measurement cycle data Tenc (0), which is the initial value of the measurement cycle data, is the elapsed time from the start of processing until the first (0th) encoder pulse signal Pe (0) is generated. is there.

  In addition, the target cycle data Tref (i) and the measurement cycle data Tenc (j) are numeric data in units of time such as milliseconds, for example, and numeric data representing the count-up number of a predetermined clock signal. It can be considered that.

  The phase error calculation unit 823 is configured to sequentially record the target period data Tref recorded in the first data buffer 8240 and the second data buffer 8250 corresponding to each other in the first ring buffer 824 and the second ring buffer 825, respectively. The phase error PHE is calculated by integrating the difference between the measurement cycle data Tenc.

  The first data buffer 8240 and the second data buffer 8250 correspond to each other in the same order in which the target cycle data Tref and the measurement cycle data Tenc are recorded. In the above example, the 0th, 1st, 2nd and 3rd first data buffers 8240 and the 0th, 1st, 2nd and 3rd second data buffers 8250 correspond to each other. Have a relationship.

  The phase error calculator 823 calculates the phase error PHE every time data is recorded in both the first ring buffer 824 and the second ring buffer 825 corresponding to each other.

  For example, whenever the phase error calculation unit 823 records data in both the k-th (0-3) first ring buffer 824 and the second ring buffer 825, the equation (1) shown above The (k + 1) th phase error PHE (k + 1) can be calculated according to However, the initial value of the phase error PHE (0) is zero.

When the phase (position) of the encoder pulse signal Pe is delayed with respect to the phase (position) of the reference pulse signal Ps, the phase error calculation unit 823 performs the (k + 1) -th operation according to the following equation (2). It is also conceivable to calculate the phase error PHE (k + 1). However, g1 in the equation (2) is the number of pulses that the encoder pulse signal Pe is delayed with respect to the reference pulse signal Ps at the time of calculation. That is, the magnitude of the error pulse EP when the phase (position) of the encoder pulse signal Pe is delayed is g1.

Similarly, when the phase (position) of the encoder pulse signal Pe is advanced with respect to the phase (position) of the reference pulse signal Ps, the phase error calculator 823 (k + 1) according to the following equation (3): It is also conceivable to calculate the th phase error PHE (k + 1). However, g2 in the equation (3) is the number of pulses that the encoder pulse signal Pe advances with respect to the reference pulse signal Ps at the time of calculation. That is, the magnitude of the error pulse EP when the phase (position) of the encoder pulse signal Pe is advanced is g2.

  Expressions (1), (2), and (3) are expressed by the target period data Tref and the measurement period data Tenc that are sequentially recorded in the first data buffer 8240 and the second data buffer 8250, respectively. This is an equation for integrating the differences.

  The phase error PHE that is an integrated value of the difference corresponds to an error (position error) of a measurement position with respect to a target position in the rotation direction of the motor 40. Unlike the general phase difference that changes only within a range of less than one period of the reference pulse signal Ps, the phase error PHE can change within a range exceeding one period of the reference pulse signal Ps.

  When the calculated phase error PHE (k + 1) is 0, the phase of the reference pulse signal Ps matches the phase of the encoder pulse signal Pe. When the value of the phase error PHE (k + 1) is a positive value, the phase of the reference pulse signal Ps is ahead of the phase of the encoder pulse signal Pe. When the value of the phase error PHE (k + 1) is a negative value, the phase of the reference pulse signal Ps is delayed from the phase of the encoder pulse signal Pe.

  For example, when the phase of the reference pulse signal Ps is ahead of the phase of the encoder pulse signal Pe or both phases are the same, the phase error calculation unit 823 notifies the number j from the measurement cycle recording unit 822. Each time, k = j, the (k + 1) -th phase error PHE (k + 1) is calculated.

  On the other hand, when the phase of the reference pulse signal Ps is delayed from the phase of the encoder pulse signal Pe, the phase error calculation unit 823 receives the number i from the target period recording unit 821 and k = The (k + 1) -th phase error PHE (k + 1) is calculated as i.

  The step in which the phase error calculation unit 823 calculates the phase error PHE is an example of a phase error calculation step.

  In the example shown in FIG. 11, the data recording to both the 0th first data buffer 8240 and the 0th second data buffer 8250 corresponding thereto is completed at the timing t2. Therefore, the phase error calculation unit 823 applies the 0th target cycle data Tref (0) and the 0th measurement cycle data Tenc (0) to the equation (1) to thereby obtain the first phase error. PHE (1) is calculated.

  Similarly, the data recording to both the first first data buffer 8240 and the first second data buffer 8250 corresponding thereto is completed at the timing t4. Therefore, the phase error calculation unit 823 applies the first target cycle data Tref (1) and the first measurement cycle data Tenc (1) to the equation (1), so that the second phase error is calculated. PHE (2) is calculated.

  Also at the time point t7, the phase error calculation unit 823 similarly calculates the third phase error PHE (3). In addition, at the timing t9, the phase error calculation unit 823 calculates the 0th phase error PHE (0) again in the same manner.

  The latest phase error PHE calculated sequentially as described above is input to the first power adjustment unit 83. Further, when the control mode is the first mode, the first power adjustment unit 83 adjusts the power supplied to the motor 40 in a direction in which the phase error PHE is reduced.

  When the control mode is the first mode, the phase error PHE that is an integrated value of the difference between the generation periods of the reference pulse signal Ps and the encoder pulse signal Pe is used as a deviation in feedback control of the motor 40. . Therefore, even if the phase error PHE (deviation) is a time difference of less than one pulse, the power supplied to the motor 40 is adjusted in such a direction that the time difference disappears. Therefore, the resolution of position measurement based on the encoder pulse signal Pe does not become a restriction on control performance, and the position of the motor 40 can be controlled with high accuracy.

  Further, the latest three or more target cycle data Tref and the measurement cycle data Tenc are stored in two ring buffers 824 and 825, respectively. Therefore, even if the phase difference (deviation) between the reference pulse signal Ps and the encoder pulse signal Pe exceeds the generation period of one of the two pulse signals, the correct phase error PHE is calculated.

  That is, if each of the two ring buffers 824 and 825 has N data buffers, the phase difference between the two pulse signals is (N−1) times the generation period of one of the two pulse signals. Even if it becomes, the information on the difference between the target position of the motor 40 and the measurement position is not lost. Therefore, even when the speed of the motor 40 is changed relatively large, such as when the motor 40 is started and stopped, that is, even when the difference between the target position and the measurement position becomes large, the position of the motor 40 Can be controlled correctly.

  In the first power adjustment unit 83, the pulse width modulation unit 871 is supplied to the motor 40 in accordance with an input signal (the power supply amount signal Xo) reflecting a proportional element of the phase error PHE. The duty ratio of the drive pulse signal Pd is adjusted. Such control is effective as control for quickly reducing the phase error PHE.

  In the present embodiment, the pulse width modulator 871 further includes the drive pulse signal Pd supplied to the motor 40 in accordance with an input signal (the power supply amount signal Xo) that also reflects the integral element of the phase error PHE. Adjust the duty ratio. Thereby, it is possible to prevent an offset from occurring in the position control of the motor 40.

  Meanwhile, when the motor 40 is started and stopped, the phase difference (the phase error PHE) between the reference pulse signal Ps and the encoder pulse signal Pe can be large. Therefore, in the phase comparison unit 82, in order to prevent the situation where the difference information between the target position and the measurement position is lost more reliably, the number of data buffers in each of the two ring buffers 824 and 825 is increased. There is a need to.

  On the other hand, in order to reduce the power consumption and cost of the motor control device 80B, it is desirable that the capacity of the memory 820 be as small as possible. Further, even when the phase error PHE becomes larger than expected, high robustness is required so that control can be surely converged.

  As described above, the motor control device 80B includes the error pulse count unit 84, the second power adjustment unit 85, and the signal selection unit 86. Accordingly, even if the number of data buffers in each of the two ring buffers 824 and 825 is small, the position control of the motor 40 can be reliably converged. This will be described below.

[Switch control mode]
The signal selection unit 86 selects the first control signal X1 when the error pulse EP is less than a predetermined threshold SL equal to or less than the number of the first data buffers 8240. As a result, the control mode becomes the first mode. The state in which the error pulse EP is less than the number of the first data buffers 8240 is a state in which information on the difference between the target position and the measurement position is not lost. For example, the threshold SL may be equal to the number of the first data buffers 8240. However, the threshold value SL is 2 or more.

  The signal selector 86 selects the second control signal X2 when at least the error pulse EP is equal to or greater than the number of the first data buffers 8240. The state where the error pulse EP is equal to or greater than the number of the first data buffers 8240 is a state where information on the difference between the target position and the measurement position is lost.

  For example, the signal selection unit 86 selects the second control signal X2 when the error pulse EP is equal to or greater than the threshold value SL. Thereby, the control mode becomes the second mode. The state where the error pulse EP is equal to or greater than the number of the first data buffers 8240 is a state where information on the difference between the target position and the measurement position is lost.

  Accordingly, the first power adjustment unit 83 adjusts the power supplied to the motor 40 when the error pulse EP is less than the number of the first data buffers 8240 in a direction in which the phase error PHE is reduced. Note that the step of adjusting the power supplied to the motor 40 by the first power adjustment unit 83 outputting the first control signal X1 is an example of a first power adjustment step.

  On the other hand, the second power adjustment unit 85 adjusts the power supplied to the motor 40 in a direction in which the error pulse EP decreases when the error pulse EP is equal to or greater than the number of the first data buffers 8240. In addition, the step of adjusting the power supplied to the motor 40 by the second power adjustment unit 85 outputting the second control signal X2 is an example of a second power adjustment step.

[Switching from the first mode to the second mode]
Hereinafter, a specific example when the control mode is switched from the first mode to the second mode will be described with reference to FIG. In the example shown below, the number N of the first data buffers 8240 and the threshold SL are both 4.

  FIG. 12 shows an example of a time chart of the reference pulse signal Ps and the encoder pulse signal Pe when the control mode of the motor control device 80B is switched from the first mode to the second mode.

  In the example of FIG. 12, at each of the rising edge timings t2, t4, t6, t7, and t9 of the reference pulse signal Ps, the target period recording unit 821 uses the target period data Tref determined at that time as the first period data. Records in each of the data buffers 8240. Similarly, at each of the rising edge timings t1, t3, t5, t8, and t10 of the encoder pulse signal Pe, the measurement cycle recording unit 822 sets the measurement cycle data Tenc determined at that time as the second data buffer 8250. Record each.

  Further, it is assumed that the phase (position) of the encoder pulse signal Pe is delayed with respect to the reference pulse signal Ps at the timing t1, and the error pulse EP is 3.

  In the time chart of FIG. 12, there is one rising edge of the reference pulse signal Ps between each of timings t1 and t3 and between timings t3 and t5. Therefore, the error pulse EP at each timing t3 and t5 is 3, which is the same as the error pulse EP at the timing t1.

  Accordingly, in the period from the timing t1 to the timing t5, the error pulse EP is less than the threshold value SL, and the signal selection unit 86 selects the first control signal X1. Therefore, the control mode in the period from timing t1 to timing t5 is the first mode. Thereby, the motor 40 is controlled with high accuracy.

  Next, between the timings t5 and t8, there are two rising edges of the reference pulse signal Ps. Furthermore, between the timings t8 and t10, there is one rising edge of the reference pulse signal Ps. Therefore, the error pulse EP at the timing t8 is increased by one from the error pulse EP at the timing t5 to 4. Further, the error pulse EP at the timing t10 is 4, which is the same as the error pulse EP at the timing t8.

  Therefore, in the period from the timing t8 to the timing t10, the error pulse EP is equal to or greater than the threshold value SL, and the signal selection unit 86 selects the second control signal X2. Therefore, the control mode in the period from timing t8 to timing t10 is the second mode.

  In the period from timing t8 to timing t10, the error pulse EP is equal to or greater than the number N of the first data buffers 8240. In this case, the difference information between the target position and the measurement position is lost in the two ring buffers 824 and 825. Therefore, feedback control in the second mode using the error pulse EP is performed. Thereby, the position of the motor can be converged to the target position based on the reference pulse signal Ps. Further, even when the phase error PHE becomes larger than expected, the control is surely converged and the robustness is improved.

[Switching from the second mode to the first mode]
Next, a specific example when the control mode is switched from the second mode to the first mode will be described with reference to FIG. In the example shown below, the number N of the first data buffers 8240 and the threshold SL are both 4.

FIG. 13 shows that the control mode of the motor control device 80B is changed from the second mode to the first mode.
An example of a time chart of the reference pulse signal Ps and the encoder pulse signal Pe when switching to a mode is shown.

  In the example of FIG. 13, at each of the rising edge timings t2, t4, t7, and t9 of the reference pulse signal Ps, the target cycle recording unit 821 sets the target cycle data Tref determined at that time as the first data buffer. 8240 each. Similarly, at each of the rising edge timings t1, t3, t5, t6, and t8 of the encoder pulse signal Pe, the measurement cycle recording unit 822 sets the measurement cycle data Tenc determined at that time as the second data buffer 8250. Record each.

  Further, it is assumed that the phase (position) of the encoder pulse signal Pe is delayed with respect to the reference pulse signal Ps and the error pulse EP is 4 at the timing t1.

  In the time chart of FIG. 13, there is one rising edge of the reference pulse signal Ps between each of timings t1 and t3 and between timings t3 and t5. Therefore, the error pulse EP at each timing t3 and t5 is 4, which is the same as the error pulse EP at the timing t1.

  Accordingly, in the period from the timing t1 to the timing t5, the error pulse EP is equal to or greater than the threshold value SL, and the signal selection unit 86 selects the second control signal X2. Therefore, the control mode in the period from timing t1 to timing t5 is the second mode. Thereby, the motor 40 is controlled based on the error pulse EP.

  Next, there is no rising edge of the reference pulse signal Ps between timings t5 and t6. Further, between the timings t6 and t8, there is one rising edge of the reference pulse signal Ps. Therefore, the error pulse EP at the timing t6 is reduced by one to 3 from the error pulse EP at the timing t5. Further, the error pulse EP at the timing t8 is 3, which is the same as the error pulse EP at the timing t6.

  Therefore, in the period from timing t6 to timing t8, the error pulse EP is less than the threshold value SL, and the signal selector 86 selects the first control signal X1. Therefore, the control mode in the period from timing t6 to timing t8 is the first mode.

  In the period before the timing t1 to the timing t6, the error pulse EP is equal to or more than the number N of the first data buffers 8240. In this case, the difference information between the target position and the measurement position is lost in the two ring buffers 824 and 825. Therefore, feedback control in the second mode using the error pulse EP is performed. Thereby, the position of the motor can be converged to the target position based on the reference pulse signal Ps.

  On the other hand, in the period from timing t6 to timing t8, the error pulse EP is less than the number N of the first data buffers 8240. Therefore, in the two ring buffers 824 and 825, information on the difference between the target position once lost and the measurement position is restored.

  That is, the phase error PHE reflecting the correct position information is calculated by applying the data recorded in the two ring buffers 824 and 825 to the above formula (2) or (3). Can do. Thereby, the position of the motor can be quickly converged to the target position based on the correct phase error PHE.

  Further, the capacities of the two ring buffers 824 and 825 can be reduced, and as a result, the power consumption and cost of the motor control device 80B can be reduced.

[Fourth Embodiment]
Next, a motor control device 80C according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 14 is a block diagram of the motor control device 80C. 14, the same components as those shown in FIG. 8 are given the same reference numerals. Hereinafter, differences of the motor control device 80C from the motor control device 80B will be described.

  The motor control device 80C has a configuration in which a target speed detection unit 881, an actual speed detection unit 882, a subtractor 883, a speed feedback control amplifier 884, and a feedforward control amplifier 885 are added to the configuration of the motor control apparatus 80B. Have.

  The target speed detector 881 detects (calculates) the target rotational speed of the motor 40 by calculating the reciprocal of the generation period of the reference pulse signal Ps. Similarly, the actual speed detector 882 detects (calculates) the actual rotation speed of the motor 40 by calculating the reciprocal of the generation period of the encoder pulse signal Pe.

  The subtracter 883 calculates a speed deviation that is a difference between the target rotation speed and the actual rotation speed. The speed feedback control amplifier 884 is an amplifier that generates a speed control signal reflecting the speed deviation by amplifying a signal corresponding to the speed deviation with a preset gain.

  The feedforward control amplifier 885 is an amplifier that generates a feedforward control signal in which an element of change in the target rotational speed is reflected by amplifying a signal corresponding to the target rotational speed with a preset gain. is there.

  The speed control signal and the feedforward control signal are added together with the proportional control signal Xp and the integral control signal Xi by the adder 834 and reflected in the first control signal X1.

  The image forming apparatus according to the fourth embodiment of the present invention has a configuration in which the motor control device 80 in the image forming device 10 is replaced with the motor control device 80C.

  As described above, the motor control device 80C performs feedback control and feedforward control based on the rotation speed of the motor 40 in parallel with feedback control based on the phase error PHE. Thereby, the phase error PHE can be reduced more quickly.

[Application example]
In the motor control devices 80, 80A, 80B, 80C, the integrator 832 and the integration element amplifier 833 can be omitted.

  The motor control device, the image forming apparatus, the motor control method, and the image forming apparatus according to the present invention can be freely combined within the scope of the invention described in each claim. Alternatively, the embodiment and application examples may be modified as appropriate, or may be configured by omitting a part thereof.

Claims (10)

Each time a reference pulse signal is generated, target period data representing an elapsed time from the previous generation of the reference pulse signal is stored in each of the first data buffers in the first ring buffer having three or more first data buffers. A target period recording section for sequentially recording;
Each time an encoder pulse signal synchronized with the rotation of the motor is generated, measurement cycle data representing the elapsed time from the previous generation of the encoder pulse signal is provided with the same number of second data buffers as the number of the first data buffers. A measurement cycle recording unit for sequentially recording each of the second data buffers in the second ring buffer;
The phase is obtained by integrating the difference between the target period data and the measurement period data sequentially recorded in the first data buffer and the second data buffer corresponding to each other in the first ring buffer and the second ring buffer, respectively. A phase error calculation unit for calculating an error;
And a power control unit that adjusts power supplied to the motor in a direction in which the phase error is reduced.   The said power adjustment part has a pulse width modulation part which adjusts the duty ratio of the drive pulse signal supplied to the said motor according to the input signal in which the proportional factor of the said phase error is reflected at least. Motor control device. An image carrier;
A motor for driving the image carrier;
An encoder that outputs an encoder pulse signal synchronized with the rotation of the motor;
An image forming apparatus comprising: the motor control device according to claim 1, which adjusts electric power supplied to the motor. Each time a reference pulse signal is generated, target period data representing an elapsed time from the previous generation of the reference pulse signal is stored in each of the first data buffers in the first ring buffer having three or more first data buffers. A target period recording step of sequentially recording;
Each time an encoder pulse signal synchronized with the rotation of the motor is generated, measurement cycle data representing the elapsed time from the previous generation of the encoder pulse signal is provided with the same number of second data buffers as the number of the first data buffers. A measurement cycle recording step of sequentially recording each of the second data buffers in the second ring buffer;
The phase is obtained by integrating the difference between the target period data and the measurement period data sequentially recorded in the first data buffer and the second data buffer corresponding to each other in the first ring buffer and the second ring buffer, respectively. A phase error calculating step for calculating an error;
A power adjustment step of adjusting a power supplied to the motor in a direction in which the phase error is reduced. An image forming apparatus comprising: an image carrier; a motor that drives the image carrier; and an encoder that outputs an encoder pulse signal synchronized with the rotation of the motor.
Adjusting the power supplied to the motor,
Each time a reference pulse signal is generated, target period data representing an elapsed time from the previous generation of the reference pulse signal is stored in each of the first data buffers in the first ring buffer having three or more first data buffers. A target period recording step of sequentially recording;
Each time an encoder pulse signal synchronized with the rotation of the motor is generated, measurement cycle data representing the elapsed time from the previous generation of the encoder pulse signal is provided with the same number of second data buffers as the number of the first data buffers. A measurement cycle recording step of sequentially recording each of the second data buffers in the second ring buffer;
The phase is obtained by integrating the difference between the target period data and the measurement period data sequentially recorded in the first data buffer and the second data buffer corresponding to each other in the first ring buffer and the second ring buffer, respectively. A phase error calculating step for calculating an error;
And a power adjustment step of adjusting the power supplied to the motor in a direction in which the phase error is reduced. Each time a reference pulse signal is generated, target period data representing an elapsed time from the previous generation of the reference pulse signal is stored in each of the first data buffers in the first ring buffer having three or more first data buffers. A target period recording section for sequentially recording;
Each time an encoder pulse signal synchronized with the rotation of the motor is generated, measurement cycle data representing the elapsed time from the previous generation of the encoder pulse signal is provided with the same number of second data buffers as the number of the first data buffers. A measurement cycle recording unit for sequentially recording each of the second data buffers in the second ring buffer;
The phase is obtained by integrating the difference between the target period data and the measurement period data sequentially recorded in the first data buffer and the second data buffer corresponding to each other in the first ring buffer and the second ring buffer, respectively. A phase error calculation unit for calculating an error;
An error pulse count unit that counts error pulses of the encoder pulse signal with respect to the reference pulse signal;
A first power adjusting unit that adjusts power supplied to the motor when the error pulse is less than the number of the first data buffers in a direction in which the phase error is reduced;
A motor control device comprising: a second power adjustment unit that adjusts the power supplied to the motor in a direction in which the error pulse decreases when the error pulse is equal to or greater than the number of the first data buffers.   The said 1st electric power adjustment part has a pulse width modulation part which adjusts the duty ratio of the drive pulse signal supplied to the said motor according to the input signal in which the proportional factor of the said phase error is reflected at least. The motor control device described. An image carrier;
A motor for driving the image carrier;
An encoder that outputs an encoder pulse signal synchronized with the rotation of the motor;
An image forming apparatus comprising: the motor control device according to claim 6, which adjusts electric power supplied to the motor. Each time a reference pulse signal is generated, target period data representing an elapsed time from the previous generation of the reference pulse signal is stored in each of the first data buffers in the first ring buffer having three or more first data buffers. A target period recording step of sequentially recording;
Each time an encoder pulse signal synchronized with the rotation of the motor is generated, measurement cycle data representing the elapsed time from the previous generation of the encoder pulse signal is provided with the same number of second data buffers as the number of the first data buffers. A measurement cycle recording step of sequentially recording each of the second data buffers in the second ring buffer;
The phase is obtained by integrating the difference between the target period data and the measurement period data sequentially recorded in the first data buffer and the second data buffer corresponding to each other in the first ring buffer and the second ring buffer, respectively. A phase error calculating step for calculating an error;
An error pulse counting step of counting error pulses of the encoder pulse signal with respect to the reference pulse signal;
A first power adjustment step of adjusting power supplied to the motor in a direction in which the phase error is reduced when the error pulse is less than the number of the first data buffers;
And a second power adjustment step of adjusting the power supplied to the motor in a direction in which the error pulse decreases when the error pulse is equal to or greater than the number of the first data buffers. An image forming apparatus comprising: an image carrier; a motor that drives the image carrier; and an encoder that outputs an encoder pulse signal synchronized with the rotation of the motor.
Adjusting the power supplied to the motor,
Each time a reference pulse signal is generated, target period data representing an elapsed time from the previous generation of the reference pulse signal is stored in each of the first data buffers in the first ring buffer having three or more first data buffers. A target period recording step of sequentially recording;
Each time an encoder pulse signal synchronized with the rotation of the motor is generated, measurement cycle data representing the elapsed time from the previous generation of the encoder pulse signal is provided with the same number of second data buffers as the number of the first data buffers. A measurement cycle recording step of sequentially recording each of the second data buffers in the second ring buffer;
The phase is obtained by integrating the difference between the target period data and the measurement period data sequentially recorded in the first data buffer and the second data buffer corresponding to each other in the first ring buffer and the second ring buffer, respectively. A phase error calculating step for calculating an error;
An error pulse counting step of counting error pulses of the encoder pulse signal with respect to the reference pulse signal;
A first power adjustment step of adjusting power supplied to the motor in a direction in which the phase error is reduced when the error pulse is less than the number of the first data buffers;
And a second power adjustment step of adjusting the power supplied to the motor in a direction in which the error pulse decreases when the error pulse is equal to or greater than the number of the first data buffers.

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