JP2017191806A - Package substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a package substrate capable of increasing a transmission rate between electronic components.SOLUTION: In a package substrate of an embodiment, only an interlayer resin insulating layer 150Fb, which is an inner layer and on which a dedicated wiring layer 158Fa is formed, contains inorganic particles having an average diameter of 0.5 μm or less and a maximum diameter of 1 μm. On the other hand, an upper-side interlayer resin insulating layer 50F, an outermost interlayer resin insulating layer 150Fb, a lower-side interlayer resin insulating layer 50S, a lower-side interlayer resin insulating layer 150Sa that is an inner layer, and a lower-side outermost interlayer resin insulating layer 150Sb contain inorganic particles having an average diameter of 5 μm or less and a maximum diameter of 10 μm.SELECTED DRAWING: Figure 1

Description

The present invention relates to a package substrate on which a plurality of electronic components are mounted.

Patent Document 1 discloses a multichip module substrate. According to FIG. 1 of Patent Document 1, two LSIs are mounted on one substrate. The two LSIs are connected by a plurality of wiring layers. In FIG. 1 of Patent Document 1, a plurality of wiring layers are drawn in different insulating layers.

JP-A-6-53349

Patent Document 1 discloses a multichip module substrate. As disclosed in FIGS. 1 and 14 of Patent Document 1, the multichip module substrate shown in FIG. 1 of Patent Document 1 has four wiring layers. According to FIG. 1 of Patent Document 1, it is considered that all four layers have wirings connecting two LSIs.
An LSI generally has a power supply line and a ground line. Therefore, it is considered that the LSI of Patent Document 1 also has a power supply line and a ground line. That is, the multichip module substrate shown in FIG. 1 of Patent Document 1 is considered to have power supply wiring and ground wiring connected to the power supply line and ground line of the LSI. Of the four wiring layers shown in FIG. 1 of Patent Document 1, it is considered that at least one wiring layer has both a wiring connecting two LSIs and a power supply wiring or a ground wiring. For this reason, with the multichip module substrate of Patent Document 1, it is assumed that it is difficult to increase the transmission speed between electronic components.

The package substrate according to the present invention is formed on the outermost interlayer resin insulation layer having a first surface and a second surface opposite to the first surface, and on the first surface of the outermost interlayer resin insulation layer. A first pad group formed by a plurality of first pads for mounting the first electronic component and a second pad formed by a plurality of second pads for mounting the second electronic component. An outermost conductor layer including a group, a first conductor layer formed under the second surface of the outermost interlayer resin insulation layer and including a plurality of first conductor circuits, and the outermost conductor layer. A first via conductor passing through the interlayer resin insulation layer and connecting the first conductor layer and the first pad; and a first conductor layer and the second pad passing through the outermost interlayer resin insulation layer. The second via conductor connected, the second surface of the outermost interlayer resin insulation layer, and formed under the first conductor layer. Having a interlayer resin insulating layer of the inner layer has. All the first conductor circuits in the first conductor layer connect one first pad in the first pad group and one second pad in the second pad group, and each layer The resin insulation layer includes inorganic particles, and the diameter of the inorganic particles contained in the inner interlayer resin insulation layer is smaller than the diameter of the inorganic particles of the other interlayer resin insulation layers including the outermost interlayer resin insulation layer.

Sectional drawing of the package board | substrate which concerns on 1st Embodiment of this invention. Sectional drawing of the application example of the package board | substrate which concerns on 1st Embodiment. Process drawing which shows the manufacturing method of the package substrate of 1st Embodiment. Process drawing which shows the manufacturing method of the package substrate of 1st Embodiment. Process drawing which shows the manufacturing method of the package substrate of 1st Embodiment. Process drawing which shows the manufacturing method of the package substrate of 1st Embodiment. Process drawing which shows the manufacturing method of the package substrate of 1st Embodiment. Process drawing which shows the manufacturing method of the package substrate of 1st Embodiment. Process drawing which shows the manufacturing method of the package substrate of 1st Embodiment. (A) The top view which shows a pad group, (B) The top view of an application example. The top view of a 1st conductor layer. Sectional drawing of the package board | substrate which concerns on 3rd Embodiment. Sectional drawing of the package board | substrate which concerns on 4th Embodiment. Sectional drawing of a skip via conductor. Sectional drawing of the package board | substrate which concerns on 2nd Embodiment. Sectional drawing of an outermost conductor layer and an outermost interlayer resin insulation layer.

[First embodiment]
FIG. 10A shows the mounting surface of the package substrate according to the first embodiment of the present invention. FIG. 10B is a plan view of an application example of the embodiment, and an electronic component is mounted on the package substrate of the embodiment.
As shown in FIG. 10A, a mounting region 77L for mounting a first electronic component such as a logic IC is formed at the center of the mounting surface of the package substrate. A first pad 76FP for mounting the first electronic component is formed in a lattice shape in the mounting region 77L. A first pad group is formed by a plurality of first pads 76FP. A solder bump 76FL for mounting the first electronic component is formed on the first pad. A mounting region 77M for mounting a second electronic component such as a memory is formed outside the mounting region 77L. In FIG. 10A, four mounting regions 77M are formed around the mounting region 77L. A second pad 76SP for mounting the second electronic component is formed in a grid pattern in each mounting region 77M. A second pad group is formed by a plurality of second pads. Solder bumps 76FM for mounting the second electronic component are formed on the second pads. In FIG. 10B, the logic IC 110L is mounted on the solder bumps 76FL in the mounting area 77L, and the memory 110M is mounted on the solder bumps 76FM in the mounting area 77M.

FIG. 1A shows a cross section of the package substrate of the embodiment between the line segments Z1-Z1 shown in FIG. FIG. 2 shows a cross section of an application example of the embodiment between the line segments Z2 and Z2 shown in FIG.

As shown in FIG. 1A, the package substrate of the embodiment has an outermost conductor layer 158Fb including pads for mounting electronic components. Further, the package substrate has an outermost interlayer resin insulation layer 150Fb that supports the outermost conductor layer 158Fb. Examples of pads for mounting electronic components included in the package substrate of the embodiment are shown in FIGS. 16 (A) and 16 (B). FIGS. 16A and 16B show cross sections of the outermost conductor layer 158Fb and the outermost interlayer resin insulation layer 150Fb. FIG. 16A shows an example in which the outermost conductor layer including the first pad 76FP and the second pad 76SP is formed on the outermost interlayer resin insulation layer. FIG. 16B shows an example in which the outermost conductor layer including the first and second pads is formed in the concave portion of the outermost interlayer resin insulating layer.

In the embodiment, the first via conductor 160Faf connected to the first pad and the second via conductor 160Fas connected to the second pad are formed in the outermost interlayer resin insulation layer. The first via conductor is preferably formed immediately below the first pad. The second via conductor is preferably formed immediately below the second pad.
A first conductor layer (158Fa) including a plurality of first conductor circuits is formed under the outermost interlayer resin insulation layer. The first pad and the second pad are connected by the first conductor circuit. That is, exchange of signals and the like between the first electronic component and the second electronic component is performed via the first conductor layer. All the first conductor circuits connect the first pad and the second pad. All conductor circuits formed on the same plane as the first conductor circuit are included in the first conductor layer. The first conductor layer is a dedicated wiring layer for exchanging signals between the first electronic component and the second electronic component. The first conductor layer has no conductor circuit other than a conductor circuit (signal line) for exchanging signals between the first electronic component and the second electronic component. The first conductor layer functions as a dedicated wiring layer for data transmission between the first electronic component and the second electronic component.

Generally, 1-bit data is sent through one signal line (one first conductor circuit). A command or data handled by an electronic device such as a personal computer is composed of 1 byte (8 bits). When the width and thickness of each signal line are different, electrical characteristics such as transmission speed are different between the signal lines. For this reason, it is assumed that a difference occurs in the transmission time of the signal in byte units. It is expected that the signal will not be processed properly and the processing time will be long. It is expected that there will be a difference in transmission time between bits within one byte. Further, it is considered that there is a signal line having a low transmission speed due to variations in the width and thickness of the signal line. The processing is expected to be slow due to the signal line.

The embodiment has a dedicated wiring layer. Therefore, when a conductor layer including a signal line (dedicated wiring layer) is formed, manufacturing conditions and the like are set according to the width and thickness of the signal line. Therefore, according to the embodiment, variations in the width and thickness of the signal line are reduced. The transmission speed of each signal line is almost the same. The signal is processed appropriately. Even if there is a lot of information, processing does not slow down.
Due to the function of the electronic component, a dedicated wiring layer can be formed in a plurality of layers in the package substrate of the embodiment. However, when a plurality of dedicated wiring layers are formed, it is expected that the difference in the thickness and width of the signal lines will increase. Therefore, in order to reduce the variation in transmission time between electronic components, it is preferable that the dedicated wiring layer is one layer. However, even if the dedicated wiring layer is formed in a different layer, the difference in transmission time is small because each layer has only a wiring for data transmission. One conductor layer includes all conductor circuits sandwiched between two interlayer resin insulation layers. However, for example, a circuit that does not transmit a signal or power, such as a dummy conductor, is not included in the conductor circuit.

An inner interlayer resin insulation layer (150Fa) is formed under the outermost interlayer resin insulation layer and the first conductor layer (dedicated wiring layer). The outermost interlayer resin insulation layer and the first conductor layer (dedicated wiring layer) are supported by the inner interlayer resin insulation layer. In FIG. 1A, all conductor circuits sandwiched between the inner interlayer resin insulation layer and the outermost interlayer resin insulation layer are first conductor circuits. It is preferable that the outermost interlayer resin insulation layer is formed immediately above the dedicated wiring layer and the inner interlayer resin insulation layer. The distance between the electronic component and the dedicated wiring layer is shortened.

A second conductor layer 58FP including a plurality of second conductor circuits is formed under the inner interlayer resin insulation layer. The power supply to the electronic component is performed through the second conductor layer. For this reason, the first pad and the second pad include a pad connected to the second conductor layer. The pad connected to the second conductor layer and the second conductor layer are formed via the skip via conductor 160Fb. The skip via conductor 160Fb is a via conductor formed in a via conductor opening (151Fb) that simultaneously penetrates the outermost interlayer resin insulation layer (150Fb) and the inner interlayer resin insulation layer (150Fa) and reaches the second conductor layer (58FP). Skip via conductor 160Fb penetrates the outermost interlayer resin insulation layer and the inner interlayer resin insulation layer simultaneously. As shown in FIG. 14, the skip via conductor may have a skip via conductor land SVL under the outermost interlayer resin insulation layer. However, the land of the skip via conductor is independent and is not connected to the first conductor layer. Such a land is not included in the first conductor circuit. Since the land of the skip via conductor formed under the outermost interlayer resin insulation layer is formed in the same layer as the first conductor layer, the formation area of the first conductor layer is reduced. From this point of view, it is preferable that there are no lands of skip via conductors formed under the outermost interlayer resin insulation layer. The first conductor layer is formed on the inner interlayer resin insulation layer (150Fa).

Since the first conductor layer 158Fa is a dedicated wiring layer, there is no via conductor other than the skip via conductor that penetrates the inner interlayer resin insulation layer. The package substrate of the embodiment does not have via conductors that penetrate only the inner interlayer resin insulation layer. Therefore, the area for forming the first conductor circuit in the first conductor layer increases. Many first conductor circuits are formed in the first conductor layer. A highly functional electronic component can be mounted on the package substrate of the embodiment. A dedicated wiring layer is formed in a single layer. Increases data transmission speed.

The conductor circuit (first conductor layer) of the dedicated wiring layer is thinner than the outermost conductor layer and the second conductor layer. The thickness of the outermost conductor layer and the thickness of the second conductor layer are substantially the same. For example, the thickness of the first conductor layer is ½ or less of the thickness of the outermost conductor layer, and is 3 μm or more. For example, the thickness of the first conductor layer is about 5 μm, and the thickness of the outermost conductor layer and the thickness of the second conductor layer are about 10 μm. Thereby, a fine conductor circuit can be formed in a dedicated wiring layer. High-performance electronic components are mounted on the package substrate.

The width of the first conductor circuit is narrower than the width of the conductor circuit included in the outermost conductor layer or the second conductor layer. Here, the width of the conductor circuit is the width of the thinnest conductor circuit in each conductor layer. The width of the first conductor circuit is 1/2 to 2/3 of the width of the conductor circuit included in the outermost conductor layer or the second conductor layer. For example, the width of the first conductor circuit is about 5 μm, and the width of the conductor circuits included in the outermost conductor layer and the second conductor layer is about 9 μm. The conductor circuit is cut along a plane perpendicular to the traveling direction of the conductor circuit. The smallest distance among the distances between the opposing walls is the width of the conductor circuit.

The distance (width) between the adjacent first conductor circuits is narrower than the distance between the adjacent second conductor circuits. The distance of the space between adjacent first conductor circuits is 1/2 to 2/3 of the distance of the space between adjacent second conductor circuits. For example, the distance between the adjacent first conductor circuits is about 5 μm, and the distance between the adjacent second conductor circuits is 12 μm. Here, the space distance is the distance of the narrowest space in each conductor layer. The distance between the spaces and the distance between adjacent conductor circuits are the same.
The signal line is preferably a strip line or a microstrip line. When the signal line is a strip line, the signal line is sandwiched between the outermost conductor layer and the second conductor layer.

The package substrate of the embodiment is formed on a dedicated wiring layer, an outermost interlayer resin insulating layer formed on the dedicated wiring layer, and an outermost interlayer resin insulating layer, and mounts a plurality of electronic components. And a via conductor passing through the outermost interlayer resin insulating layer and connecting the pad and a dedicated wiring layer. The pad has a first pad for mounting the first electronic component and a second pad for mounting the second electronic component. Further, the first pad has a first pad connected to a dedicated wiring and a first pad connected to a conductor layer other than the dedicated wiring layer. The second pad has a second pad connected to a dedicated wiring layer and a second pad connected to other than the dedicated wiring layer. Pads connected to other than the dedicated wiring layer are connected to the skip via conductor. The circuit is closed by the first pad connected to the dedicated wiring layer, the signal line in the dedicated wiring layer, and the second pad connected to the dedicated wiring layer.
The package substrate of the embodiment further has a skip via conductor penetrating the second conductor layer, the inner interlayer resin insulation layer on the second conductor layer, the outermost interlayer resin insulation layer, and the inner interlayer resin insulation layer. Can do. The dedicated wiring layer is formed on the inner interlayer resin insulation layer. The dedicated wiring layer is sandwiched between the outermost interlayer resin insulation layer and the inner interlayer resin insulation layer.

The package substrate of the embodiment may include a core substrate having a conductor layer. In that case, the inner interlayer resin insulation layer is formed on the core substrate, and the conductor layer of the core substrate corresponds to the second conductor layer. Furthermore, the package substrate of the embodiment may have a buildup layer between the core substrate and the inner interlayer resin insulation layer. An example in which the buildup layer is formed of one interlayer resin insulation layer and one conductor layer is shown in FIG. The conductor layer 58FP sandwiched between the interlayer resin insulating layer 50F on the core substrate and the inner interlayer resin insulating layer 150Fa is the second conductor layer. The build-up layer includes an interlayer resin insulation layer and a conductor layer, and the interlayer resin insulation layer and the conductor layer are alternately laminated. A package substrate having a core substrate and a manufacturing method thereof are disclosed in, for example, JP2007227512A.
The package substrate of the embodiment may be a coreless substrate. The coreless substrate includes an interlayer resin insulation layer and a conductor layer, and the interlayer resin insulation layer and the conductor layer are alternately laminated. The coreless substrate and the manufacturing method thereof are disclosed in, for example, JP2005236244A. At least one of the conductor layers is a dedicated wiring layer. The thickness of each interlayer resin insulation layer of the coreless substrate is 30 μm to 60 μm.

The package substrate 10 shown in FIG. 1 has a core substrate 30 similar to JP2007227512A. The core substrate 30 includes an insulating substrate 20z having a first surface (F) and a second surface (S) opposite to the first surface. The conductor layer 34F is formed on the first surface F of the insulating substrate 20z, and the conductor layer 34S is formed on the second surface S. The insulating substrate 20z has a plurality of through holes 31, and a through hole conductor 36 for connecting the conductor layer 34F and the conductor layer 34S is formed inside the through hole 31. The shape of the through-hole 31 for the through-hole conductor is an hourglass shape similar to JP2007227512A.

A first buildup layer 55 </ b> F is formed on the first surface F of the core substrate 30. The first surface of the core substrate and the first surface of the insulating substrate are the same surface. The first buildup layer 55F includes an interlayer resin insulation layer (upper interlayer resin insulation layer) 50F formed on the core substrate 30, a second conductor layer 58FP on the interlayer resin insulation layer 50F, and an interlayer resin insulation. A via conductor 60F that penetrates the layer 50F and connects the second conductor layer 58FP and the conductor layer 34F is provided.

The first buildup layer further includes an inner interlayer resin insulating layer (150Fa) formed on the interlayer resin insulating layer (50F) and the second conductor layer (58FP), and a first conductor formed on the inner interlayer resin insulating layer (150Fa). Layer 158Fa. The first conductor layer is a dedicated wiring layer. There is no via conductor penetrating only the inner interlayer resin insulation layer (150Fa).
The first buildup layer further includes an uppermost interlayer resin insulation layer (outermost interlayer resin insulation layer) 150Fb formed on the inner interlayer resin insulation layer 150Fa and the first conductor layer 158Fa, and an uppermost interlayer resin insulation. The uppermost conductor layer (outermost conductor layer) 158Fb formed on the layer 150Fb and a via conductor (uppermost via conductor) that penetrates the uppermost interlayer resin insulation layer and connects the uppermost conductor layer and the first conductor layer. ) 160Fa and a skip via conductor 160Fb that penetrates the uppermost interlayer resin insulation layer and the inner interlayer resin insulation layer and connects the uppermost conductor layer and the second conductor layer. The uppermost conductor layer includes a first pad 76FP for mounting the first electronic component and a second pad 76SP for mounting the second electronic component. The uppermost via conductor is a first via conductor (uppermost first via conductor) 160Faf connecting the first pad and the first conductor layer, and a second via conductor (uppermost second conductor) connecting the second pad and the first conductor layer. Via conductor) 160Fas. The skip via conductor includes a first skip via conductor 160Fbf that connects the first pad and the second conductor layer, and a second skip via conductor 160Fbs that connects the second pad and the second conductor layer.
When a plurality of dedicated wiring layers are formed, the dedicated wiring layer is preferably formed only in the first buildup layer.

A second buildup layer 55 </ b> S is formed on the second surface S of the core substrate 30. The second buildup layer 55S includes a lower interlayer resin insulation layer 50S, a lower inner interlayer resin insulation layer 150Sa, a lower outermost interlayer resin insulation layer 150Sb, a lower second conductor layer 58S, a lower The outermost conductive layer (158S) on the side is included, and the interlayer resin insulation layers and the conductive layers are alternately laminated. The first buildup layer and the second buildup layer are preferably formed symmetrically across the core substrate.

A solder resist layer 70F having an opening 71F is formed on the first buildup layer 55F, and a solder resist layer 70S having an opening 71S is formed on the second buildup layer 55S. The first pad 76FP and the second pad 76SP are exposed through the opening 71F of the solder resist layer 70F on the first buildup layer 55F. A solder bump 76FL is formed on the first pad (first solder bump), and a solder bump (second solder bump) 76FM is formed on the second pad. It is preferable that the melting point of the first solder bump is different from the melting point of the second solder bump. Mounting yield and connection reliability are improved. In addition, electronic parts can be easily replaced. Solder bumps (third solder bumps) 76S for connecting to the mother board are formed on the pads 76MP exposed through the openings 71S of the solder resist layer 70S on the second buildup layer 55S. A metal film 72 such as Ni / Au or Ni / Pd / Au is formed on the pads 76FP, 76SP, and 76MP. As shown in FIGS. 2 and 10B, the IC chip 110L is mounted on the solder bump 76FL for mounting the IC chip, and the memory 110M is mounted on the solder bump 76FM for mounting the memory. The package substrate 10 is mounted on the mother board via the solder bumps 76S formed on the second buildup layer. The melting points of the first solder bump, the second solder bump, and the third solder bump are preferably different from each other. High mounting yield and connection reliability.

FIG. 11 is a plan view showing a part of a dedicated wiring layer (first conductor layer) 158Fa. The conductor drawn in a circle in the figure is a pad. The pad drawn on the left side is the first via conductor pad 158Fai, and the pad drawn on the right side is the second via conductor pad 158Fam. A first via conductor 160Faf is formed on the first via conductor pad, and a second via conductor 160Fas is formed on the second via conductor pad. The first conductor circuit includes a first via conductor pad (158Fai), a second via conductor pad (158Fam), a first via conductor pad (158Fai), and a connection wiring (158Fal) connecting the second via conductor pad (158Fam). In the package substrate of the first embodiment, all data transmission between the first electronic component such as the logic chip and the second electronic component such as the memory chip is performed via the first conductor layer.

The first conductor circuit 158Fa is sandwiched between a plane layer 158FbP included in the uppermost conductor layer and a plane layer 580FP included in the second conductor layer to form a strip line. The transmission characteristics of the first conductor circuit are improved.

The thickness of the inner interlayer resin insulation layer is different from the thickness of the other interlayer resin insulation layers. Of the interlayer resin insulation layers, the thicknesses of the interlayer resin insulation layers other than the inner interlayer resin insulation layer are equal. The thickness of the interlayer resin insulation layer is equal to the distance between adjacent conductor layers. In FIG. 1, the thickness t1 of the outermost interlayer resin insulation layer 150Fb is equal to the thickness t3 of the upper interlayer resin insulation layer 50F. The thicknesses t1 and t3 of the interlayer resin insulation layers other than the inner interlayer resin insulation layer are 15 μm to 40 μm. The thickness t2 of the inner interlayer resin insulation layer is 7.5 μm to 20 μm. The thickness t2 of the inner interlayer resin insulation layer is 1/2 to 1/3 of the thicknesses t1 and t3 of the other interlayer resin insulation layers. A fine skip via conductor is formed. The formation area of the first conductor layer is unlikely to be reduced by the skip via conductor. The package substrate becomes smaller. For example, the thickness t2 of the inner interlayer resin insulating layer 150Fa is 13 μm, and the thickness of the interlayer resin insulating layers other than the inner interlayer resin insulating layer is 35 μm.

Upper interlayer resin insulation layer 50F constituting first buildup layer 55F, inner interlayer resin insulation layer 150Fa, outermost interlayer resin insulation layer 150Fb, lower interlayer resin insulation layer constituting second buildup layer 55S 50S, the lower inner interlayer resin insulation layer 150Sa, and the lower outermost interlayer resin insulation layer 150Sb all contain inorganic particles such as silica and a thermosetting resin such as epoxy. Here, only the inner interlayer resin insulation layer (150Fa) has a small inorganic particle diameter. For example, the average diameter of the inorganic particles of the inner-layer interlayer resin insulation layer (150Fa) is 0.5 μm or less, and the maximum diameter of the contained inorganic particles is 1 μm. In contrast, the upper interlayer resin insulation layer 50F, the outermost interlayer resin insulation layer 150Fb, the lower interlayer resin insulation layer 50S, the lower inner interlayer resin insulation layer 150Sa, and the lower outermost interlayer resin insulation layer The average diameter of the inorganic particles in the layer 150Sb is 5 μm or less, and the maximum diameter of the contained inorganic particles is 10 μm.

In the package substrate of the first embodiment, the dedicated wiring layer is formed immediately below the outermost interlayer resin insulation layer 150Fb, so that the wiring distance between the electronic components is shortened. Signal transmission speed between electronic components can be increased. Since the package substrate of the embodiment has a dedicated wiring layer, the electrical characteristics of each signal line are approximated. Uniform transmission time of byte unit signal. Even if the transmission speed is high, the signal is properly transmitted. Even if the amount of information increases, processing does not slow down.
The package substrate of the embodiment does not have a via conductor that penetrates only the inner interlayer resin insulation layer. The package substrate of the embodiment has a skip via conductor that penetrates through an inner interlayer resin insulation layer and an interlayer resin insulation layer on the inner interlayer resin insulation layer. The size of the package substrate is reduced. Uniform transmission time of byte unit signal. Even if the transmission speed is high, the signal is properly transmitted. Processing does not slow down even if the amount of information is measured.

[Method of Manufacturing Package Substrate of First Embodiment]
A manufacturing method of the package substrate 10 of the first embodiment is shown in FIGS. 3 to 9. (1) A starting substrate 20 having a first surface F and a second surface S opposite to the first surface is prepared. The starting substrate is preferably a double-sided copper clad laminate. The double-sided copper-clad laminate includes an insulating substrate 20z having a first surface F and a second surface S opposite to the first surface, and metal foils 22 and 22 laminated on both surfaces (FIG. 3A). ). The starting substrate of the first embodiment is a double-sided copper-clad laminate. Blackening treatment is performed on the surface of the copper foil 22.

The insulating substrate 20z is formed of a resin and a reinforcing material, and examples of the reinforcing material include glass cloth, aramid fiber, and glass fiber. Examples of the resin include an epoxy resin and a BT (bismaleimide triazine) resin.

(2) The double-sided copper clad laminate is processed, and the upper conductor layer 34F and lower conductor layer 34S made of the metal foil 22, the electroless plating film 24, and the electrolytic plating film 26 are formed in the through hole 31. The core substrate 30 including the hole conductors 36 is completed (FIG. 3B). The first surface of the core substrate 30 and the first surface of the insulating substrate 20z are the same surface, and the second surface of the core substrate 30 and the second surface of the insulating substrate 20z are the same surface. The core substrate 30 is manufactured by, for example, a method disclosed in US77786390.

(3) Upper interlayer resin insulation layer (50 </ b> F) is formed on first surface (F) of core substrate 30. A lower interlayer resin insulation layer 50S is formed on the second surface S of the core substrate (FIG. 3C). The interlayer resin insulation layer may further include a reinforcing material such as glass cloth. The thickness of the interlayer resin insulation layers 50F and 50S is about 35 μm.

(4) Next, via conductor openings 51F and 51S are formed in the interlayer resin insulation layers 50F and 50S by a CO2 gas laser, respectively (FIG. 4A).

(5) Electroless copper plating films 52 and 52 are formed on the interlayer resin insulation layers 50F and 50S and on the inner walls of the openings 51F and 51S (FIG. 4B).

(6) A plating resist 54 is formed on the electroless copper plating film 52 (FIG. 4C).

(7) An electrolytic copper plating film 56 is formed on the electroless copper plating film 52 exposed from the plating resist 54. At this time, the openings 51F and 51S are filled with the electrolytic plating film 56. Via conductors 60F and 60S are formed (FIG. 4D).

(8) The plating resist 54 is removed. The electroless plating film 52 exposed from the electrolytic plating film 56 is removed. A second conductor layer (upper second conductor layer) 58FP is formed on interlayer resin insulating layer 50F. A second conductor layer (lower second conductor layer) 58S is formed on interlayer resin insulating layer 50S (FIG. 5A).

(9) A B-stage resin film having a first surface and a second surface opposite to the first surface is prepared. A seed layer 151 is formed on the first surface of the resin film by sputtering. The seed layer is made of copper or the like. The thickness of the seed layer (sputtered film) is 0.05 μm to 0.3 μm. The resin film with a seed layer is laminated on the upper second conductor layer (58FP) and the upper interlayer resin insulation layer (50F) so that the second surface of the resin film faces the upper interlayer resin insulation layer (50F). Thereafter, by curing the resin film, an inner interlayer resin insulating layer (upper inner interlayer resin insulating layer) 150Fa is formed on the upper second conductor layer 58FP and the upper interlayer resin insulating layer 50F. In the embodiment, the upper inner interlayer resin insulation layer is an interlayer resin insulation layer with a seed layer.

The package substrate of the embodiment does not have via conductors that penetrate only the inner interlayer resin insulation layer. Therefore, a seed layer can be formed on the resin film before lamination. Since the seed layer is formed by sputtering before lamination, the seed layer is thin and uniform.
However, the seed layer may be formed on the inner interlayer resin insulating layer after the inner interlayer resin is formed. The package substrate of the embodiment does not have via conductors that penetrate only the inner interlayer resin insulation layer. Therefore, even if the seed layer is formed after the lamination, it is not necessary to form the seed layer on the inner wall of the via conductor opening, so that the thickness of the seed layer is thin and uniform.
Similarly, an inner interlayer resin insulating layer (lower inner interlayer resin insulating layer) 150Sa is formed on the lower second conductor layer 58S and the lower interlayer resin insulating layer 50S (FIG. 5B). ). In the embodiment, the lower inner interlayer resin insulation layer is an interlayer resin insulation layer with a seed layer.
The thickness of the inner interlayer resin insulation layers (150Fa, 150Sa) is about ½ of the thickness of the interlayer resin insulation layers (50F, 50S), and is 17 μm.
The average diameter of the inorganic particles of the inner-layer interlayer resin insulation layer (150Fb) is 0.5 μm or less, and the maximum diameter of the contained inorganic particles is 1 μm. And the average diameter of the inorganic particle of the interlayer resin insulation layer 150Sa of the lower inner layer is 5 μm or less, and the maximum diameter of the contained inorganic particle is 10 μm.

(10) A part of the seed layer formed on the inner interlayer resin insulation layer is removed. Thereby, the seed layer on the alignment mark ALM formed in the second conductor layer is removed (FIG. 5C). At this time, a seed layer in an area where an alignment mark ALM2 described later is formed is also removed. Alignment mark ALM2 is formed in the inner interlayer resin insulation layer with reference to the alignment mark formed in the second conductor layer (FIG. 6A). An example of the alignment mark ALM2 is depicted in FIG. The hatched portion is the upper surface of the inner interlayer resin insulation layer. The part where nothing is drawn is a groove. An alignment mark is formed by a groove formed in the inner interlayer resin insulating layer and the inner interlayer resin insulating layer. For example, the alignment mark is a ring-shaped groove formed in the inner interlayer resin, and is formed by a laser.

(11) A plating resist 153a is formed on the seed layer 151 using the alignment mark ALM2 as a reference (FIG. 7A). The plating resist 153a on the lower inner interlayer resin insulation layer is formed on the entire surface.

(12) An electrolytic copper plating layer 156 is formed on the seed layer 151 exposed from the plating resist 153a (FIG. 7B).

(13) The plating resist 153a is removed (FIG. 7C). The exposed seed layer 151 is removed from the electrolytic copper plating layer 156, and the first conductor layer (upper first conductor layer) 158Fa comprising the seed layer 151 and the electrolytic copper plating layer 156 on the seed layer is the upper inner resin layer. An insulating layer 150Fa is formed (FIG. 8A). A part of the first conductor layer 158Fa is shown in FIG. FIG. 11 is a plan view. L / S (line / space) of the first conductor circuit included in the first conductor layer is, for example, 5/5 μm. The first via conductor pad 158Fai and the second via conductor pad 158Fam are also formed at the same time. The first conductor layer has a first alignment mark formed simultaneously with these via conductor pads. The first alignment mark is not shown.
When the resin film for forming the lower inner interlayer resin insulation layer is a resin film with a seed layer, the seed layer is removed. Since the seed layer is completely removed, the inner interlayer resin insulating layer in the second buildup layer is preferably formed from a resin film having no seed layer. No conductor layer is formed on the lower inner interlayer resin insulation layer.

(14) Outermost interlayer resin insulation layer (upper outermost interlayer resin insulation layer) 150Fb is formed on the upper inner interlayer resin insulation layer and upper first conductor layer (dedicated wiring layer). The outermost interlayer resin insulation layer (lower outermost interlayer resin insulation layer) 150Sb is formed on the lower inner interlayer resin insulation layer (FIG. 8B). The thickness of interlayer resin insulation layers (150Fb, 150Sb) is the same as the thickness of interlayer resin insulation layers (50F, 50S).

(15) Using the first alignment mark as a reference, a first opening 151Fa that penetrates the uppermost outermost interlayer resin insulation layer (150Fb) and reaches the first conductor layer (158Fa) and an uppermost outermost interlayer resin insulation layer by laser. A second opening 151Fb that penetrates 150Fb and the upper inner interlayer resin insulation layer (150Fa) and reaches the upper second conductor layer (58FP) is formed.
An opening 151S that penetrates the lower outermost interlayer resin insulation layer 150Sb and the lower inner interlayer resin insulation layer 150Sa to reach the lower second conductor layer 58S is formed (FIG. 8C).

(16) Via conductors 160Fa, 160Fb, 160S are formed in the via conductor forming openings 151Fa, 151Fb, 151S by a known semi-additive method. In addition, outermost conductor layers 158Fb and 158S are formed (FIG. 9A). Via conductors 160Fb and 160S are skip via conductors that penetrate the outermost interlayer resin insulation layer and the inner interlayer resin insulation layer simultaneously, and connect the outermost conductor layer and the second conductor layer. The outermost conductor layer and the second conductor layer have a plane layer sandwiching the first conductor circuit. The outermost conductor layer and the first conductor layer are connected by a via conductor 160Fa.
The uppermost outermost conductor layer includes a first pad group and a second pad group. The second pad group includes a first group, a second group, a third group, and a fourth group. As shown in FIG. 10, the second pad group surrounds the first pad group. Each second pad group is formed outside each side of the first pad group.

(17) An upper solder resist layer 70F having an opening 71F is formed on the first buildup layer, and a lower solder resist layer 70S having an opening 71S is formed on the second buildup layer (FIG. 9 (B)). The upper surfaces of the first pad 76FP and the second pad 76SP are exposed from the opening 71F of the first solder resist layer 70F. On the other hand, the conductor layer exposed from the opening 71S of the second solder resist layer 70S and the upper surface of the via land function as a pad 76MP for connecting to the motherboard.

(18) A nickel plating layer is formed on the pads 76FP, 76SP, and 76MP, and a gold plating layer is further formed on the nickel plating layer (FIG. 9C). A nickel-palladium-gold layer or an OSP film may be formed instead of the nickel-gold layer.

(19) Solder balls are mounted on the pads 76FP, 76SP, and 76MP, and solder bumps 76FM, 76FL, and 76S are formed by reflow. The package substrate 10 is completed (FIG. 1).

(20) The logic IC chip 110L is mounted on the solder bump 76FL on the first pad, and the memory 110M is mounted on the solder bump 76FM on the second pad (FIG. 2, FIG. 10B). Then, an underfill 114 is filled between the package substrate, the IC chip 110L, and the memory 110M (FIG. 2).

In the manufacturing method of the package substrate of the first embodiment, the first conductor layer 158Fa is formed using a seed layer of a resin film with a seed layer. Since the seed layer is formed on a single film, the thickness of the seed layer and the thickness of the seed layer can be reduced. Also, the seed layer can be formed by sputtering. Since the first conductor layer is a dedicated wiring layer for transmitting data, the thickness of the first conductor layer can be reduced. Since the seed layer is thin, when the conductor circuit is formed, the seed layer is removed with a small etching amount. Therefore, a fine conductor circuit can be formed in the first conductor layer. For example, the first conductor layer has a fine signal line having an L / S of 8 μm / 8 μm or less.
In the first embodiment, since no conductor layer is present on the lower inner interlayer resin insulation layer, the lower inner interlayer resin insulation layer may be omitted. In that case, in order to reduce the warpage of the package substrate, the thickness of one interlayer resin insulating layer included in the second buildup layer is preferably thicker than the thickness of the other interlayer resin insulating layers. The thickness of the interlayer resin insulation layer is a thickness obtained by adding the thickness of the interlayer resin insulation layer on the upper inner layer and the thickness of the interlayer resin insulation layer other than the interlayer resin insulation layer on the upper inner layer.

[Second Embodiment]
FIG. 15 shows a package substrate according to the second embodiment. The second embodiment has a plurality of dedicated wiring layers.
In the second embodiment, a second dedicated wiring layer 158Sa is formed on the lower inner interlayer resin insulation layer. Thus, according to the embodiment, the dedicated wiring layer can be formed in different layers. In the second embodiment, the second dedicated wiring layer is formed in the second buildup layer. However, the second dedicated wiring layer may be formed in the first buildup layer. Since the first buildup layer is close to the electronic component, it is preferable that the second dedicated wiring layer is formed on the first buildup layer.

[Third embodiment]
The package substrate of the third embodiment is shown in FIG. In the third embodiment, the second buildup layer does not have an inner interlayer resin insulation layer. The outermost interlayer resin insulation layer 150Sb of the second buildup layer is formed at the same time as the outermost interlayer resin insulation layer 150Fa of the first buildup layer is formed. The thickness of the interlayer resin insulation layer 150Sb is a thickness obtained by adding the thickness of the interlayer resin insulation layer 150Fa and the thickness of the interlayer resin insulation layer 150Fb.

[Fourth embodiment]
An example of a coreless substrate is shown in FIG. For example, it is manufactured by the method shown in JP2005236244A.
FIG. 13 shows the Z axis. + Indicates the top and-indicates the bottom. The mounting surface is the upper surface in FIG.
The coreless substrate can also have a second dedicated wiring layer.
The coreless substrate shown in FIG. 13 includes a plurality of interlayer resin insulation layers and a plurality of conductor layers that are alternately stacked. Of the plurality of interlayer resin insulation layers, at least one interlayer resin insulation layer is an interlayer resin insulation layer for a dedicated wiring layer (dedicated interlayer resin insulation layer). A dedicated wiring layer is formed on the dedicated interlayer resin insulation layer. In addition, at least one of the plurality of conductor layers is a dedicated wiring layer, and the dedicated wiring layer is formed on a dedicated interlayer resin insulation layer. As shown in FIG. 13A, when pads 760FP and 760SP for mounting electronic components are buried in the outermost interlayer resin insulation layer, the coreless substrate has an interlayer resin insulation layer and a conductor layer on the pads. Manufactured by stacking alternately. Therefore, the outermost interlayer resin insulation layer (uppermost interlayer resin insulation layer) 1500 Fa can be used as a dedicated interlayer resin insulation layer. In that case, the uppermost interlayer resin insulation layer has a first surface F and a second surface S opposite to the first surface. A first pad group including a plurality of first pads 760FP and a second pad group including a plurality of second pads 760SP are formed on the first surface of the uppermost interlayer resin insulating layer (dedicated interlayer resin insulating layer), A dedicated wiring layer 1580Fa is formed on the second surface of the uppermost interlayer resin insulation layer. A second interlayer resin insulation layer 1500Fb having a first surface FF and a second surface SS opposite to the first surface is formed on the second surface of the dedicated interlayer resin insulation layer and the dedicated wiring layer. . A dedicated wiring layer is sandwiched between the second surface S of the dedicated interlayer resin insulation layer 1500Fa and the first surface FF of the second interlayer resin insulation layer. A second conductor layer 1580Fb is formed on the second surface of the second interlayer resin insulation layer. The pad connected to the dedicated wiring layer is connected to the dedicated wiring layer through a via conductor 1600Fa penetrating the dedicated interlayer resin insulating layer. Similar to the first embodiment, the via conductor 1600Fa includes a via conductor 1600Faf connected to the first pad and a via conductor 1600Fas connected to the second pad. The pads connected to the second conductor layer are connected by a skip via conductor 1600Fb that penetrates the dedicated interlayer resin insulation layer 1500Fa and the second interlayer resin insulation layer 1500Fb simultaneously. The second conductor layer 1580Fb shown in FIG. 13A corresponds to the second conductor layer 58FP of the first embodiment. The dedicated wiring layer 1580Fa shown in FIG. 13A corresponds to the first conductor layer 158Fa of the first embodiment.

The coreless substrate shown in FIG. 13B includes an insulating substrate 20z, a lower conductor layer 34S and a second buildup layer 55S from the package substrate of the first embodiment shown in FIG. Lower solder resist layer 70S, metal film 72, and solder bumps 76FL, 76FM, and 76S are removed. Then, as shown in FIG. 13B, the upper conductor layer 34F of the core substrate is buried in the lower surface of the upper interlayer resin insulation layer 50F. The conductor layer 34F is a conductor layer including a pad for connecting to another substrate such as a mother board. The conductor layer 34F shown in FIG. 13B may be formed only of pads for connecting to another substrate such as a mother board. The core resin insulating layer 50F of the coreless substrate shown in FIG. 13B corresponds to the lowermost interlayer resin insulating layer in the coreless substrate of the fourth embodiment. The conductor layer 58FP formed on the lowermost interlayer resin insulation layer is the second conductor layer. An interlayer resin insulation layer (150Fa) formed on the lowermost interlayer resin insulation layer and the second conductor layer is an inner interlayer resin insulation layer, and a conductor layer (158Fa) formed on the inner interlayer resin insulation layer is formed. This is a dedicated wiring layer. The interlayer resin insulation layer 150Fb formed on the inner interlayer resin insulation layer and the dedicated wiring layer is the uppermost interlayer resin insulation layer. The conductor layer 158Fb formed on the uppermost interlayer resin insulation layer is the outermost conductor layer. The outermost conductor layer includes a first pad group including a first pad and a second pad group including a second pad, as in the first embodiment. Similarly to the first embodiment, the coreless substrate shown in FIGS. 13A, 13B, and 13C includes first via conductors 160Faf, 1600Faf, second via conductors 160Fas, 1600Fas, and skip vias. It has conductors 160Fb and 1600Fb.

As shown in FIG. 13C, the coreless substrate shown in FIG. 13A has another interlayer resin insulation between a dedicated interlayer resin insulation layer 1500Fa and pads 760FP and 760SP for mounting electronic components. There may be a layer 1500Fc and another conductor layer 1580Fc.

In each embodiment, when a plurality of second electronic components are mounted on the package substrate, even if all the second electronic components are the same electronic component, some of the plurality of second electronic components are Different electronic components may be used. The first electronic component and the second electronic component may be the same electronic component.

10 Package substrate 30 Core substrate 36 Through-hole conductor 58FP Second conductor layer 76FP, 76SP, 76MP Pad 150Fa Inner layer resin insulation layer 150Fb Outermost interlayer resin insulation layer 158Fa First conductor layer 158Fal Connection wiring 160Fa Uppermost via conductor 160Fb Skip via conductor

Claims (7)

An outermost interlayer resin insulation layer having a first surface and a second surface opposite to the first surface;
A first pad group and a second electronic component formed on the first surface of the outermost interlayer resin insulation layer and formed by a plurality of first pads for mounting the first electronic component are mounted. An outermost conductor layer including a second pad group formed of a plurality of second pads for:
A first conductor layer formed under the second surface of the outermost interlayer resin insulation layer and including a plurality of first conductor circuits;
A first via conductor penetrating the outermost interlayer resin insulation layer and connecting the first conductor layer and the first pad;
A second via conductor passing through the outermost interlayer resin insulation layer and connecting the first conductor layer and the second pad;
A package substrate having the second surface of the outermost interlayer resin insulation layer and an inner interlayer resin insulation layer formed under the first conductor layer,
All the first conductor circuits in the first conductor layer connect one first pad in the first pad group and one second pad in the second pad group;
Each interlayer resin insulation layer includes inorganic particles, and the diameter of the inorganic particles contained in the interlayer resin insulation layer of the inner layer is larger than the diameter of inorganic particles of other interlayer resin insulation layers including the outermost interlayer resin insulation layer. small. 2. The package substrate according to claim 1, wherein the first conductor layer does not have a conductor circuit other than the first conductor circuit, and the first conductor layer is between the first electronic component and the second electronic component. This is a dedicated wiring layer for data transmission. 2. The package substrate according to claim 1, further comprising: a second conductor layer formed under the inner interlayer resin insulating layer; the outermost interlayer resin insulating layer; and the inner interlayer resin insulating layer simultaneously. A skip via conductor that penetrates and connects the outermost conductor layer and the second conductor layer is provided. 4. The package substrate according to claim 3, wherein the package substrate does not have via conductors that penetrate only the inner interlayer resin insulation layer. 4. The package substrate according to claim 3, wherein the thickness of the outermost interlayer resin insulation layer is at least twice the thickness of the inner interlayer resin insulation layer. 4. The package substrate according to claim 3, wherein a stripline is formed by the outermost conductor layer, the first conductor circuit, and the second conductor layer. 2. The package substrate according to claim 1, wherein the first electronic component is a logic IC, and the second electronic component is a memory.

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