JP2002190672A - Build-up core board, build-up circuit board and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a board in which thermal and electric conductivity posts are sealed with very small irregularities in shape and size, to enables wiring of a short distance and to increase the operating frequency. SOLUTION: A method for manufacturing a build-up core board comprises steps of (1) connecting a post forming layer (made of Cu or the like) on one main surface of a barrier layer (made of Ni, Ti, Sn or the like) and a carrier layer (made of Fe-Ni alloy or the like) on another main surface, (2) removing by etching to arrive at the barrier layer, forming a plurality of pattern etched products made to stand at a prescribed pitch of the post (made of Cu or the like), laminating a prepreg, heating and pressing to form a first laminated item, (3) removing the carrier layer from the first laminated item, and (4) obtaining the second laminate by removing the barrier layer, laminating the prepreg, heating and pressing, to manufacture the build-up core board.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a core board of a build-up wiring board and a build-up wiring board to which a built-up layer is added and an electronic component is mounted on a surface to transmit a signal. The deviation of the shape and dimensions that enable the semiconductor package is extremely small, and the heat dissipation is excellent.
The present invention relates to a device having an inclined structure and improved reliability.

[0002]

2. Description of the Related Art Semiconductor packages have been required to have many functions. First, small and high-density (fine pitch) wiring is possible. The unit area accompanying it,
Good heat dissipation due to an increase in the amount of heat generated per unit volume. Further, the semiconductor chip must be able to cope with an increase in the speed of signals processed. Further, since the cost reduction requirement for the electronic package is becoming severer year by year, it is also important to reduce the manufacturing cost.

The density of a semiconductor package has been evaluated by a CD (Critical Dimension) using the width of a wiring pattern or the distance between two wiring patterns as an index, and efforts have been made to reduce the size year by year. The width of the wiring pattern or the distance between the two wiring patterns has a large effect on device performance, not only in miniaturization but also in delay of a transmission signal due to a longer transmission line.

Conventional methods for forming a wiring pattern of a semiconductor package include a semi-additive method, a full-additive method,
There are many manufacturing methods such as a subtractive method. The semi-additive method consists of (laser drilling of substrate)-(roughening treatment of resin)-(zincate treatment, that is, Zn plating)-(coating of resist)-(selective removal by resist etching)-(copper plating) -Through the process of completing the wiring pattern. The zincate membrane can be removed at the end,
Necessary to prevent short circuit. The full additive method is
(Laser drilling of substrate)-(Roughening treatment)-(Resist formation)-(Selective removal by resist etching)-(Electroless copper plating)-Completion of wiring pattern. The subtractive method involves the steps of (laser drilling), (roughening), (copper plating), (etching), and completion of a wiring pattern. As described above, the conventional manufacturing method has required many complicated steps.

[0005] The conventional manufacturing method will be described in more detail. After drilling through holes at required positions on the copper-clad board,
An electroless plating process and a copper plating process are performed to form a copper plating layer on the entire surface. Then, after a photoresist film is formed on the entire surface by electrodeposition, an ink mask is formed on the photoresist film by screen printing. Thereafter, an exposure process is performed to cure the photoresist film exposed through the ink mask, and then a development process is performed to dissolve and remove a portion of the photoresist film that has not been irradiated with light, and to remove the portion according to the wiring pattern. A resist pattern is formed. Then, after the exposed copper plating layer and the copper foil thereunder are removed by etching, the resist pattern is peeled off to form a desired wiring pattern using the copper plating layer and the copper foil. The semiconductor package is three-dimensionally mounted and formed into a multi-layer substrate for high-density mounting, and electrical connections between the layers are made through holes.

[0006] Semiconductor devices are also sensitive to heat. Therefore, the development of semiconductor element substrates that can effectively dissipate the heat generated by the semiconductor element and that can be manufactured at a low cost with a simple structure has been actively performed. Conventionally, a plurality of through holes have been drilled at a pitch of about 1.27 mm using a drill of about 0.3 mm, and then plated with Cu or the like to conduct conduction in the vertical direction of the substrate. For example, JP-A-10-313071 discloses that
A heat radiation pattern is formed on the other main surface of the substrate, and a heat radiation plate is formed on this heat radiation pattern, which serves as a bonding surface when mounted on a wiring board, and further radiates heat so as to penetrate in the thickness direction of the substrate. A metal material is filled in the heat dissipation through-hole, and the heat generated by the bare chip is conducted to the heat dissipation plate through the heat dissipation through-hole filled with the metal material and the heat dissipation pattern. Is disclosed.

Japanese Unexamined Patent Application Publication No. 9-199632 discloses an electronic component mounting substrate which is excellent in heat dissipation, facilitates drilling, and enables high-density wiring in a flexible substrate. Disclose. This Japanese Patent Laid-Open No. 9-1
According to Japanese Patent Application No. 99632, "electrically insulating flexible film and 2 in the thickness direction of the flexible film.
A multi-layer board composed of conductor circuits provided with at least layers, a through-hole penetrating all the flexible films, a heat-dissipating metal plate provided on the upper surface side of the multilayer board so as to cover the through-hole, and the through-hole and the heat-dissipating metal plate And a mounting recess for mounting an electronic component, and a through hole provided on the multilayer substrate and conducting to a conductor circuit. The thickness of the flexible film is preferably from 30 to 200 μm. "

According to the embodiment of Japanese Patent Application Laid-Open No. 9-199632, the manufacturing method is as follows. A flexible film made of a glass fiber-containing epoxy material is prepared. Flexible film is 0.05m thick
m, a flexible band-shaped film having a width of 2.5 to 15 cm. This flexible film is wound in a roll shape in advance to form a plurality of roll bodies. Next, while pulling out the flexible film from the roll, an insulating adhesive made of a thermoplastic glass fiber-containing epoxy material is adhered to the lower surface of the flexible film. Next, a through hole is formed in a substantially central portion of the flexible film by punching. Next, a copper foil having a thickness of 35 mm is bonded to the lower surface side of the flexible film via the insulating adhesive. And
The inside of the through hole is filled with solder.

In recent years, with the miniaturization of equipment, the pattern of semiconductor package substrates has been getting finer and finer, and is called a so-called build-up wiring board. An insulating layer is applied to both sides of a core substrate and a build-up layer is added. Then, a method of forming a pattern by a plating method is performed. FIG. 11 shows an example of a conventional build-up wiring board. The build-up wiring board 3 includes the build-up core board 1 and upper and lower build-up layers. The build-up core substrate 1 often uses a glass fiber reinforced epoxy-rigid material. The upper buildup layer 2a is C4 connected to the semiconductor (Si) chip 4 via the wiring pattern 7 and the solder balls 5a. C4 connection means controlled coll
Abbreviation for apsible chip connector, a connection method that forms an electrically and thermally effective conductive path that flows an electric signal of an LSI chip and generated heat to a substrate via a pad.

The symbol 4 may be a semiconductor device such as an LSI or a CSP. The underfill 6 has a function of sealing with a resin or the like to improve moisture resistance and impact resistance. The lower buildup layer 2b is connected to an external circuit via the solder ball 5b. In the core substrate 1, Cu plating is performed on the inner wall of the through hole 8 to fill the hole, and the inner wall of the through hole 8 is filled with resin and flattened. The upper and lower buildup layers are electrically and thermally connected. The lower build-up layer 2b normally surrounds the build-up core substrate 1 and balances vertically symmetrically,
In many cases, the entire build-up wiring board 3 is provided to provide flatness without warpage. Build-up layers 2a, 2b
Is generally 1 to 3 layers, and Cu of this layer is often formed by plating. The circuit pattern is formed by etching plated Cu or plating by an additive method.

[0011]

The conventional build-up core board and the build-up wiring board have various problems. The first is a decrease in reliability due to a large difference in the coefficient of thermal expansion from the semiconductor chip, the second is difficult to cope with a narrow pitch,
The third is a decrease in the degree of utilization of the build-up layer, the fourth is a decrease in heat dissipation, the fifth is non-uniformity in processing man-hours, the sixth is generation of stray capacitance, and the seventh is a problem in a through-hole drilling process. is there. Hereinafter, each problem will be described.

(1) A decrease in reliability due to a large difference in the coefficient of thermal expansion from the semiconductor chip. Si of a semiconductor chip constituting an FC-BGA (Flip Chip-Ball Grid Array) has a thermal expansion coefficient of 3.2 (ppm).
/ ° C), whereas PWB (PrintedWire B
oard) is about 17 (ppm / ° C.) depending on the material, and the difference between the two is large. Due to the effect of the difference in thermal expansion, the solder ball connection between the chip and the interposer may be changed by a temperature cycle (-55 ° C).
(+ 125 ° C.) There was a problem that the fatigue breakage of the solder ball occurred in the test.

(2) It is difficult to cope with a narrow pitch. The through hole 8 of the conventional build-up core substrate 1 is difficult to narrow the pitch because the glass fiber which is usually drilled with a 0.3 mm drill and put as a reinforcing material is a hindrance, and is at most about 1.27 mm. You can only do rough things. Therefore, there is a large mismatch between the pitch of the bumps of the semiconductor chip 4 and the pitch of the solder balls 5a, the pitch of which decreases year by year.
The wiring of the build-up layer 2a must be largely routed, and the interlayer coupling must be a so-called stagger system, which increases the wiring length. This is a problem contrary to the need for high-speed transmission under the current situation where the signal transmission speed is reduced and the operating frequency reaches 1 GHz. There is also a problem that the rewiring length in the build-up core substrate becomes longer and the signal connection of the upper build-up layer 2a is limited.

Further, there is a land as a factor inhibiting the narrow pitch. In a conventional build-up core substrate, as illustrated in FIG.
The land 71 of about m was essential. Therefore, when a wiring pattern is desired to be provided between lands, there is a problem that the number of wiring patterns provided for preventing a short circuit with the land is limited.

(3) The degree of utilization of the build-up layer is reduced. Further, there is a problem that the lower buildup layer 2b cannot be effectively used because the number of through holes is small. BG
This is because it can be used only for connection with the solder ball 5b for A. In a conventional manufacturing method in which a hole is drilled, the diameter of the through hole is large and the pitch is large, and the development of the wiring tends to be biased toward the upper surface of the build-up wiring board 3. Since the through hole of the build-up core substrate is much lower than the bump density of the semiconductor chip 4, there is a problem that the channel of the lower build-up layer 2b cannot be used. (4) Decrease in heat dissipation. Further, in the conventional build-up core substrate 1 shown in FIG. 11, there is a problem that heat dissipation is inferior to the heat dissipation due to the level of the plating layer on the inner wall of the through hole 8.

(5) Processing man-hours are not uniform. Furthermore, after half-etching the Cu plate of the build-up core substrate and embedding the resin, a plurality of heat and heat
There is a method of polishing until the end of the electrically conductive post is exposed. In this case, the exposed heat / electrically conductive posts and the unexposed heat / electrically conductive posts coexist, resulting in not only large variations, but also poor heat dissipation and poor reliability and workability. there were. In conventional etching of a Cu plate, the shape and depth of holes formed by etching usually vary. This is because the etchability varies depending on the location. Next, the prepreg is laminated to fill all the etched holes, the Cu layer side is inverted and the back side is polished, and a plurality of Cu heat / electrically conductive posts are embedded in the resin at a predetermined pitch. In the case of manufacturing, there is a problem that the thickness of the Cu layer and the thickness of the insulating layer vary each time depending on where the polishing surface is stopped.

This problem will be described in detail with reference to FIG. FIG. 12A shows a cross-sectional shape of a conventional Cu plate after etching. There is unevenness in the etching depth, and the shape deviates from the ideal trapezoid. This is shown in FIG.
When the resin is filled as shown in FIG. 12 and the etching is performed from the Cu plate side in FIG. 12B, the etching is left as shown in FIG. 12C, and the resin protrudes and a short circuit (electric short circuit) occurs. For this reason, mechanical polishing of the back surface is further required, resulting in a problem that extra man-hours are required and uniformity is poor. This has been a problem of slowing down the signal transmission speed.

(6) Generation of stray capacitance. Also, the receiving pad of the semiconductor element 4 needs to be large in order to ensure reliability, and therefore, the upper build-up layer 2a
In addition, the balance between the channel capacitance of the lower build-up layer 2b and that of the lower build-up layer 2b is deteriorated, and there is a problem that a stray capacitance is formed. (7) Problems in the through-hole drilling process. Also, when using a glass fiber reinforced epoxy resin substrate,
Drilling of through holes by drilling not only hinders fine drilling by glass fiber, but also causes fiber breakage, lower reliability, and various problems such as infiltration of plating solution in the subsequent plating process. . In addition, a filler is often added to the resin in order to adjust the coefficient of thermal expansion. However, in the case of processing a micro via (through hole), there is a problem that the particle size itself of the filler is hindered. .

Therefore, the present invention provides a novel manufacturing method capable of uniformly controlling the thickness of the heat / electrically conductive post and the insulating layer without using mechanical polishing, and as a result, the coefficient of thermal expansion with the semiconductor chip is provided. It is an object of the present invention to provide a build-up wiring board with improved reliability by reducing the difference between the two.

[0020]

Means for Solving the Problems The present invention has the following constitution to solve the above-mentioned problems. The symbols used in FIGS. 1 to 9 are shown in parentheses () for easy understanding. The technical idea of the present invention is not limited to the embodiment shown in FIGS. Note that the post forming layer 1
0, the heat / electrically conductive post 15, and the perforated plate 19 use the same or similar ones with different symbols depending on the process. For example, when explaining etching (FIG. 1)
A post forming layer 10, a heat / electrically conductive post 15 in the case of the build-up core substrate of FIG.
The whole including 8 is called perforated plate 19. Similarly, the prepregs 12 and 13 that form the insulating plate, the filling resin 14, and the insulating material 17 are, for example, prepregs 12 and 13 in the description of the method of manufacturing a build-up core substrate that is laminated and heated and pressed in FIG. 2. 3, the filling resin 14 is used for the description of the manufacturing method of the build-up core substrate by the screen printing method, and the insulating material 17 is used for the symbol in FIG. I have.

{1} A thermally and electrically conductive plate 15 having a low thermal expansion coefficient and having a plurality of through holes 18 in the thickness direction, and a material different from the thermally and electrically conductive plate 15 having the plurality of through holes 18. A plurality of thermally and electrically conductive posts 16 isolated in the form of islands provided in the through holes 18; and a plurality of thermally and electrically conductive posts 16 provided on the outer periphery of the plurality of thermally and electrically conductive posts 16 and having a low coefficient of thermal expansion. Insulating member 17 interposed between the conductive plate 15 and the plurality of thermally and electrically conductive posts 16
And insulating plates 12 and 13 joined to both main surfaces of the low thermal expansion coefficient thermally and electrically conductive plate 15, and an extremely thin 18 μm or thinner provided on one or both main surfaces of the insulating plates. A build-up core substrate 1 comprising a copper foil layer 21. The heat / electrically conductive post (16) may be called a metal post or a metal core as a lower concept.

{2} The plurality of thermally and electrically conductive posts 1
6 is Cu or a Cu alloy;
8 having a low coefficient of thermal expansion having a low thermal expansion coefficient
-The build-up core substrate (1) according to {1}, which is made of a Ni alloy. {3} The diameter of the plurality of thermally and electrically conductive posts 16 is
The build-up core substrate (1) according to {1}, wherein the build-up core substrate has a thickness of 0.01 to 0.2 mm and a pitch of 0.1 to 1.0 mm. In addition, a more preferable lower limit of the diameter of the plurality of heat / electrically conductive posts 16 is 0.04 mm.

{4} The insulating material 17 is made of a glass fiber reinforced epoxy resin, a glass fiber reinforced bismaleimide triazine (BT) resin, or an epoxy resin containing polyether sulfone (PES), a polyimide resin, or a polyamide imide resin. The build-up core substrate 1 according to {1}, wherein {5} On the outer periphery of the plurality of heat / electrically conductive posts 16,
The build-up core substrate 1 according to {1}, comprising an insulating material 17 and a perforated plate 19. {6} A build-up wiring board 3 including the build-up core substrate 1 according to the above-mentioned {1}, and build-up layers 2a and 2b formed on the main surface of the build-up core substrate 1.

{7} A method for manufacturing a build-up core substrate (1), comprising the following steps. 1. The post forming layer 10 is bonded to one main surface of the barrier layer 9 and the carrier layer 11 is bonded to the other main surface. 2. A mask for removing a predetermined region is placed on the post forming layer 10. 3. The predetermined area is removed by etching until reaching the barrier layer 11, and the heat and electric conductive post 1 is removed.
6 make a plurality of first patterned etching products. 4. The first pattern etching product and the perforated plate 19 are combined. 5. The first pattern etching product and the perforated plate 19 are roughened. 6. After that, the insulating plates 12 are laminated and heated and pressed to form a first laminated product. 7. The carrier layer 11 is removed from the first laminate. 8. Further, the barrier layer 9 is removed to obtain a second laminated product. 9. The second laminate and the insulating plate 13 are laminated. 10. An ultra-thin copper foil layer having a thickness of 18 μm or less is laminated on one or both main surfaces of the insulating plates 12 and 13 to manufacture a build-up core substrate. In addition, the above-mentioned barrier layer (9),
Preferred materials for the post forming layer (10), the carrier layer (11), the heat / electrically conductive post (16), and the perforated plate (19) are as follows: the barrier layer (9) is made of Ni, Ti, Sn, etc.
The post forming layer (10) is Cu, and the carrier layer (11) is F
e-Ni alloy, heat and electric conductive post (16) is Cu,
The perforated plate (19) is an Fe-Ni alloy.

{8} A method of manufacturing a build-up core substrate 1 comprising the following steps. 1. The post forming layer 10 is bonded to one main surface of the barrier layer 9 and the carrier layer 11 is bonded to the other main surface. 2. A mask for removing a predetermined region is placed on the post forming layer 10. 3. The predetermined area is removed by etching until the barrier layer 9 is reached, and the heat and electric conductive post 16 is removed.
Make a plurality of first patterned etching products. 4. An assembly having a cavity is obtained by combining the first pattern-etched product and a perforated plate. 5. The first pattern-etched product and the perforated plate are roughened. 6. The cavity is filled with a resin by a screen printing method. 7. The carrier layer is etched away. 8. Further, the barrier layer is removed by etching. 9. Next, insulating plates are laminated from both sides of the main surface. 10. A thickness of 18 on one or both major surfaces of the insulating plate;
A build-up core substrate is manufactured by laminating an ultra-thin copper foil layer of μm or less. Note that the barrier layer 9 and the post forming layer 1 described above are used.
0, the carrier layer 11, the heat / electrically conductive post 16, and the perforated plate 19 are preferably made of Ni, Ni, respectively.
The post forming layer 10 such as Ti or Sn is made of Cu, the carrier layer 11 is made of an Fe—Ni alloy, and the thermally and electrically conductive post 16 is made of C.
u, the perforated plate 19 is an Fe-Ni alloy.

[9] The build-up core substrate according to [1], wherein the ultra-thin copper foil has a thickness of 5 μm or less. {10} The method for manufacturing a build-up core substrate according to {7} or {8}, wherein the thickness of the ultra-thin copper foil is 5 μm or less.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, the heat / electrically conductive post 16 is made of Cu and the perforated plate 19 is made of an Fe--Ni alloy. With the Fe-NI perforated plate 19 having an expansion coefficient, the overall thermal expansion coefficient of the interposer can be controlled so as to be 6 to 12 ppm / ° C. There is a remarkable effect that the heat dissipation is improved while improving the heat dissipation by 10 to 10 times. Further, the build-up core substrate 1 has a thickness of 18
Since the ultra-thin copper foil layer having a thickness of not more than 5 μm, more preferably not more than 5 μm is provided, a wiring pattern having a narrow pitch (also called a fine pitch) can be easily formed with high precision by etching or the like. Hereinafter, a method for manufacturing a build-up core substrate according to the present invention will be described with reference to the drawings.

FIG. 1 is a view showing a pattern etching assembly of a build-up core substrate according to the present invention. FIG.
(A) is a plan view of a mask used for etching. This mask is used to etch away a plurality of thermally and electrically conductive posts 16 from the post forming layer 10. The material of the post forming layer 10 is preferably a material having good heat and electric conductivity, for example, Cu or a Cu alloy. FIG. 1 (b)
FIG. 3 is a cross-sectional view taken along the line A-A. Of the post-forming layer 10 and the Fe—Ni alloy carrier layer 11 joined to both main surfaces of the barrier layer 9, the post-forming layer 10 has a plurality of thermal and electrical conductive properties. This shows a state where the post 16 has been removed by etching.
This is combined with a perforated plate 19 (FIG. 1 (c)) made of an Fe—Ni alloy having a small coefficient of thermal expansion to produce the assembly shown in FIG. 1 (d).

A suitable material for the post forming layer 10 in the present invention is Cu or an alloy thereof, which is a conductor having good heat and electricity. Cu is an oxygen-free copper wire (OFC: Ox
ygenFree Copper), electrolytic copper or the like can be used. However, when metallurgical bonding such as diffusion bonding is used instead of adhesion with the barrier layer 9, it is preferable to add Sn, for example, to improve heat resistance. The material of the barrier layer 9 is Ti,
Sn, Ni and the like are suitable. The post forming layer 10 and the carrier layer 11 of the Fe—Ni alloy are joined to both surfaces of the barrier layer 9 with an epoxy resin or the like. Alternatively, it may rely on metallurgical diffusion bonding. Further, the present invention does not have a limitation that it is required to be provided at a predetermined pitch illustrated in FIG. If necessary, the heat and electric conductive posts 16 having a non-uniform pitch and a non-cylindrical shape can be formed.

In the present invention, since a drill is not used as in the prior art, the pitch can be reduced to 1.0 mm or less, which is a narrower pitch than about 1.27 mm in the related art. In the present invention, the lower limit of the pitch has been decreasing year by year with the progress of the etching technology, and currently, it is possible to reach about 0.1 mm. It goes without saying that this lower limit will be further reduced in the future.

The post forming layer 10 is concentrically removed by etching until the post forming layer 10 reaches the barrier layer 9.
6 is a pattern-etched product that stands at a predetermined pitch (FIG. 1)
(B)). FIG. 4 shows a prepreg 1 made of glass fiber reinforced epoxy resin, etc.
2 shows a cross-sectional perspective view enclosed in FIG. When the build-up core substrate 1 of the present invention is used, as shown in FIG. 9, heat is generated not only in the vertical direction of the plurality of heat / electrically conductive posts 16 but also in other adjacent heat / electrically conductive posts. It is transmitted to the relay type and heat is dissipated.

When the barrier layer 9 is made of Ti, an ethylenediamine-based Enstrip TL-142 (trade name, manufactured by Meltex Corporation) concentrated solution is used as the chemical etching solution. In addition, depending on the material of the barrier layer 9, Metec S
Commercial solutions such as CB (trade name of McDermid),
A mixture of nitric acid and hydrogen peroxide and a mixed acid of chromic acid and sulfuric acid can be used.

In the present invention, since the barrier layer 9 functions as an etching stop layer, it is possible to obtain an array of a plurality of thermally and electrically conductive posts 16 that are precisely controlled without uneven height. . Further, no extra mechanical polishing is required. According to the present invention, it has excellent etching properties, and the result of observing the corner portion of the wiring portion with a microscope also confirmed that the wiring portion was etched into an ideal shape.

The feature of the present invention that there is no height non-uniformity is important. It can be understood from the characteristic impedance of the microstrip line when the substrate is used for an electronic circuit. The characteristic impedance is expressed as natural logarithm ln (4h / (0.
536w + 0.67t)) is known in many textbooks, for example, Kisaburo Nakazawa et al., "VLSI System Design". Here, the symbol h is the thickness of the insulating layer, the symbol w is the wiring width, and the symbol t is the wiring thickness. From this relational expression, it is understood that controlling the thickness of each of the insulating layer and the conductor layer is important for controlling the impedance. When the characteristic impedance is constant (for example, 50Ω), as the wiring width becomes smaller, the insulation thickness becomes smaller, and the tolerance thereof becomes smaller. Also,
Management of width and thickness becomes more strict. That is,
In the era of high-speed operation where the operating frequency is approaching 1 GHz, it is important to control the thickness of each of the insulating layer and the conductor layer.

Next, the method for manufacturing the build-up core substrate according to the present invention will be described with reference to FIG. As shown in FIG. 2 (a), the assembly shown in FIG. 1 (d) is laminated with a prepreg 12 such as a glass fiber reinforced epoxy resin and heated and pressed to form a first laminated product (FIG. 2 (a)). The carrier layer 11 is removed from the first laminate with a ferric chloride solution. The carrier layer 11 improves handling due to its rigidity.

In order to improve the adhesive strength between the assembly (FIG. 1D) and the prepreg 12 used as an insulating plate, it is preferable to roughen the metal surface of the assembly (FIG. 1D). Although there is no particular limitation on the method of the roughening treatment, fine bumps are formed by plating or mechanically polished to improve the adhesive force between the metal surface and the epoxy resin.

As a material of the prepreg, besides glass fiber reinforced epoxy resin, glass fiber reinforced bismaleimide triazine (BT) resin or polyether sulfone (PES: poly-et)
her sulphon) epoxy resin, polyimide resin, polyamide imide resin, RCC (resin copper foil (Resin C
oated Copper)) and the like.

Other uncured or semi-cured prepregs include reinforced base materials such as glass cloth, glass fiber and paper, and polyimide resin, epoxy resin, phenolic resin, or a mixture of these resins. A material impregnated with a curing agent or a material cured to a semi-cured state (B-stage) by heating can be used. As this resin, a thermoplastic resin such as a fluorine resin can also be used. In the present invention, the formation of the insulating layers 12 and 13 is limited to a prepreg (a molding material in which a premixed resin, a pigment, a release agent, and the like to which a curing agent has been added is converted into a reinforcing fiber to be in a semi-cured state). Not done. An insulating layer such as a resin may be formed by a known method such as coating and hot melt.

In recent years, lead-free solder has been rapidly developed. Due to a rise in the temperature of the reflow furnace due to the lead-free process, a higher Tg (vitrification temperature) of the base material and the build-up layer is required. It is necessary to consider the build-up core substrate and the build-up layer of the present invention.

Further, the barrier layer 9 is formed by Enstrip TL
-142 concentrate to remove the second layered product (Fig. 2
(C)), the second laminate and the prepreg 13 are laminated, and heated and pressed to build up a core substrate (FIG. 2 (d)).
Get. Here, the material of the barrier layer is Ti, Sn, N
i or an alloy thereof, and the material of the post forming layer is Cu
Alternatively, the alloy and the material of the carrier layer are preferably Cu or an alloy thereof. In the present invention, the barrier layer 9 can be used as a means for controlling an accurate etching depth.

Now, a part of the build-up core substrate shown in FIG. 2D in which an insulating layer 10 such as a resin is provided on the outer periphery of the heat / electrically conductive post 16 and a perforated post forming layer 10 is provided on the outer periphery. completed. Next, 35 shown in FIG.
An adhesive release layer 21 is formed on a carrier copper foil 211 of about μm.
A member provided with an ultra-thin copper foil 21 having a thickness of about 3 to 5 μm via 2 is prepared. The parts shown in FIG.
The copper foil layer 21 is provided on the outermost layer by the member shown in FIG. Note that the release layer 21 of the member (FIG. 2E) is not necessarily limited to an adhesive layer, and does not hinder the technical idea of the present invention at all if it can be removed later. In the example of the manufacturing method shown in FIG.
However, the present invention is not limited thereto, and the ultra-thin copper foil layer 21 may be appropriately formed by a known method such as electrolytic or electroless plating, vapor deposition, or the like. When a member as shown in FIG. 2E is used, formation of an ultra-thin copper foil is easy.

Another manufacturing method of the build-up core substrate according to the present invention will be described with reference to FIG. The process described with reference to FIG. 2 can be used up to the process of forming an assembly (FIG. 1D) in which a plurality of the heat / electrically conductive posts 16 stand. Next, the semi-cured resin 14 is filled into the cavity 18 of the assembly (FIG. 3A) by heating by screen printing (FIG. 3B). Then, the carrier layer 11 is removed by etching (FIG. 3C). Further, the barrier layer 9 is removed by etching (FIG. 3D), and prepregs 12 and 13 are laminated from both sides of the main surface, and heated and pressed to obtain a build-up core substrate (FIG. 3E).

FIG. 4 is a partial sectional perspective view of a part of the build-up core substrate 1 according to the present invention from which the outer copper foil layer 21 and the prepreg layers 12 and 13 have been removed. An insulating material 17 surrounds the outer periphery of a plurality of standing thermally and electrically conductive posts 16 such as Cu, and a perforated plate 19 having a low coefficient of thermal expansion such as Fe-Ni is provided on the outer periphery. The use of the build-up core board 1 according to the present invention is, for example, a build-up wiring board 3 in which build-up layers 2a and 2b are added above and below the build-up core board 1, as illustrated in FIG. Generally, a build-up wiring board is, for example, a base part made of a glass-epoxy laminate, and a through-hole connecting the surface of the base is filled with an epoxy resin, or a surface-mounted build-up, or the aforementioned build-up. It refers to a combination of a wiring board and surface mounting. A wiring conductor layer is formed on each of the upper surface of the build-up layer 2a and the lower surface of the build-up layer 2b. The number of build-up layers is not limited to one but is often a plurality.

When the build-up core substrate 1 of the present invention is used as a build-up wiring board, the encapsulated heat and electric conductive posts are selectively used by opening them with a laser, for example. Thereby, the heat / electrically conductive post can be formed with extremely high precision. The heat / electrically conductive post functions as a thermal via, and has a configuration in which heat is efficiently transmitted through the thermal via.

The manufacture of the build-up wiring board illustrated in FIG. 5 in which the build-up layers (2a, 2b) are added to the build-up core board (1) is not particularly limited, and the above-described manufacturing methods are appropriately combined. Good. For example, a metal foil obtained by pattern-etching a circuit pattern on the build-up core substrate (1), the build-up core substrate (1), and the prepreg may be overlaid and pressurized and heated. As shown in FIG.
It is also easy to manufacture a more complicated build-up wiring board.

A method of manufacturing the build-up core substrate 3 shown in FIG. 6 will be described with reference to FIGS. FIG. 7 (a) shows the heat and heat of a plurality of forests such as Cu on one surface of the barrier layer 9.
FIG. 7 (b) shows the prepreg 12
FIG. 7C shows a perforated plate 19 made of Fe—Ni alloy or the like in which holes of 0.3 mm in diameter are formed at a pitch of 0.4 mm.
For example, one manufactured by pattern etching is shown. As shown in FIG. 7D, the heat / electrically conductive posts 16, the prepreg 12, and the pattern-etched product 20 are laminated and pressed with a heated pressing plate to produce a laminated product.

FIG. 8A is a diagram showing the laminated product manufactured in FIG. 7D in an inverted state. This F
The carrier layer 11 of the e-Ni alloy and then a part of the Ti barrier layer 9 are etched away as shown in FIG. Next, this is laminated with the prepreg 13 shown in FIG. 8 (c), and heated and pressed to form a laminate product shown in FIG. 8 (d).
That is, the build-up core substrate 1 is obtained.

The thermal expansion coefficient of the 42 alloy was 4.2 ppm.
On the other hand, Cu is as large as 16 ppm, but in the build-up core substrate of the present invention, for example, as shown in the schematic diagram of FIG. The ratio of 19 is overwhelmingly large. Therefore, the thermal expansion coefficient of the build-up core substrate as a whole is very low, close to 42 alloy.

Since the Fe—Ni alloy is used for the purpose of imparting low thermal expansion characteristics, it is desirable to arrange an alloy thin plate having an average thermal expansion coefficient in the range of 30 to 300 ° C. in the range of 4 to 6 ppm / ° C. Specific examples of the Fe-Ni alloy used include a so-called invar alloy of an Fe-42% Ni alloy and an Fe-36% Ni alloy, and an Fe-31% Ni-5% C alloy.
o-alloy, so-called Super Invar alloy, Fe-29%
Ni-30% such as Ni-17% Co alloy, balance Fe
Alternatively, a material in which Ni is partially substituted with Co as a basic element can be used. Among them, for example, to form on the upper surface of the silicon chip, an Fe-36% Ni alloy or an Fe-31%
It is desirable to use a Ni-5% Co alloy.

Conventionally, as a factor that greatly impaired connection reliability, there is a problem of disconnection of a solder ball portion caused by a difference between a silicon chip and a substrate or an interposer (coefficient of thermal expansion of about 16 ppm / ° C.). According to the present invention, it is possible to reduce the thermal expansion of the base material of the substrate and at the same time impart heat radiation characteristics to the problem. It can diffuse in the horizontal and horizontal directions. The heat / electrically conductive post is also called a conductive post.

When an Fe—Ni alloy is used for the perforated plate 19 in the present invention, a good thermal expansion coefficient gradient and layer can be obtained between the semiconductor chip 4 and the build-up wiring board 3. In addition, reliability deterioration due to cracks due to heat cycle, heat shock, etc. can be greatly improved. In one embodiment shown in FIG. 5, the build-up wiring board 3 on which the semiconductor chip 4 is mounted and the printed wiring board PWB (not shown) on which the build-up wiring board 3 is mounted have a thermal expansion coefficient of 3.2 ppm / ° C, 8-10 ppm / ° C, 1
7 ppm / ° C., which shows a good gradient and hierarchy of the coefficient of thermal expansion.

In the build-up wiring board illustrated in FIG. 6, as shown by Vcc and Vss in the drawing, it is possible to selectively use the power supply voltage layer and the earth layer according to the circuit configuration. According to the present invention, in order to easily enable such a configuration, in the present situation where the voltage fluctuation is likely to occur due to an increase in the clock frequency of the chip, a stable ground (ground, ground) Also called). Although FIG. 6 shows an example of the perforated plate 19 superimposed on two layers, according to the present invention, any number of layers can be easily manufactured.

An example of a method for manufacturing a build-up core substrate according to the present invention has been described with reference to FIGS. 2 and 3, but the present invention is not limited to this. Metal foils and resin films wound on reels And a roller-to-reel (reel-to-reel) method can be used to continuously process up to the photoetching and laminating steps. FIG. 10 shows an example. FIG. 10 (a) shows a state of being wound on a reel, and FIGS. 10 (b) and 10 (c) are partially enlarged views thereof. This corresponds to, for example, FIG. In the case of such a reel shape, there is an advantage that handling properties are remarkably improved and automatic production of electronic packages is facilitated.

According to the present invention, an interposer provided with a plurality of heat / electrically conductive posts can be easily obtained, and an island-shaped heat / electricity isolated from the insulating substrate as a heat / electrically conductive post by etching the substrate. An electrically conductive post portion is formed. Since the substrate of the present invention uses a conductive plate having excellent etching properties, it is suitable for high-density wiring with a narrow pitch, so that the number of conventional build-up layers can be reduced. Therefore, when the substrate of the present invention is used, the wiring density of the substrate itself can be increased, and it is particularly effective for a build-up wiring substrate on which the substrate of the present invention is laminated, for example, flip-chip mounting, Wafer Level CSP, and the like. Reducing the number of build-up layers directly leads to cost reduction.

Further, according to the present invention, a semiconductor device can be formed using a build-up wiring board. Although the semiconductor device of the present invention is not particularly limited, it is flip-chip mounted via a solder ball for guiding a signal from a semiconductor chip to the outside, and further mounted on a build-up wiring board in which a plurality of printed boards are stacked. Since the semiconductor device can transmit a signal and uses a conductive plate having a good etching property suitable for a narrow pitch, it is particularly suitable for a semiconductor device directly mounted on a build-up wiring board.

Further, in the present invention, since it is suitable for high-density wiring with a narrow pitch, the wiring density can be increased by using the substrate of the present invention, so that the number of conventional build-up laminations can be reduced. . As described above, in the present invention, preferred materials for the barrier layer (9), the post forming layer (10), the carrier layer (11), the heat / electrically conductive post (16), and the perforated plate (19) are each a barrier layer. (9) is N
For example, i, Ti, Sn, etc., the post forming layer (10) is Cu, the carrier layer (11) is an Fe-Ni alloy, the thermoelectrically conductive plate (15) is an Fe-Ni alloy, and the thermoelectrically conductive post (1).
6) is Cu, and the perforated plate (19) is an Fe-Ni alloy, but the technical idea of the present invention can be applied as long as it has an equivalent function and effect.

In the build-up core substrate according to the present invention, a copper foil 21 is further adhered to the outer insulating layer 12. For the attachment, a composite copper foil having an organic-based release layer 212 between the carrier copper foil layer 211 (which is to be peeled and removed after use) and the ultra-thin copper foil 21 may be used. Hereinafter, the manufacturing method will be outlined. As the carrier copper foil layer 211, an electrolytic copper foil having a thickness of 35 μm is used. Such an electrolytic copper foil has a rough surface (matte surface) and a smooth (glossy) surface. On the glossy surface side, an organic release layer is formed as follows, and then primary copper electrodeposition, secondary copper electrodeposition, roughening treatment and rust prevention treatment are performed.

(A) Formation of Release Layer A 35 μm copper foil was immersed in a 2 g / L solution of carboxybenzotriazole (CBTA) at 30 ° C. for 30 seconds, taken out, and washed with deionized water to form an organic release layer of CBTA. Form. SIM the thickness of the obtained organic release layer
It was 60 ° when measured from an image obtained by using a (scanning ion microscope).

(B) Primary Copper Electrodeposition On the surface of the formed organic release layer, a pH 8.5 copper pyrophosphate copper electrodeposition bath containing 17 g / L of copper and 500 g / L of potassium pyrophosphate was applied. Bath temperature 50 ° C, current density 3A /
Cathodic electrolysis was carried out at dm ² to deposit 1 μm thick copper. (C) Secondary copper electrodeposition The surface of the formed ultra-thin copper foil was washed with water, and using a copper sulfate electrodeposition bath containing copper 80 g / L and sulfuric acid 150 g / L, a bath temperature of 50 ° C. and a current density of 60 A / dm ² for cathodic electrolysis, 5μm
Is deposited to form an ultrathin copper foil layer having a total thickness of 6 μm.

(D) Roughening treatment The surface of the ultra-thin copper foil layer thus formed is subjected to a roughening treatment. The current density is increased to form conductive copper fine particles on the surface of the ultra-thin copper foil. (E) Rust prevention treatment The surface of the ultra-thin copper foil layer subjected to the roughening treatment is subjected to zinc chromate rust prevention treatment by electrodeposition to obtain a composite copper foil.

The "transfer method" can be used for forming the ultra-thin copper foil layer. The outline will be described below. After forming an Ni plating layer as a barrier material using an electrolytic copper foil as a carrier material as a cathode, copper sulfate plating is performed as a wiring portion forming material to prepare a three-layer transfer method foil material. next,
A dry film resist is laminated, a desired resist pattern is formed by exposure and development, a wiring portion forming material is selectively etched, and the resist remaining on the wiring forming material is peeled off using a potassium hydroxide solution.

Next, the foil material for the transfer method obtained by the above process was set in a mold, the copper wiring pattern side was transferred to a glass epoxy resin, and the carrier material and the barrier material were selectively etched and transferred. Since only the copper wiring pattern can be left, it can be said that this method is suitable for forming a wiring having a narrow pitch with a wiring width of 50 μm or less and a wiring distance of 50 μm or less. The thickness of ultra-thin copper foil by transfer method is 5-18
It is about μm. Therefore, the thickness of the copper foil used in the present invention is 18 μm or less when the transfer method is used, and can be 5 μm or less when the above-described composite copper foil with a release layer is used.

The build-up core substrate according to the present invention has an extremely thin copper foil layer on the outermost layer 21. Therefore, a fine pitch etching pattern can be easily formed,
The effects of miniaturization and high density of the semiconductor package are great. Further, unlike the conventional case, it is not necessary to perform the blackening process for preventing the reflection of the laser beam at the time of laser drilling. This is because the laser beam can easily pass through the copper foil because the copper foil is extremely thin.

[0064]

According to the etching method using the barrier layer, it is possible to obtain a substrate enclosing the heat and electric conductive posts with extremely small variation in shape and size. Further, since short-distance wiring is enabled, it is possible to easily cope with an increase in operating frequency. Further, according to the present invention, since the metal core is used, the dimensional stability is excellent, and the rigidity is high even if it is thin.
Since the electrically conductive post is used, a drilling process of a through hole by a drill or a laser for the core substrate as in the related art is not required. No plating is necessary on the inner surface of the through-hole. In addition, since it can be manufactured at a high density, the upper and lower surfaces of the build-up layer can be effectively used, so that the cost can be reduced by reducing the number of layers.

[Brief description of the drawings]

FIG. 1 is a view showing a pattern-etched product of a build-up core substrate according to the present invention.

FIG. 2 is a view illustrating a method of manufacturing a build-up core substrate according to the present invention.

FIG. 3 is a view showing another method of manufacturing the build-up core substrate according to the present invention.

FIG. 4 is a perspective and partial sectional view of a build-up core substrate according to the present invention.

FIG. 5 is a diagram of a build-up wiring board according to the present invention.

FIG. 6 is a diagram of another build-up wiring board according to the present invention.

FIG. 7 is a view illustrating a part of a manufacturing process of the build-up core substrate illustrated in FIG. 6;

FIG. 8 is a view showing the remaining part of the manufacturing process of the build-up core substrate shown in FIG. 6;

FIG. 9 is a schematic diagram showing a state of heat radiation of the build-up wiring board according to the present invention.

FIG. 10 is a view showing still another method of manufacturing the build-up core substrate according to the present invention.

FIG. 11 is a view showing a conventional build-up wiring board.

FIG. 12 is a diagram illustrating a problem of a conventional etching method.

[Explanation of symbols]

1. Build-up core substrate, 2a. Side build-up layer,
2b. Lower build-up layer, build-up wiring board,
4. Semiconductor chips, 5a, 5b. 5. solder balls; 6. Underfill, 7. 7. wiring pattern; 8. through hole,
10. barrier layer; 10. post-forming layer; Carrier layer, 1
2,13. Insulating plate, 14. 14. filled resin; 15. heat and electric conductive plate; 17. thermal and electrical conductive posts; Insulating material,
18. Cavity, 19. Perforated plate

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[Procedure amendment]

[Submission date] February 5, 2001 (2001.2.5)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 23/12 501 H01L 23/12 501B H05K 1/05 H05K 1/05 Z 1/11 1/11 L 3 / 40 3/40 H 3/44 3/44 BF term (reference) 5E315 AA05 AA11 BB05 BB14 BB18 CC16 CC21 DD16 DD17 DD20 GG01 GG07 GG20 5E317 AA24 BB01 BB12 BB18 CC60 CD21 CD25 CD27 CD32 GG01 GG11 A12A04A12 AA29 AA32 AA42 AA43 CC04 CC09 CC32 DD16 DD23 DD24 DD32 EE09 EE13 EE19 FF01 FF27 GG15 GG22 HH11 HH17 HH31

Claims (10)

[Claims] 1. A thermally and electrically conductive plate having a low coefficient of thermal expansion having a plurality of through holes in a plate thickness direction, and a material different from the thermally and electrically conductive plate having a plurality of through holes and having a low coefficient of thermal expansion. A plurality of island-shaped thermally and electrically conductive posts provided in the through hole, and a plurality of thermally and electrically conductive plates provided on the outer periphery of the plurality of thermally and electrically conductive posts and having a low coefficient of thermal expansion. An insulating material interposed therebetween for electrically insulating the plurality of thermally and electrically conductive posts, an insulating plate joined to both main surfaces of the thermally and electrically conductive plate having a low coefficient of thermal expansion, A build-up core substrate comprising an ultrathin copper foil layer having a thickness of 18 μm or less provided on one or both main surfaces of a plate. 2. The method according to claim 2, wherein the plurality of thermally and electrically conductive posts are Cu.
Or a Cu alloy, which has the plurality of through holes
The build-up core substrate according to claim 1, wherein the electric conductive plate is made of an Fe-Ni alloy. 3. The plurality of thermally and electrically conductive posts have a diameter of 0.01 to 0.2 mm and a pitch of 0.1 to 1.0 m.
The build-up core substrate according to claim 1, wherein m is m. 4. The insulating material is a glass fiber reinforced epoxy resin, a glass fiber reinforced bismaleimide triazine (B
T) Resin or polyether sulfone (PES)
2. The composition according to claim 1, wherein the resin is one of a compounded epoxy resin, a polyimide resin, and a polyamideimide resin.
The build-up core substrate as described. 5. The build-up core substrate according to claim 1, wherein an insulating material and a perforated plate are provided on the outer periphery of the plurality of heat and electric conductive posts. 6. A build-up wiring board comprising: the build-up core board according to claim 1; and build-up layers formed on both main surfaces of the build-up core board. 7. A method for manufacturing a build-up core substrate, comprising the following steps. (1) A post forming layer is bonded to one main surface of the barrier layer, and a carrier layer is bonded to the other main surface. (2) A mask for removing a predetermined region is placed on the post forming layer. (3) The predetermined region is removed by etching until the barrier layer is reached, thereby producing a first pattern-etched product having a plurality of thermal and electric conductive posts. (4) Combine the first pattern-etched product with a perforated plate. (5) The first pattern-etched product and the perforated plate are plated with Cu or roughened. (6) Thereafter, the insulating plates are laminated, and heated and pressed to form a first laminated product. (7) removing the carrier layer from the first laminate. (8) The barrier layer is further removed to obtain a second laminate. (9) The second laminate and the insulating plate are laminated. (10) A thickness of 1 on one or both main surfaces of the insulating plate.
An ultra-thin copper foil layer of 8 μm or less is laminated to produce a build-up core substrate. 8. A method for manufacturing a build-up core substrate, comprising the following steps. (1) A post forming layer is bonded to one main surface of the barrier layer, and a carrier layer is bonded to the other main surface. (2) A mask for removing a predetermined region is placed on the post forming layer. (3) The predetermined region is removed by etching until the barrier layer is reached, thereby producing a first pattern-etched product having a plurality of thermal and electric conductive posts. (4) An assembly having a cavity is obtained by combining the first pattern-etched product with a perforated plate. (5) The first pattern-etched product and the perforated plate are subjected to Cu plating or roughening treatment. (6) The cavity is filled with a resin by a screen printing method. (7) The carrier layer is removed by etching. (8) The barrier layer is further removed by etching. (9) Next, insulating plates are laminated from both sides of the main surface. (10) A thickness of 1 on one or both main surfaces of the insulating plate.
An ultra-thin copper foil layer of 8 μm or less is provided to manufacture a build-up core substrate. 9. The build-up core substrate according to claim 1, wherein the thickness of the ultra-thin copper foil is 5 μm or less. 10. The method for manufacturing a build-up core substrate according to claim 7, wherein the thickness of the ultra-thin copper foil is 5 μm or less.