JP2017188505A - Semiconductor device and active matrix substrate using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that is advantageous to reduction in power consumption, and to provide an active matrix substrate using the same.SOLUTION: A semiconductor device 1A according to an embodiment comprises: an insulation substrate 10 that includes a pixel region DA and a peripheral circuit region PA around the pixel region; a first insulating layer 11 provided on the insulation substrate and containing at least nitrogen; second insulating layers 12A and 12B provided at least on the first insulating layer in the peripheral circuit region; a first thin-film transistor TrA provided above the first insulating layer in the pixel region, and comprising a first oxide semiconductor layer 13A; and a second thin-film transistor TrB provided on the second insulating layer in the peripheral circuit region, and comprising a second oxide semiconductor layer 13B. A film thickness TA of the second insulating layer in the pixel region is thinner than that in the peripheral circuit region.SELECTED DRAWING: Figure 1

Description

  Embodiments of the present invention generally relate to a semiconductor device and an active matrix substrate using the semiconductor device.

  For example, in a display device such as a television, a personal computer, a smartphone, or a tablet terminal, a thin film transistor for configuring each pixel is known (see, for example, Patent Document 1).

  In such a display device, not only the improvement of the image quality of the pixel region but also the reduction of the power consumption of the semiconductor device and the active matrix substrate used in the display device have become more important.

JP 2011-228622 A

  The present embodiment provides a semiconductor device advantageous for reducing power consumption and an active matrix substrate using the semiconductor device.

  The semiconductor device according to the embodiment includes an insulating substrate including a pixel region and a peripheral circuit region around the pixel region, a first insulating layer including at least nitrogen provided on the insulating substrate, and at least the peripheral circuit region. A second insulating layer provided on the first insulating layer, a first thin film transistor provided on the pixel region above the first insulating layer and including a first oxide semiconductor layer, and the peripheral circuit region And a second thin film transistor provided with a second oxide semiconductor layer. The film thickness of the second insulating layer in the pixel region is the second thin film transistor in the peripheral circuit region. 2 It is thinner than the thickness of the insulating layer.

  The semiconductor device according to the embodiment includes an insulating substrate including a pixel region and a peripheral circuit region around the pixel region, a first insulating layer provided on the insulating substrate and including at least nitrogen, and the first insulating layer A second insulating layer provided on the first insulating film; a first thin film transistor including a first oxide semiconductor layer provided on the second insulating layer in the pixel region; and on the second insulating layer in the peripheral circuit region. And a second thin film transistor including a second oxide semiconductor layer, wherein the film thickness of the first insulating layer in the pixel region is greater than the film thickness of the first insulating layer in the peripheral circuit region. Also thick.

1 is a cross-sectional view schematically showing an example of a semiconductor device applied to an active matrix substrate according to a first embodiment. FIG. 3 is a diagram for explaining threshold voltages of first and second thin film transistors shown in FIG. 1. Sectional drawing which shows an example of the manufacturing method of the semiconductor device shown in FIG. Sectional drawing which shows the manufacturing process following FIG. Sectional drawing which shows the manufacturing process following FIG. Sectional drawing which shows the manufacturing process following FIG. Sectional drawing which shows the manufacturing process following FIG. Sectional drawing which shows the manufacturing process following FIG. Sectional drawing which shows the manufacturing process following FIG. 9 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device applied to an active matrix substrate according to Modification Example 1. FIG. Sectional drawing which shows the manufacturing process following FIG. Sectional drawing which shows the manufacturing process following FIG. FIG. 14 is a cross-sectional view schematically showing an example of a semiconductor device applied to an active matrix substrate according to Modification Example 2. Sectional drawing which shows the semiconductor device applied to the active matrix substrate which concerns on 2nd Embodiment. FIG. 15 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. 14. Sectional drawing which shows the manufacturing process following FIG. Sectional drawing which shows the manufacturing process following FIG. The block diagram which shows roughly an example of the display apparatus to which the active matrix substrate using the semiconductor device which concerns on 1st, 2nd embodiment and the modifications 1 and 2 is applied. FIG. 19 is an equivalent circuit diagram schematically showing an example of the pixel region and the peripheral circuit region shown in FIG. 18.

  Hereinafter, the present embodiment will be described with reference to the drawings. Note that the drawings are schematically shown for the sake of clarity. For this reason, although the width | variety, thickness, shape, etc. of each part may differ from an actual aspect, the interpretation of this invention is not limited. In addition, in the present specification and each drawing, components that exhibit the same or similar functions as those described above are denoted by the same reference numerals, and redundant descriptions may be omitted as appropriate.

(First embodiment)
A semiconductor device applied to the active matrix substrate according to the first embodiment will be described with reference to FIGS.

[1. Constitution]
1-1. Sectional Configuration A semiconductor device 1A applied to the active matrix substrate according to the first embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device 1A applied to the active matrix substrate according to the first embodiment. In FIG. 1, a horizontal direction parallel to the substrate surface of the insulating substrate 10 is indicated as an X direction, and a direction crossing the X direction substantially at right angles is indicated as a Y direction. Here, the semiconductor device 1A will be described by taking an organic electroluminescence (organic EL) display device as an example, but is not limited thereto as will be described later.

  As shown in FIG. 1, the semiconductor device 1A includes first and second thin film transistors TrA and TrB provided on a substrate including an insulating substrate 10.

  The substrate includes an insulating substrate 10 and a base layer (undercoat layer) 19 that is provided on the insulating substrate 10 and prevents diffusion of impurities in the insulating substrate 10.

  The insulating substrate 10 includes a pixel area DA and a peripheral circuit area PA around the pixel area DA. The insulating substrate 10 is formed of an insulating material such as glass or resin.

  The foundation layer (undercoat layer) 19 includes a foundation layer 19A provided in the pixel area DA and a foundation layer 19B provided in the peripheral circuit area PA. The base layer 19 </ b> A in the pixel area DA includes a first insulating layer 11 provided on the insulating substrate 10 and a second insulating layer 12 </ b> A provided on the first insulating layer 11. The base layer 19B in the peripheral circuit area PA includes a first insulating layer 11 provided on the insulating substrate 10 and a second insulating layer 12B provided on the first insulating layer 11.

The first insulating layer 11 is formed of an insulating material containing at least nitrogen (N). The first insulating layer 11 is formed of, for example, a silicon nitride (Si ₃ N ₄ ) film or a silicon oxynitride (SiON) film. The film thickness T11 of the first insulating layer 11 is, for example, about 200 nm, and is provided so as to have substantially the same (common) film thickness in the pixel area DA and the peripheral circuit area PA.

The second insulating layers 12A and 12B are formed of an insulating material containing at least oxygen (O). The second insulating layers 12A and 12B are formed of, for example, a silicon oxide film (SiO ₂ ) or the like. The film thickness T12A of the second insulating layer 12A in the pixel area DA is, for example, about 50 nm to 100 nm. The film thickness T12B of the second insulating layer 12B in the peripheral circuit area PA is, for example, about 200 nm. Accordingly, the thickness T12B of the second insulating layer 12B in the peripheral circuit area PA is configured to be thicker than the film thickness T12A of the second insulating layer 12A in the pixel area DA (T12B> T12A). As a result, the film thickness TB of the base layer 19B in the peripheral circuit area PA is configured to be thicker (TB> TA) than the film thickness TA of the base layer 19A in the pixel area DA.

(First and second thin film transistors TrA and TrB)
The first and second thin film transistors TrA and TrB are, for example, n-type top gate thin film transistors (TFTs). The first thin film transistor TrA includes an oxide semiconductor layer 13A provided on the second semiconductor layer 12A. The second thin film transistor TrB includes an oxide semiconductor layer 13B provided on the second semiconductor layer 12B.

  The oxide semiconductor layers 13A and 13B include a source / drain region (not shown) and a channel region provided between the source region and the drain region. The oxide semiconductor layers 13A and 13B are formed of a transparent amorphous semiconductor (TAOS) such as indium gallium zinc oxide (IGZO), for example. Note that the material forming the oxide semiconductor layers 13A and 13B only needs to contain at least one of indium (In), gallium (Ga), and tin (Sn), for example, indium gallium oxide (IGO), oxide Indium zinc (IZO), zinc tin oxide (ZnSnO), zinc oxide (ZnO), or the like may be used.

  As will be described later, the oxide semiconductor layer 13A in the pixel area DA has a higher carrier density and lower resistance than the oxide semiconductor layer 13B in the peripheral circuit area PA. Therefore, the threshold voltage VthA of the first thin film transistor TrA is configured to be lower than the threshold voltage VthB of the second thin film transistor TrB (VthA <VthB).

  On the channel regions of the oxide semiconductor layers 13A and 13B, a gate insulating film 14 formed of, for example, a silicon oxide (SiO) film is provided.

  On the gate insulating film 14, a gate electrode 15 formed of a metal film such as a layer structure of titanium, aluminum, and molybdenum nitride is provided. The gate electrode 15 may be, for example, an alloy of aluminum (Al), copper (Cu), copper (Cu), or an alloy thereof.

  Interlayer insulating films 16 and 18 formed of, for example, a silicon oxide film are provided so as to cover the first and second transistors TrA and TrB. Source / drain contact wirings 17 are provided in the interlayer insulating films 16 and 18 on the source / drain regions of the oxide semiconductor layers 13A and 13B, respectively.

  Although not shown here, the semiconductor device 1 </ b> A may further include a corresponding substrate or the like on the interlayer insulating film 18.

1-2. Threshold Voltage The threshold voltage of the first and second thin film transistors TrA and TrB having the above configuration will be described with reference to FIG. FIG. 2 is a diagram for explaining the threshold voltages of the first and second thin film transistors TrA and TrB, and shows the relationship between the gate voltage Vg of the first and second thin film transistors TrA and TrB and the drain current Id. Show.

  As shown in FIG. 2, the threshold voltage VthA of the first thin film transistor TrA is configured to be lower than the threshold voltage VthB of the second thin film transistor TrB (VthA <VthB). This is because, as described above, the oxide semiconductor layer 13A in the pixel area DA has a higher carrier density and lower resistance than the oxide semiconductor layer 13B in the peripheral circuit area PA.

  According to the above configuration, as shown in FIG. 2, for example, when the gate voltage Vg1 is applied to each gate electrode, in the first thin film transistor TrA, the gate voltage Vg1 is sufficiently larger than the threshold voltage VthA. Therefore, the current path of the first thin film transistor TrA becomes conductive, and a sufficiently large drain current IdA flows in the channel region of the oxide semiconductor device 13A. On the other hand, in this case, in the second thin film transistor TrB, the gate voltage Vg1 is lower than the threshold voltage VthB. Therefore, the current path of the second thin film transistor TrB becomes non-conductive, and only a sufficiently small drain current IdB flows in the channel region of the oxide semiconductor device 13B.

  As a result, even when the same gate voltage Vg1 is applied, it is possible to contribute to improvement in image quality by obtaining a larger drain current IdA in the pixel area DA, and leakage by suppressing the drain current IdB to a small amount in the peripheral area PA. The current can be kept small, and the power consumption can be reduced.

[2. Production method]
Next, a method for manufacturing the semiconductor device 1A according to the first embodiment will be described with reference to FIGS.

As shown in FIG. 3, a silicon nitride film having a thickness T11 of about 200 nm is formed on the insulating substrate 10 in the pixel area DA and the peripheral circuit area PA by using, for example, a plasma chemical vapor deposition method (plasma CVD method). A first insulating layer 11 is formed by deposition. When forming the plasma CVD method by the first insulating layer 11, the deposition temperature is a 400 ° C. of about from 300 ° C., such as silane _(SiH 4), ammonia (NH ₃₎ reactions involving hydrogen (H), such as Plasma generated using gas is used. Therefore, the first insulating layer 11 is formed in a state including a part of hydrogen (H) in the reaction gas.

Subsequently, as shown in FIG. 4, a silicon oxide film having a thickness of T12B of about 200 nm is deposited on the first insulating layer 11 in the pixel area DA and the peripheral circuit area PA by using, for example, a plasma CVD method. Two insulating layers 12 are formed. Similarly, when the second insulating layer 12 is formed by plasma CVD, plasma is generated using a reaction gas containing hydrogen (H) such as silane (SiH ₄ ) or dinitrogen monoxide (N ₂ O). Is used. Therefore, even when the second insulating layer 12 is formed, the first insulating layer 11 similarly contains a part of hydrogen (H) in the reaction gas.

  Subsequently, a photoresist 20 is applied on the entire surface of the second insulating layer 12, and the photoresist 20 is patterned so that the surface of the second insulating layer 12A in the pixel area DA is exposed. Subsequently, using the patterned photoresist 20 as a mask, for example, etching such as dry etching by RIE method or predetermined wet etching is performed, and the film thickness T12A of the second insulating layer 12A in the pixel region DA is set to, for example, 50 nm in the Y direction. To about 100 nm. As a result, the film thickness T12B of the second insulating layer 12B in the peripheral circuit area PA is formed to be thicker (T12B> T12A) than the film thickness T12A of the second insulating layer 12A in the pixel area DA.

  Subsequently, as shown in FIG. 5, the photoresist 20 in the peripheral circuit area PA is removed, and the base layer 19 </ b> A composed of the first and second insulating layers 11 and 12 </ b> A in the pixel area DA and the peripheral circuit area PA are formed. An underlying layer 19B composed of the first and second insulating layers 11 and 12B is formed. As a result, the film thickness TB of the base layer 19B in the peripheral circuit area PA is formed thicker (TB> TA) than the film thickness TA of the base layer 19A in the pixel area DA.

  Subsequently, as shown in FIG. 6, the second insulating layers 12 </ b> A and 12 </ b> B include at least one of indium (In), gallium (Ga), and tin (Sn) by using, for example, a sputtering method, and have a desired shape. Oxide semiconductor layers 13A and 13B that are patterned are formed.

  The temperature of the first insulating layer 11 in this step is about 300 ° C. to 400 ° C., which is the film formation temperature. Therefore, hydrogen (H) contained in the first insulating layer 11 diffuses from the first insulating layer 11 to the surroundings. Here, the film thickness T12B of the second insulating layer 12B in the peripheral circuit area PA is formed to be thicker (T12B> T12A) than the film thickness T12A of the second insulating layer 12A in the pixel area DA. Therefore, in the peripheral circuit region PA, the second insulating layer 12B functions as a barrier for diffused hydrogen, and the diffused hydrogen is prevented from diffusing into the oxide semiconductor layer 13B.

  On the other hand, in the pixel area DA, since the first insulating layer 11A is thin, the diffused hydrogen reaches the oxide semiconductor layer 13A. Therefore, the hydrogen reaching the oxide semiconductor layer 13A causes the oxide semiconductor layer 13A to have a higher hydrogen density than the oxide semiconductor layer 13B.

  The hydrogen diffusion into the oxide semiconductor layer 13A is for controlling the threshold voltage of the first and second thin film transistors TrA and TrB. Hydrogen is not limited to the lower surface of the oxide semiconductor layer 13A, but is oxidized. The entire semiconductor semiconductor layer 13A may diffuse. Further, the diffusion of hydrogen from the first insulating layer 11 is not limited to the step of forming the oxide semiconductor layers 13A and 13B. If the temperature of the first insulating layer 11 is about 300 ° C. to 400 ° C., which is the film forming temperature, hydrogen can diffuse from the first insulating layer 11 in the same manner. For example, as will be described later, the threshold voltage of the first and second thin film transistors TrA and TrB can be controlled by using an annealing process after the first and second thin film transistors TrA and TrB are formed. Good.

  Subsequently, a silicon oxide film for forming a gate insulating film covering the oxide semiconductor layers 13A and 13B is formed on the entire surface by using, for example, a CVD method. Subsequently, a metal film for forming a gate electrode is formed on the formed silicon oxide film by using, for example, a sputtering method. The metal film is formed with a layer structure of, for example, titanium, aluminum, and molybdenum nitride.

  Subsequently, as shown in FIG. 7, for example, a predetermined etching process is performed on the metal film using a photoresist (not shown) patterned corresponding to the approximate center of the oxide semiconductor layers 13A and 13B as a mask. Each gate electrode 15 is formed. Subsequently, the silicon oxide film is etched by using predetermined dry etching or the like to form each gate insulating film 14. In this etching step, the oxide semiconductor layers 13A and 13B are over-etched in a region where the gate electrode 15 and the gate insulating film 14 are not formed. In the overetched regions of the oxide semiconductor layers 13A and 13B, oxygen vacancies are generated, and source / drain regions with high carrier density and low resistance of the n-channel MOS transistor are formed. In the oxide semiconductor layers 13A and 13B, a channel region having a carrier density lower than that of the source / drain region is formed in a region not overetched, that is, a region covered with the gate insulating film 14. The carrier density in the channel regions of the oxide semiconductor layers 13A and 13B is controlled according to the above-described hydrogen density, and the carrier density of the oxide semiconductor layer 13A is higher than the carrier density of the oxide semiconductor layer 13B.

  Subsequently, as shown in FIG. 8, a silicon oxide film is formed on the entire surface so as to cover the gate electrode 15 by using, for example, a CVD method, and an interlayer insulating film 16 is formed. Subsequently, contact holes 161 reaching the source / drain regions of the oxide semiconductor layers 13A and 13B are formed in the interlayer insulating film 16 by using, for example, the RIE method.

  Subsequently, as shown in FIG. 9, a metal film having a laminated structure such as molybdenum, aluminum, and molybdenum nitride is buried in each contact hole 161 by using, for example, a sputtering method, and the contact wiring in the source / drain region. 17 are formed. Subsequently, a silicon oxide film is formed on the entire surface by, for example, a similar process, and an interlayer insulating film 18 (not shown) is formed.

  With the above manufacturing method, the semiconductor device 1A including the first and second thin film transistors TrA and TrB shown in FIG. 1 is manufactured.

[Function and effect]
As described above, the film thickness T12B of the second insulating layer 12B in the peripheral circuit area PA according to the first embodiment is larger than the film thickness T12A of the second insulating layer 12A in the pixel area DA (T12B>). T12A) is configured. As a result, the film thickness TB of the base layer 19B in the peripheral circuit area PA is configured to be larger than the film thickness TA of the base layer 19A in the pixel area DA (TB> TA).

  In the above configuration, in the process of forming the oxide semiconductor layer 13 illustrated in FIG. 6, in the peripheral circuit region PA, the second insulating layer 12 </ b> B functions as a barrier for hydrogen diffused from the first insulating layer 11, and the oxide semiconductor Hydrogen is prevented from diffusing into the layer 13B. On the other hand, in the pixel region DA, since the second insulating layer 12A is thin, hydrogen diffused from the first insulating layer 11 reaches the oxide semiconductor layer 13A. The hydrogen that has reached the oxide semiconductor layer 13A increases the carrier density of the oxide semiconductor layer 13A and lowers the resistance of the oxide semiconductor layer 13A.

  In this way, in the pixel area DA and the peripheral circuit area PA, the threshold voltages VthA and VthB of the first and second thin film transistors TrA and TrB arranged adjacent to each other can be made separately. For example, the threshold voltage VthA of the first thin film transistor TrA is configured to be lower than the threshold voltage VthB of the second thin film transistor TrB (VthA <VthB).

  According to the above configuration, as shown in FIG. 2, for example, even when the same gate voltage Vg1 is applied, it is possible to contribute to improvement in image quality by obtaining a larger drain current IdA in the pixel area DA. On the other hand, in the peripheral circuit area PA, the leakage current can be reduced by suppressing the drain current IdB to a small amount, which is advantageous in that the power consumption can be reduced.

  In addition, when the threshold voltages VthA and VthB are separately formed, in the etching process shown in FIG. 4, for example, by controlling the etching time, the thickness T12A of the second insulating layer 12A in the pixel area DA is controlled. It is only necessary to control the thinning. For example, if the film thickness T12A is reduced to about 50 nm by controlling the etching time longer, the threshold voltage VthA can be formed lower. Therefore, it is advantageous for reducing the manufacturing cost.

(Modification 1)
Another manufacturing method of the semiconductor device 1A according to the first embodiment will be described with reference to FIGS. Since the configuration is substantially the same as that of the first embodiment, detailed description thereof is omitted.

[Production method]
As shown in FIG. 10, a silicon nitride film having a film thickness T11 of about 200 nm is deposited on the insulating substrate 10 in the pixel area DA and the peripheral circuit area PA using, for example, plasma CVD, and the first insulating layer 11 is formed. Form.

  Subsequently, a silicon oxide film having a film thickness T121 of about 100 nm is deposited on the first insulating layer 11 in the pixel area DA and the peripheral circuit area PA by using, for example, a plasma CVD method to form the insulating layer 121.

  Subsequently, as shown in FIG. 11, a photoresist 21 is applied on the entire surface, and the photoresist 21 is patterned so that the surface of the insulating layer 121 in the pixel area DA is exposed. Subsequently, using the patterned photoresist 21 as a mask, etching such as RIE is performed on the surface of the first insulating layer 11 in the Y direction to remove the insulating layer 121 in the pixel region DA.

  Subsequently, as shown in FIG. 12, the photoresist 21 in the peripheral circuit area PA is removed, and a film thickness T122 of about 100 nm is formed on the entire surface of the pixel area DA and the peripheral circuit area PA by using, for example, a plasma CVD method. A silicon oxide film is deposited and an insulating layer 122 is formed.

  As a result, in the pixel area DA, the base layer 19A composed of the first insulating layer 11 and the second insulating layer 122 (12A) is formed. In the peripheral circuit area PA, a base layer 19B composed of the first insulating layer 11 and the second insulating layers 121 and 122 (12B) is formed. Therefore, the film thickness TB of the base layer 19B in the peripheral circuit area PA is formed thicker (TB> TA) than the film thickness TA of the base layer 19A in the pixel area DA.

  Thereafter, the semiconductor device 1A is manufactured using a manufacturing method similar to the manufacturing method of the first embodiment described above.

[Function and effect]
According to the configuration of the first modification and the manufacturing method thereof, the same effects as those of the first embodiment can be obtained. Further, in Modification 1, after the insulating layer 121 in the pixel area DA is removed, the insulating layer 122 is formed on the entire surface of the pixel area DA and the peripheral circuit area PA (FIGS. 11 and 12). In this way, by removing the insulating layer 121 in the pixel area DA and forming the second insulating layers 121 and 122, the film thickness difference (TB> TA) between the pixel area DA and the peripheral circuit area PA can be more reliably increased. Can be formed. Therefore, it is advantageous in that the difference between the threshold voltages VthA and VthB (VthB> VthA) can be provided more reliably.

(Modification 2 (an example in which the underlying layer of the pixel region does not include the second insulating layer))
A semiconductor device 1B according to Modification 2 of the first embodiment will be described with reference to FIG. The semiconductor device 1B according to the modification 2 relates to an example in which the base layer 19A in the pixel area DA does not include the second insulating layer 12. FIG. 13 is a cross-sectional view schematically showing an example of the semiconductor device 1B applied to the active matrix substrate according to the second modification.

[Constitution]
As shown in FIG. 13, in the semiconductor device 1B according to the second modification, the base layer 19A in the pixel area DA is not provided with the second insulating layer 12A and the base layer is compared with the first embodiment and the first modification. 19A is composed of only the first insulating layer 11. In other words, the film thickness of the second insulating layer 12A of the base layer 19A in the pixel area DA according to Modification 2 is substantially zero.

  Since other configurations are practically the same as those of the first embodiment and the first modification, detailed description thereof is omitted.

[Production method]
Regarding the manufacturing method, compared with the first embodiment, in the etching process shown in FIG. 4, for example, the etching time is controlled to be longer than that in the first embodiment until the surface of the first insulating layer 11 is exposed. The difference is that the second insulating layer 12A in the pixel area DA is etched. In other words, in this etching step, the etching is continued until the film thickness T12A of the second insulating layer 12A becomes substantially zero.

  Other configurations are substantially the same as those in the first embodiment and the first modification, and thus detailed description thereof is omitted.

[Function and effect]
In the semiconductor device 1B according to the second modification, the base layer 19A in the pixel area DA does not include the second insulating layer 12A, and the base layer 19A includes only the first insulating layer 11.

  Therefore, the base layer 19A in the pixel area DA does not include the second insulating layer 12 that functions as a barrier for preventing hydrogen diffused from the first insulating layer 11. Accordingly, hydrogen diffused from the first insulating layer 11 is diffused directly into the oxide semiconductor layer 13A. As a result, the oxide semiconductor layer 13A according to the modification 2 has a higher carrier density and lower resistance than the first embodiment and the modification 1. Thus, the second modification is advantageous in that the difference between the threshold voltages VthA and VthB (VthB> VthA) can be provided more directly and reliably.

  Further, since all the second insulating layer in the pixel area DA is removed, it is not necessary to control to leave the thin second insulating layer 12A as compared with the first embodiment. Therefore, manufacturing can be facilitated as compared with the first embodiment.

(Second embodiment (an example of controlling the thickness of the first insulating layer as a hydrogen generation source))
The configuration of the semiconductor device 1C according to the second embodiment and the manufacturing method thereof will be described with reference to FIGS. The second embodiment relates to an example of controlling the film thickness of the first insulating layer 11 as a hydrogen (H) generation source. With respect to this description, detailed description of portions substantially overlapping with the first embodiment will be omitted.

[Constitution]
Here, in the first embodiment, in the pixel region DA and the peripheral circuit region PA, the film thickness T11 of the first insulating layer 11 serving as a hydrogen generation source is equal (common), while preventing hydrogen diffusion. A difference is provided in the film thickness of the second insulating layer 12 as the barrier layer.

  On the other hand, in the second embodiment shown in FIG. 14, the film thickness T11A of the first insulating layer 11A in the pixel area DA is thicker than the film thickness T11B of the first insulating layer 11B in the peripheral circuit area PA. (T11A> T11B). On the other hand, the film thickness T12 of the second insulating layer 12 is substantially the same in the pixel area DA and the peripheral circuit area PA. As a result, in the second embodiment, the film thickness TB of the base layer 19B in the peripheral circuit area PA is configured to be smaller than the film thickness TA of the base layer 19A in the pixel area DA (TB <TA).

  Since the base layers 19A and 19B are configured as described above, the amount of hydrogen (H) generated from the first insulating layer 11A in the pixel area DA is equal to that generated from the first insulating layer 11B in the peripheral circuit area PA. More than the amount of (H). On the other hand, the film thickness T12 of the second insulating layer 12 as a barrier layer for preventing the diffusion of hydrogen (H) is constant in the pixel area DA and the peripheral circuit area PA.

  Therefore, the oxide semiconductor layer 13A in the pixel area DA has a higher carrier density and lower resistance than the oxide semiconductor layer 13B in the peripheral circuit area PA. As a result, similarly, the threshold voltage VthA of the first thin film transistor TrA is configured to be lower than the threshold voltage VthB of the second thin film transistor TrB (VthA <VthB).

  Since other configurations are substantially the same as those in the first embodiment, detailed description thereof is omitted.

[Production method]
Next, a method for manufacturing the semiconductor device 1C according to the second embodiment will be described with reference to FIGS.

  As shown in FIG. 15, a silicon nitride (SiN) film having a film thickness of about 200 nm is deposited on the insulating substrate 10 in the pixel area DA and the peripheral circuit area PA by using, for example, a plasma CVD method. Layer 11 is formed. Similarly, when the first insulating layer 11 is formed, the film formation temperature is about 300 ° C. to 400 ° C., and hydrogen (H) is used as a reactive gas for plasma CVD. Therefore, the first insulating layer 11 is formed in a state containing the hydrogen (H).

  Subsequently, a photoresist 22 is applied on the entire surface, and the photoresist 22 is patterned so that the surface of the first insulating layer 11 in the peripheral circuit area PA is exposed. Subsequently, using the patterned photoresist 22 as a mask, etching such as RIE is performed to control the etching time and the like, and the film thickness T11B of the first insulating layer 11 in the peripheral circuit region PA is set to about 100 nm in the Y direction, for example. To thin film.

  Subsequently, as shown in FIG. 16, the photoresist 22 is removed. As a result, the film thickness T11B of the first insulating layer 11B in the peripheral circuit area PA is formed to be smaller than the film thickness T11A of the first insulating layer 11A in the pixel area DA (T11B <T11A).

  Subsequently, as shown in FIG. 17, similarly, a silicon oxide film having a film thickness T12 of about 200 nm is formed on the first insulating layers 11A and 11B in the pixel area DA and the peripheral circuit area PA by using, for example, a plasma CVD method. And the second insulating layer 12 is formed. As a result, a base layer 19A configured by the first and second insulating layers 11A and 12 in the pixel area DA and a base layer 19B configured by the first and second insulating layers 11B and 12 in the peripheral circuit area PA are provided. Form. Accordingly, the film thickness TB of the base layer 19B in the peripheral circuit area PA is formed to be smaller than the film thickness TA of the base layer 19A in the pixel area DA (TB <TA).

  Thereafter, the semiconductor device 1C according to the second embodiment is manufactured using the same manufacturing method as described above.

[Function and effect]
According to the configuration and the manufacturing method of the second embodiment, the same effects as those of the first embodiment can be obtained. Furthermore, it is possible to apply 2nd Embodiment as needed.

(Application example (organic EL display device))
An example of a display device to which the semiconductor devices 1A to 1C according to the first and second embodiments and the first and second modifications 1 and 2 can be applied will be described with reference to FIGS. A display device 1 shown in FIG. 18 is, for example, an active matrix organic EL display device having an organic EL element. The organic EL display device 1 described here is an example, and the present invention is not limited to this.

[Overall configuration of display device]
The overall configuration of the display device 1 will be described with reference to FIG. FIG. 18 is a block diagram schematically showing an example of the display device 1 to which the active matrix substrate according to the first and second embodiments and the first modification is applied. As shown in the figure, the display device 1 includes a pixel area DA and a drive unit disposed in a peripheral circuit area PA around the pixel area DA. The driving unit includes a first scanning line driving circuit 3, a second scanning line driving circuit 4, a data line driving circuit 5, a control circuit 6, and a power supply circuit 7.

  The first scanning line driving circuit 3 and the second scanning line driving circuit 4 are arranged, for example, in the vicinity of both sides in the row direction of the pixel area DA, and the data line driving circuit 5, the control circuit 6, and the power supply circuit 7 are arranged in the column of the pixel area DA. It is arranged near one side of the direction. The first scanning line driving circuit 3, the second scanning line driving circuit 4, and the data line driving circuit 5 are at least partially formed on a panel (not shown) constituting the display device 1.

  The pixel area DA includes a plurality of pixels PX arranged in a matrix (matrix). In the pixel area DA, corresponding to these pixels PX, a plurality of first scanning lines WL and a plurality of second scanning lines RL arranged in the row direction, and a plurality of data arranged in the column direction intersecting the row direction. Line DL etc. are arranged.

  The first thin film transistor TrA according to the first and second embodiments and Modifications 1 and 2 is applied to a switching element included in the pixel PX in the pixel area DA, as will be described later. The second thin film transistor TrB is applied to a peripheral transistor disposed in a peripheral circuit such as a protection circuit in the peripheral circuit area PA.

  Each first scanning line WL extends outside the pixel area DA and is electrically connected to the first scanning line driving circuit 3. Each second scanning line RL extends outside the pixel area DA and is electrically connected to the second scanning line driving circuit 4. Each data line DL extends outside the pixel area DA and is electrically connected to the data line driving circuit 5.

  The first scanning line driving circuit 3 sequentially supplies a writing scanning signal WS to each first scanning line WL. Thereby, the plurality of pixels PX arranged in the row direction are sequentially selected.

  The second scanning line driving circuit 4 supplies the driving scanning signal AZ to the second scanning line RL in synchronization with the writing scanning signal WS supplied from the first scanning line driving circuit 3. Thereby, the light emission operation and the quenching operation of the pixel PX are controlled.

  The data line driving circuit 5 selectively supplies, for example, a signal voltage Vsig and a reference voltage Vofs to the data line DL. The signal voltage Vsig is a signal voltage corresponding to the luminance of the video signal. The reference voltage Vofs is a voltage that serves as a reference of the signal voltage, and corresponds to a voltage of a signal indicating a black level, for example. The reference voltage Vofs is also used to correct variations in threshold voltage of a driving transistor that drives an organic EL element described later.

  The control circuit 6 generates various signals necessary for displaying an image in the pixel area DA based on an external signal supplied from an external signal source. The control circuit 6 outputs the generated various signals to the first scanning line driving circuit 3, the second scanning line driving circuit 4, and the data line driving circuit 5, respectively, and the first scanning line driving circuit 3 and the second scanning line. The drive circuit 4 and the data line drive circuit 5 are controlled to operate in synchronization with each other.

[Detailed configuration of pixel area and peripheral circuit area]
Next, the configuration of the pixel area DA and the peripheral circuit area PA of the display device 1 will be described in detail with reference to FIG. FIG. 19 is an equivalent circuit diagram schematically showing an example of the configuration of the pixel PX and the peripheral circuit area PA in the pixel area DA.

(Pixel PX)
As illustrated, the pixel PX includes a writing transistor Tr1, a driving transistor Tr2, a reset transistor Tr3, a capacitor element Cs, and a light emitting element EL. The write transistor Tr1, the drive transistor Tr2, and the reset transistor Tr3 are the first thin film transistors TrA.

  The write transistor Tr1 has a gate electrode connected to the first scanning line WL, one of the source / drain electrodes connected to the data line DL, and the other connected to the first electrode of the capacitor Cs and the gate electrode of the drive transistor Tr2. The

  One of the source / drain electrodes of the drive transistor Tr2 is connected to the wiring to which the power supply voltage Vcc is supplied, and the other is connected to the anode electrode of the light emitting element EL, the second electrode of the capacitor element Cs, and the source / drain electrode of the reset transistor Tr3. Connected to one side. A cathode voltage Vcath is supplied to the cathode electrode of the light emitting element EL.

  The gate electrode of the reset transistor Tr3 is connected to the second scanning line RL, and the other of the source / drain electrodes is connected to a wiring to which a fixed voltage Vini is supplied.

  In the pixel PX having the above-described configuration, the writing transistor Tr1 becomes conductive when the writing scanning signal WS is supplied to the first scanning line WL. In the conductive state, the write transistor Tr1 supplies the signal voltage Vsig or the reference voltage Vofs supplied via the data line DL to the gate electrode of the drive transistor Tr2. The capacitive element Cs holds the signal voltage Vsig or the reference voltage Vofs. The drive transistor Tr2 is turned on when the voltage held in the capacitive element Cs exceeds the threshold voltage, and supplies a current based on the voltage held in the capacitive element Cs to the light emitting element EL. The light emitting element EL emits light with luminance corresponding to the current supplied from the driving transistor Tr2.

  The reset transistor Tr3 becomes conductive when the drive scanning signal AZ is supplied to the second scanning line RL. In the conductive state, the reset transistor Tr3 supplies the fixed voltage Vini to the source electrode of the drive transistor Tr2 and the anode electrode of the light emitting element EL, and resets (initializes) the voltage of these electrodes to the fixed voltage Vini. Here, when the threshold voltage of the light emitting element EL is Vth, the relationship between the threshold voltage Vth, the cathode voltage Vcath, and the fixed voltage Vini is expressed by the following equation.

Vini <Vth + Vcath
(Peripheral circuit)
Next, peripheral circuits arranged in the peripheral circuit area PA will be described. Here, as an example of the peripheral circuit, a protection circuit ESD for protecting the pixel PX arranged in the pixel area DA from electrostatic discharge (ESD) will be described.

  The protection circuit ESD includes two protection transistors Tr4 and Tr5. These two protection transistors Tr4 and Tr5 are second thin film transistors TrB.

  The gate electrode of the protection transistor Tr4 is connected to one of the source / drain electrodes via the first scanning line WL and the wiring L1, and the other source / drain electrode is connected to the gate electrode of the protection transistor Tr5 and the data line DL via the wiring L2. Connected to.

  The gate electrode of the protection transistor Tr5 is connected to one of the source / drain electrodes via the wiring L2, and the other source / drain electrode is one of the source / drain electrodes of the protection transistor Tr4 and the gate of the protection transistor Tr4 via the wiring L1. Connected to the electrode and the first scanning line WL.

  In the configuration of the protection circuit ESD, consider a case where a voltage Vesd that is higher than the threshold voltage VthB of the protection transistors Tr4 and Tr5 is applied to the first scanning line WL by, for example, electrostatic discharge. In this case, since the voltage Vesd is larger than the threshold voltage VthB, the current paths of the protection transistors Tr4 and Tr5 are turned on, and the drain current can be passed. Therefore, the high voltage Vesd is not applied to the pixel PX in the pixel area DA via the current line of the protection transistors Tr4 and Tr5 and the wirings L1 and L2 which are in the conductive state, but via the data line DL. Applied to the peripheral circuit area PA.

  As described above, the pixel PX in the pixel area DA can be protected from the high voltage Vesd due to electrostatic discharge by the protection operation.

[Function and effect]
By applying the active matrix substrate and the first and second thin film transistors TrA and TrB according to the first and second embodiments and the first and second modifications to the display device 1 having the above configuration, the image quality and reliability of the display device 1 are improved. The leakage current and power consumption can be reduced.

(Other application examples)
The display device is not limited to the organic EL display device 1 described in the application example, and may be another display device such as a liquid crystal display device having a liquid crystal layer.

  Furthermore, the semiconductor devices 1A to 1C are not limited to display devices, and can be applied to, for example, an imaging device. In the imaging device, the first thin film transistor TrA is applied to each transistor constituting a plurality of pixels arranged in the pixel area PA, and the peripheral transistor constituting the peripheral circuit arranged in the peripheral circuit area PA around the pixel area DA. For example, the second thin film transistor TrB can be applied.

  Further, the peripheral circuit to which the second thin film transistor TrB can be applied is not limited to the protection circuit ESD. The second thin film transistor TrB is applicable to, for example, an inspection transistor for inspecting the image quality of the pixel PX arranged in the peripheral circuit area PA. One end of the source / drain electrode of the inspection transistor is electrically connected to a data bus line connected to the pixel PX in the pixel area DA. The pixel area PA is inspected based on whether or not the pixel PX that is electrically connected according to the on / off state of the inspection transistor is issued with normal luminance.

  Needless to say, the present invention can be similarly applied to configurations and manufacturing methods in which the disclosed contents of the first and second embodiments and the first and second modifications are combined.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 1A, 1B, 1C ... Semiconductor device, 3 ... 1st scanning line drive circuit, 4 ... 2nd scanning line drive circuit, 5 ... Data line drive circuit, 6 ... Control circuit, 7 ... Power supply circuit, 10 Insulating substrate, DA ... Pixel region, PA ... Peripheral circuit region, 11, 11A, 11B ... First insulating layer, 12, 12A, 12B ... Second insulating layer, 13A, 13B ... Oxide semiconductor layer, 14 ... Gate insulation Films 15... Gate electrode 16. Interlayer insulating film 17. Contact wiring 18. Interlayer insulating film 19 A and 19 B. Underlayer (undercoat layer) TrA 1st thin film transistor TrB 2nd thin film transistor

Claims (10)

An insulating substrate including a pixel region and a peripheral circuit region around the pixel region;
A first insulating layer containing at least nitrogen provided on the insulating substrate;
A second insulating layer provided on at least the first insulating layer in the peripheral circuit region;
A first thin film transistor provided above the first insulating layer in the pixel region and including a first oxide semiconductor layer;
A second thin film transistor provided on the second insulating layer in the peripheral circuit region and provided with a second oxide semiconductor layer;
The thickness of the second insulating layer in the pixel region is smaller than the thickness of the second insulating layer in the peripheral circuit region. The semiconductor device according to claim 1, wherein the film thickness of the first insulating layer is equal in the pixel region and the peripheral circuit region. An insulating substrate including a pixel region and a peripheral circuit region around the pixel region;
A first insulating layer provided on the insulating substrate and containing at least nitrogen;
A second insulating layer provided on the first insulating layer;
A first thin film transistor provided on the second insulating layer in the pixel region and including a first oxide semiconductor layer;
A second thin film transistor provided on the second insulating layer in the peripheral circuit region and provided with a second oxide semiconductor layer;
The thickness of the first insulating layer in the pixel region is larger than the thickness of the first insulating layer in the peripheral circuit region. The semiconductor device according to claim 3, wherein a film thickness of the second insulating layer is equal in the pixel region and the peripheral circuit region. The semiconductor device according to claim 1, wherein a threshold voltage of the first thin film transistor is lower than a threshold voltage of the second thin film transistor. The semiconductor device according to claim 1, wherein the first insulating layer is one of a silicon nitride film and a silicon oxynitride film. The semiconductor device according to claim 1, wherein the first thin film transistor is any one of a write transistor, a drive transistor, and a reset transistor that constitute a pixel disposed in the pixel region. The semiconductor device according to claim 1, wherein the second thin film transistor is a protection transistor for protecting the pixel region from electrostatic discharge or an inspection transistor for inspecting the pixel region. The semiconductor device according to claim 1, wherein the semiconductor device is an organic EL display device, a liquid crystal display device, or an imaging device.   An active matrix substrate using the semiconductor device according to claim 1.

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