JP2013214731A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transistor having a low off-state current which is one of leakage currents of the transistor; and improve an integration degree of a semiconductor device including the transistor having the low off-state current.SOLUTION: A semiconductor device comprises a transistor in which an outer peripheral end of a drain electrode is arranged inside an outer peripheral end of a gate electrode in planar view. It can be described as a transistor in which a gate electrode is arranged so as to surround a drain electrode. Accordingly, a transistor of low power consumption which has a low off-state current and stable electrical characteristics can be provided. Further, the transistor having the above-described configuration and another passive element such as a part of components of a capacitative element share each other. Accordingly, an integration degree of a semiconductor device including a transistor having a low off-state current is improved and a semiconductor device capable of being manufactured with high productivity can be provided.

Description

The present invention relates to a semiconductor device.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and a transistor, a memory element, an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

A technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. Such a thin film transistor is widely applied to an electronic device such as an integrated circuit (IC) or an image display device (display device) (for example, Patent Document 1 and Patent Document 2).

In these electronic devices, transistors are being miniaturized for integration and high-speed operation. However, with the miniaturization of transistors, the ratio of leakage current to the power consumption of electronic devices has become ignorable.

In addition, with the spread of portable devices such as smartphones and portable game machines, electronic devices that can operate for a long time with a small amount of power are required.

Thus, the demand for lower power consumption of electronic devices is increasing.

As approaches for reducing power consumption, there are a method of devising circuit design and applying power gating technology and the like, and a method of improving the structure and reducing the leakage current of transistors.

As the leakage current of the transistor, there are a tunnel current generated when the physical film thickness of the gate insulating film is reduced, an off current flowing between the source and the drain when the transistor is in an off state, and the like.

JP 2006-222462 A JP 2006-165528 A

An object of one embodiment of the present invention is to provide a transistor with low off-state current, which is one of leakage currents of the transistor. Another object is to improve the integration degree of a semiconductor device including a transistor with low off-state current.

In order to solve the above problems, in one embodiment of the present invention, a transistor having a structure in which an outer peripheral end portion of a drain electrode is provided inside an outer peripheral end portion of a gate electrode in a plan view. This may be rephrased as a transistor having a structure in which a gate electrode is provided so as to surround the drain electrode.

In this manner, by forming a transistor in which the drain electrode is provided inside the outer peripheral edge of the gate electrode and the semiconductor film, at least the drain electrode does not contact the side surface of the semiconductor film in the region overlapping with the gate electrode. A channel is never formed. Therefore, a transistor with low off-state current, stable electrical characteristics, and low power consumption can be provided.

In one embodiment of the present invention, a part of components of the transistor having the above structure and another passive element such as a capacitor is shared. Thus, the degree of integration of a semiconductor device having a transistor with a low off-state current can be improved.

In addition, by sharing part of the components of the transistor and the capacitor, the transistor and the capacitor can be manufactured with the same number of steps as the transistor manufacturing. Therefore, a semiconductor device that can be manufactured with high productivity can be provided.

Specifically, according to one embodiment of the present invention, a semiconductor film provided over an insulating surface, an insulating film, a gate electrode provided so as to overlap with the semiconductor film with the insulating film interposed therebetween, and an outer periphery of the semiconductor film A transistor including a first electrode that is provided on an inner side of the end portion and the outer peripheral end portion of the gate electrode and that is in contact with the semiconductor film; and a second electrode that is in contact with the semiconductor film; an insulating film; A semiconductor device comprising: an electrode; and a capacitor formed by a third electrode at least partially overlapping the second electrode with an insulating film interposed therebetween.

The second electrode may be provided in contact with the outer peripheral end of the semiconductor film.

The third electrode may be the same layer and the same material as the gate electrode.

The semiconductor film may have an impurity addition region in a region that does not overlap with the gate electrode.

The semiconductor film may be an oxide semiconductor film. In the case of an oxide semiconductor film, at least indium can be included. In the case of an oxide semiconductor film, the oxide semiconductor film has an amorphous part and a crystal part, and the crystal part has a c-axis in a direction parallel to the normal vector of the surface where the oxide semiconductor film is formed or the normal vector of the surface. You may have it.

According to one embodiment of the present invention, a transistor with low off-state current can be provided. In addition, the integration degree of a semiconductor device including a transistor with low off-state current can be improved.

4A and 4B are a plan view, a cross-sectional view, and a circuit diagram illustrating one embodiment of a semiconductor device. 4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. 4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. 4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. 4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. 4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. 9A and 9B are a cross-sectional view and a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 6 is a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 6 is a circuit diagram illustrating one embodiment of a semiconductor device. The figure which shows the example of (A) structure of a pixel, (B) The example of operation | movement. FIG. 4 is a cross-sectional view of a part of a pixel of a display device using an organic EL element and a cross-sectional view of a light emitting layer. FIG. 6 is a circuit diagram and a cross-sectional view of a pixel of a display device using a liquid crystal element. 10A and 10B each illustrate an electronic device. 10A and 10B each illustrate an electronic device.

Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the invention disclosed in this specification is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed. Further, the invention disclosed in this specification is not construed as being limited to the description of the embodiments below. The ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. In addition, a specific name is not shown as a matter for specifying the invention in this specification.

Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

In addition, the functions of “source” and “source electrode” and “drain” and “drain electrode” may be switched when transistors having different polarities are employed or when the direction of current changes in circuit operation. . Therefore, in this specification and the like, the terms “source” and “drain” can be used interchangeably. In this specification and the like, a channel region refers to a region where a source region (source electrode) and a drain region (drain electrode) face each other.

Note that in this specification and the like, “electrically connected” includes a case of being connected via “something having an electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets.

(Embodiment 1)
In this embodiment, a structure and material of one embodiment of a semiconductor device will be described with reference to FIGS.

<< Configuration of Semiconductor Device >>
1A-1 is a plan view of the transistor 31 and the capacitor 32. FIG. 1A-2 is a cross-sectional view taken along dashed-dotted line AB in FIG. 1A-1, and FIG. 3) is a cross-sectional view taken along one-dot chain line CD in FIG. Note that in FIG. 1A-1, some components (for example, the insulating film 16 and the like) of the transistor 31 and the capacitor 32 are omitted in order to avoid complexity. FIG. 1B is a circuit diagram showing the connection between the transistor 31 and the capacitor 32.

1 includes a semiconductor film 12a provided over a substrate 10 having an insulating surface, an insulating film 16, a gate electrode 18a provided so as to overlap with the semiconductor film with the insulating film interposed therebetween, and a semiconductor The first electrode 14a is provided on the inner side not reaching the outer peripheral end of the film 12a and the outer peripheral end of the gate electrode 18a, and has a second electrode 14b in contact with the semiconductor film.

The insulating film 16 of the transistor 31 functions as a gate insulating film, the electrode 14a functions as a drain electrode, and the electrode 14b functions as a source electrode.

The capacitive element 32 includes an insulating film 16, a second electrode 14b, and a third electrode 18b that at least partially overlaps the second electrode 14b with the insulating film 16 interposed therebetween.

In the present specification and the like, the outer peripheral end portion is an outer peripheral end portion of the electrode or the like when the island-like or annular electrode or the like is viewed in plan view. The inner peripheral end is an end portion of the inner periphery of the electrode when the annular electrode or the like is viewed in plan. For example, in the transistor 31 of FIG. 1, the outer peripheral end of the gate electrode 18a is the end facing the electrode 18b. The inner peripheral end of the gate electrode 18a is the end facing the electrode 14a.

Even if a part of an annular electrode or the like has a notch (for example, a U-shape or the like), it is similarly expressed as an outer peripheral end and an inner peripheral end.

One of the factors that cause the off-state current of a transistor is the generation of a parasitic channel. A parasitic channel is an unintended carrier movement path. For example, when the side surface of the outer peripheral end portion of the semiconductor film has a lower resistance than other portions, and a source and a drain are electrically connected to the region, a parasitic channel may be generated in the low resistance region. In other words, it is a semiconductor film in a region overlapping with the gate, and a channel (also referred to as the former channel) formed in the shortest path between the source and drain according to the voltage between the gate and the source, and a parasitic channel (also referred to as the latter channel). 2 types of channels can be formed.

In a transistor in which two types of channels can be formed, in many cases, the threshold voltage between the gate and the source in which each channel is formed is different. Typically, the threshold voltage at which the former channel is formed is higher than the threshold voltage at which the latter channel is formed. The current driving capability of the former channel is higher than the current driving capability of the latter channel. Therefore, when the voltage between the gate and the source of the transistor in the off state is increased, the current between the source and the drain changes in two steps. Specifically, a first-stage change (increase in current between the source and drain) is confirmed in the vicinity of the threshold voltage at which the latter channel is formed, and further, the threshold at which the former channel is formed. A second-stage change (an increase in current between the source and drain) is confirmed in the vicinity of the voltage.

Therefore, the formation of the parasitic channel (the latter channel) causes a problem that the threshold voltage of the transistor shifts to a negative value and the off-current increases.

Therefore, as shown in FIG. 1, the drain electrode (electrode 14a) and the semiconductor film 12a are positioned by placing the outer peripheral end of the drain electrode (electrode 14a) inside the outer peripheral end of the gate electrode (gate electrode 18a) and the semiconductor film 12a. The structure is such that the side surface of the outer peripheral end of the film 12a does not contact. Therefore, even if the side surface of the semiconductor film 12a has a lower resistance than other portions, the characteristics of the transistor are not affected. As a result, generation of a parasitic channel can be prevented and the threshold voltage of the transistor 31 can be prevented from shifting to minus. Therefore, a transistor having stable electrical characteristics and low power consumption can be provided.

However, the configuration in which the drain electrode is provided inside the gate electrode and the outer peripheral end portion of the semiconductor film may increase the occupied area per transistor.

Thus, at least a part of the electrode 14b and the electrode 18b is provided so as to overlap. Thus, a transistor and a capacitor can be provided over the area of one transistor. Accordingly, the integration degree of a semiconductor device including a transistor with a low off-state current can be improved.

Further, by sharing the electrode 14b and the insulating film 16 between the transistor 31 and the capacitor 32, the transistor 31 and the capacitor 32 can be formed with the same number of steps as that of the transistor, which can be manufactured with high productivity. Can be provided.

<< Constituent materials for semiconductor devices >>
<Substrate 10>
There is no particular limitation on a substrate that can be used as the substrate 10, but at least heat resistance enough to withstand heat treatment in manufacturing a semiconductor device is required. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and a semiconductor element provided on these substrates, It may be used as the substrate 10.

Further, a flexible substrate may be used as the substrate 10. In order to obtain a flexible semiconductor device, the transistor 31 including the semiconductor film 12a may be directly formed over a flexible substrate, or the transistor 31 including the semiconductor film 12a may be formed over another manufacturing substrate. Thereafter, it may be peeled off and transferred to the flexible substrate. Note that a separation layer (eg, a metal layer or a tungsten oxide layer) is preferably provided between the formation substrate and the transistor 31 including the semiconductor film 12a in order to separate and transfer the formation substrate to the flexible substrate.

Further, an insulating film functioning as a base film may be provided over the substrate 10. As the insulating film, an oxide insulating material such as silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide, silicon nitride, silicon oxynitride, aluminum nitride, or oxynitride is formed by PECVD or sputtering. A single-layer structure or a stacked structure can be provided using a nitride insulating material such as aluminum or a mixed material thereof.

For example, a stacked structure of a silicon nitride film and a silicon oxynitride film is preferably used as the insulating film. By using the silicon nitride film, the metal, hydrogen, or the like from the substrate can be prevented from reaching the semiconductor film 12a.

<Semiconductor film 12a>
As the semiconductor film 12a, silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), or the like can be used. Alternatively, a compound semiconductor such as gallium nitride (GaN) having a wider band gap than silicon, an oxide semiconductor formed of a metal oxide such as zinc oxide (ZnO), or the like may be used. Among these, an oxide semiconductor can be manufactured by a sputtering method or a wet method (such as a printing method), and has an advantage of being excellent in mass productivity. Further, an oxide semiconductor can be formed over a cheap and easily available glass substrate, and a semiconductor element formed using an oxide semiconductor can be stacked over an integrated circuit. In addition, it is possible to cope with an increase in the size of the substrate. Thus, among the above-described semiconductors, an oxide semiconductor has a merit that mass productivity is high. Even when a crystalline oxide semiconductor is obtained in order to improve the performance (eg, reliability) of the transistor, a crystalline oxide semiconductor can be obtained by heat treatment at 250 ° C. to 800 ° C.

In this embodiment, an oxide semiconductor is used for the semiconductor film 12a.

In the case where an oxide semiconductor is used for the semiconductor film 12a, it is preferable that at least indium (In) or zinc (Zn) be included. In particular, it is preferable to contain In and Zn. In addition, it is preferable to include a stabilizer for reducing variation in electrical characteristics of the transistor including the oxide semiconductor. The stabilizer only needs to have at least one of gallium (Ga), tin (Sn), hafnium (Hf), and aluminum (Al).

As other stabilizers, lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb) , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu).

For example, an In—Sn—Ga—Zn-based oxide that is an oxide of a quaternary metal, an In—Ga—Zn-based oxide that is an oxide of a ternary metal, an In—Sn—Zn-based oxide, In-Al-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La- Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn I-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn-based oxides, and binary metal oxides -Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based material, unified An In-based oxide, a Sn-based oxide, a Zn-based oxide, or the like that is an oxide of a metal based metal can be used.

Note that here, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0) may be used as the oxide semiconductor. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0) may be used as the oxide semiconductor.

For example, an In—Ga—Zn-based oxide having an atomic ratio of In: Ga: Zn = 3: 1: 2, In: Ga: Zn = 1: 1: 1 or In: Ga: Zn = 2: 2: 1 Or an oxide in the vicinity of the composition can be used. Alternatively, an In—Sn—Zn-based oxide having an atomic ratio of In: Sn: Zn = 1: 1: 1, In: Sn: Zn = 2: 1: 3, or In: Sn: Zn = 2: 1: 5 Or an oxide in the vicinity of the composition may be used.

For example, an oxide in which the atomic ratio of In, Ga, Zn is In: Ga: Zn = a: b: c (a + b + c = 1) has an atomic ratio of In: Ga: Zn = A: B: A, b, and c are the vicinity of r of the oxide of C (A + B + C = 1).
(A−A) ² + (b−B) ² + (c−C) ² ≦ r ²
Satisfying. For example, r may be 0.05. The same applies to other oxides.

However, the composition is not limited to these, and a material having an appropriate composition may be used depending on required semiconductor characteristics (field effect mobility, threshold voltage, and the like). In order to obtain the required semiconductor characteristics, it is preferable that the carrier concentration, the impurity concentration, the defect density, the atomic ratio between the metal element and oxygen, the interatomic distance, the density, and the like are appropriate.

A transistor in which an oxide semiconductor is used for a channel region can have an off-state current (here, a potential difference from a gate potential with respect to a source potential is 0 V in an off state by purifying the oxide semiconductor) Or the drain current when the voltage is lower than or equal to the threshold voltage) can be sufficiently reduced. For example, hydrogen or a hydroxyl group, which are malignant impurities for an oxide semiconductor, can be prevented from being included in the film by heating film formation, or can be removed from the film by heating after film formation, so that high purity can be achieved. In a transistor using an In—Ga—Zn-based oxide in a channel region by being highly purified, the channel length is 10 μm, the thickness of the semiconductor layer is 30 nm, and the drain voltage is in a range of about 1 V to 10 V. The off current can be 1 × 10 ⁻¹³ A or less. The off current per channel width (the value obtained by dividing the off current by the channel width of the transistor) is about 1 × 10 ⁻²³ A / μm (10 yA / μm) to 1 × 10 ⁻²² A / μm (100 yA / μm). Is possible.

The semiconductor film 12a is in a single crystal state, a polycrystalline (also referred to as polycrystal) state, an amorphous state, or the like.

The semiconductor film 12a is preferably a CAAC-OS (C Axis Crystallized Oxide Semiconductor) film.

For example, the CAAC-OS may be able to confirm a crystal part in an observation image obtained by a transmission electron microscope (TEM: Transmission Electron Microscope). In many cases, a crystal part included in the CAAC-OS fits in a cube with a side of 100 nm, for example, as an observation image obtained by a TEM. In addition, in the CAAC-OS, there is a case where the boundary between the crystal part and the crystal part cannot be clearly confirmed in an observation image by TEM. In some cases, the CAAC-OS cannot clearly confirm a grain boundary (also referred to as a grain boundary) in an observation image obtained by a TEM. For example, the CAAC-OS does not have a clear grain boundary; In addition, since the CAAC-OS does not have a clear grain boundary, for example, the density of defect states is rarely increased. In addition, since the CAAC-OS does not have a clear grain boundary, for example, the decrease in electron mobility is small.

For example, the CAAC-OS includes a plurality of crystal parts, and the c-axis is aligned in a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface of the plurality of crystal parts. Therefore, when CAAC-OS is analyzed by an out-of-plane method using, for example, an X-ray diffraction (XRD) apparatus, a peak at 2θ of around 31 ° may appear. The peak at 2θ of around 31 ° indicates that it is oriented in the (009) plane in the case of InGaZnO ₄ crystal. In the CAAC-OS, for example, a peak where 2θ is around 36 ° may appear. The peak at 2θ of around 36 ° indicates that it is oriented in the (222) plane if it is a Ga ₂ ZnO ₄ crystal. The CAAC-OS preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

In the CAAC-OS, for example, the directions of the a-axis and the b-axis may not be uniform between different crystal parts. For example, in the case of a CAAC-OS including an InGaZnO ₄ crystal, when an analysis is performed by an in-plane method in which X-rays are incident from a direction perpendicular to the c-axis using an XRD apparatus, a peak at 2θ of around 56 ° is obtained. May appear. The peak where 2θ is around 56 ° indicates the (110) plane of the InGaZnO ₄ crystal. Here, when 2θ is fixed in the vicinity of 56 ° and the sample is rotated with the surface normal vector as the axis (φ axis) and the analysis (φ scan) is performed, the directions of the a axis and the b axis are aligned. In the case of a crystalline oxide semiconductor, six symmetry peaks appear, but in the case of a CAAC-OS, a clear peak does not appear.

Thus, for example, the CAAC-OS may be c-axis oriented and the a-axis and / or b-axis may not be aligned in a macro manner.

In the CAAC-OS, for example, spots (bright spots) may be observed in an electron diffraction pattern. In particular, an electron beam diffraction image obtained using an electron beam having a beam diameter of 10 nmφ or less or 5 nmφ or less is referred to as a micro electron beam diffraction image.

The crystal part included in the CAAC-OS is aligned so that, for example, the c-axis is in a direction parallel to the normal vector of the formation surface of the CAAC-OS or the normal vector of the surface, and from a direction perpendicular to the ab plane. The metal atoms are arranged in a triangular shape or a hexagonal shape as viewed, and the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers as viewed from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, the term “perpendicular” includes a range of 80 ° to 100 °, preferably 85 ° to 95 °. In addition, a simple term “parallel” includes a range of −10 ° to 10 °, preferably −5 ° to 5 °.

In addition, the CAAC-OS can be formed by reducing the density of defect states, for example. In an oxide semiconductor, for example, oxygen vacancies are defect levels. Oxygen deficiency may become a trap generation level or become a carrier generation source by capturing hydrogen. In order to form the CAAC-OS, for example, it is important to prevent oxygen vacancies from being generated in the oxide semiconductor. Therefore, the CAAC-OS is an oxide semiconductor with a low density of defect states. Alternatively, the CAAC-OS is an oxide semiconductor with few oxygen vacancies.

A low impurity concentration and a low defect level density (small oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. An oxide semiconductor that is highly purified intrinsic or substantially highly purified intrinsic has few carrier generation sources, and thus may have a low carrier density. Therefore, a transistor in which the oxide semiconductor is used for a channel formation region may rarely have electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states, and thus may have a low density of trap states. Therefore, a transistor in which the oxide semiconductor is used for a channel formation region may have a small change in electrical characteristics and be a highly reliable transistor. Note that the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which an oxide semiconductor with a high trap state density is used for a channel formation region may have unstable electric characteristics.

In addition, a transistor using a high-purity intrinsic or substantially high-purity intrinsic CAAC-OS has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

For example, the oxide semiconductor may include polycrystal. Note that an oxide semiconductor including polycrystal is referred to as a polycrystalline oxide semiconductor. A polycrystalline oxide semiconductor includes a plurality of crystal grains.

For example, the oxide semiconductor may include microcrystal. Note that an oxide semiconductor including microcrystal is referred to as a microcrystalline oxide semiconductor.

For a microcrystalline oxide semiconductor, for example, a crystal portion may not be clearly identified in an observation image using a TEM. In most cases, a crystal part included in the microcrystalline oxide semiconductor has a size of 1 nm to 100 nm, or 1 nm to 10 nm, for example. In particular, for example, a microcrystal of 1 nm or more and 10 nm or less is called a nanocrystal (nc: nanocrystal). An oxide semiconductor including nanocrystals is referred to as an nc-OS (nanocrystalline Oxide Semiconductor). In addition, for example, the nc-OS may not be able to clearly confirm the boundary between the crystal part in the observation image by TEM. Further, for example, nc-OS does not have a clear grain boundary in an observation image obtained by a TEM, and thus impurities are hardly segregated. In addition, since the nc-OS does not have a clear grain boundary, for example, the density of defect states is rarely increased. Further, since the nc-OS does not have a clear grain boundary, for example, the decrease in electron mobility is small.

For example, the nc-OS may have periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm). In addition, for example, since nc-OS has no regularity between crystal parts, there is a case where periodicity is not seen in the atomic arrangement macroscopically or long-range order is not seen macroscopically. . Therefore, the nc-OS may not be distinguished from an amorphous oxide semiconductor depending on, for example, an analysis method. For example, when the nc-OS is analyzed by an out-of-plane method with X-rays having a beam diameter larger than that of a crystal part using an XRD apparatus, a peak indicating orientation may not be detected. In nc-OS, for example, a halo pattern may be observed in an electron beam diffraction image using an electron beam having a beam diameter larger than that of a crystal part (for example, 20 nmφ or more, or 50 nmφ or more). In nc-OS, for example, a spot may be observed in a microelectron beam diffraction image using an electron beam having a beam diameter (for example, 10 nmφ or less, or 5 nmφ or less) that is the same as or smaller than the crystal part. . Further, in the micro electron beam diffraction image of the nc-OS, for example, a region with high luminance may be observed so as to draw a circle. In addition, in the micro electron beam diffraction image of the nc-OS, for example, a plurality of spots may be observed in the region.

Since the nc-OS may have periodicity in atomic arrangement in a minute region, the density of defect states is lower than that of an amorphous oxide semiconductor. Note that the nc-OS has no regularity between crystal parts, and thus has a higher density of defect states than the CAAC-OS.

Note that the oxide semiconductor may be a mixed film including two or more of a CAAC-OS, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. For example, the mixed film may include two or more of any of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a polycrystalline oxide semiconductor region, and a CAAC-OS region. . The mixed film includes, for example, a stacked structure of any two or more of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a polycrystalline oxide semiconductor region, and a CAAC-OS region. May have.

Note that although the semiconductor film 12a is described as a CAAC-OS film in this embodiment, it may be single crystal, polycrystalline (also referred to as polycrystal), or amorphous.

In the case where an oxide semiconductor is used for the semiconductor film 12a, the channel formation region is preferably a region that is highly purified by reducing impurities such as water or hydrogen and reducing oxygen vacancies. A highly purified oxide semiconductor (purified OS) is infinitely close to i-type (intrinsic semiconductor) or i-type. Therefore, a transistor in which the above oxide semiconductor is used for a channel formation region has characteristics that an off-state current is extremely low and a threshold voltage shifts in a minus direction (that is, a normally-off characteristic is easily obtained).

Specifically, the channel formation region of the semiconductor film 12a has a measured value of hydrogen concentration by secondary ion mass spectrometry (SIMS) of less than 5 × 10 ¹⁸ / cm ³ , more preferably 5 × 10 8. ¹⁷ / cm ³ or less, more preferably 1 × 10 ¹⁶ / cm ³ or less. The carrier density of the oxide semiconductor film that can be measured by Hall effect measurement is less than 1 × 10 ¹⁴ / cm ³ , preferably less than 1 × 10 ¹² / cm ³ , and more preferably less than 1 × 10 ¹¹ / cm ³ . It is preferable. The band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. By using an oxide semiconductor that is highly purified by sufficiently reducing the impurity concentration and reducing oxygen vacancies in a region where a channel is formed, the off-state current of the transistor is reduced and the threshold voltage is negative. It is possible to reduce the direction shift (that is, to obtain a normally-off characteristic).

In the semiconductor film 12a, generation of carriers can be suppressed because hydrogen and oxygen vacancies are reduced. By suppressing the carrier density from increasing, the shift of the threshold voltage in the negative direction can be reduced. Note that oxygen is easily released from the end portion of the semiconductor film 12a, and thus the carrier density is easily increased.

Therefore, in one embodiment of the present invention, as shown in FIG. 1, the outer peripheral end portion of the electrode 14a functioning as the drain electrode is positioned inside the outer peripheral end portion of the gate electrode 18a, thereby functioning as the drain electrode 14a. And the side surface of the outer peripheral end of the semiconductor film 12a are not in contact with each other. Therefore, it is not affected by the outer peripheral end portion of the semiconductor film 12a. As a result, the threshold voltage of the transistor 31 can be prevented from shifting to minus.

In the case where an oxide semiconductor is used as the semiconductor film 12a, it is preferable to provide an insulating film that releases oxygen when heat is applied as a base film. By providing the oxide semiconductor in contact with the insulating film from which oxygen is released by application of heat, oxygen can be released from the insulating film and diffused (or supplied) to the oxide semiconductor during heat treatment. it can. Accordingly, the oxygen deficiency density of the oxide semiconductor can be reduced. In addition, the interface state between the insulating film and the oxide semiconductor can be reduced. As a result, electric charges that can be generated due to the operation of the transistor and the like can be suppressed from being captured at the interface between the insulating film and the oxide semiconductor, so that the threshold voltage shifts in the negative direction. Can be suppressed.

As the insulating film from which oxygen is released by application of heat, an insulating film containing more oxygen than oxygen that satisfies the stoichiometric ratio is preferably used. As the insulating film, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, hafnium oxide, yttrium oxide, or the like can be used.

In addition, the interface between the semiconductor film 12a and the gate insulating layer 108a is preferably flat. When the interface is flat, the interface state is good, so that the characteristics of the transistor are improved. For example, it is preferable that the arithmetic average roughness (Ra) of JIS B 0601: 2001 is 0.2 nm or less.

<Electrode 14a, Electrode 14b>
As the electrode 14a functioning as a drain electrode and the electrode 14b functioning as a source electrode, a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, or an alloy material containing these as a main component is used. Can do. The electrodes 14a and 14b are formed of indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, and indium oxide oxide. A conductive material such as indium tin oxide to which zinc or silicon oxide is added can also be used. Further, the electrode 14a and the electrode 14b can have a single-layer structure or a stacked structure using the above conductive material.

When the electrodes 14a and 14b have a single layer structure, for example, a tungsten film with a thickness of 100 nm may be used.

When the electrode 14a and the electrode 14b have a two-layer stacked structure, for example, a stacked structure of a tantalum nitride film with a thickness of 30 nm and a copper film with a thickness of 200 nm may be used. By using a copper film, wiring resistance can be reduced. Further, a tungsten film, a tungsten nitride film, a molybdenum nitride film, or a titanium nitride film may be used instead of the tantalum nitride film with a thickness of 30 nm. A tungsten film may be used instead of the copper film having a thickness of 200 nm.

In the case where the electrodes 14a and 14b have a three-layer structure, for example, a tantalum nitride film with a thickness of 30 nm, a copper film with a thickness of 200 nm, and a tungsten film with a thickness of 30 nm may be used. Further, a tungsten film, a tungsten nitride film, a molybdenum nitride film, or a titanium nitride film may be used instead of the tantalum nitride film with a thickness of 30 nm. Further, a molybdenum film may be used instead of the tungsten film with a thickness of 30 nm. By using a copper film, wiring resistance can be reduced. In addition, by stacking a tungsten film or a molybdenum film on the copper film, it is possible to suppress copper from reaching.

<Insulating film 16>
As the insulating film 16 functioning as a gate insulating film, an oxide insulating material such as silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, or gallium oxide, silicon nitride, silicon oxynitride, aluminum nitride, or oxynitride is used. A single-layer structure or a stacked structure can be provided using a nitride insulating material such as aluminum or a mixed material thereof. In the case where an oxide semiconductor is used as the semiconductor film 12a, an insulating film that releases oxygen when heat is applied is preferably used as the insulating film 16.

<Gate electrode 18a, electrode 18b>
As the gate electrode 18a and the electrode 18b functioning as a capacitor element electrode, the same material as the electrode 14a and the electrode 14b can be used.

Note that a tungsten film or a molybdenum film is preferable because it has a relatively high work function and is therefore preferably used as a gate electrode because the threshold voltage of the transistor is easily increased (that is, the transistor is normally off). Note that the tungsten film and the molybdenum film are not necessarily formed if the insulating film 16 can prevent copper from reaching the semiconductor film 12.

Although not illustrated, an insulating film is preferably provided over the transistor 31 and the capacitor 32. The insulating film may be formed in one process or may be formed through a plurality of processes. Further, films made of different materials may be stacked. As the material of the insulating film, the same material as that of the insulating film 16 can be used.

(Embodiment 2)
In this embodiment, a structure of one embodiment of a semiconductor device different from that in Embodiment 1 will be described with reference to FIGS.

2A-1 is a plan view of the transistor 31 and the capacitor 32. FIG. 2A-2 is a cross-sectional view taken along dashed-dotted line AB in FIG. 2A-1, and FIG. 3) is a cross-sectional view taken along one-dot chain line CD in FIG. Note that in FIG. 2A-1, some components (eg, the insulating film 16) of the transistor 31 and the capacitor 32 are omitted in order to avoid complexity.

The main difference between the semiconductor device of FIG. 1 of Embodiment 1 and the semiconductor device of FIG. 2 is that the semiconductor film 12a has an impurity-added region 12a1 in FIG. The impurity added region 12a1 is a region having an impurity that changes the conductivity of the semiconductor film 12a, and is provided in a region that does not overlap with any of the gate electrode 18a, the electrode 14a, and the electrode 14b.

By providing the impurity doped region 12 a 1, the region functions as an LDD region of the transistor 31. By providing the LDD region, electric field concentration at the end of the drain electrode can be relaxed and hot carrier deterioration can be prevented. In addition, since the influence of the electric field from the end of the drain electrode becomes small at the end of the source electrode, the punch-through phenomenon due to DIBL can be suppressed.

Note that in the semiconductor film 12a, a region to which an impurity is added (impurity-added region 12a1) tends to be in an amorphous state because the crystal structure is disordered. Therefore, when a crystalline film such as a CAAC-OS film is used as the semiconductor film 12a and an impurity is added to the film, the channel formation region maintains the state of the CAAC-OS film, and the impurity-added region 12a1 has An oxide semiconductor film in an amorphous state (or an oxide semiconductor film including a large amount of an amorphous state) tends to be formed.

An amorphous oxide semiconductor film (or an oxide semiconductor film including a large amount of an amorphous state) includes hydrogen contained in an oxide semiconductor film having crystallinity such as a CAAC-OS film provided in contact therewith. It is easy to getter impurities such as donors. For this reason, an impurity serving as a donor such as hydrogen is gettered from the channel formation region to the impurity-added region 12a1, and the electrical characteristics of the transistor 31 can be improved.

As impurities, group 15 elements (typically phosphorus (P), arsenic (As), antimony (Sb)), boron (B), aluminum (Al), nitrogen (N), argon (Ar), One or more selected from helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn) can be used. Since the ion implantation uses a mass separator that extracts only necessary ions, only impurities can be selectively added to the target. Therefore, it is preferable because impurities (for example, hydrogen) are less mixed into the semiconductor film 12a than in the case of adding by ion doping. However, the ion doping method is not excluded.

3A-1 is a plan view of the transistor 31 and the capacitor 32. FIG. 3A-2 is a cross-sectional view taken along dashed-dotted line AB in FIG. 3A-1, and FIG. 3) is a cross-sectional view taken along one-dot chain line CD in FIG. Note that in FIG. 3A-1, some components (eg, the insulating film 16) of the transistor 31 and the capacitor 32 are omitted in order to avoid complexity.

The main difference between the semiconductor device of FIG. 1 of Embodiment 1 and the semiconductor device of FIG. 3 is the arrangement of the drain electrode and the source electrode. In FIG. 1, the electrode 14a and the electrode 14b that function as the drain electrode and the source electrode are provided on the semiconductor film 12a, whereas in FIG. 2, the electrode 20a and the electrode 20b that function as the drain electrode and the source electrode are formed in the semiconductor film. 12a is provided below.

Even with such a configuration, generation of a parasitic channel can be prevented and the threshold voltage of the transistor 31 can be prevented from shifting to minus. Further, since the electrode 14b functioning as a source electrode and the electrode 18b functioning as a capacitor element electrode are provided so as to overlap with each other, the degree of integration of the semiconductor device can be improved.

4A-1 is a plan view of the transistor 31 and the capacitor 32. FIG. 4A-2 is a cross-sectional view taken along dashed-dotted line AB in FIG. 4A-1, and FIG. 3) is a cross-sectional view taken along one-dot chain line CD in FIG. Note that in FIG. 4A-1, some components (eg, the insulating film 16) of the transistor 31 and the capacitor 32 are omitted in order to avoid complexity.

The main difference between the semiconductor device of FIG. 1 of Embodiment 1 and the semiconductor device of FIG. 4 is the arrangement of gate electrodes. In FIG. 1, the gate electrode 18a is provided on the semiconductor film 12a, whereas in FIG. 4, the gate electrode 22a is provided below the semiconductor film 12a. 4 includes the electrode 18b, the insulating film 23, and the electrode 14a.

Even in such a configuration, it is possible to prevent the generation of a parasitic channel and to prevent the threshold voltage of the transistor 31 from shifting to a negative value. Therefore, a transistor with low off-state current, stable electrical characteristics, and low power consumption can be provided. Further, when the electrode 14b and the electrode 18b are provided to overlap with each other, the degree of integration of the semiconductor device including a transistor with low off-state current can be improved.

In the semiconductor device of FIG. 4, the gate electrode 22a and the electrode 18b functioning as a capacitor element electrode are formed of different conductive layers, but the present invention is not limited to this. The gate electrode and the electrode functioning as a capacitor element electrode may be formed of the same layer and the same material. With such a structure, a semiconductor device that can be manufactured with high productivity can be provided.

5A-1 is a plan view of the transistor 31 and the capacitor 32, and FIG. 5A-2 is a cross-sectional view taken along dashed-dotted line AB in FIG. 5A-1, FIG. 3) is a cross-sectional view taken along one-dot chain line CD in FIG. Note that in FIG. 5A-1, some components (for example, the insulating film 16 and the like) of the transistor 31 and the capacitor 32 are omitted in order to avoid complexity.

The main difference between the semiconductor device of FIG. 1 of Embodiment 1 and the semiconductor device of FIG. 5 is the shape of the semiconductor film 12a. In FIG. 1, the outer peripheral end of the semiconductor film 12a is provided in contact with the electrode 14b, whereas in FIG. 5, the semiconductor film 12a is also provided outside the electrode 14b.

Even with such a configuration, generation of a parasitic channel can be prevented and the threshold voltage of the transistor 31 can be prevented from shifting to minus. Therefore, a transistor with low off-state current, stable electrical characteristics, and low power consumption can be provided. Further, since the electrode 14b functioning as a source electrode and the electrode 18b functioning as a capacitor element electrode are provided so as to overlap with each other, the degree of integration of a semiconductor device having a transistor with low off-state current can be improved.

6A-1 is a plan view of the transistor 31 and the capacitor 32. FIG. 6A-2 is a cross-sectional view taken along dashed-dotted line AB in FIG. 6A-1, and FIG. 3) is a cross-sectional view taken along one-dot chain line CD in FIG. Note that in FIG. 6A-1, some components (for example, the insulating film 16 and the like) of the transistor 31 and the capacitor 32 are omitted in order to avoid complexity.

The main difference between the semiconductor device of FIG. 1 of Embodiment 1 and the semiconductor device of FIG. 6 is the arrangement and shape of the electrode 14b and the electrode 18b. In FIG. 1, the electrode 14b and the electrode 18b are provided so as to surround the gate electrode 18a, whereas in FIG. 6, the electrode 14b and the electrode 18b are provided to face one side of the gate electrode 18a.

Even with such a configuration, generation of a parasitic channel can be prevented and the threshold voltage of the transistor 31 can be prevented from shifting to minus. Further, since the electrode 14b functioning as a source electrode and the electrode 18b functioning as a capacitor element electrode are provided so as to overlap with each other, the degree of integration of a semiconductor device having a transistor with low off-state current can be improved.

Note that in FIGS. 1 to 6, the gate electrode 18a or the gate electrode 22a is described so as not to overlap with the electrode functioning as the source electrode and the electrode functioning as the drain electrode, that is, the configuration having the offset region or the LDD region. However, the electrode may overlap with the electrode functioning as the source electrode and the electrode functioning as the drain electrode through the insulating film.

1 to 6 illustrate a transistor having a rectangular electrode functioning as a gate electrode, a drain electrode, and a source electrode, these components may have other shapes such as a circle.

Alternatively, a transistor having a combination of the characteristics of the transistors in FIGS.

(Embodiment 3)
In this embodiment, an example of a memory element according to one embodiment of the present invention will be described with reference to FIGS.

The transistor 31 and the capacitor 32 in FIG. 1B can be used as a memory element of a DRAM (Dynamic Random Access Memory). A DRAM stores information by selecting a transistor constituting a memory element and accumulating electric charge in a capacitor element.

When used for a memory element of a DRAM, an oxide semiconductor is preferably used for the semiconductor film of the transistor 31. By using an oxide semiconductor, a transistor with extremely low off-state current can be obtained. Thus, when the transistor 31 is turned off, the charge given to the capacitor 32 can be held for a long time. Therefore, the frequency of the refresh operation can be made extremely low and the power consumption can be further reduced.

That is, a substantially nonvolatile random access memory can be realized using the transistor 31 and the capacitor 32.

Incidentally, a magnetic tunnel junction element (MTJ element) is known as a nonvolatile random access memory. The MTJ element is an element that stores information by being in a low resistance state if the spin directions in the films arranged above and below the insulating film are parallel and in a high resistance state if the spin directions are antiparallel. Therefore, the principle is completely different from that of the memory including an oxide semiconductor described in this embodiment. Table 1 shows a comparison between the MTJ element and the semiconductor device according to the present embodiment.

Since the MTJ element uses a magnetic material, there is a drawback that the magnetism is lost when the temperature is higher than the Curie temperature. Further, since the MTJ element is current driven, it is compatible with a silicon bipolar device, but the bipolar device is not suitable for integration. The MTJ element has a problem that although the write current is small, the power consumption increases due to the increase in the memory capacity.

The MTJ element is said to have a write current per cell of 50 μA to 500 μA. However, in the semiconductor device according to this embodiment, data is saved by supplying electric charge to the capacitor element. The current required for data writing can be suppressed to about 1/100 of that of the MTJ element. Therefore, power consumption can be further reduced in the semiconductor device according to one embodiment of the present invention.

Further, in principle, the MTJ element is weak in magnetic field resistance, and when exposed to a strong magnetic field, the direction of spin tends to go wrong. In addition, it is necessary to control the magnetization fluctuation caused by the nanoscale formation of the magnetic material used in the MTJ element.

Furthermore, since the MTJ element uses rare earth elements, the MTJ element is considered to be expensive in terms of the material cost per bit.

On the other hand, the transistor including an oxide semiconductor described in this embodiment has the same element structure and operation principle as a silicon MOSFET except that a semiconductor material forming a channel is a metal oxide. In addition, a transistor including an oxide semiconductor is not affected by a magnetic field and has a characteristic that a soft error cannot occur. Therefore, it can be said that the compatibility with the silicon integrated circuit is very good.

Next, an example of a memory element different from that in FIG.

FIG. 7A is a cross-sectional view of a memory element according to one embodiment of the present invention, and FIG. 7B is a circuit diagram thereof. The memory element illustrated in FIG. 7 includes a transistor 31, a capacitor 32, and a transistor 34. As the transistor 31 and the capacitor 32, the transistor and the capacitor described in Embodiments 1 and 2 can be used.

As shown in FIG. 7A, the semiconductor film 12a, the insulating film 16, the electrode 14a, the electrode 14b, and the gate electrode 18a constitute a transistor 31. The electrode 14b, the insulating film 16, and the electrode 18b constitute a capacitive element 32. In addition, the channel formation region 117a, the drain electrode 117b, the source electrode 117c, the gate insulating film 108, and the gate electrode 107 constitute the transistor 34.

7B, in the memory element according to one embodiment of the present invention, the first wiring (1st Line) and the source electrode or the drain electrode 117b of the transistor 34 are electrically connected to each other. The wiring (2nd Line) of the transistor 34 and the drain electrode or the source electrode 117c of the transistor 34 are electrically connected. In addition, the third wiring (3rd Line) and the electrode 14a functioning as the drain electrode of the transistor 31 are electrically connected, and the fourth wiring (4th Line) and the gate electrode 18a of the transistor 31 are electrically connected. Connected. The gate electrode 107 of the transistor 34 and the electrode 14b functioning as the source electrode of the transistor 31 are electrically connected, and the electrode 14b also serves as one of the electrodes of the capacitor 32. Further, the fifth wiring (5th Line) and 18b functioning as the other electrode of the capacitor 32 are electrically connected.

Here, an oxide semiconductor is preferably used for the semiconductor film of the transistor 31. By using an oxide semiconductor, a transistor with extremely low off-state current can be obtained. Therefore, when the transistor 31 is turned off, the potential of the gate electrode of the transistor 34 can be held for an extremely long time. By including the capacitor 32, the potential applied to the gate electrode of the transistor 34 can be easily retained, and the retained data can be easily read.

The transistor 34 includes a semiconductor film including a channel formation region 117 a, a source or drain electrode 117 b, a drain or source electrode 117 c, a gate insulating film 108, and a gate electrode 107 over a substrate 150. An insulating film 101 is provided around the transistor 34.

The transistor 34 is not particularly limited with respect to the channel conductivity type and its semiconductor material. As for the channel conductivity type of the transistor, when a p-channel type is used, reading can be performed without using a low potential, so that a peripheral circuit for generating a low potential is not necessary. On the other hand, when the n-channel type is used, high-speed reading is possible. As the semiconductor material, it is preferable to use a transistor with a high switching speed such as a transistor using single crystal silicon from the viewpoint of improving the data reading speed.

In the semiconductor device described in this embodiment, the node FG operates in the same manner as a floating gate of a floating gate transistor such as a flash memory. However, the node FG in this embodiment includes a floating gate such as a flash memory and the like. Has essentially different characteristics.

In the flash memory, since the potential applied to the control gate is high, it is necessary to maintain a certain distance between the cells so that the potential does not affect the floating gate of the adjacent cell. This is one of the factors that hinder the high integration of semiconductor devices. This factor is due to the fundamental principle of flash memory in which a high voltage is applied to generate a tunnel current.

On the other hand, the semiconductor device according to the present embodiment operates by switching the transistor 31 and does not use the principle of charge injection by the tunnel current as described above. That is, a high voltage for injecting charges as in a flash memory is not necessary. As a result, it is not necessary to consider the influence of the high voltage due to the control gate on the adjacent cells, so that high integration is facilitated.

Another advantage over the flash memory is that a high electric field is unnecessary and a large peripheral circuit (such as a booster circuit) is unnecessary. For example, the maximum value of the voltage applied to the memory cell according to the present embodiment (the difference between the maximum potential and the minimum potential applied simultaneously to each terminal of the memory cell) is two-stage (1 bit) data. Can be set to 5 V or less, preferably 3 V or less in one memory cell.

(Embodiment 4)
In this embodiment, a semiconductor circuit according to one embodiment of the present invention will be described. Note that the transistor and the capacitor described in the above embodiment can be applied to the transistor and the capacitor provided in the semiconductor circuit. Since the transistor and the capacitor described in the above embodiment have stable electric characteristics and low power consumption, the reliability of the semiconductor circuit can be increased and power consumption can be reduced.

FIG. 8 illustrates a buffer circuit 100 including n-channel transistors as a structural example of a semiconductor circuit according to one embodiment of the present invention.

A buffer circuit 200 illustrated in FIG. 8 includes first to sixth transistors and a capacitor. In the first transistor 201, a first terminal and a third terminal are connected to a power supply line V _dd on the high potential side. The second terminal is connected to the first terminal of the second transistor 202 and the third terminal of the third transistor 203. In the second transistor 202, the second terminal is connected to the power supply line V _ss on the low potential side. is connected, a third terminal is connected to the input V _in the buffer circuit 200, the third transistor 203, the first terminal is connected to the power supply line V _dd on the high potential side, a second terminal, the first 4 is connected to the first terminal of the fourth transistor 204 and the third terminal of the fifth transistor 205. In the fourth transistor 204, the second terminal is connected to the power supply line V _ss on the low potential side, and the third terminal is , Buffer times Is connected to the input _{V in} of 200, the fifth transistor 205, a first terminal is connected to the power supply line _{V dd} on the high potential side, a second terminal, the first terminal and the buffer of the sixth transistor 206 is connected to the output _{V out} of _the circuit 200, the transistor 206 of the sixth, second terminal is connected to the power supply line _{V ss} of the low potential side, a third terminal is connected to the input _{V in} the buffer circuit 200 The second terminal of the first transistor 201 is connected to the output unit _Vout through the capacitor 207.

  The buffer circuit 200 illustrated in FIG. 8 has high driving capability and can increase the gain of high-frequency components. Furthermore, such a buffer circuit has a high slew rate. Furthermore, since it can be configured by transistors having the same polarity, it can be manufactured by a simple process.

For example, as the transistor 206 and the capacitor 207, the transistor and the capacitor of the above embodiment can be used. Thus, a buffer circuit with low power consumption and a small exclusive area can be obtained.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 5)
In this embodiment, a semiconductor circuit according to one embodiment of the present invention will be described. Note that the transistor and the capacitor described in the above embodiment can be applied to the transistor and the capacitor provided in the semiconductor circuit. Since the transistor and the capacitor described in the above embodiment have stable electric characteristics and low power consumption, the reliability of the semiconductor circuit can be increased and power consumption can be reduced.

FIG. 9 illustrates a memory element 300 as an example of a structure of a semiconductor circuit according to one embodiment of the present invention. The memory element 300 includes a memory circuit 301, a memory circuit 302, a switch 303, a switch 304, a switch 305, a logic element 306 that inverts a logical value, and a capacitor 307. The memory circuit 301 holds data only during a period when the power supply voltage is supplied. The memory circuit 302 includes a capacitor 308, a transistor 309, and a transistor 310.

  Note that the memory element 300 may further include other circuit elements such as a diode, a resistance element, and an inductor as necessary.

For example, the transistor and the capacitor of the above embodiment can be applied to the transistor 309 and the capacitor 308. Accordingly, a buffer circuit with low power consumption and high integration can be obtained.

  In FIG. 9, the switch 303 is formed using a transistor 313 of one conductivity type (for example, an n-channel type), and the switch 304 includes a transistor 314 of a conductivity type (for example, a p-channel type) different from the one conductivity type. An example configured using this is shown. Here, the first terminal of the switch 303 corresponds to one of the source and the drain of the transistor 313, the second terminal of the switch 303 corresponds to the other of the source and the drain of the transistor 313, and the switch 303 corresponds to the gate of the transistor 313. In accordance with the control signal S2 input to, the conduction or non-conduction between the first terminal and the second terminal (that is, the on state or the off state of the transistor 313) is selected. The first terminal of the switch 304 corresponds to one of the source and the drain of the transistor 314, the second terminal of the switch 304 corresponds to the other of the source and the drain of the transistor 314, and the switch 304 is input to the gate of the transistor 314. The control signal S2 selects the conduction or non-conduction between the first terminal and the second terminal (that is, the on state or the off state of the transistor 314).

  One of a source and a drain of the transistor 309 is electrically connected to one of a pair of electrodes of the capacitor 308 and a gate of the transistor 310. Here, the connection part is referred to as a node M2. One of a source and a drain of the transistor 310 is electrically connected to a power supply line to which the potential V1 is applied, and the other is electrically connected to a first terminal of the switch 303 (one of a source and a drain of the transistor 313). The The second terminal of the switch 303 (the other of the source and the drain of the transistor 313) is electrically connected to the first terminal of the switch 304 (one of the source and the drain of the transistor 314). A second terminal of the switch 304 (the other of the source and the drain of the transistor 314) is electrically connected to a power supply line to which the potential V2 is applied. A second terminal of the switch 303 (the other of the source and the drain of the transistor 313), a first terminal of the switch 304 (one of a source and a drain of the transistor 314), and an input terminal of the logic element 306 that inverts the logic value The capacitor element 307 is electrically connected to one of the pair of electrodes. Here, the connection part is referred to as a node M1. The other of the pair of electrodes of the capacitor 307 can have a structure in which a constant potential is input. For example, a low power supply potential (such as a ground potential) or a high power supply potential can be input. The other of the pair of electrodes of the capacitor 307 may be electrically connected to a power supply line to which the potential V1 is applied. The other of the pair of electrodes of the capacitor 308 can have a structure in which a constant potential is input. For example, a low power supply potential (such as a ground potential) or a high power supply potential can be input. The other of the pair of electrodes of the capacitor 308 may be electrically connected to a power supply line to which the potential V1 is applied. FIG. 9 illustrates an example in which the other of the pair of electrodes of the capacitor 307 and the other of the pair of electrodes of the capacitor 308 are electrically connected to a power supply line to which the potential V1 is applied.

  Note that the capacitor 307 can be omitted by positively using the parasitic capacitance of the transistor. The capacitor 308 can be omitted by positively using the parasitic capacitance of the transistor.

  A control signal S <b> 1 is input to the gate of the transistor 309. The switch 303 and the switch 304 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal S2 that is different from the control signal S1, and the first terminal and the second terminal of one switch When the terminals of the other switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state. The switch 305 selects a conduction state or a non-conduction state between the first terminal and the second terminal by a control signal S3 different from the control signal S1 and the control signal 2.

  A signal corresponding to data held in the memory circuit 301 is input to the other of the source and the drain of the transistor 309. FIG. 9 illustrates an example in which a signal output from the output terminal (described as OUT in FIG. 9) of the memory circuit 301 is input to the other of the source and the drain of the transistor 309. A signal output from the second terminal of the switch 303 (the other of the source and the drain of the transistor 313) becomes an inverted signal whose phase is inverted by the logic element 306 that inverts the logic value, and the first signal is generated by the control signal S3. The signal is input to the memory circuit 301 through the switch 305 in which the terminal and the second terminal are in a conductive state.

  Note that in FIG. 9, a signal output from the second terminal of the switch 303 (the other of the source and the drain of the transistor 313) is input to the memory circuit 301 through the logic element 306 and the switch 305 that invert the logic values. Although an example of inputting in (shown as IN in FIG. 9) is shown, the present invention is not limited to this. A signal output from the second terminal of the switch 303 (the other of the source and the drain of the transistor 313) may be input to the memory circuit 301 without being inverted in phase. For example, when there is a node in the memory circuit 301 that holds a signal whose phase of the signal input from the input terminal is inverted, the second terminal of the switch 303 (the other of the source and the drain of the transistor 313) An output signal can be input to the node.

  In FIG. 9, a voltage corresponding to the potential difference between the potential V1 and the potential V2 is supplied to the memory element 300 as a power supply voltage. A voltage corresponding to the potential difference between the potential V1 and the potential V2 may be supplied to the memory circuit 301 as a power supply voltage. In the period when the power supply voltage is not supplied to the memory circuit 301, the potential difference between the potential V1 and the potential V2 can be substantially eliminated.

  Note that the switch 305 can be formed using a transistor. The transistor may be an n-channel transistor or a p-channel transistor. Further, an n-channel transistor and a p-channel transistor may be used in combination. For example, the switch 305 can be an analog switch.

  In FIG. 9, the transistor 309 can be a transistor having two gates above and below with an oxide semiconductor layer interposed therebetween. The control signal S1 can be input to one gate, and the control signal S4 can be input to the other gate. The control signal S4 may be a signal having a constant potential. The constant potential may be the potential V1 or the potential V2. Note that the control signal S1 may be input by electrically connecting two gates provided above and below the oxide semiconductor layer. The threshold voltage of the transistor 309 can be controlled by a signal input to the other gate of the transistor 309. For example, the off-state current of the transistor 309 can be further reduced.

  In FIG. 9, among the transistors used for the memory element 300, a transistor other than the transistor 309 can be a transistor in which a channel is formed in a layer or substrate including a semiconductor other than an oxide semiconductor. For example, a transistor in which a channel is formed in a silicon layer or a silicon substrate can be used. Further, all the transistors used for the memory element 300 can be transistors in which a channel is formed in an oxide semiconductor layer. Alternatively, the memory element 300 may include a transistor in which a channel is formed in an oxide semiconductor layer in addition to the transistor 309, and the remaining transistors are formed in a layer or a substrate formed using a semiconductor other than an oxide semiconductor. It can also be a transistor.

  The memory circuit 301 in FIG. 9 includes a logic element that inverts the first logic value and a logic element that inverts the second logic value, and the input terminal of the logic element that inverts the first logic value is the second The input terminal of the logic element that inverts the first logic value is electrically connected to the output terminal of the logic element that inverts the first logic value. Other configurations can be used. Each of the logic element that inverts the first logic value and the logic element that inverts the second logic value outputs a signal corresponding to the input signal only during a period in which the power supply potential is supplied.

  Moreover, as a logic element which inverts a logic value, an inverter, a clocked inverter, etc. can be used, for example.

  In the memory element 300, data stored in the memory circuit 301 corresponding to a volatile memory can be held by the capacitor 308 provided in the memory circuit 302 while the power supply voltage is not supplied.

  In the case where an oxide semiconductor is used as the semiconductor film of the transistor 309, the off-state current of the transistor 309 can be extremely small as compared with the off-state current of a transistor in which a channel is formed in crystalline silicon, for example. Therefore, the signal held in the capacitor 308 is kept for a long time even when the power supply voltage is not supplied to the memory element 300. In this manner, the memory element 300 can hold the memory content (data) even while the supply of power supply voltage is stopped.

  In addition, since the memory element is characterized in that the precharge operation is performed by providing the switch 303 and the switch 304, the time until the memory circuit 301 holds the original data again after the supply of the power supply voltage is resumed. Can be shortened.

  In the memory circuit 302, a signal held by the capacitor 308 is input to the gate of the transistor 310. Therefore, after the supply of the power supply voltage to the memory element 300 is restarted, the signal held by the capacitor 308 is converted into the state of the transistor 310 (on state or off state) and read from the memory circuit 302. Can do. Therefore, the original signal can be accurately read even if the potential corresponding to the signal held in the capacitor 308 varies somewhat.

  By using such a storage element 300 for a storage device such as a register or a cache memory included in the signal processing circuit, it is possible to prevent data in the storage device from being lost due to the supply of power supply voltage being stopped. In addition, after the supply of the power supply voltage is resumed, the state before the power supply stop can be restored in a short time. Therefore, since the power supply can be stopped in a short time in the entire signal processing circuit or in one or more logic circuits constituting the signal processing circuit, the signal processing circuit that can reduce power consumption and power consumption can be suppressed. It is possible to provide a method for driving the signal processing circuit.

  This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 6)
In this embodiment, a display device according to one embodiment of the present invention will be described.

<Example of display device using EL element>
First, an example of a display device using an EL element will be described with reference to FIGS.

FIG. 10 is a circuit diagram illustrating a configuration example of the pixel 410. Here, a case where an element including an organic substance that emits light by current excitation between a pair of electrodes (hereinafter, also referred to as an organic electroluminescence (EL) element) is used as the display element will be described.

A pixel 410 illustrated in FIG. 10 includes transistors 411 to 416, capacitor elements 417 and 418, and an organic EL element 419.

Here, for example, the transistor and the capacitor described in the above embodiment can be applied to the transistor 416 and the capacitor 418. By using the transistor and the capacitor described in the above embodiment, power consumption of a circuit included in the pixel 410 can be reduced and the degree of integration can be improved.

  In the transistor 411, one of a source and a drain is electrically connected to the signal line 408, and a gate is electrically connected to the scan line 406.

  In the transistor 412, one of a source and a drain is electrically connected to a wiring for supplying the potential V1, and a gate is electrically connected to the scan line 405. Note that here, the potential V1 is lower than the high power supply potential (Vdd) and higher than the low power supply potential (Vss).

  In the transistor 413, one of a source and a drain is electrically connected to the power supply line 409, and a gate is electrically connected to the other of the source and the drain of the transistor 412.

  In the transistor 414, one of a source and a drain is electrically connected to one of the source and the drain of the transistor 411, the other of the source and the drain is electrically connected to the other of the source and the drain of the transistor 413, and a gate is a scan line. 405 is electrically connected.

  In the transistor 415, one of a source and a drain is electrically connected to a wiring for supplying the potential V0, and the other of the source and the drain is electrically connected to the other of the source and the drain of the transistor 413 and the other of the source and the drain of the transistor 414. And the gate is electrically connected to the scanning line 404. Note that here, the potential V0 is lower than the potential V1 and higher than the low power supply potential (Vss).

  In the transistor 416, one of a source and a drain is electrically connected to the other of the source and the drain of the transistor 413, the other of the source and the drain of the transistor 414, and the other of the source and the drain of the transistor 415, and a gate is the inverted scanning line 407. Is electrically connected.

  In the capacitor 417, one electrode is electrically connected to the other of the source and the drain of the transistor 412 and the gate of the transistor 413, and the other electrode is the other of the source and the drain of the transistor 411 and the source and the drain of the transistor 414. Is electrically connected to one of the two.

  In the capacitor 418, one electrode is electrically connected to the other of the source and the drain of the transistor 411, one of the source and the drain of the transistor 414, and the other electrode of the capacitor 417, and the other electrode is a source of the transistor 413. And the other of the drain, the other of the source and the drain of the transistor 414, the other of the source and the drain of the transistor 415, and one of the source and the drain of the transistor 416.

  In the organic EL element 419, an anode is electrically connected to the other of the source and the drain of the transistor 416, and a cathode is electrically connected to a wiring that supplies a common potential. Note that the common potential applied to the wiring to which one of the source and the drain of the transistor 412 is electrically connected may be different from the common potential applied to the cathode of the organic EL element 419.

  Note that here, the potential supplied from the power supply line 409 is lower than the high power supply potential (Vdd) and higher than the potential V1, and the common potential is lower than the low power supply potential (Vss). Suppose that

  In the following, a node to which the other of the source and the drain of the transistor 412, the gate of the transistor 13, and one electrode of the capacitor 417 are electrically connected is referred to as a node D, and the other of the source and the drain of the transistor 411, A node to which one of the source and the drain of the transistor 414, the other electrode of the capacitor 417, and the one electrode of the capacitor 418 are electrically connected is referred to as a node E, and the other of the source and the drain of the transistor 413 and the transistor 414 A node to which the other of the source and the drain, the other of the source and the drain of the transistor 415, the one of the source and the drain of the transistor 416, and the other electrode of the capacitor 418 are electrically connected is referred to as a node F.

FIG. 11A illustrates a portion including a transistor 416 and a capacitor 418 in a cross-sectional view of the pixel 410.

Over the transistor 416 and the capacitor 418, a planarization insulating film 480 having an opening reaching the source electrode or the drain electrode of the transistor 416 is provided.

An anode 481 is provided over the planarization insulating film 480. The anode 481 is in contact with the source electrode or the drain electrode of the transistor 416 through the opening of the planarization insulating film 480.

A partition wall 484 having an opening reaching the anode 481 is provided on the anode 481.

A light-emitting layer 482 that is in contact with the anode 481 through an opening provided in the partition wall 484 is provided over the partition wall 484.

A cathode 483 is provided over the light-emitting layer 482.

A region where the anode 481, the light emitting layer 482, and the cathode 483 overlap is an organic EL element 419.

Note that the planarization insulating film 480 may be selected from the materials described as the planarization insulating film 4126.

The light-emitting layer 482 is not limited to a single layer, and a plurality of kinds of light-emitting materials may be stacked. For example, a structure as shown in FIG. FIG. 11B illustrates a structure in which the intermediate layer 485a, the light-emitting layer 486a, the intermediate layer 485b, the light-emitting layer 486b, the intermediate layer 485c, the light-emitting layer 486c, and the intermediate layer 485d are stacked in this order. At this time, when an appropriate light-emitting color material is used for the first light-emitting layer 486a, the light-emitting layer 486b, and the light-emitting layer 486c, the organic EL element 419 having high color rendering properties or high light emission efficiency can be formed.

White light may be obtained by stacking a plurality of types of light emitting materials. Although not shown in FIG. 11A, a structure in which white light is extracted through a colored layer may be used.

Although a structure in which three light emitting layers 482 and four intermediate layers are provided is shown here, the present invention is not limited to this, and the number of light emitting layers and the number of intermediate layers can be changed as appropriate. For example, the intermediate layer 485a, the light emitting layer 486a, the intermediate layer 485b, the light emitting layer 486b, and the intermediate layer 485c can be used alone. Alternatively, the intermediate layer 485a, the light-emitting layer 486a, the intermediate layer 485b, the light-emitting layer 486b, the light-emitting layer 486c, and the intermediate layer 485d may be included, and the intermediate layer 485c may be omitted.

As the intermediate layer, a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and the like can be used in a stacked structure. Note that the intermediate layer may not include all of these layers. These layers may be appropriately selected and provided. Note that a layer having a similar function may be provided in an overlapping manner. In addition to the carrier generation layer, an electronic relay layer or the like may be appropriately added as an intermediate layer.

For the anode 481, a conductive film having visible light permeability may be used. Having visible light transmittance means that the average transmittance in the visible light region (for example, a wavelength range of 400 nm to 800 nm) is 70% or more, particularly 80% or more.

Examples of the anode 481 include an In—Zn—W-based oxide film, an In—Sn-based oxide film, an In—Zn-based oxide film, an In-based oxide film, a Zn-based oxide film, and a Sn-based oxide film. An oxide film such as the above may be used. In addition, a small amount of Al, Ga, Sb, F, or the like may be added to the above oxide film. Alternatively, a metal thin film that transmits light (preferably, approximately 5 nm to 30 nm) can be used. For example, an Ag film, an Mg film, or an Ag—Mg alloy film having a thickness of 5 nm may be used.

Alternatively, the anode 481 is preferably a film that reflects visible light efficiently. For the anode 481, for example, a film containing lithium, aluminum, titanium, magnesium, lanthanum, silver, silicon, or nickel may be used.

The cathode 483 can be selected from the films shown as the anode 481 and used. However, when the anode 481 has visible light permeability, it is preferable that the cathode 483 reflects visible light efficiently. In the case where the anode 481 reflects visible light efficiently, the cathode 483 preferably has visible light permeability.

Note that although the anode 481 and the cathode 483 are provided with the structure shown in FIG. 11A, the anode 481 and the cathode 483 may be interchanged. A material having a high work function is preferably used for the electrode functioning as the anode, and a material having a low work function is preferably used for the electrode functioning as the cathode. However, when the carrier generation layer is provided in contact with the anode, various conductive materials can be used for the anode without considering the work function.

The partition 484 may be selected from the materials shown for the planarization insulating film 4126.

Since the transistor 416 connected to the organic EL element 419 has little variation in electrical characteristics, display quality of the display device can be improved.

<Example of display device using liquid crystal element>
Although FIGS. 10 and 11 show in detail a display device using an organic EL element as a display element, the present invention is not limited to this. For example, those skilled in the art can easily conceive applying this embodiment to a display device using a liquid crystal element as a display element.

As a specific example, a pixel structure applicable to a display device using a liquid crystal element is described below with reference to FIGS.

FIG. 12A is a circuit diagram illustrating a structure example of a pixel of a display device using a liquid crystal element. A pixel 450 illustrated in FIG. 12A includes a transistor 451, a capacitor 452, and an element (hereinafter also referred to as a liquid crystal element) 453 in which a liquid crystal material is filled between a pair of electrodes.

Here, the transistor and the capacitor described in the above embodiment can be applied to the transistor 451 and the capacitor 452. By using the transistor and the capacitor described in the above embodiment, power consumption of a circuit included in the pixel 450 can be reduced and the degree of integration can be improved.

In the transistor 451, one of a source and a drain is electrically connected to the signal line 455, and a gate is electrically connected to the scanning line 454.

In the capacitor 452, one electrode is electrically connected to the other of the source and the drain of the transistor 451, and the other electrode is electrically connected to a wiring for supplying a common potential.

In the liquid crystal element 453, one electrode is electrically connected to the other of the source and the drain of the transistor 451, and the other electrode is electrically connected to a wiring for supplying a common potential. Note that the common potential applied to the wiring to which the other electrode of the capacitor 452 is electrically connected may be different from the common potential applied to the other electrode of the liquid crystal element 453.

FIG. 12B illustrates a portion including a transistor 451 and a capacitor 452 in the cross section of the pixel 450.

Over the transistor 451 and the capacitor 452, a planarization insulating film 490 having an opening reaching the source electrode or the drain electrode of the transistor 451 is provided.

An electrode 491 is provided over the planarization insulating film 490. The electrode 491 is in contact with the source electrode or the drain electrode of the transistor 451 through the opening of the planarization insulating film 490.

An insulating film 492 that functions as an alignment film is provided over the electrode 491.

A liquid crystal layer 493 is provided over the insulating film 492.

An insulating film 494 functioning as an alignment film is provided over the liquid crystal layer 493.

A spacer 495 is provided over the insulating film 494.

An electrode 496 is provided over the spacer 495 and the insulating film 494.

A substrate 497 is provided over the electrode 496.

Note that the planarization insulating film 490 may be selected from the materials described as the planarization insulating film 4126.

The liquid crystal layer 493 may be formed using a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

Note that a liquid crystal material exhibiting a blue phase may be used for the liquid crystal layer 493. In that case, a structure in which the insulating films 492 and 494 functioning as alignment films are not provided may be employed.

As the electrode 491, a conductive film having visible light permeability may be used.

Examples of the electrode 491 include an In—Zn—W-based oxide film, an In—Sn-based oxide film, an In—Zn-based oxide film, an In-based oxide film, a Zn-based oxide film, and a Sn-based oxide film. An oxide film such as the above may be used. In addition, a small amount of Al, Ga, Sb, F, or the like may be added to the above oxide film. Alternatively, a metal thin film that transmits light (preferably, approximately 5 nm to 30 nm) can be used.

Alternatively, the electrode 491 is preferably a film that reflects visible light efficiently. For the electrode 491, for example, a film containing aluminum, titanium, chromium, copper, molybdenum, silver, tantalum, or tungsten may be used.

The electrode 496 can be selected from the films shown as the electrode 491 and used. However, in the case where the electrode 491 has visible light permeability, it is preferable that the electrode 496 reflects visible light efficiently. In the case where the electrode 491 reflects visible light efficiently, the electrode 496 preferably has visible light permeability.

Note that although the electrode 491 and the electrode 496 are provided with the structure illustrated in FIG. 9B, the electrode 491 and the electrode 496 may be interchanged.

The insulating films 492 and 494 may be selected from an organic compound material or an inorganic compound material.

The spacer 495 may be selected from an organic compound material or an inorganic compound material. Note that the spacer 495 can have various shapes such as a columnar shape and a spherical shape.

Since the transistor 451 connected to the liquid crystal element 453 has little variation in electrical characteristics, display quality of the display device can be improved.

A region where the electrode 491, the insulating film 492, the liquid crystal layer 493, the insulating film 494, and the electrode 496 overlap with each other serves as the liquid crystal element 453.

For the substrate 497, a glass material, a resin material, a metal material, or the like may be used. The substrate 497 may have flexibility.

Since the transistor 451 has little variation in electrical characteristics, display quality of the display device can be improved.

As described in this embodiment, the transistor described in the above embodiment can be applied to part of a display device. Since the transistor has little variation in electrical characteristics, display quality of the display device can be improved.

(Embodiment 7)
The semiconductor device disclosed in this specification can be applied to a variety of electronic devices (including game machines). Electronic devices include television devices (also referred to as televisions or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, audio Examples include a playback device, a gaming machine (such as a pachinko machine or a slot machine), and a game housing. Specific examples of these electronic devices are shown in FIGS.

FIG. 13A illustrates a table 9000 having a display portion. In the table 9000, a display portion 9003 is incorporated in a housing 9001, and an image can be displayed on the display portion 9003. Note that a structure in which the housing 9001 is supported by four legs 9002 is shown. In addition, the housing 9001 has a power cord 9005 for supplying power.

The semiconductor device described in the above embodiment can be used for the display portion 9003 and power consumption of the electronic device can be reduced.

The display portion 9003 has a touch input function. By touching a display button 9004 displayed on the display portion 9003 of the table 9000 with a finger or the like, screen operation or information can be input. It is good also as a control apparatus which controls other household appliances by screen operation by enabling communication with household appliances or enabling control. For example, the display portion 9003 may have a touch input function.

Further, the hinge of the housing 9001 can be used to stand the screen of the display portion 9003 perpendicular to the floor, which can be used as a television device. In a small room, if a television apparatus with a large screen is installed, the free space becomes narrow. However, if the display portion is built in the table, the room space can be used effectively.

FIG. 13B illustrates a television device 9100. In the television device 9100, a display portion 9103 is incorporated in a housing 9101 and an image can be displayed on the display portion 9103. Note that here, a structure in which the housing 9101 is supported by a stand 9105 is illustrated.

The television device 9100 can be operated with an operation switch included in the housing 9101 or a separate remote controller 9110. Channels and volume can be operated with an operation key 9109 provided in the remote controller 9110, and an image displayed on the display portion 9103 can be operated. The remote controller 9110 may be provided with a display portion 9107 for displaying information output from the remote controller 9110.

A television device 9100 illustrated in FIG. 13B includes a receiver, a modem, and the like. The television device 9100 can receive a general television broadcast by a receiver, and is connected to a wired or wireless communication network via a modem, so that it can be unidirectional (sender to receiver) or bidirectional. It is also possible to perform information communication (such as between a sender and a receiver or between receivers).

The semiconductor device described in the above embodiment can be used for the display portions 9103 and 9107, and power consumption of the television device and the remote controller can be reduced.

FIG. 13C illustrates a computer, which includes a main body 9201, a housing 9202, a display portion 9203, a keyboard 9204, an external connection port 9205, a pointing device 9206, and the like.

The semiconductor device described in the above embodiment can be used for the display portion 9203 and can be a computer with low power consumption.

14A and 14B illustrate a tablet terminal that can be folded. FIG. 14A shows an open state, in which the tablet terminal includes a housing 9630, a display portion 9631a, a display portion 9631b, a display mode switching switch 9034, a power switch 9035, a power saving mode switching switch 9036, and a fastener 9033. And an operation switch 9038.

The semiconductor device described in the above embodiment can be used for the display portion 9631a and the display portion 9631b, and can be a tablet terminal with low power consumption.

Part of the display portion 9631 a can be a touch panel region 9632 a and data can be input when a displayed operation key 9638 is touched. Note that in the display portion 9631a, for example, a structure in which half of the regions have a display-only function and a structure in which the other half has a touch panel function is shown, but the structure is not limited thereto. The entire region of the display portion 9631a may have a touch panel function. For example, the entire surface of the display portion 9631a can display keyboard buttons to serve as a touch panel, and the display portion 9631b can be used as a display screen.

Further, in the display portion 9631b, as in the display portion 9631a, part of the display portion 9631b can be a touch panel region 9632b. Further, a keyboard button can be displayed on the display portion 9631b by touching a position where the keyboard display switching button 9539 on the touch panel is displayed with a finger or a stylus.

Touch input can be performed simultaneously on the touch panel region 9632a and the touch panel region 9632b.

A display mode switching switch 9034 can switch the display direction such as vertical display or horizontal display, and can select switching between monochrome display and color display. The power saving mode change-over switch 9036 can optimize the display luminance in accordance with the amount of external light during use detected by an optical sensor built in the tablet terminal. The tablet terminal may include not only an optical sensor but also other detection devices such as a gyroscope, an acceleration sensor, and other sensors that detect inclination.

FIG. 14A shows an example in which the display areas of the display portion 9631b and the display portion 9631a are the same, but there is no particular limitation. One size and the other size may be different, and the display quality is also high. May be different. For example, one display panel may be capable of displaying images with higher definition than the other.

FIG. 14B illustrates a closed state, in which the tablet terminal includes a housing 9630, a solar battery 9633, a charge / discharge control circuit 9634, a battery 9635, and a DCDC converter 9636. Note that FIG. 14B illustrates a structure including a battery 9635 and a DCDC converter 9636 as an example of the charge / discharge control circuit 9634.

Note that since the tablet terminal can be folded in two, the housing 9630 can be closed when not in use. Accordingly, since the display portion 9631a and the display portion 9631b can be protected, a tablet terminal with excellent durability and high reliability can be provided from the viewpoint of long-term use.

In addition, the tablet terminal shown in FIGS. 14A and 14B has a function for displaying various information (still images, moving images, text images, etc.), a calendar, a date or a time. A function for displaying on the display unit, a touch input function for performing touch input operation or editing of information displayed on the display unit, a function for controlling processing by various software (programs), and the like can be provided.

Electric power can be supplied to the touch panel, the display unit, the video signal processing unit, or the like by the solar battery 9633 mounted on the surface of the tablet terminal. Note that the solar cell 9633 is preferable because it can efficiently charge the battery 9635 on one or two surfaces of the housing 9630. Note that as the battery 9635, when a lithium ion battery is used, there is an advantage that reduction in size can be achieved.

Further, the structure and operation of the charge / discharge control circuit 9634 illustrated in FIG. 14B will be described with reference to a block diagram in FIG. FIG. 14C illustrates the solar battery 9633, the battery 9635, the DCDC converter 9636, the converter 9637, the switches SW1 to SW3, and the display portion 9631. The battery 9635, the DCDC converter 9636, the converter 9637, and the switches SW1 to SW3 are illustrated. This corresponds to the charge / discharge control circuit 9634 shown in FIG.

First, an example of operation in the case where power is generated by the solar cell 9633 using external light is described. The power generated by the solar battery is boosted or lowered by the DCDC converter 9636 so as to be a voltage for charging the battery 9635. When power from the solar cell 9633 is used for the operation of the display portion 9631, the switch SW1 is turned on, and the converter 9637 increases or decreases the voltage required for the display portion 9631. In the case where display on the display portion 9631 is not performed, the battery 9635 may be charged by turning off SW1 and turning on SW2.

Note that although the solar cell 9633 is shown as an example of the power generation unit, the configuration is not particularly limited, and the battery 9635 is charged by another power generation unit such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). It may be. For example, it is good also as a structure performed combining a non-contact electric power transmission module which transmits / receives electric power by radio | wireless (non-contact), and another charging means.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

DESCRIPTION OF SYMBOLS 10 Substrate 12 Semiconductor film 12a Semiconductor film 12a1 Impurity addition region 13 Transistor 14a Electrode 14b Electrode 16 Insulating film 18a Gate electrode 18b Electrode 20a Electrode 20b Electrode 20a Gate electrode 23 Insulating film 31 Transistor 32 Capacitance element 34 Transistor 100 Buffer circuit 101 Insulating film 107 Gate electrode 108 Gate insulating film 108a Gate insulating layer 117a Channel formation region 117b Drain electrode 117c Source electrode 150 Substrate 200 Buffer circuit 201 Transistor 202 Transistor 203 Transistor 204 Transistor 205 Transistor 206 Transistor 207 Capacitor element 300 Memory element 301 Memory circuit 302 Memory circuit 303 Switch 304 Switch 305 Switch 306 Logic element 307 for inverting logic value Element 308 Capacitor 309 Transistor 310 Transistor 313 Transistor 314 Transistor 404 Scan line 405 Scan line 406 Scan line 407 Inverted scan line 408 Signal line 409 Power line 410 Pixel 411 Transistor 412 Transistor 413 Transistor 414 Transistor 415 Transistor 416 Transistor 417 Capacitor 418 Capacity Element 419 Organic EL element 450 Pixel 451 Transistor 452 Capacitor element 453 Liquid crystal element 454 Scan line 455 Signal line 480 Flattening insulating film 481 Anode 482 Light emitting layer 483 Cathode 484 Partition wall 485a Intermediate layer 485b Intermediate layer 485c Intermediate layer 485d Intermediate layer 486a Light emitting layer 486b Light-emitting layer 486c Light-emitting layer 490 Flattening insulating film 491 Electrode 492 Insulating film 493 Liquid crystal layer 494 Edge film 495 Spacer 496 Electrode 497 Substrate 4126 Flattened insulating film 9000 Table 9001 Case 9002 Leg 9003 Display portion 9004 Display button 9005 Power cord 9033 Fastener 9034 Switch 9035 Power switch 9036 Switch 9038 Operation switch 9100 Television apparatus 9101 Case 9103 Display unit 9105 Stand 9107 Display unit 9109 Operation key 9110 Remote control operating device 9201 Main body 9202 Case 9203 Display unit 9204 Keyboard 9205 External connection port 9206 Pointing device 9630 Case 9631 Display unit 9631a Display unit 9631b Display unit 9632a Region 9632b Region 9633 Sun Battery 9634 Charge / discharge control circuit 9635 Battery 9636 DCDC converter 9537 Over data 9638 operation key 9639 button

Claims (7)

A semiconductor film provided on an insulating surface; an insulating film; a gate electrode provided so as to overlap the semiconductor film with the insulating film interposed therebetween; an outer peripheral end portion of the semiconductor film; and an outer peripheral end of the gate electrode A transistor having a first electrode in contact with the semiconductor film and a second electrode in contact with the semiconductor film, provided on the inner side not reaching the portion;
A semiconductor device comprising: the insulating film; the second electrode; and a capacitor formed by the third electrode at least partially overlapping the second electrode with the insulating film interposed therebetween. apparatus. In claim 1,
The semiconductor device, wherein the second electrode is provided in contact with an outer peripheral end of the semiconductor film. In claim 1 or claim 2,
The third electrode is a semiconductor device made of the same layer and the same material as the gate electrode. In any one of Claim 1 thru | or 3,
The semiconductor film has an impurity added region,
A semiconductor device in which the impurity doped region does not overlap with the gate electrode. In any one of Claims 1 thru | or 4,
The semiconductor device, wherein the semiconductor film is an oxide semiconductor film. In claim 5,
The oxide semiconductor film is a semiconductor device containing at least indium. In either claim 5 or claim 6,
The oxide semiconductor film has an amorphous part and a crystal part,
The crystal part is a semiconductor device in which the c-axis is aligned in a direction parallel to a normal vector of a surface where the oxide semiconductor film is formed or a normal vector of a surface of the oxide semiconductor film.

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