JP2017184800A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of detecting a fraudulent act in which a game is played by misunderstanding that a normal game medium is used.SOLUTION: A token selector 201 comprises: a token rail 210 for forming a passage through which a token passes; a CMOS image sensor 232 for capturing an image of a token passing through the passage; and a control LSI 234 for detecting whether the token is a normal token or not on the basis of the image data of the captured token. The control LSI 234 includes an image recognition DSP circuit 242 and an image recognition accelerator circuit 249, and rotation integration processing and marking determination processing on the image data of the captured token are performed by these circuits. In addition, the image recognition accelerator circuit 249 performs coordinate conversion of the image data, referring to a conversion parameter 280 in which processing contents of the coordinate conversion are designated.SELECTED DRAWING: Figure 23

Description

  The present invention relates to a gaming machine.

  Conventionally, a game called pachislot, comprising a plurality of reels each having a plurality of symbols arranged on each surface, a start switch, a stop switch, a stepping motor provided for each reel, and a control unit. The machine is known. The start switch detects that the start lever has been operated by the player after a game medium such as a medal has been inserted into the gaming machine (hereinafter also referred to as “start operation”), and starts the rotation of all reels. Output the requested signal. The stop switch detects that a stop button provided for each reel has been pressed by the player (hereinafter also referred to as “stop operation”), and outputs a signal requesting the rotation of the corresponding reel to stop. To do. The stepping motor transmits the driving force to the corresponding reel. Further, the control unit controls the operation of the stepping motor based on the signals output from the start switch and the stop switch, and performs the rotation operation and stop operation of each reel.

  In such a gaming machine, when a start operation is detected, lottery processing using random numbers (hereinafter referred to as “internal lottery processing”) is performed on the program, and the result of the lottery (hereinafter referred to as “internal winning combination”). And the rotation of the reel is stopped based on the timing of the stop operation. Then, when the rotation of all the reels is stopped and the symbol combination related to the winning is displayed, a privilege corresponding to the symbol combination is given to the player.

  In addition, such a gaming machine is provided with a medal selector for detecting a medal inserted at the end of the medal slot. In addition, for this medal selector, a medal (illegal medal) that is not a proper medal (regular medal) is inserted into the medal insertion slot, or a device is inserted into the medal insertion slot, so that a regular medal is inserted into the gaming machine. Measures are taken against fraudulent acts in which a game is played by misunderstanding that it has been inserted.

  For example, in Patent Document 1, two medal detection proximity sensors are provided in a medal passage, and it is determined whether a game medal has passed through the medal passage based on the output of each proximity sensor. A slot machine is described that detects fraud using a tool such as a body.

  On the other hand, Patent Document 2 discloses an image processing apparatus that performs distortion correction processing on input image data and outputs an output image. In this image processing apparatus, a DMAC that controls data transfer between memories is disclosed. Using (Direct Memory Access Controller), data transfer via the bus is performed in response to a control signal from the DMAC instead of the CPU.

  Patent Document 3 discloses a data transfer apparatus that performs data transfer using the above-described DMAC between a storage circuit that stores image data and a processing circuit that performs distortion correction processing. In the apparatus, data transfer via a bus between the storage circuit and the cache memory in the processing circuit is performed in response to a control signal from the DMAC instead of the CPU.

JP 2002-342814 A JP 2013-186624 A JP 2013-186705 A

  However, in the slot machine described in Patent Document 1, medals are inserted by illegally operating the counting function of the medal selector by inserting various shapes of fraudulent instruments other than plates into the medal slot. It is impossible to detect fraudulent acts that seem to be performed and obtain a large number of credits, or fraudulent acts that are performed using illegal medals.

  For example, if the lending unit loaned in the hall where this slot machine is installed is a medals with 20 yen per piece and medals with 5 yen per piece having the same diameter and only different colors and stamps (patterns), Can not be discriminated, and there are those who perform illegal games such as using medals obtained with low betting game machines (so-called 5 slots) with normal gaming machines (so-called 20 slots), Damage has occurred.

  In addition, the slot machine described in Patent Document 1 is attached to a medal lent out in a hall in which a gaming machine is installed, a medal lent out in another hall, or a gaming machine purchased at a used machine dealer. When a medal or a counterfeit medal (including an instrument pretending to be a medal) is the same diameter and only differs in color or stamp (pattern), these cannot be discriminated. For this reason, it has been difficult to detect (detect) an illegal act of playing a game using medals other than regular medals (unauthorized medals).

  Therefore, the fraud determination in the prior art using a normal sensor, such as the slot machine described in Patent Document 1, cannot cope with the various frauds described above, and the effect is limited. Yes.

  Furthermore, when it is attempted to perform fraud determination on a game medium such as a medal by image processing, there is a problem of processing time. In other words, when performing highly accurate fraud determination for highly imitated counterfeit medals, etc., it is necessary to image medals inserted into a slot machine or the like with high resolution, and to perform multiple image processing for each captured pixel data Even if a high-performance CPU or image processing circuit is used, the fraud determination requires a considerably long time.

  In addition, since game media such as medals are normally continuously inserted into a slot machine or the like, it is very difficult to perform fraud determination by image processing as described above on each of the inserted medals in real time. It is difficult to.

  Various approaches are being considered in connection with shortening the time of fraud determination by image processing relating to such game media. However, the processing time using DMA transfer as described in Patent Document 2 and Patent Document 3 is considered. A gaming machine including a circuit that realizes shortening of the above has not been proposed so far.

  In addition, a game machine including a circuit that performs an illegal determination of a game medium by image processing has advantages in terms of manufacturing cost and security, and includes a circuit that uses DMA transfer to reduce processing time. It has not been.

In addition, no circuit has been proposed so far for determining whether a game medium is fraudulent such that the content of coordinate transformation executed in image processing for determining whether the game medium is fraudulent is specified by a conversion parameter.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to detect an illegal act of playing a game by misidentifying that a regular gaming medium is used in the gaming machine. It is to provide a gaming machine.

In order to achieve the above object, the first embodiment of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, medal insertion slot 21) into which a game medium (for example, a medal) is inserted;
Game medium detection means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the insertion slot,
The game medium detection means includes
A game medium passage portion (for example, medal rail 210) serving as a passage through which the game medium passes;
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object that is an object passing through the passage;
By performing image processing based on image data obtained through the imaging means (for example, a captured image 362A acquired by the imaging unit 361), it is determined whether or not the game medium is genuine. Game medium determination means (for example, control LSI 234),
The game medium determining means is
It is configured as a dedicated integrated circuit for determining the game medium,
First storage means for storing data (for example, SRAM 243);
A conversion unit that performs a predetermined format conversion on the image data obtained through the imaging unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.)
Feature image generation means (for example, a feature image generation unit 364, an image recognition accelerator circuit 249, etc.) for generating a feature image indicating the characteristics of the game medium based on the image data after the format conversion,
The feature image generation means includes
Image data relating to the image data after the format conversion is acquired from the first storage means, image processing including coordinate conversion is performed on the acquired image data, and the image data after the image processing is converted into the first data. Memorize it in the memory means,
The processing content of the coordinate transformation is specified by a transformation parameter (for example, transformation parameter 280),
The game medium determination means further includes
Direct transfer control means for controlling direct transfer of data (for example, DMAC 252),
At least one of storage in the first storage unit of the image data after the format conversion in the conversion unit, and storage in the first storage unit of the image data after the image processing in the feature image generation unit, This is done by the direct transfer.

  With such a configuration of the present invention, the regular medal discrimination process can be executed using the image data acquired by the imaging means. Since each process of image conversion and image recognition performed based on the captured image makes it possible to determine a medal or the like, it is possible to determine a difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, an illegal act from the outside (for example, invalidating the regular medal discrimination process or setting the processing logic of the regular medal discrimination process) (The act of trying to steal)) and has a significant security advantage. In addition, by changing the conversion parameter, the content of the coordinate conversion process can be changed as appropriate. Furthermore, since the writing and reading of the image data with respect to the storage means (SRAM or the like) of the game medium determination means is realized by the direct transfer control means that controls the direct transfer of data, the host controller ( (Processor) is not involved and each circuit (hardware) included in the game medium determination means can be processed in parallel. As a result, the processing efficiency is improved and the processing time for determining the game medium is shortened.

The second embodiment of the present invention has the following configuration in the first embodiment.
The feature image generation means includes
It is configured as a circuit in the game medium determination means,
Second storage means (for example, a memory 274) for storing the conversion parameter;
The coordinate conversion is performed based on the conversion parameter acquired from the second storage unit.

  With such a configuration of the present invention, when image processing including coordinate conversion is performed in the feature image generation means, conversion parameters can be acquired by accessing the memory in the circuit, and access via the bus is avoided. Thus, the bus bandwidth can be secured and the processing efficiency can be further improved.

The third embodiment of the present invention has the following configuration in the first embodiment or the second embodiment.
The conversion parameter is configured to indicate at least one of coordinate conversion related to rotation, coordinate conversion related to enlargement, coordinate conversion related to reduction, and coordinate conversion related to parallel movement.

  According to such a configuration of the present invention, it is possible to instruct coordinate conversion related to rotation, coordinate conversion related to enlargement, coordinate conversion related to reduction, and coordinate conversion related to parallel movement by the conversion parameter.

  According to the present invention, it is possible to detect an illegal act of playing a game by misidentifying that a regular gaming medium is used in the gaming machine.

It is explanatory drawing explaining the functional flow in the game machine of one Embodiment of this invention. It is a perspective view which shows the example of an external appearance structure in the game machine of one Embodiment of this invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing an internal structure of a gaming machine according to an embodiment of the present invention, with a middle door closed. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing an internal structure of a gaming machine according to an embodiment of the present invention, with a middle door opened. It is explanatory drawing which shows the inside of the cabinet in the game machine of one Embodiment of this invention. It is explanatory drawing which shows the back surface side of the front door in the game machine of one Embodiment of this invention. It is the perspective view which looked at the medal selector in the gaming machine of one embodiment of the present invention from the slanting back of the gaming machine. It is an exploded view of the medal selector in the gaming machine of one embodiment of the present invention. It is the perspective view which looked at the medal selector in the gaming machine of one embodiment of the present invention from the diagonal front of the gaming machine. It is a perspective view of the select plate of the medal selector in the gaming machine of one embodiment of the present invention. It is a figure which shows the path | route of a medal when the medal selector in the game machine of one Embodiment of this invention guides a medal to a hopper apparatus. It is a figure which shows the path | route of a medal when the medal selector in the gaming machine of one embodiment of the invention guides the medal to the medal shoot. It is a block diagram which shows the control system in the game machine of one Embodiment of this invention. It is a block diagram which shows the structural example of the main control circuit in the game machine of one Embodiment of this invention. It is a block diagram which shows the structural example of the sub control circuit in the game machine of one Embodiment of this invention. It is a block diagram which shows the circuit structural example of the medal selector in the game machine of one Embodiment of this invention. It is a block diagram which shows the circuit structural example of control LSI in the game machine of one Embodiment of this invention. It is a functional block diagram of the camera unit in the gaming machine of one embodiment of the present invention. It is a figure which shows an example of the regular medal used for the game machine of one Embodiment of this invention, A shows one side of a regular medal, B is a figure which shows the image data of a regular medal. It is a figure for demonstrating the production | generation (synthesis | combination) of the process image data regarding the regular medal used for the game machine of one Embodiment of this invention. It is a block diagram which shows the circuit structural example of the image recognition accelerator circuit contained in control LSI in the gaming machine of one Embodiment of this invention. It is a figure which shows the concept which performs coordinate conversion with respect to object image data, and produces | generates the image data after conversion. It is a figure which shows the circuit structural example of the coordinate transformation circuit of the image recognition accelerator circuit contained in control LSI in the gaming machine of one Embodiment of this invention. It is a figure which shows the example of the conversion parameter of the image recognition accelerator circuit contained in control LSI in the game machine of one Embodiment of this invention. It is a figure which shows the example of the specific information of the image recognition accelerator circuit contained in control LSI in the game machine of one Embodiment of this invention. It is a figure which shows typically the example in which the image data after conversion are produced | generated by the conversion parameter from which a rotation angle differs by the image recognition accelerator circuit contained in control LSI in the game machine of one Embodiment of this invention. It is a figure for demonstrating an example of the coordinate transformation by a transformation parameter. It is a figure which shows the concept which synthesize | combines several image data after conversion and produces | generates process image data. It is a figure for demonstrating the outline | summary of operation | movement of the image processing circuit of the image recognition accelerator circuit contained in control LSI in the gaming machine of one Embodiment of this invention. It is a figure which shows the structure of the image processing circuit of the image recognition accelerator circuit contained in control LSI in the game machine of one Embodiment of this invention. It is a figure for demonstrating the flow of the regular medal discrimination | determination process regarding the 1st medal in the gaming machine of one embodiment of the present invention. It is a figure for demonstrating the flow of the regular medal discrimination | determination process regarding the 1st-6th medal in the gaming machine of one embodiment of the present invention. It is a figure which shows the operation | movement flow of the image recognition accelerator circuit contained in control LSI in the gaming machine of one Embodiment of this invention. It is a figure which shows the example of the image data of one side of an unauthorized medal, and an unauthorized medal. It is a figure which shows the example of one side of an unauthorized medal, the image data of an unauthorized medal, and the process image data of an unauthorized medal. It is a figure which shows typically an example of the captured image obtained via the imaging device of the camera unit in the gaming machine of one embodiment of the present invention. It is a functional block diagram of the camera unit in the gaming machine of one embodiment of the present invention. It is a figure which shows the structure of the characteristic image generation part in the game machine of one Embodiment of this invention in detail. It is a flowchart which shows a series of operation | movement of the regular medal discrimination | determination process implemented with the camera unit in the game machine of one Embodiment of this invention. It is a figure which shows an example of a medal area typically. It is a figure which shows an example of a background image typically. It is a figure which shows an example of a background difference image typically. It is a figure which shows an example of an external shape template typically. It is a figure for demonstrating template matching. It is a figure for demonstrating the extraction process of a medal area. It is a figure which shows an example of an edge image typically. It is a figure for demonstrating the production | generation method of a rotation synthetic | combination image. It is a figure which shows the circuit structural example of the image recognition accelerator circuit contained in the control LSI in the modification 1 of one Embodiment of this invention. It is a figure which shows the concept of producing | generating process image data by superimposing several coordinate transformation with respect to object image data. It is a figure which shows the circuit structural example of the image recognition accelerator circuit contained in the control LSI in the modification 2 of one Embodiment of this invention. It is a figure which shows the circuit structural example of the image processing circuit of the image recognition accelerator circuit contained in the control LSI in the modification 2 of one Embodiment of this invention. It is a figure which shows the example of the conversion parameter of the image recognition accelerator circuit contained in the control LSI in the modification 2 of one Embodiment of this invention. It is a figure which shows the example of the specific information of the image recognition accelerator circuit contained in the control LSI in the modification 2 of one Embodiment of this invention. It is a figure for demonstrating operation | movement of the image recognition accelerator circuit contained in the control LSI in the modification 2 of one Embodiment of this invention. It is a figure which shows the circuit structural example of the image recognition accelerator circuit contained in the control LSI in the modification 3 of one Embodiment of this invention. It is a figure which shows the circuit structural example of the image processing circuit of the image recognition accelerator circuit contained in the control LSI in the modification 3 of one Embodiment of this invention. It is a figure which shows the circuit structural example of the image processing circuit of the image recognition accelerator circuit contained in the control LSI in the modification 4 of one Embodiment of this invention.

<< One Embodiment >>
Hereinafter, a pachislot machine that is a gaming machine according to an embodiment of the present invention will be described with reference to FIGS.

<Function flow>
First, the functional flow of the pachislot will be described with reference to FIG. In the pachislot of this embodiment, medals are used as game media for playing games. Note that all the embodiments and modifications of the present invention are not limited to the pachislot machine, and can be applied to other gaming machines (for example, pachinko machines) other than the pachislot machine. In addition to medals, the game media can be coins, game balls, game point data, tokens, or the like.

  At the start of the game, when a player inserts a medal and operates the start lever, one value (hereinafter referred to as a random value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535). Is done.

  The internal lottery means performs lottery based on the extracted random number value and determines an internal winning combination. This internal lottery means is carried out by a main control circuit described later. By determining the internal winning combination, a combination of symbols that permits display along a winning determination line described later is determined. The types of symbol combinations include those related to “winning” in which benefits such as paying out medals, re-games, bonuses, etc. are given to players, and other so-called “loses”. Is provided.

  Further, when the start lever is operated, a plurality of reels are rotated. Thereafter, when the player presses the stop button corresponding to the predetermined reel, the reel stop control means performs control to stop the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. Do. The reel stop control means is responsible for a main control circuit described later.

  In the pachislot, basically, a control for stopping the rotation of the corresponding reel is performed within a specified time (190 msec or 75 msec) from when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within the specified time is referred to as “the number of sliding symbols”. When the specified period is 190 msec, the maximum number of sliding symbols is set to 4 symbols, and when the specified period is 75 msec, the maximum number of sliding symbols is set to 1 symbol.

  When the internal winning combination allowing the symbol combination display related to winning is determined, the reel stop control means usually displays the symbol combination within the specified time of 190 msec (four symbols) for the winning determination line. The rotation of the reel is stopped so as to display as much as possible. In addition, the reel stop control means is defined for one or more reels when, for example, a challenge bonus (CB), which is a second-type special accessory, and a middle bonus (MB) for continuously operating the CB are operated. The reel rotation is stopped so that the combination of symbols is displayed as much as possible along the winning determination line within a time of 75 msec (for one symbol). Furthermore, the reel stop control means uses various specified times corresponding to the gaming state to rotate the reels so that combinations of symbols that are not permitted to be displayed by the internal winning combination are not displayed along the winning determination line. Stop.

  Thus, when the rotation of the plurality of reels is all stopped, the winning determination means determines whether or not the combination of symbols displayed along the winning determination line is related to winning. This winning determination means is carried out by a main control circuit described later. When it is determined by the winning determination means that it is related to winning, a privilege such as paying out medals is given to the player. In the pachislot, a series of flows as described above is performed as one game.

  Further, in the pachislot, in the above-described series of flows, video display performed by a display device such as a liquid crystal display device, light output performed by various lamps, sound output performed by a speaker, or a combination thereof is used. Various productions are performed.

  When the start lever is operated, an effect random number value (hereinafter referred to as effect random number value) is extracted separately from the random number value used for determining the internal winning combination. When the effect random number value is extracted, the effect content determining means determines, by lottery, what is to be executed this time from among a plurality of types of effect contents associated with the internal winning combination. This effect content determination means is carried out by a sub-control circuit described later.

  When the contents of the effect are determined, the effect executing means executes the corresponding effect in conjunction with each opportunity, such as when the rotation of the reels starts, when the rotation of each reel stops, or when determining whether there is a winning. In this way, in the pachislot, the player is given an opportunity to know or predict the determined internal winning combination (in other words, the combination of symbols to be aimed at) by executing the production contents associated with the internal winning combination. It is possible to improve the player's interest.

<Pachislot structure>
Next, the structure of the pachislo 1 according to the present embodiment will be described with reference to FIGS.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachi-slot 1.

  As shown in FIG. 2, the pachi-slot 1 includes an exterior body 2. The exterior body 2 includes a cabinet 2a that houses a hopper device 51, a medal auxiliary storage 52, and the like (see FIG. 5), which will be described later, and a front door 2b that is attached to the cabinet 2a so as to be opened and closed. Handles 7 are provided on both side surfaces of the cabinet 2a (only one handle 7 is shown in FIG. 2). The handle 7 is a recess that is put on when carrying the pachi-slot 1.

  Three reels 3L, 3C, and 3R are provided side by side in the exterior body 2. Hereinafter, the reels 3L, 3C, and 3R are referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each reel 3L, 3C, 3R has a reel body formed in a cylindrical shape and a translucent sheet material mounted on the peripheral surface of the reel body. A plurality of (for example, 20) symbols are drawn on the surface of the sheet material at predetermined intervals along the circumferential direction.

  The front door 2b includes a door body 9, a front panel 10, and a liquid crystal display device 11 showing a specific example of the display device.

  The door body 9 is attached to the cabinet 2a using a hinge (not shown), and opens and closes the opening of the cabinet 2a. The hinge is provided at the left end of the door body 9 when the door body 9 is viewed from the front of the pachi-slot 1. The liquid crystal display device 11 is attached to the upper part of the door body 9. The liquid crystal display device 11 includes a display unit (display screen) 11a, and the liquid crystal display device 11 performs an effect by displaying an image.

  The front panel 10 is disposed so as to overlap the display unit 11 a side of the liquid crystal display device 11, and is formed in a frame shape having a panel opening 10 a that exposes the display unit 11 a of the liquid crystal display device 11. A lamp group 18 is provided on the front panel 10. The lamp group 18 is configured by an LED (Light Emitting Diode) or the like, and turns on and off the light in a pattern corresponding to the effect content.

  A pedestal 12 is formed in the center of the front door 2b. The pedestal portion 12 is provided with a symbol display area 4 and various devices to be operated by the player.

  The symbol display area 4 is arranged on the front side superimposed on the three reels 3L, 3C, 3R when viewed from the front, and is provided corresponding to the three reels 3L, 3C, 3R. The symbol display area 4 functions as a display window, and is configured to be able to pass through the reels 3L, 3C, and 3R provided behind it. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

  When the reels 3L, 3C, and 3R provided behind the reel display window 4 are stopped from rotating, the reel display window 4 has an upper stage, a middle stage, and a lower stage within the frame among the plural types of symbols of the reels 3L, 3C, and 3R. One symbol (three in total) is displayed in each area. In the present embodiment, a target for determining whether or not to win a pseudo line configured by combining any one of the three regions including the upper, middle and lower regions of the reel display window 4 is determined. Is defined as a line (winning determination line).

  The reel display window 4 is formed by a frame member 13 provided on the pedestal portion 12. The frame member 13 has a reel display window 4, an information display window 14, and a stop button attachment portion 15.

  The information display window 14 is provided continuously below the reel display window 4 and opens upward. That is, the reel display window 4 and the information display window 14 are formed as one continuous opening. The information display window 14 and the reel display window 4 are covered with a transparent window cover 16.

  The window cover 16 is disposed on the inner surface side of the frame member 13 and cannot be removed from the front side of the front door 2b. In addition, the frame member 13 includes a sheet placement portion 17 that faces the opening of the information display window 14 with the window cover 16 interposed therebetween. And between the sheet | seat mounting part 17 and the window cover 16, the sheet | seat member (information sheet) in which the information regarding a game was described is arrange | positioned. Therefore, the information sheet is covered with the window cover 16 having a smooth surface without unevenness or gaps.

  The window cover 16 that constitutes the information sheet attachment portion cannot be removed from the front side of the front door 2b, and has a smooth surface with no irregularities or gaps. Can prevent fraudulent access to the inside.

  The stop button mounting portion 15 is provided below the information display window 14 and is formed on a plane facing the front. The stop button mounting portion 15 is provided with a through hole through which the stop buttons 19L, 19C, 19R pass. The stop buttons 19L, 19C, 19R are associated with the three reels 3L, 3C, 3R, respectively, and are provided to stop the rotation of the corresponding reels. Hereinafter, the stop buttons 19L, 19C, and 19R are referred to as a left stop button 19L, a middle stop button 19C, and a right stop button 19R, respectively.

  The stop buttons 19L, 19C, and 19R show examples of various devices that are targets of operations by the player. In addition, the pedestal portion 12 is provided with a medal slot 21, a BET button 22, and a start lever 23 as various devices to be operated by the player.

  The medal slot 21 is provided to accept a medal dropped from the outside by the player. The medals accepted by the medal slot 21 are inserted into one game with a predetermined number (for example, three) as the upper limit, and the amount exceeding the specified number is deposited inside the pachislot 1. (So-called credit function).

  The BET button 22 is provided to determine the number of coins to be inserted into one game from medals deposited inside the pachislot 1. The start lever 23 is provided to start the rotation of all the reels (3L, 3C, 3R).

  In addition, a 7-segment display 24 including a 7-segment LED (Light Emitting Diode) is provided on the left side of the reel display window 4 when the front door 2b is viewed from the front. The 7-segment display 24 digitally displays information such as the number of medals to be paid out to the player as a privilege (hereinafter referred to as payout number) and the number of medals deposited in the pachislot (hereinafter referred to as credit number). .

  A settlement button 27 is provided on the left side of the base 12 when the front door 2b is viewed from the front. The checkout button 27 is provided to pull out (discharge) the outside stored in the interior of the pachislot machine 1. A lower panel unit 31 is provided below the pedestal 12. The waist panel unit 31 includes a decorative panel on which an arbitrary image is drawn and a light source that emits light for illuminating the decorative panel from the back side.

  Below the waist panel unit 31, a medal payout port 32, speaker holes 33L and 33R, and a medal tray unit 34 are provided. The medal payout port 32 guides medals discharged from a medal selector 201 described later and medals discharged by driving a hopper device 51 described later to the outside. The medals discharged from the medal payout opening 32 are stored in the medal tray unit 34. The speaker holes 33L and 33R are provided to output sound such as sound effects and music corresponding to the contents of the performance.

[Internal structure]
3 and 4 are perspective views showing the internal structure of the pachi-slot 1. FIG. 3 shows a state in which the front door 2b is opened and the middle door 41 provided on the back side of the front door 2b is closed with respect to the front door 2b. FIG. 4 shows a state where the front door 2b is opened and the middle door 41 is opened with respect to the front door 2b. FIG. 5 is an explanatory diagram showing the inside of the cabinet 2a. FIG. 6 is an explanatory view showing the back side of the front door 2b.

  The cabinet 2a includes a top plate 20a, a bottom plate 20b, left and right side plates 20c and 20d, and a back plate 20e (see FIG. 5). A cabinet-side speaker 42 is disposed on the upper side inside the cabinet 2a. The cabinet-side speaker 42 is attached to the back plate 20e of the cabinet 2a via attachment brackets 43L and 43R. The cabinet side speaker 42 is, for example, a speaker for outputting sound effects.

  A cabinet-side relay board 44 is disposed on the left side of the cabinet-side speaker 42 when the inside of the cabinet 2a is viewed from the front. The cabinet side relay board 44 is attached to the left side plate 20c of the cabinet 2a. The cabinet-side relay board 44 includes a main control board 71 (see FIG. 13), which will be described later, attached to the middle door 41 (see FIGS. 3 and 4), a hopper device 51, a medal auxiliary storage switch (not shown), and a medal payout. The wiring connecting the count switch (not shown) is relayed.

  An amplifier board 45 that controls the output of sound from the cabinet-side speaker 42 is disposed in the center of the cabinet 2a. The amplifier board 45 is attached to an attachment shelf 46 fixed to the left and right side plates 20c and 20d.

  Further, an external concentrated terminal plate 47 is disposed on the right side of the amplifier board 45 when the inside of the cabinet 2a is viewed from the front (see FIG. 5). The external concentrated terminal plate 47 is attached to the right side plate 20d of the cabinet 2a. The external concentration terminal board 47 is provided for outputting signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachislot machine 1.

  A sub power supply device 48 is disposed on the left side of the amplifier board 45 when the inside of the cabinet 2a is viewed from the front. The sub power supply 48 is attached to the left side plate 20c of the cabinet 2a. The sub power supply device 48 supplies power with an AC voltage of 100 V to the power supply device 53 described later. Further, the power of the AC voltage 100V is converted into the power of the DC voltage and supplied to the amplifier board 45.

  A medal payout device (hereinafter referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply device 53 are disposed on the lower side of the cabinet 2a.

  The hopper device 51 is attached to the central portion of the bottom plate 20b in the cabinet 2a. This hopper device 51 can accommodate a large amount of medals, and has a structure capable of discharging them one by one. For example, when the settlement button 27 (see FIG. 2) is pressed to settle the medals stored in the pachislot, the hopper device 51 discharges the stored medals by the number of credits. The medals paid out by the hopper device 51 are discharged from the medal payout port 32 (see FIG. 2).

  The medal auxiliary storage 52 stores medals overflowing from the hopper device 51. The medal auxiliary storage 52 is disposed on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. The medal auxiliary storage 52 is engaged with the bottom plate 20b of the cabinet 2a, and is configured to be detachable from the bottom plate 20b.

  The power supply device 53 is disposed on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side plate 20c. The power supply device 53 includes a power switch 53a and a power supply board 53b (see FIG. 13). The power supply device 53 converts the power of the AC voltage 100V supplied from the sub power supply device 48 into the power of the DC voltage necessary for each part, and supplies the converted power to each part.

  As shown in FIGS. 3, 4 and 6, the middle door 41 is arranged at the center of the back surface of the front door 2b, and is configured to open and close the reel display window 4 (see FIG. 4) from the back side. Door stoppers 41a, 41b, and 41c are provided at the upper and lower portions of the middle door 41. The door stoppers 41a, 41b, 41c fix (prohibit) the opening operation of the middle door 41 in a state where the reel display window 4 is closed from the back side. That is, in order to open the middle door 41, it is necessary to rotate the door stoppers 41a, 41b, 41c to release the middle door 41 from being fixed.

  A main control board case 55 that houses a main control board 71 (see FIG. 13) and three reels 3L, 3C, and 3R are attached to the middle door 41. Stepping motors are connected to the three reels 3L, 3C, and 3R through gears having a predetermined reduction ratio.

  As shown in FIG. 6, the main control board case 55 is provided with a setting key type switch 56. The setting key type switch 56 is used when changing the setting of the pachislot 1 or confirming the setting of the pachislot 1. In the present embodiment, a main control board unit is configured by the main control board case 55 and the main control board 71 accommodated in the main control board case 55.

  The main control board 71 accommodated in the main control board case 55 constitutes a main control circuit 91 (see FIG. 14) described later. The main control circuit 91 is a circuit that controls the main flow of the game in the pachislot 1 such as determination of an internal winning combination, rotation and stop of the reels 3L, 3C, 3R, and determination of the presence or absence of winning. A specific configuration of the main control circuit 91 will be described later.

  A sub control board case 57 that accommodates the sub control board 72 (see FIG. 13) is disposed above the middle door 41, and a center speaker 58 is disposed above the sub control board case 57. The sub control board 72 housed in the sub control board case 57 constitutes the sub control circuit 101 (see FIG. 15). The sub-control circuit 101 is a circuit that controls execution of effects by displaying images. A specific configuration of the sub control circuit 101 will be described later.

  A sub relay board 61 is disposed on the right side of the sub control board case 57 when the front door 2b is viewed from the back side. The sub relay board 61 relays the wiring connecting the sub control board 72 and the main control board 71. Further, it is a board that relays the wiring that connects the sub-control board 72 and the board disposed around the sub-control board 72. In addition, as a board | substrate arrange | positioned around the sub control board 72, LED board 62A, 62B, 62C mentioned later is mentioned.

  The LED boards 62A, 62B, and 62C are disposed on both sides of the sub control board case 57 when viewed from the back side of the front door 2b. These LED boards 62A, 62B, and 62C have a plurality of LEDs (Light Emitting Diodes) 85 (see FIG. 13) showing a specific example of the light source in accordance with the effects executed by the control of the sub-control circuit 101 (see FIG. 15). ) To display a blinking pattern. Note that the gaming machine according to the present embodiment includes a plurality of LED boards in addition to the LED boards 62A, 62B, and 62C.

  Below the sub-relay board 61, a 24h door opening / closing monitoring unit 63 is disposed. The 24h door opening / closing monitoring unit 63 stores the opening / closing history of the middle door 41. When the middle door 41 is opened, a signal for displaying an error on the liquid crystal display device 11 is output to the sub control board 72 (sub control circuit 101).

  Below the middle door 41, a board speaker 64 and lower speakers 65L and 65R are arranged. The board speaker 64 faces the waist panel unit 31 (see FIG. 2), and the lower speakers 65L and 65R face the speaker holes 33L and 33R (see FIG. 2), respectively.

  Above the lower speaker 65L, a medal selector 201, a medal chute 202, and a door open / close monitoring switch 67 are disposed. The medal selector 201 is a device that determines whether or not the material and shape of the medal are appropriate. The medal selector 201 guides the medal inserted into the medal insertion slot 21 to the hopper device 51 via the slope 203 or the medal. Guide to the chute 202. A specific configuration of the medal selector 201 will be described later.

  The medal chute 202 is a substantially Y-shaped cylindrical member, and guides the medal guided by the medal selector 201 and the medal discharged from the hopper device 51 to the medal payout opening 32 (see FIG. 2).

  The door open / close monitoring switch 67 is disposed on the left side of the medal selector 201 when the front door 2b is viewed from the back side. The door open / close monitoring switch 67 outputs a security signal for notifying the opening / closing of the front door 2b to the outside of the pachi-slot 1.

  Further, a door relay terminal plate 68 is disposed in a region below the reel display window 4 and opened and closed by the middle door 41 (see FIG. 4). The door relay terminal board 68 includes a main control board 71 (see FIG. 13) in the main control board case 55, various buttons and switches, a sub-control board 72 (see FIG. 13), a medal selector 201, and a game operation display board. It is a board | substrate which relays wiring with 81 (refer FIG. 13). Examples of the various buttons and switches include a BET button 22, a settlement button 27, a door open / close monitoring switch 67, a BET switch 77, a start switch 79, and the like, which will be described later.

<Composition of medal selector>
Next, a specific configuration of the medal selector 201 will be described with reference to FIGS. FIG. 7 is a perspective view of the medal selector 201 when viewed from an oblique rear side of the pachi-slot 1. FIG. 8 is an exploded view of the medal selector 201. FIG. 9 is a perspective view of the medal selector 201 as viewed obliquely from the front of the pachi-slot 1. FIG. 10 is a perspective view of a select plate 207, which will be described later, of the medal selector 201. FIG. FIG. 11 is a diagram showing a medal path when the medal selector 201 guides the medal to the hopper device 51. FIG. 12 is a diagram showing a medal path when the medal selector 201 guides the medal to the medal chute 202. In addition, the arrow X shown in FIGS. 7-12 shows the left-right direction of the pachislot 1, the arrow Y shows the front-back direction of the pachislot 1, and the arrow Z shows the up-down direction.

  As shown in FIGS. 7 to 9, the medal selector 201 includes a base plate portion 204, a sub plate 205, a cancel shooter 206, a select plate 207, a medal solenoid 208 (see FIG. 9), a camera unit 209, It has.

  The base plate portion 204 is a substantially plate-like member that constitutes the outer frame housing of the medal selector 201, and is molded so that both left and right end portions of the pachi-slot 1 bend to the rear of the pachi-slot 1. The base plate portion 204 has a rear surface 204b that is one plane orthogonal to the front-rear direction of the pachislot 1 and a front surface 204a (see FIG. 9) that is the other plane. A medal rail 210 is formed on the rear surface 204b so as to be recessed forward of the pachi-slot 1 and in a substantially L shape. A plurality of ridges are formed on the surface of the medal rail 210.

  At the upper end portion of the base plate portion 204, a medal entrance portion 211 that receives a medal inserted from the medal insertion port 21 (see FIG. 2) is provided. A medal inserted into the medal selector 201 from the medal entrance 211 moves along the medal rail 210 from above to below. A medal outlet portion 204c (see FIG. 8) is provided at the lower portion of the base plate portion 204. The medals that have moved in the medal selector 201 are discharged from the medal outlet 204c and are accommodated in the hopper device 51 via the slope 203 (see FIG. 4).

  A central hole 212 penetrating in the front-rear direction is formed at a substantially intermediate position of the medal rail 210, and an end of the medal pressure 213 (see FIG. 8) is exposed from the central hole 212. As shown in FIG. 9, the medal pressure 213 is rotatably supported by a shaft portion 214 provided on the front surface 204 a of the base plate portion 204. A coil spring 215 is attached to the shaft portion 214, and the medal pressure 213 is urged by the coil spring 215 so that the medal pressure 213 protrudes from the central hole 212.

  As shown in FIG. 9, a magnet 217 is provided on the front surface 204 a of the base plate portion 204. The magnet 217 attracts (magnetizes) an illegal medal that is not an appropriate material among medals moving on the medal rail 210.

  As shown in FIG. 8, an upper exposure hole 219 that penetrates in the front-rear direction and exposes a rear end portion of an after-medal pressure 218, which will be described later, is formed in a substantially central portion of the downstream region of the medal rail 210. . Further, a lower exposure hole 220 that penetrates in the front-rear direction and exposes a later-described medal stopper portion 227 of the select plate 207 is formed in the lower portion of the downstream area of the medal rail 210.

  As shown in FIG. 9, the after medal pressure 218 is pivotally supported on the front surface 204 a of the base plate portion 204 so as to be rotatable. When the front end of the after medal pressure 218 is pressed rearward of the pachislot 1 by the medal solenoid 208, the after medal pressure 218 rotates, and the rear end of the after medal pressure 218 passes through the upper exposure hole 219 (see FIG. 8). Exposed.

  As shown in FIGS. 7 and 8, the cancel shooter 206 is a substantially plate-like member, and is molded so that both ends in the left-right direction of the pachislot 1 bend forward of the pachislot 1. The cancel shooter 206 is detachably fixed to the base plate portion 204 and covers the lower portion of the base plate portion 204 from the rear. The cancel shooter 206 guides the medals discharged without going through the medal outlet 204c to the medal chute 202 (see FIG. 4). A cutout portion 206 a that is cut out in a substantially rectangular shape is formed at the upper portion of the substantially central portion in the left-right direction of the cancel shooter 206.

  As shown in FIG. 7, the sub plate 205 is a plate-like member that covers the medal rail 210 from behind. The sub-plate 205 has a flat plate-like main body part 221 and a shaft part 222 provided on the upper part of the main body part 221. A through hole 221a penetrating in the front-rear direction is provided in a substantially central portion of the main body portion 221, and a downstream region is exposed from the substantially central portion of the medal rail 210 from the through hole 221a.

  The shaft portion 222 is supported by the base plate portion 204, and the sub-plate 205 is attached to the base plate portion 204 so as to be rotatable about the shaft portion 222. A coil spring 223 is attached to the shaft portion 222. Under normal conditions, the sub plate 205 is pressed against the base plate portion 204 side by the biasing force of the coil spring 223. At this time, a space through which medals can pass is formed between the sub plate 205 and the upper part of the medal rail 210 covered with the sub plate 205. That is, the sub plate 205 functions as a guide plate that allows the medal to pass therethrough.

  Here, for example, when a medal jam occurs in the medal selector 201, the sub plate 205 can be rotated against the urging force of the coil spring 223 to eliminate the medal jam.

  As shown in FIG. 8, the select plate 207 is a member that guides a medal that moves in a substantially central portion of the medal rail 210 that is not covered by the sub plate 205. As shown in FIG. 10, the select plate 207 includes a substantially trapezoidal plate main body 224 and a pair of bearing portions formed by bending both left and right end portions of the plate main body 224 forward of the pachislot 1. 225. A flange portion 226 is formed on the upper portion of the plate main body 224. The flange portion 226 is formed by bending the pachislot 1 forward and bending the rear end portion upward. One bearing portion 225 is formed with a medal stopper portion 227 extending downward.

  As shown in FIG. 8, the plate main body 224 is opposed to the substantially central portion of the medal rail 210 not covered by the sub-plate 205 in the front-rear direction of the pachislot 1.

  As shown in FIG. 9, the select plate 207 is rotatably supported by a shaft portion 228 provided on the front surface 204 a of the base plate portion 204. The shaft portion 228 is provided with a coil spring 229 and biases the flange portion 226 forward of the pachislot 1. The flange portion 226 is in contact with one end portion of the medal solenoid 208. When the medal solenoid 208 is in the ON state, the flange portion 226 is pressed by one end of the medal solenoid 208 and moves to the rear of the pachislot 1 against the urging force of the coil spring 229. The rotation position of the select plate 207 at this time is referred to as a “guide position”. The distance between the plate body 224 of the select plate 207 at the guide position and the medal rail 210 is set to a predetermined distance that allows the medal to be guided to the hopper device 51 without discharging the medal to the cancel shooter 206 side. At this time, the medal stopper portion 227 does not protrude from the lower exposure hole 220 (see FIG. 8).

  When the medal solenoid 208 is in the OFF state, the flange portion 226 is released from the pressing of the medal solenoid 208 and moves forward of the pachislot 1 by the biasing force of the coil spring 229. The rotation position of the select plate 207 at this time is referred to as a “discharge position”. The distance between the plate body 224 of the select plate 207 at the discharge position and the medal rail 210 is set to be longer than a predetermined distance. At this time, the flange portion 226 that moves forward of the pachislot 1 is pressed, and one end of the medal solenoid 208 moves forward of the pachislot 1. Along with this, the other end of the medal solenoid 208 moves to the rear of the pachislot 1 and presses the front end of the after medal pressure 218. As a result, the after medal pressure 218 rotates and the rear end of the after medal pressure 218 is exposed from the upper exposure hole 219 (see FIG. 8).

  The medal stopper 227 does not protrude from the lower exposure hole 220 (see FIG. 8) when the select plate 207 is at the guide position, and protrudes from the lower exposure hole 220 when at the discharge position.

  As shown in FIG. 11, when the medal moving on the medal rail 210 satisfies the standard dimension, the select plate 207 at the guide position comes into contact with the upper part of the moving medal and the medal outlet 204c (see FIG. 8). ) When the medal is guided by the select plate 207, the medal pressure 213 is pressed forward of the pachislot 1. In FIG. 11, illustration of the sub plate 205 and the cancel shooter 206 of the medal selector 201 is omitted.

  On the other hand, as shown in FIG. 12, the select plate 207 in the discharge position has a distance between the plate body 224 and the medal rail 210 even if the medal moving on the medal rail 210 satisfies the standard dimension. Therefore, the medal cannot be guided to the medal outlet 204c (see FIG. 8). The medal is pushed out by the medal pressure 213, the after medal pressure 218 protruding from the upper exposure hole 219, or the medal stopper portion 227 protruding from the lower exposure hole 220, and is discharged toward the cancel shooter 206. In FIG. 12, as in FIG. 11, the sub-plate 205 and the cancel shooter 206 of the medal selector 201 are not shown.

  In this embodiment, the select plate 207 is normally positioned at the guide position. However, under a predetermined condition (for example, when a predetermined number of medals are inserted, when an error occurs, when a game starts, etc.), It is positioned.

  If the medal moving on the medal rail 210 has a smaller diameter than the standard dimension, even if the select plate 207 is in the guide position, the medal is not guided to the select plate 207 but pushed out to the medal pressure 213 and the cancel shooter 206 It is discharged toward

  As shown in FIGS. 7 and 8, the camera unit 209 includes a first board 230 and a second board 231, and determines whether or not an object moving on the medal rail 210 is a regular medal. It is. The first substrate 230 is provided with a CMOS image sensor 232 (see FIG. 16) and an LED 233 (see FIG. 16). The second substrate 231 is provided with a control LSI 234 (see FIG. 16) connected to the CMOS image sensor 232 and the LED 233 so as to be communicable and controllable. The first substrate 230 and the second substrate 231 are connected by a BtoB (Board-to-Board) type connector (not shown), and by legs 235 provided at the corners of the substrates 230 and 231. It is fixed. The specific configuration of the camera unit 209 circuit will be described later. Further, in the present embodiment, the mode in which the camera unit 209 is configured by the two substrates 230 and 231 has been described, but instead of this, the camera unit 209 is configured by a single substrate provided with the CMOS image sensor 232, the LED 233, and the control LSI 234. May be configured.

  The camera unit 209 is fixed by screwing the first substrate 230 into a screw hole 206b provided around a notch 206a at the top of the cancel shooter 206. The CMOS image sensor 232 (see FIG. 16) is provided at a substantially central portion of the first substrate 230. The CMOS image sensor 232 images a medal that moves on the medal rail 210 and outputs image data of the imaged medal to the control LSI 234 (see FIG. 16). The LED 233 (see FIG. 16) emits light around the CMOS image sensor 232, and irradiates the medal moving on the medal rail 210 with light. The control LSI 234 (see FIG. 16) determines whether the object moving on the medal rail 210 is a regular medal based on the image data output from the CMOS image sensor 232, and outputs the determination result. That is, in the present embodiment, the control LSI 234 constitutes a game medium determination unit that determines whether or not a medal moving on the medal rail 210 is a regular medal. In this embodiment, the mode in which the camera unit 209 is fixed to the cancel shooter 206 by screwing in the screw hole 206b formed around the notch portion 206a has been described. However, the camera unit fixing mode is limited to this. Not. For example, an attachment rail is provided between the first substrate 230 and the second substrate 231, and a recess is provided in the upper part of the cancel shooter 206. The attachment rail and the cancel shooter 206 are fitted in the recess. May be fixed with screws or an adhesive.

<Pachislot circuit configuration>
Next, a configuration of a circuit included in the pachislo 1 will be described with reference to FIGS. First, the outline of the entire circuit provided in the pachislot machine 1 will be described with reference to FIG. FIG. 13 is a block configuration diagram of the entire circuit provided in the pachi-slot 1.

  The pachi-slot 1 has a main control board 71 disposed on the middle door 41 and a sub-control board 72 disposed on the front door 2b. The main control board 71 includes a reel relay terminal board 74, a setting key switch 56, an external concentration terminal board 47, a hopper device 51, a medal auxiliary storage switch 75, and a power supply board 53b of the power supply 53. It is connected. The setting key switch 56, the external concentration terminal board 47, the hopper device 51, and the medal auxiliary storage switch 75 are connected to the main control board 71 via the cabinet-side relay board 44. Since the external concentration terminal board 47 and the hopper device 51 have been described above, description thereof will be omitted.

  The reel relay terminal board 74 is disposed inside the reel body of each of the reels 3L, 3C, 3R. The reel relay terminal plate 74 is electrically connected to stepping motors (not shown) of the reels 3L, 3C, and 3R, and relays signals output from the main control board 71 to the stepping motors.

  The medal auxiliary storage switch 75 passes through a switch through hole (not shown) of the medal auxiliary storage 52. The medal auxiliary storage switch 75 detects whether or not the medal auxiliary storage 52 is full of medals.

  A power switch 53 a is connected to the power supply board 53 b of the power supply device 53. The power switch 53a is turned on when supplying necessary power to the pachislot machine 1.

  The main control board 71 has a medal selector 201, a door open / close monitoring switch 67, a BET switch 77, a settlement switch 78, a start switch 79, a stop switch board 80, and a game operation display board 81 via a door relay terminal board 68. The sub-relay board 61 is connected. Since the door opening / closing monitoring switch 67 and the sub relay board 61 have been described above, the description thereof will be omitted. The circuit configuration of the medal selector 201 will be described later.

  The BET switch 77 detects that the BET button 22 has been pressed by the player. The settlement switch 78 detects that the settlement button 27 has been pressed by the player. The start switch 79 detects that the start lever 23 has been operated by the player (start operation).

  The stop switch substrate 80 is a substrate constituting a circuit for stopping the rotating reel and a circuit for displaying the stopable reel by an LED or the like. The stop switch substrate 80 is provided with a stop switch. The stop switch detects that each stop button 19L, 19C, 19R has been pressed by the player (stop operation).

  The game operation display board 81 displays the number of inserted medals on the 7-segment display 24 when accepting insertion of medals, when the three reels 3L, 3C, 3R are rotatable and when replaying. It is a substrate for making it. A 7-segment display 24 and an LED 82 are connected to the game operation display board 81. The LED 82 lights, for example, a mark for displaying the start of a game or a mark for performing a re-game.

  The sub control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub relay board 61. A sound I / O board 84, LED boards 62A, 62B, 62C, and a 24h door open / close monitoring unit 63 are connected to the sub control board 72 through a sub relay board 61. Since these LED substrates 62A, 62B, 62C and the 24h door opening / closing monitoring unit 63 have been described above, the description thereof will be omitted.

  The sound I / O board 84 outputs sound to a center speaker 58, a board speaker 64, lower speakers 65L and 65R, and a speaker (not shown) provided on the front door 2b.

  The sub-control board 72 is connected to a ROM cartridge board 86 and a liquid crystal relay board 87. The ROM cartridge substrate 86 and the liquid crystal relay substrate 87 are housed in the sub control board case 57 together with the sub control board 72. The ROM cartridge substrate 86 is a substrate for managing production images (video), sound, LED substrates 62A and 62B, other LED substrates (not shown), and communication data. The liquid crystal relay substrate 87 is a substrate that relays wiring that connects the sub-control board 72 and the liquid crystal display device 11.

[Main control circuit]
Next, the main control circuit 91 constituted by the main control board 71 will be described with reference to FIG. FIG. 14 is a block diagram illustrating a configuration example of the main control circuit 91 of the pachi-slot 1.

  The main control circuit 91 includes a microcomputer 92 installed on the main control board 71 as a main component. The microcomputer 92 includes a main CPU 93, a main ROM 94, and a main RAM 95. The main CPU 93 and the hopper device 51 described above constitute a game medium payout device of the present invention.

  The main ROM 94 is used to transmit various control commands (commands) to the control program executed by the main CPU 93 (for example, the program for executing the internal lottery process described above), the data table, and the sub-control circuit 101. Data etc. are stored. The main RAM 95 is provided with a storage area for storing various data such as an internal winning combination determined by execution of the control program.

  The main CPU 93 is connected to a clock pulse generation circuit 96, a frequency divider 97, a random number generator 98, and a sampling circuit 99. The clock pulse generation circuit 96 and the frequency divider 97 generate clock pulses. The main CPU 93 executes a control program based on the generated clock pulse. The random number generator 98 generates a random number in a predetermined range (for example, 0 to 65535). The sampling circuit 99 extracts one value from the generated random numbers.

  The main CPU 93 counts the number of times pulses are output to the stepping motors of the reels 3L, 3C, and 3R after detecting the reel index. Thereby, the main CPU 93 manages the rotation angle of each reel 3L, 3C, 3R (mainly, how many symbols the reel has rotated). The reel index is information indicating that the reel has made one revolution. For example, the reel index is provided at a predetermined position of each of the reels 3L, 3C, and 3R, and the light sensor and the light receiving unit are rotated by rotation of the reels 3L, 3C, and 3R. Detection is performed by a reel position detection unit (not shown) including a detection piece interposed therebetween.

  Here, management of the rotation angles of the reels 3L, 3C, and 3R will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 95. Each time the output of a predetermined number of pulses (for example, 16 times) necessary for the rotation of one symbol is counted by the pulse counter, the symbol counter provided in the main RAM 95 is incremented by one. The symbol counter is provided for each reel 3L, 3C, 3R. The value of the symbol counter is cleared when a reel index is detected by a reel position detector (not shown).

  In other words, in the present embodiment, by managing the symbol counter, it is possible to manage how many symbols have been rotated since the reel index was detected. Therefore, the position of each symbol on each reel 3L, 3C, 3R is detected with reference to the position where the reel index is detected.

  As described above, when the maximum number of sliding symbols is set to four symbols, the symbol of the left reel 3L in the middle of the reel display window 4 when the left stop button 19L is pressed, and the four symbols. Each symbol within the range up to the previous symbol becomes a symbol that can be stopped at the middle stage of the reel display window 4.

[Sub control circuit]
Next, the sub control circuit 101 constituted by the sub control board 72 will be described with reference to FIG. FIG. 15 is a block diagram illustrating a configuration example of the sub control circuit 101 of the pachi-slot 1.

  The sub control circuit 101 is electrically connected to the main control circuit 91 and performs processing such as determination and execution of effect contents based on a command transmitted from the main control circuit 91. The sub control circuit 101 basically includes a sub CPU 102, a sub RAM 103, a rendering processor 104, a drawing RAM 105, and a driver 106.

  The sub CPU 102 controls the output of video, sound, and light according to the control program stored in the ROM cartridge substrate 86 in accordance with the command transmitted from the main control circuit 91. The ROM cartridge substrate 86 basically includes a program storage area and a data storage area.

  A control program executed by the sub CPU 102 is stored in the program storage area. For example, the control program includes a main board communication task for controlling communication with the main control circuit 91 and an effect registration task for extracting and registering effect contents (effect data) by extracting effect random numbers. Is included. Further, a drawing control task for controlling display of an image by the liquid crystal display device 11 (see FIG. 2) based on the determined contents of the effect, a lamp control task for controlling light output by a light source such as the LED 85, and the speakers 58, 64, 65L. , 65R, etc., a voice control task for controlling the output of sound by a speaker.

  The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data related to creation of video. Also included are a storage area for storing sound data related to BGM and sound effects, a storage area for storing lamp data related to the light on / off pattern, and the like.

  The sub-RAM 103 is provided with a storage area for registering the determined contents and effects data, and a storage area for storing various data such as an internal winning combination transmitted from the main control circuit 91.

  The sub CPU 102, the rendering processor 104, the drawing RAM (including the frame buffer) 105, and the driver 106 create a video according to the animation data designated by the contents of the presentation, and display the created video on the liquid crystal display device 11.

  Further, the sub CPU 102 causes a speaker such as speakers 58, 64, 65L, and 65R to output a sound such as BGM according to the sound data specified by the production contents. Further, the sub CPU 102 controls the turning on and off of the light source such as the LED 85 according to the lamp data designated by the contents of the effect.

<Circuit configuration of medal selector>
Next, the circuit configuration of the medal selector 201 will be described with reference to FIG. FIG. 16 is a block diagram illustrating a circuit configuration example of the medal selector 201.

  As shown in FIG. 16, the medal selector 201 includes a camera unit 209 and a medal solenoid 208. The medal selector 201 is connected to the main control board 71 via the door relay terminal board 68. That is, the medal selector 201 is electrically connected to the main control circuit 91. Therefore, the main control circuit 91 can set the medal solenoid 208 of the medal selector 201 to the ON state or the OFF state.

  The camera unit 209 includes a control LSI 234, a CMOS image sensor 232, and an LED 233. The control LSI 234 of the camera unit 209 is configured as an LSI dedicated to image processing control such as an application specific integrated circuit (ASIC) or a field-programmable gate array (FPGA), and is electrically connected to the CMOS image sensor 232 and the LED 233, for example. Has been. The control LSI 234 controls the light emission of the LED 233. Further, the control LSI 234 determines whether the insertion is a regular medal based on the image data output from the CMOS image sensor 232, and outputs the determination result to the main control board 71 via the door relay terminal board 68. . In the present embodiment, the adopted CMOS image sensor 232 is a CMOS image sensor having a resolution of 648 × 488 pixels and a frame rate of 240 fps (Frames Per Second), but is limited to such an image sensor. Need not be done (an imaging device other than CMOS may also be used). Moreover, light-emitting devices other than LED can also be used.

[Control LSI circuit configuration]
Next, the circuit configuration of the control LSI 234 will be described with reference to FIGS. FIG. 17 is a block diagram illustrating a circuit configuration example of the control LSI 234. 18 is a functional block diagram of the camera unit 209 including the control LSI 234, FIG. 19 is a diagram for explaining a regular medal, FIG. 19A shows one side of the regular medal, and FIG. 19B is an image of the regular medal. Data are shown. FIG. 20 is a diagram for explaining generation (combination) of processed image data (gradient average image data) related to a regular medal. The camera unit 209 includes a light emitting unit made of an LED or the like, but is not shown in FIG.

  The control LSI 234 includes a host controller 241, an image recognition DSP (digital signal processor) circuit 242, a DMAC (Direct Memory Access Controller) 252, an SRAM (Static Random Access Memory) 243, a flash memory 244, an ISP (Image Signal Processing) circuit 245 and medal count circuit 246 are provided. The control LSI 234 includes a color recognition circuit 247, a fisheye correction scaler circuit 248, an image recognition accelerator circuit 249, and a GPIO (General Purpose Input / Output) 250. These devices constituting the control LSI 234 are connected to each other via a bus, and the control LSI 234 of this embodiment employs AXI (Advanced eXtensible Interface) as a bus protocol.

  The control LSI 234 includes an ISI (Image Sensor Interface) circuit 251. The ISI circuit 251 is electrically connected to the CMOS image sensor 232 and the ISP circuit. The ISI circuit 251 converts the image data output from the CMOS image sensor 232 by the LVDS (Low voltage differential signaling) method into an RGB Bayer image and outputs the RGB data to the ISP circuit 245.

  The DMAC 252 is a circuit that controls direct transfer (that is, DMA (direct memory access) transfer) in which data is transferred between a memory and an input / output device without going through the host controller 241. In the present embodiment, when data transfer is performed between the memory of each of the above-described circuits included in the control LSI 234 and the SRAM 243, DMA transfer under the control of the DMAC 252 is performed as necessary. In the present embodiment, DMA transfer is performed under the control of the DMAC 252 for at least one transfer / storage as required for predetermined data, but the DMAC 252 is deleted from the configuration without performing such DMA transfer. You can also. In other words, in this embodiment, the DMAC 252 that performs DMA control for directly transferring data between each circuit and the SRAM 243 without using the host controller 241 constitutes a direct transfer control unit.

  When receiving the RGB Bayer image from the ISI circuit 251, the ISP circuit 245 outputs a VSYNC (Vertical Synchronization) interrupt signal to the host controller 241. The ISP circuit 245 also performs format conversion processing for converting the RGB Bayer image output from the ISI circuit 251 into various formats. In the format conversion process, the ISP circuit 245 converts the RGB Bayer image to Y (the luminance of each pixel), and stores the converted image data in the SRAM 243 by, for example, DMA transfer. Further, the ISP circuit 245 converts the RGB Bayer image into image data (YUV image data) corresponding to the YUV color space, and outputs data relating to the luminance in the YUV image data to the medal count circuit 246. Further, the ISP circuit 245 converts the RGB Bayer image into image data (HSV image data) corresponding to the HSV color space, and outputs data relating to hue and saturation in the HSV image data to the color recognition circuit 247.

  Here, the CMOS image sensor 232 corresponds to the imaging unit 261 shown in FIG. Also, a processing function for converting the ISI circuit 251 (and the host controller 241 that controls the ISI circuit 251) and a part of the ISP circuit 245 (at least an RGB Bayer image into image data (YUV image data) corresponding to the YUV color space). And a host controller 241 for controlling the same correspond to the conversion unit 263 in FIG. The captured image 262 is sent from the imaging unit 261 to the conversion unit 263.

  The medal count circuit 246 performs count processing based on the data relating to the luminance output from the ISP circuit 245. In the counting process, the medal count circuit 246 compares data relating to the brightness of the count area, which is a predetermined area in the image, with the count threshold value, and determines whether or not a medal has passed by the background difference method. The count threshold value is a threshold value determined in advance based on data relating to the brightness of the count area in the regular medal image. The medal count circuit 246 determines that the medal has passed if the difference is small, and determines that the medal has not passed (other than the medal has passed) if the difference is large. Then, the medal count circuit 246 stores the determination result in the SRAM 243.

  The count area can be arbitrarily set according to the medal used as a regular medal by the pachislot 1. However, it is preferable to set the count area so that the rotation angle of the medal does not greatly affect the difference in luminance. For example, when a regular medal 400 having the same marking (pattern) on both sides as shown in FIG. 19A is used, in the image data 402 (see FIG. 19B) of the regular medal 400, one of the regular medals in the area. The place (area 403 in FIG. 19B) is set as the count area so that the marking (pattern) on the surface of the face does not change with the rotation angle of the medal, that is, the rotation angle of the medal does not greatly affect the difference in luminance. Is preferred. Further, the count process can be speeded up as the range of the count area is narrowed.

  The color recognition circuit 247 performs color determination processing based on data relating to hue and saturation output from the ISP circuit 245. In the color determination process, the color recognition circuit 247 first expresses an integrated value of data related to hue and saturation near the center of the image data as a vector (vector conversion), and calculates the angle of the vector in a three-dimensional space. To do. Next, the color recognition circuit 247 compares the calculated vector angle with a predetermined color threshold value, and determines whether or not it matches the color of the regular medal. The predetermined threshold value is a threshold value determined in advance based on the vector angle calculated by the same method as that described above for the image data related to the regular medal (for example, 3 for the regular medal to be compared). (Within ± 10 degrees of the angle on the individual coordinates (XYZ) of the vector in the dimensional space). The color recognition circuit 247 stores the determination result in the SRAM 243.

  The fish-eye correction scaler circuit 248 acquires image data obtained by converting the RGB Bayer image from the SRAM 243 by Y (luminance of each pixel) by, for example, DMA transfer, and performs fish-eye correction processing. In the fish-eye correction process, the fish-eye correction scaler circuit 248 performs fish-eye correction (for example, bilinear interpolation) on the acquired image data, and creates reduced image data reduced to 1/2, 1/4, and 1/8. . Then, the fisheye correction scaler circuit 248 stores the created reduced image data in the SRAM 243 by, for example, DMA transfer.

  The fisheye correction scaler circuit 248 and the host controller 241 that controls the fisheye correction scaler circuit 248 are included in the conversion unit 263 of FIG.

  The image recognition DSP circuit 242 obtains reduced image data (in this embodiment, reduced image data reduced to ¼) from the SRAM 243 by, for example, DMA transfer, and performs preprocessing. In the preprocessing, the image recognition DSP circuit 242 converts the obtained reduced image data into edge image data through a non-linear diffusion filter, and stores the edge image data in the SRAM 243 by, for example, DMA transfer.

  Here, a part of the image recognition DSP circuit 242 (the above-described processing function unit that converts the acquired reduced image data into edge image data through a non-linear diffusion filter) and the host controller 241 that controls this are shown in FIG. It is included in the conversion unit 263.

  The image recognition accelerator circuit 249 performs image processing (for example, rotation integration processing here) for creating processed image data (for example, gradient average image data here). In this image processing, the image recognition accelerator circuit 249 obtains edge image data from the SRAM 243 by, for example, DMA transfer, and obtains the obtained edge image data (for example, the image data 402 shown in FIG. 19B), for example, in units of 1 degree. The post-conversion image data for 360 degrees generated by rotating in (1) is integrated (superposed) to generate processed image data. The processed image data generated by the image recognition accelerator circuit 249 is stored in the SRAM 243 by DMA transfer, for example. As an example in which processed image data is generated (synthesized), FIG. 20 shows processed image data 405 of a regular medal 400 shown in FIG. 19A. The processed image data 405 is image data (gradient average image data) in which edge image data having the shape of “A” is integrated while rotating 360 degrees (ie, 360 times), but here, Is shown in a simplified manner.

  Note that the processing function unit that generates the processing image data and the host controller 241 that controls the processing function unit of the image recognition accelerator circuit 249 correspond to the feature image generation unit 264 of FIG.

  Further, the image recognition DSP circuit 242 performs a stamp determination process for determining whether or not the stamp (pattern) of the medal matches the stamp of the regular medal. In the marking determination process, the image recognition DSP circuit 242 acquires processed image data created by the image recognition accelerator circuit 249 through image processing from the SRAM 243 by, for example, DMA transfer. Next, the image recognition DSP circuit 242 makes a difference between the acquired processed image data and template data for engraving determination processing (for example, processed image data of regular medals stored in the SRAM 243 or the flash memory 244 prepared in advance). Is calculated. Then, the image recognition DSP circuit 242 determines whether or not the medal stamp matches the stamp of the regular medal based on the calculated difference value and the threshold value for stamp determination, and stores the determination result in the SRAM 243. . For example, the image recognition DSP circuit 242 compares the luminance of each pixel of the acquired processed image data and template data to determine whether or not they match (in the case of multi-tone, whether the difference is within a predetermined range), If there are more than a certain number of matching pixels (difference is within a predetermined range), it is determined that the medal stamp (pattern) matches the stamp of the regular medal. If the number of matching pixels is less than the predetermined number, the medal stamp ( It is determined that the pattern) does not match the stamp of the regular medal.

  Note that the processing function unit related to the marking determination process of the image recognition DSP circuit 242 and the host controller 241 that controls the processing function unit correspond to the determination unit 265 shown in FIG. 18, and the template data is the template data 267. Corresponding to

  The image recognition DSP circuit 242 and the host controller 241 that perform the above-described engraving determination processing and the like operate according to a program (sequence program), and the program is, for example, a memory (for example, a memory (for example, the image recognition DSP circuit 242 or the host controller 241). , DRAM). Further, these programs may be stored in the SRAM 243 or the flash memory 244. The template data is stored in, for example, the SRAM 243.

  The host controller 241 includes a processor, and controls each device, that is, the medal count circuit 246, the color recognition circuit 247, the fisheye correction scaler circuit 248, the image recognition DSP circuit 242, the image recognition accelerator circuit 249, and the GPIO 250. In addition, the host controller 241 outputs a signal relating to a lighting instruction or a lighting instruction to the LED 233 via the GPIO 250. Further, the host controller 241 outputs, via the GPIO 250, the determination result related to the count process, the determination result related to the color determination process, and the determination result related to the marking determination process stored in the SRAM 243.

  Note that the GPIO 250 that outputs a determination result related to the color determination process or the marking determination process and the host controller 241 that controls the GPIO 250 correspond to the input / output unit 266 shown in FIG. 18, and the determination result is the determination of FIG. Corresponds to result 268.

  Each of the host controller 241, the image recognition DSP circuit 242, the fisheye correction scaler circuit 248, and the image recognition accelerator circuit 249 has a memory (for example, DRAM), and parameters and data (for example, for example) used for various processes are stored in the memory. Image data). Also, these parameters and data can be stored in the SRAM 243 and the flash memory 244.

[Configuration of image recognition accelerator circuit]
Next, the configuration of the image recognition accelerator circuit 249 will be described with reference to FIG. FIG. 21 is a block diagram illustrating a circuit configuration example of the image recognition accelerator circuit 249.

  As shown in FIG. 21, the image recognition accelerator circuit 249 includes an input frame buffer 271, a coordinate conversion circuit 272, an image processing circuit 273, and a memory 274 (the memory 274 is configured by a storage circuit such as a DRAM). It has. The input frame buffer 271 receives target image data 275 that is generated based on the medal image data captured by the CMOS image sensor 232 and stored in the SRAM 243 or the like.

  The image recognition accelerator circuit 249 can access the SRAM 243 without the host controller 241 under the control of the DMAC 252 and transfer the target image data 275 from the SRAM 243 to the input frame buffer 271 (DMA transfer). That is, data transfer is performed between the image recognition accelerator circuit 249 and the SRAM 243 without going through the CPU of the host controller 241.

  The input frame buffer 271 can store target image data 275 for one frame. The DMAC 252 controls to read the target image data 275 stored in the SRAM 243 and write the data to the input frame buffer 271. The DMAC 252 repeats such control at a predetermined timing, reads the target image data 275 stored in the SRAM 243, and sequentially stores it in the input frame buffer 271.

  The DMAC 252 can also be configured to have a buffer capable of storing image data composed of a plurality of pixel data. The buffer is composed of, for example, a FIFO (first in first out) buffer. In this case, the DMAC 252 reads the target image data 275 stored in the SRAM 243 and temporarily stores the data in the buffer. Then, the DMAC 252 writes a plurality of pixel data in the buffer to the input frame buffer 271. By repeating this process a plurality of times, the target image data 275 for one frame is written into the input frame buffer 271.

  The coordinate conversion circuit 272 performs image coordinate conversion on the target image data 275 stored in the input frame buffer 271. The converted image data 276 subjected to the coordinate conversion is input to the image processing circuit 273. When new target image data 275 is stored in the input frame buffer 271, the coordinate conversion circuit 272 performs image coordinate conversion on the new target image data 275 stored in the input frame buffer 271. In this specification, image data that has undergone coordinate transformation by the coordinate transformation circuit 272 is referred to as “post-conversion image data”, and image data before coordinate transformation is referred to as “target image data”.

  The coordinate conversion circuit 272 is provided with a conversion parameter 280 stored in the memory 274. For example, the conversion parameter 280 is copied from the SRAM 243 at a timing such as initial setting of the image recognition accelerator circuit 249.

  The image processing circuit 273 performs predetermined image processing on the converted image data 276 obtained by the coordinate conversion circuit 272. For example, the image processing circuit 273 synthesizes a plurality of converted image data 276 obtained by the coordinate conversion circuit 272 and outputs processed image data 277 obtained thereby. In this specification, as a result of image processing by the image processing circuit 273, image data generated (for example, image data obtained by integrating a plurality of converted image data or a plurality of coordinate conversions on target image data is executed. Image data) is referred to as “processed image data”.

  The processed image data 277 generated by the image processing circuit 273 is transferred to the SRAM 243 (DMA transfer) under the control of the DMAC 252. If the DMAC 252 has a buffer, the DMAC 252 temporarily stores a plurality of pixel data of the processed image data 277 output from the image processing circuit 273 in the buffer, and then writes the plurality of pixel data in the buffer to the SRAM 243. By repeating this process a plurality of times, processed image data for one frame is written into the SRAM 243.

[Operation and configuration of coordinate transformation circuit]
Here, the outline of the operation of the coordinate conversion circuit 272 will be described first, and then the configuration and detailed operation of the coordinate conversion circuit 272 will be described.

[Outline of operation of coordinate transformation circuit]
The coordinate conversion circuit 272 performs a plurality of coordinate conversions using the target image data 275 for one frame stored in the input frame buffer 271. Specifically, as shown in FIG. 22, the coordinate conversion circuit 272 individually performs a plurality of coordinate conversions on the target image data 275 to obtain a plurality of converted image data 276 (for example, 276- 1-276-360).

  In the present embodiment, the coordinate conversion circuit 272 performs coordinate conversion on the target image data 275 for performing affine conversion of the image. Specifically, the coordinate conversion circuit 272 performs coordinate conversion for rotating the image on the target image data 275. As a result, the coordinate conversion circuit 272 rotates the target image data 275, and the rotated image data is obtained as the converted image data 276. Here, the rotation of the image means rotation of the subject shown in the image, and even if the image is rotated, the outer shape of the image does not change. Hereinafter, the rotated image represented by the converted image data 276 may be simply referred to as “rotated image”.

  The coordinate conversion circuit 272 separately performs a plurality of coordinate conversions on the target image data 275 stored in the input frame buffer 271 to generate a plurality of converted image data 276 having different rotation angles. Each time the target image data 275 is written in the input frame buffer 271, the coordinate conversion circuit 272 separately performs a plurality of coordinate conversions on the target image data 275 stored in the input frame buffer 271.

[Configuration of coordinate conversion circuit]
FIG. 23 is a diagram mainly showing the configuration of the coordinate conversion circuit 272, and the image recognition accelerator circuit 249 shown in FIG. 23 is a circuit similar to that shown in FIG. As shown in FIG. 23, the coordinate conversion circuit 272 includes a conversion circuit 281 that performs coordinate conversion, and a control circuit 282. The coordinate conversion circuit 272 according to the present embodiment is configured as hardware that operates without using software, unlike, for example, a configuration in which predetermined processing is performed by executing a program with a CPU.

  As shown in FIG. 23, the memory 274 stores conversion parameters 280 used for coordinate conversion. The conversion parameter 280 includes a plurality of conversion parameters 280 necessary for a plurality of coordinate conversions. The conversion parameter 280 is written from the SRAM 243 to the memory 274 by the host controller 241 as described later.

  The conversion circuit 281 individually performs a plurality of coordinate conversions on one target image data 275 stored in the input frame buffer 271 to generate a plurality of converted image data 276.

  FIG. 24 is a diagram illustrating an example of a state in which the conversion parameter 280 is stored in the memory 274. As shown in FIG. 24, the conversion parameter 280 includes a plurality of conversion parameters (280-1 to 280-360) for performing a plurality of rotations on the image. The conversion parameter 280 illustrated in FIG. 24 is, for example, 360 conversion parameters (280-1 to 280-360) for rotating the image from 1 ° to 360 °.

  In the memory 274, the conversion parameter 280 having a smaller rotation angle is stored in a storage area having a smaller address. Therefore, when viewing the 360 conversion parameters 280 stored in the memory 274 in ascending order of addresses of the storage areas in which they are stored, the 360 conversion parameters 280 are arranged in the order of the smaller rotation angle.

  The conversion circuit 281 performs coordinate conversion on the target image data 275 based on the conversion parameter 280 stored in the memory 274. As a result, the target image data 275 is subjected to coordinate conversion processing so as to rotate by a rotation angle corresponding to the conversion parameter 280. In the present embodiment, it is assumed that the target image data 275 is converted so as to be rotated clockwise around the center of gravity of the figure represented in the target image data 275, for example.

  The control circuit 282 sequentially reads a plurality of conversion parameters 280 from the memory 274 and provides the conversion parameters 280 to the conversion circuit 281. Thus, the conversion circuit 281 is sequentially input with a plurality of conversion parameters 280 stored in the memory 274 by the operation of the control circuit 282, and the conversion circuit 281 is input each time the conversion parameter 280 is input. Based on the conversion parameter 280, the target image data 275 of the input frame buffer 271 is rotated, and the converted image data 276 obtained thereby is output to the image processing circuit 273.

  The control circuit 282 also has a register 283. The register 283 has a specification for specifying a plurality of conversion parameters 280 used in the conversion circuit 281 among the conversion parameters 280 (360 conversion parameters (280-1 to 280-360 in the example of FIG. 24)). Information 290 is stored. The control circuit 282 sequentially reads the conversion parameters 280 from the memory 274 based on the specific information 290 in the register 283. The specific information 290 is set in the register 283 by the host controller 241 as described later.

  FIG. 25 is a diagram illustrating an example of the specific information 290. As illustrated in FIG. 25, the specific information 290 includes, for example, a use parameter number 291, a use start position 292, and a use interval 293. In the present embodiment, as described above, the coordinate conversion circuit 272 performs coordinate conversion of the target image data 275 sequentially and continuously based on a plurality of conversion parameters 280 that are sequentially input. In addition, the conversion parameters 280 input in this way are provided in the order of, for example, those with a small rotation angle (for performing coordinate conversion).

  The number of used parameters 291 indicates the number of conversion parameters 280 used in the coordinate conversion circuit 272 for one target image data 275. In the present embodiment, since one conversion parameter 280 is used for the target image data 275 and one coordinate conversion is performed, the number of used parameters 291 indicates the number of coordinate conversions for one target image data 275. It can be said that it shows. When the number of used parameters 291 indicates, for example, “180”, the conversion circuit 281 individually performs 180 coordinate conversions on one target image data 275, and 180 converted image data having different rotation angles. 276 is continuously generated.

  The use start position 292 indicates the storage position of the conversion parameter 280 to be used first, that is, the address (in the storage area of the memory 274) where the conversion parameter 280 to be used first is stored. In the example of FIG. 25, when the use start position 292 indicates “0001h”, for example, the conversion parameter (280-2) for rotating the target image data 275 by 2 ° is used first.

  The use interval 293 indicates how many conversion parameters 280 are used apart from the conversion parameter 280 used in the previous coordinate conversion among the plurality of conversion parameters 280 arranged in order of the small rotation angle when performing coordinate conversion. Show. For example, when the use interval 293 indicates “2”, when the coordinate conversion is performed, the conversion parameter 280 used in the previous coordinate conversion (for example, the conversion parameter 280 − for rotating the target image data 275 by 2 °) is used. A conversion parameter 280 (for example, a conversion parameter 280-4 for rotating the target image data 275 by 4 °) separated by 2 from 2) is used.

  As described above, when one target image data 275 stored in the input frame buffer 271 is rotated by 2 ° from 2 ° to 360 °, the use parameter number 291 is “180” and the use start position 292 is “0001h”. ”And the use interval 293 becomes“ 2 ”. In this case, the control circuit 282 reads from the memory 274 a conversion parameter 280-2 with a rotation angle of 2 °, a conversion parameter 280-4 with a rotation angle of 4 °, a conversion parameter 280-6 with a rotation angle of 6 °,. Conversion parameters 280 to 358 with a rotation angle of 358 ° and conversion parameters 280 to 360 with a rotation angle of 360 ° are sequentially read out and sequentially input to the conversion circuit 281. Thereby, in the conversion circuit 281, as shown in FIG. 26, 180 post-conversion image data 276 (276-1, 276-2, 276-3,... 276-179, 276) whose rotation angles are different by 2 °. -180) are generated sequentially.

  In addition, in the example of FIG. 25, if “360” is set in the number of used parameters 291, “0000h” is set in the use start position 292, and “1” is set in the use interval 293, the data is stored in the input frame buffer 271. The single target image data 275 is rotated by 1 ° from 1 ° to 360 °, and 360-converted image data 276 is generated.

  Also, the number of use parameters 291 is set to “36”, the use start position 292 is set to the address of the storage area where the conversion parameter 280 having a rotation angle of 10 ° is stored, and the use interval 293 is set to “10”. Then, one target image data 275 stored in the input frame buffer 271 is rotated by 10 ° from 10 ° to 360 °, and 36 converted image data 276 are generated.

  Also, the use parameter number 291 is set to “18”, the use start position 292 is set to the address of the storage area in which the conversion parameter 280 having a rotation angle of 270 ° is stored, and the use interval 293 is set to “5”. Then, one target image data 275 stored in the input frame buffer 271 is rotated by 5 ° from 270 ° to 360 °, and 18 converted image data 276 is generated.

  The conversion circuit 281 outputs the converted image data 276 one by one to the image processing circuit 273. Also, the conversion circuit 281 outputs a plurality of pixels constituting the converted image data 276 to the image processing circuit 273 in units of a predetermined number of pixels or one pixel at a time (every time the pixel is generated). be able to.

  As described above, in the coordinate conversion circuit 272, since the conversion parameter 280 is specified by the specification information 290, it is possible to determine what kind of coordinate conversion is to be performed by the coordinate conversion circuit 272 by the specification information 290. .

  Further, since the conversion parameter 280 is specified by the specific information 290, the control LSI 234 and the medal selector 201 make the specific information 290 used by the coordinate conversion circuit 272 different, so that a plurality of control LSIs 234 and medal selectors 201 Different coordinate transformations can be executed between the two.

  Further, a plurality of specific information 290 may be used in one control LSI 234 or medal selector 201. In this case, the coordinate conversion circuit 272 uses the first specifying information 290-1 when performing coordinate conversion on certain target image data 275, and performs coordinate conversion on other target image data 275 ′. The second specific information 290-2 different from the first specific information 290-1 is used. Accordingly, the coordinate conversion circuit 272 can perform different coordinate conversion for each target image data.

  In the present embodiment, the specific information 290 is configured to include the number of used parameters 291, the use start position 292, and the use interval 293, but some information can be omitted (for example, If the number of conversion parameters 280 stored in the memory 274 is known, the number of used parameters 291 can be omitted).

[Example of conversion parameters]
In the coordinate conversion of the target image data 275, the pixel at the coordinate CZ corresponding to the certain coordinate Z in the target image data 275 is adopted as the pixel at the certain coordinate Z in the converted image data 276. In the target image data 275, when there is no pixel at the coordinate CZ corresponding to the coordinate Z in the converted image data 276, the pixel data at the corresponding coordinate CZ includes a plurality of pixels around the corresponding coordinate CZ. Is obtained by interpolation using pixel data of a plurality of pixels existing at the coordinates PCZ. For example, bilinear interpolation or bicubic interpolation is used for the pixel interpolation.

  FIG. 27 is a diagram for explaining an example of coordinate conversion by the conversion parameter 280. In the present embodiment, the conversion parameter 280 includes an image represented by the target image data 275 corresponding to the coordinates A1, B1, C1, and D1 of the four corner pixels in the image represented by the converted image data 276. 4 coordinates A0, B0, C0 and D0 are included.

  When the conversion parameter 280 is input, the conversion circuit 281 receives the coordinates of a plurality of pixels constituting the post-conversion image data 276 based on the four coordinates A0, B0, C0, and D0 included in the input conversion parameter 280. A plurality of coordinates in the target image data 275 respectively corresponding to are obtained. Then, the conversion circuit 281 determines pixel data at each of the plurality of coordinates obtained with respect to the target image data 275 based on the pixel data of the plurality of pixels constituting the target image data 275. At this time, pixel interpolation is used as necessary. Thereafter, the conversion circuit 281 employs pixel data at corresponding coordinates in the target image data 275 as pixel data at each coordinate in the converted image data 276. As a result, the conversion circuit 281 rotates the image represented by the target image data 275 based on the input conversion parameter 280 to generate a rotated image.

  Note that image distortion such as barrel distortion included in the target image data 275 can be corrected by performing predetermined coordinate transformation on the target image data 275. Therefore, a conversion parameter 280 corresponding to both the coordinate conversion for rotating the image and the coordinate conversion for performing distortion correction is stored in the memory 274 as the conversion parameter 280, and the coordinate conversion circuit 272 is based on the conversion parameter 280. Thus, image rotation and distortion correction may be performed on the target image data 275 at the same time. Patent Document 2 and Patent Document 3 described above disclose barrel distortion correction techniques.

[Operation and configuration of image processing circuit]
Here, the outline of the operation of the image processing circuit 273 will be described first, and then the configuration and detailed operation of the image processing circuit 273 will be described.

[Overview of image processing circuit operation]
As shown in FIG. 28, the image processing circuit 273 synthesizes a plurality of converted image data 276 generated by the coordinate conversion circuit 272, and the processed image data 277 obtained thereby is output to the SRAM 243 (DMA) as output image data. Output). The image processing circuit 273 has a frame memory capable of storing image data for one frame, and generates processed image data 277 using the frame memory.

  FIG. 29 is a diagram for explaining the outline of the operation of the image processing circuit 273. The image processing circuit 273 generates processed image data 277 (processed image data 277- (N-1) shown in FIG. 29) by sequentially integrating the N converted image data 276 '.

  As shown in FIG. 29, the image processing circuit 273 generates the converted image data 276-1 first generated by the conversion circuit 281 (for example, the converted image data 276-1 having a rotation angle of 2 ° in the example of FIG. 26). Are stored in the frame memory.

  Next, the image processing circuit 273 converts the converted image data 276-2 generated second by the conversion circuit 281 (for example, corresponds to the converted image data 276-2 having a rotation angle of 4 ° in the example of FIG. 26). Is added to the first converted image data 276-1 in the frame memory to generate one-time processed image data 277-1. Here, the image processing circuit 273 stores the once-processed image data 277-1 in the frame memory.

  Next, the image processing circuit 273 converts the converted image data 276-3 generated third by the conversion circuit 281 (for example, corresponds to the converted image data 276-3 having a rotation angle of 6 ° in the example of FIG. 26). Are added to the once processed image data 277-1 in the frame memory to generate twice processed image data 277-2. Here, the image processing circuit 273 stores the twice-processed image data 277-2 in the frame memory.

  Thereafter, the image processing circuit 273 repeats the same operation, and the converted image data 276-N finally generated by the conversion circuit 281 (for example, the converted image data 276-180 having a rotation angle of 360 ° in the example of FIG. 26). Is added to (N-2) -time processed image data 277- (N-2) in the frame memory to generate (N-1) -time processed image data 277- (N-1). . The (N-1) -time processed image data 277- (N-1) is processed image data 277. The image processing circuit 273 stores the processed image data 277 in the frame memory. Thereafter, the processed image data 277 in the frame memory is output from the frame memory to the SRAM 243 by DMA transfer under the control of the DMAC 252.

[Configuration of image processing circuit]
FIG. 30 is a diagram showing the configuration of the image processing circuit 273. As illustrated in FIG. 30, the image processing circuit 273 includes a frame memory 309, a storage control unit 300, an addition processing unit 305, a write buffer 306, a read buffer 307, and an output control unit 308. The image processing circuit 273 in the present embodiment is hardware that operates without using software, unlike, for example, a configuration in which predetermined processing is performed by executing a program by a CPU. Therefore, the storage control unit 300 can be called a storage control circuit, the addition processing unit 305 can be called an addition processing circuit, and the output control unit 308 can be called an output control circuit. The image processing circuit 273 is a kind of data processing device that processes image data.

  The frame memory 309 is a kind of storage circuit, and is composed of, for example, an SRAM. The frame memory 309 can store image data for one frame (one frame), for example. The frame memory 309 may be configured to store image data for a plurality of frames.

  The output control unit 308 inputs data read from the frame memory 309, and further controls to output the data to the SRAM 243 (by DMA transfer). Further, the output control unit 308 can be configured to have, as operation modes, a DMA output mode that outputs input data by DMA transfer and a non-DMA output mode that outputs input data without DMA transfer. . In this embodiment, the output control unit 308 basically operates in the non-DMA output mode, and operates in the DMA output mode only when output target data is read from the frame memory 309. As a result, the output target data read from the frame memory 309 is output from the output control unit 308 by DMA transfer.

  The storage control unit 300 controls the frame memory 309, the write buffer 306, the read buffer 307, and the output control unit 308. When the storage control unit 300 controls the frame memory 309, data is written to the frame memory 309 or data is read from the frame memory 309. The output control unit 308 controls the output by DMA transfer for the data read from the frame memory 309 according to the control by the storage control unit 300. The storage control unit 300 will be described in detail later.

  The addition processing unit 305 adds the converted image data generated by the conversion circuit 281 to the addition target image read from the frame memory 309 under the control of the storage control unit 300. For example, as shown in FIG. 29, the addition target image for the second converted image data 276-2 is the first converted image data 276-1, and the mth (m is a variable, 3 ≦ m ≦ The image to be added for the converted image data 276-m of (N) is (m-2) times processed image data 277- (m-2).

  Here, one of the two image data to be added is referred to as “first image data”, and the other is referred to as “second image data”. Each of the plurality of pixel data constituting the first image data is referred to as “first pixel data”, and each of the plurality of pixel data constituting the second image data is referred to as “second pixel data”.

  For each of the plurality of first pixel data constituting the first image data, the addition processing unit 305 performs the first processing at the same position (coordinates) as the first pixel data in the first pixel data and the second image data. By adding the two pixel data, the first image data and the second image data are added.

  In the present embodiment, the coordinate conversion circuit 272 outputs a plurality of pixel data constituting the image data of the converted image data 276 one pixel at a time as described above. When the pixel data of the first converted image data 276 is input for one pixel, the addition processing unit 305 writes the input pixel data as it is in the write buffer 306 without performing addition processing. For example, the write buffer 306 can store pixel data for four pixels. When the pixel data for four pixels is accumulated in the write buffer 306, the pixel data for four pixels in the write buffer 306 is written into the frame memory 309 at a time by the control of the frame memory 309 by the storage control unit 300. By repeating such writing processing, pixel data is repeatedly written into the frame memory 309 in units of four pixels.

  In the frame memory 309, the pixel data for four pixels in the write buffer 306 is stored in the frame memory 309 and written into the storage area of the same address of the read original image data. When the data in the write buffer 306 is written into the frame memory 309, the written data is erased from the write buffer 306. As described above, when image data after image processing is written in the frame memory 309, the image data is erased from the write buffer 306, so that the image data is written from the write request output unit 302 immediately after the image data is written. As a result, the image data can be efficiently written to the write buffer 306 sequentially.

  Pixel data is read from the frame memory 309 in units of four pixels by the control of the frame memory 309 by the storage controller 300. That is, pixel data for four pixels is read from the frame memory 309 by one read access to the frame memory 309. Pixel data for four pixels read from the frame memory 309 at a time is written into the read buffer 307.

  When the pixel data input from the coordinate conversion circuit 272 is the pixel data of the converted image data 276-L of the Lth (L is a variable and 2 ≦ L ≦ N), the addition processing unit 305 receives from the read buffer 307. Read pixel data to be added. Then, the addition processing unit 305 adds the input pixel data to the pixel data read from the read buffer 307. As a result, the addition processing unit 305 obtains pixel data of (L-1) -time processed image data 277- (L-1).

  The addition processing unit 305 stores the pixel data of (L−1) -time processed image data 277-(L−1) in the write buffer 306. Pixel data in the write buffer 306 is stored in the frame memory 309. The addition processing unit 305 performs the same processing every time pixel data is input from the coordinate conversion circuit 272. As a result, the frame memory 309 stores the image data of the processed image data 277 (that is, (N-1) -time processed image data 277- (N-1)). When data is read from the read buffer 307, the read data is erased from the read buffer 307. As described above, when image data to be subjected to image processing is read for image processing, the image data is erased from the read buffer 307, so that the first data is read immediately after the image data is read. Requests from the read request output unit 301 can be made, and as a result, efficient reading of image data to the read buffer 307 is sequentially performed.

  As described above, the addition processing unit 305 adds the pixel data of the L-th converted image data 276-L to the pixel data to be added in the read buffer 307, and performs (L-1) times processing. Pixel data of the image data 277- (L-1) is generated.

  For example, when the pixel data of the second converted image data 276-2 is input from the coordinate conversion circuit 272, the pixel data to be added with respect to the input pixel data is the first converted image data 276-1. The pixel data at the same position as the input pixel data in FIG. When the pixel data of the third converted image data 276-3 is input from the coordinate conversion circuit 272, the pixel data to be added for the input pixel data is the one-time processed image data 277-1. The pixel data at the same position as the input pixel data. The pixel data to be added is stored in the read buffer 307 when the input pixel data is provided to the addition processing unit 305 by control of the frame memory 309 by the storage control unit 300.

  In the present embodiment, the frame memory 309 is, for example, a 1-port memory. Therefore, data cannot be written to the frame memory 309 when data is being read from the frame memory 309.

  Further, the image processing circuit 273 performs read modify write on the frame memory 309. For example, after pixel data stored in a storage area at a certain address in the frame memory 309 is read from the frame memory 309, an addition process is performed in the addition processing unit 305, and (L-1) times processed image data 277- (L−1) pixel data is generated and stored in the write buffer 306. Thereafter, the pixel data thus subjected to addition processing is written back from the write buffer 306 to the storage area of the same address in the frame memory 309.

  In other words, when the pixel data of the processed image data stored in the write buffer 306 is written in the frame memory 309, the pixel data of the processed image data is stored in the frame memory 309 where the pixel data to be added is stored. Is stored at the same position.

  In the present embodiment, pixel data for four pixels is read from the frame memory 309 at a time and stored in the read buffer 307. Also, the pixel data for four pixels of the write buffer 306 stored by the addition process is written to the frame memory 309 at a time.

  In the image processing circuit 273, pixel data for four pixels stored in a storage area at a certain address in the frame memory 309 is read from the frame memory 309, temporarily stored in the read buffer 307, and then added. Addition processing is executed by the unit 305. The pixel data for the four pixels subjected to the addition processing is temporarily stored in the write buffer 306 and then written back to the frame memory 309 (a storage area having the same address as the certain address).

  As described above, in this embodiment, the frame memory 309 is a one-port memory, and read-modify-write is performed on the frame memory 309. Therefore, with such a configuration, the circuit scale of the frame memory 309 can be reduced, and as a result, the circuit scale of the image processing circuit 273 can be reduced.

  The final processed image data 277 stored in the frame memory 309 is output from the output control unit 308 to the SRAM 243 by DMA transfer. For example, when the pixel data of the processed image data 277 is read from the frame memory 309 by the control of the frame memory 309 by the storage control unit 300, the output control unit 308 outputs the read pixel data to the SRAM 243 by DMA transfer. To do. Since the pixel data for four pixels is read from the frame memory 309 at a time, the output control unit 308 outputs the processed image data 277 read from the frame memory 309 in units of four pixels. The pixel data of the processed image data 277 read from the frame memory 309 is not stored in the read buffer 307 due to control of the read buffer 307 by the storage control unit 300.

  When the DMAC 252 has a buffer, the DMAC 252 temporarily stores the pixel data input from the image processing circuit 273 in the buffer. The buffer can store pixel data for a plurality of pixels. The DMAC 252 controls to transfer pixel data for a plurality of pixels in the buffer to the SRAM 243 when the buffer is full. Thereby, the processed image data 277 generated by the image recognition accelerator circuit 249 is stored in the SRAM 243. In the DMAC 252, when the data in the buffer is transferred to the SRAM 243, the transferred data is erased from the buffer. The DMAC 252 can also be configured to transfer the buffer data to the SRAM 243 when the data amount of the data in the buffer exceeds a predetermined value.

[Detailed Operation in Storage Control Unit of Image Processing Circuit]
The storage control unit 300 executes a first readout process for reading out the pixel data to be added processed by the addition processing unit 305 from the frame memory 309. Further, the storage control unit 300 performs a writing process for writing the pixel data of the processed image data 277 generated by the addition processing unit 305 into the frame memory 309. It can be said that the pixel data of the processed image data 277 is pixel data subjected to addition processing by the addition processing unit 305. Then, the storage control unit 300 executes a second reading process for reading out the pixel data of the processed image data 277, which is the final output target data, from the frame memory 309.

  The storage control unit 300 includes a first read request output unit 301, a write request output unit 302, a second read request output unit 303, and an arbitration unit 304.

  The first read request output unit 301 outputs a first read request that is an execution request for the first read process. The write request output unit 302 outputs a write request that is an execution request for the write request. The second read request output unit 303 outputs a second read request that is an execution request for the second read process.

  The output of the first read request by the first read request output unit 301 is, for example, outputting a first read request signal indicating the first read request. The first read request signal includes an address of a storage area in the frame memory 309 where pixel data to be read is stored.

  The output of the write request by the write request output unit 302 is, for example, outputting a write request signal indicating the write request. The write request signal includes the address of the storage area in the frame memory 309 where the pixel data to be written is written.

  The output of the second read request by the second read request output unit 303 is to output a second read request signal indicating the second read request. The second read request signal includes the address of the storage area in the frame memory 309 where the pixel data to be read is stored.

  The first read request output unit 301, the write request output unit 302, and the second read request output unit 303 output the first read request, the write request, and the second read request based on mutually independent criteria, respectively. To do.

  For example, when the read buffer 307 is empty, the first read request output unit 301 outputs a first read request (first read request signal). In this way, the first read request output unit 301 outputs a request to read image data to be subjected to image processing from the frame memory 309 when the read buffer 307 is empty, so that the circuit scale of the read buffer 307 is increased. Further, the read timing of the image data is determined by an independent and effective standard.

  When a predetermined amount of data is written in the write buffer 306 (for example, when the data is full, that is, when the same amount of data as the capacity of the write buffer 306 is written), the write request output unit 302 A write request (write request signal) is output. Thus, the write request output unit 302 outputs a request to write image data after image processing from the write buffer 306 to the frame memory 309 when the write buffer 306 is full, for example. The circuit scale of 306 can be reduced, and the writing timing of the image data is determined by an independent and effective reference.

  The second read request output unit 303 reads out the processed image data 277 stored in the frame memory 309 and transfers the data to the SRAM 243 under the control of the DMAC 252 at a predetermined timing. Signal).

  Further, when the DMAC 252 includes a buffer, the second read request output unit 303 outputs a second read request (second read request signal) based on, for example, the buffer availability of the DMAC 252. For example, the second read request output unit 303 outputs a second read request when the buffer is empty. Alternatively, the second read request output unit 303 outputs a second read request when the free space of the buffer is equal to or greater than a predetermined amount (for example, when the amount of data of pixel data for four pixels is equal to or greater). In other words, the second read request output unit 303 outputs a second read request when the amount of data that can be stored in the buffer is greater than or equal to a predetermined amount.

  However, if output target data, that is, processed image data 277 is not stored in the frame memory 309, the storage control unit 300 cannot read the output target data from the frame memory 309. Therefore, the second read request output unit 303 outputs the second read request when the pixel data of the processed image data 277 is stored in the frame memory 309 for four pixels or more and the buffer is empty. To do. Alternatively, the second read request output unit 303 is the case where the pixel data of the processed image data 277 is stored in the frame memory 309 for four pixels or more, and the buffer free space is a predetermined amount or more. 2 Read request is output.

  In this manner, the first read request output unit 301, the write request output unit 302, and the second read request output unit 303 are based on the mutually independent criteria, and the first read request, the write request, and the second read Since each request is output, at least two requests of the first read request, the write request, and the second read request may conflict. That is, a request may be simultaneously output from at least two of the first read request output unit 301, the write request output unit 302, and the second read request output unit 303.

  Therefore, the storage control unit 300 is provided with an arbitration unit 304 that arbitrates at least two conflicting requests when at least two requests of the first read request, the write request, and the second read request conflict. Yes.

  When the first read request, the write request, and the second read request do not conflict, the arbitrating unit 304 performs processing corresponding to the input request on the frame memory 309. On the other hand, when at least two requests of the first read request, the write request, and the second read request conflict, the arbitrating unit 304 arbitrates the at least two conflicting requests, thereby adjusting the two requests. Select one. Then, the arbitrating unit 304 performs processing on the frame memory 309 according to the selected request.

  In the present embodiment, each of the first read request, the write request, and the second read request (or each of the first read request output unit 301, the write request output unit 302, and the second read request output unit 303). Processing priority is assigned to the output unit). For example, the highest priority is assigned to the first read request, the second highest priority is assigned to the write request, and the lowest priority is assigned to the second read request. Then, the arbitrating unit 304 arbitrates the request based on the priority of the conflicting request. In the arbitrating unit 304, a request having the highest priority is selected from the conflicting requests, and processing according to the selected request is performed. Therefore, for example, when the three requests of the first read request, the write request, and the second read request conflict, the first read request is selected. Further, when the two requests, the write request and the second read request, conflict, the write request is selected.

  When the arbitration unit 304 performs processing in response to the first read request, the arbitration unit 304 outputs the address included in the first read request signal input from the first read request output unit 301 and the read signal to the frame memory 309. To do. As a result, the pixel data for four pixels is read from the storage area of the address included in the first read request signal in the frame memory 309, and the read pixel data is written to the read buffer 307. When the arbitration unit 304 performs processing in response to the first read request, the data read from the frame memory 309 is output from the output control unit 308 because the output control unit 308 operates in the non-DMA output mode. It is not output to the SRAM 243 or the like.

  The arbitration unit 304 reads out the pixel data for four pixels from the write buffer 306 and outputs the pixel data to the frame memory 309 when performing processing according to the write request, and also receives the write input from the write request output unit 302. The address and write signal included in the write request signal are output to the frame memory 309. As a result, the pixel data for four pixels output from the write buffer 306 is written to the storage area of the address included in the write request signal in the frame memory 309.

  When the arbitration unit 304 performs processing in response to the second read request, the arbitration unit 304 outputs the address included in the second read request signal input from the second read request output unit 303 and the read signal to the frame memory 309. At the same time, the operation mode of the output control unit 308 is changed from the non-DMA output mode to the DMA output mode. Thereby, the pixel data for four pixels is read from the storage area of the address included in the second read request signal in the frame memory 309, and the read pixel data for four pixels is read from the output control unit 308 from the DMAC 252. Is output to the SRAM 243 under the control of.

  In the above example, the processing time in the coordinate conversion circuit 272 is relatively long, and the pixel data of the converted image data 276 cannot be obtained immediately in the coordinate conversion circuit 272. As a result, the pixel data of the processed image data 277 In order to improve the processing speed of the entire control LSI 234, the priority of the first read request and the write request necessary for generating the pixel data of the processed image data 277 is set to the second priority. The priority is higher than the priority of the read request. However, the method of assigning priority to the first read request, the write request, and the second read request is not limited to this.

  For example, when the processed image data 277 of the frame memory 309 is DMA-transferred to the SRAM 243 under the control of the DMAC 252, the bus utilization rate of the control LSI 234 is always high, and it is difficult to transfer data to the SRAM 243. When the transfer rate of the processed image data 277 does not increase, output target data (pixel data of the processed image data 277) is easily stored in the frame memory 309. In this case, if the priority of the first read request and the write request is higher than the priority of the second read request, the processed image data 277 stored in the frame memory 309 is not output from the image processing circuit 273 indefinitely. there is a possibility. Therefore, in such a case, the priority of the second read request for reading the processed image data 277 from the frame memory 309 is set higher than the priority of the first read request and the write request. The processing speed of the entire control LSI 234 can be improved.

  In addition, for example, when the DMAC 252 includes a buffer, and the bus usage rate of the control LSI 234 is always high, it is difficult to transfer data from the DMAC 252 to the SRAM 243, and as a result, it is difficult for the DMAC 252 buffer to be empty. This is a situation where the output target data (pixel data of the processed image data 277) is likely to be accumulated in the frame memory 309. In this case, if the priority of the first read request and the write request is higher than the priority of the second read request, the processed image data 277 stored in the frame memory 309 is not output from the image processing circuit 273 indefinitely. there is a possibility. Therefore, in such a case, the priority of the second read request for reading the processed image data 277 from the frame memory 309 is set higher than the priority of the first read request and the write request. The processing speed of the entire control LSI 234 can be improved.

  As described above, in the storage control unit 300, when at least two requests of the first read request, the write request, and the second read request compete, the at least two requests are arbitrated. Therefore, the first read request output unit 301, the write request output unit 302, and the second read request output unit 303 can operate independently of each other. Therefore, it is possible to suppress processing at a specific output unit among the first read request output unit 301, the write request output unit 302, and the second read request output unit 303 from becoming a bottleneck. As a result, the processing speed of the entire control LSI 234 can be improved.

  The processing priority can be changed. For example, the control LSI 234 may be configured so that the processing priority can be changed by a user operation or automatically. Further, the image processing circuit 273 may change the processing priority according to the operation status of the control LSI 234. For example, a bus usage rate calculation circuit for determining the bus usage rate is provided in the control LSI 234 so that the image processing circuit 273 changes the processing priority based on the bus usage rate obtained by the bus usage rate calculation circuit. It may be configured. Specifically, when the bus usage rate is greater than a predetermined value, the priority of the second read request is set higher than the priority of the first read request and the write request, and the bus usage rate is If the value is equal to or less than the predetermined value, the priority of the first read request and the write request is set higher than the priority of the second read request. In this way, the processing speed of the entire image processing circuit 273 can be further improved by dynamically changing the processing priority.

[Flow of regular medal discrimination process by control LSI 234]
Next, referring to FIG. 31 to FIG. 33, a process performed by the control LSI 234 for determining whether or not the object moving on the medal rail 210 is a regular medal (hereinafter referred to as “regular medal determination process”). Explain).

  FIGS. 31 and 32 are diagrams for explaining the regular medal discrimination process of the control LSI 234. FIG. 31 and FIG. 32 show the relationship of processing in each device constituting the control LSI 234 in time series, and the relatively thick line portion of the vertical line extending below each device name indicates that the device is It shows that the various processes described above are being performed. A broken line arrow extending from a line corresponding to each device toward a vertical line extending below “IN” in the host controller indicates an interrupt signal output from each device to the host controller 241.

  A broken line arrow extending from a vertical line extending below “OUT” in the host controller toward a line corresponding to each device indicates a signal output from the host controller 241 to each device. In addition, a solid arrow between a vertical line extending below “IN” and a vertical line extending below “OUT” in the host controller indicates an interrupt signal detected by the host controller 241 and the host controller 241. The correspondence relationship with the output signal is shown.

  Note that FIG. 31 shows an extraction process of the first medal regarding the regular medal determination process when six medals are continuously inserted into the medal insertion slot 21 (see FIG. 2). Shows the entire regular medal discrimination process when 6 medals are inserted consecutively (including the discrimination process for the first medal). In addition, in order to clarify the number of medals related to the signal, a number indicating the order of insertion of medals is attached to the head of the code attached to each signal. For example, a VSYNC interrupt signal output to the host controller 241 from an ISP circuit 245, which will be described later, related to the first medal is labeled with “1IH”, and the same VSYNC interrupt related to the second medal is assigned. The signal was labeled “2IH”.

  First, when the CMOS image sensor 232 (see FIG. 17) images an object moving on the medal rail 210 (in this example, the first medal) and outputs the image data to the control LSI 234, the ISP circuit 245 causes the ISI circuit Image data is acquired (received) via 251 and a VSYNC (Vertical Synchronization) interrupt signal is output to the host controller 241 (1IH). Further, the ISP circuit 245 performs conversion processing for converting the RGB Bayer image into various formats. Then, the converted image data and the hue, saturation, and luminance data relating to the image data are output to the SRAM 243, the medal count circuit 246, and the color recognition circuit 247. The detailed description of the conversion process has been described above, and will not be repeated.

  When receiving data from the ISP circuit 245, the color recognition circuit 247 performs color determination processing, stores the determination result in the SRAM 243, and outputs a color determination interrupt signal to the host controller 241 (1CH). Note that the detailed description of the color determination process has been described above, and will be omitted.

  When the medal count circuit 246 receives data from the ISP circuit 245, the medal count circuit 246 performs count processing, stores the determination result in the SRAM 243, and outputs a medal count interrupt signal to the host controller 241 (1MH). Note that the detailed description of the count process has been described above, and is therefore omitted.

  When the host controller 241 detects the color determination interrupt signal, the host controller 241 acquires the determination result of the color determination processing from the SRAM 243 and outputs it to the allocation PORT of the GPIO 250 (1HG1). That is, the host controller 241 outputs the determination result of the color determination process to the main control board 71 (main control circuit 91) via the GPIO 250.

  When the host controller 241 detects the count interrupt signal, the host controller 241 acquires the determination result of the count process from the SRAM 243 and outputs it to the allocation PORT of the GPIO 250 (1HG2). That is, the host controller 241 outputs the determination result of the count process to the main control board 71 (main control circuit 91) via the GPIO 250. When the determination result of the counting process is “medal has passed”, the main control circuit 91 sets the value of the inserted number counter, which is a counter provided for the main CPU 93 to count the number of inserted medals. Add one. When the value of the inserted number counter is the maximum value (for example, 3), 1 is added to the value of a credit counter that is a counter provided for the main CPU 93 to count the number of credited medals. When the credit counter is the maximum value (for example, 50), the main control circuit 91 sets the medal solenoid 208 of the medal selector 201 to the OFF state. As a result, the select plate 207 is positioned at the “discharge position”, and medals inserted after the credit counter reaches the maximum value are guided to the medal chute 202 and discharged from the medal payout opening 32 to the medal tray unit 34. In the present embodiment, when the value of the insertion number counter is a specified value (for example, 2 or 3), when the start lever is operated, the main CPU 93 performs the above-described internal lottery process.

  When the image data converted by the ISP circuit 245 is stored in the SRAM 243, the fish-eye correction scaler circuit 248 performs fish-eye correction processing, stores the generated reduced image data in the SRAM 243, and causes the host controller 241 to reduce the reduction completion rate. Send a signal (1SH). Since the detailed description of the fisheye correction process has been described above, it will be omitted.

  When the host controller 241 detects the reduction end interrupt signal, the host controller 241 refers to the SRAM 243, and the determination result of the count process is “the medal has passed”, and the determination result of the color determination process is “matches the color of the regular medal” On the condition that it is “Yes”, the image recognition DSP circuit 242 is instructed to start preprocessing (1HD).

  The image recognition DSP circuit 242 performs preprocessing according to an instruction from the host controller 241, stores the edge image data in the SRAM 243, and outputs a preprocessing end interrupt signal to the host controller 241 (1DH1). Note that the detailed description of the pre-processing has been described above and is omitted. Further, the image recognition DSP circuit 242 of the present embodiment acquires reduced image data from the SRAM 243 by DMA transfer, and further stores the edge image data generated as a result of the preprocessing in the SRAM 243 by DMA transfer. Compared with the same circuit that does not use DMA transfer, the processing time of the preprocessing is shortened.

  When the host controller 241 detects the preprocessing completion interrupt signal, the host controller 241 instructs the image recognition accelerator circuit 249 to start image processing (for example, rotation integration processing here) (1HA).

  The image recognition accelerator circuit 249 performs image processing in accordance with an instruction from the host controller 241, stores the processed image data in the SRAM 243, and outputs an image processing end interrupt signal to the image recognition DSP circuit 242 (1AD). Note that the detailed description of the rotation integration process, which is an example of the image processing, has been described above, and is omitted here. Further, the image recognition accelerator circuit 249 according to the present embodiment acquires edge image data from the SRAM 243 by DMA transfer, and stores the generated processed image data in the SRAM 243 by DMA transfer. Compared with the circuit, the processing time of the image processing is shortened.

  When the image recognition DSP circuit 242 detects the image processing end interrupt signal, the image recognition DSP circuit 242 acquires the processed image data stored in the SRAM 243, performs a marking determination process, and stores the determination result in the SRAM 243. Then, the image recognition DSP circuit 242 outputs a marking determination end interrupt signal to the host controller 241 (1DH2). Further, the image recognition DSP circuit 242 of the present embodiment acquires the processed image data created by the image processing from the SRAM 243 by, for example, DMA transfer. Processing time of processing is shortened.

  When the host controller 241 detects the marking determination end interrupt signal, the host controller 241 acquires the determination result of the marking determination process stored in the SRAM 243 and outputs it to the GPIO allocation PORT (1HG3). That is, the host controller 241 outputs the determination result of the marking determination process to the main control board 71 (main control circuit 91) via the GPIO 250.

  As shown in FIG. 31, in this embodiment, the preprocessing and engraving determination processing by the image recognition DSP circuit 242 and the image processing by the image recognition accelerator circuit 249 are shortened by DMA transfer as described above. It takes a relatively long time. Therefore, when medals are continuously inserted, when the host controller 241 detects a reduction end interrupt signal (1SH or the like), at this time, the image recognition DSP circuit 242 or the image recognition accelerator circuit 249 is processing ( If none of the processing is in progress, control is performed to instruct the image recognition DSP circuit 242 to perform preprocessing and marking determination processing and the image recognition accelerator circuit 249 to start image processing.

  Next, with reference to FIG. 32, the entire regular medal discrimination process when six medals are inserted in succession will be described. FIG. 32 includes all the determination processes related to the first medal shown in FIG.

  In the example shown in FIG. 32, since the regular medal determination process is continuously performed for medals continuously inserted, the reduction end interrupt signals (2SH and 4SH) relating to the second and fourth medals are hosted. When the controller 241 detects, since the image recognition DSP circuit 242 or the image recognition accelerator circuit 249 is being processed (busy state), the host controller 241 instructs the above-described image processing start (preprocessing, image processing, and (Instruction for starting the marking determination process) is not performed. Therefore, for the second and fourth medals, count processing, color determination processing, and fisheye correction processing are performed, but preprocessing, image processing, and marking determination processing are not performed. On the other hand, when the host controller 241 detects the reduction end interrupt signal (3SH) related to the third medal, the image recognition DSP circuit 242 and the image recognition accelerator circuit 249 are not being processed (busy state). Therefore, for the third medal, in addition to the count process, the color determination process, and the fisheye correction process, a pre-process, an image process, and a marking determination process are performed.

  Also, here, the ISP circuit 245 causes the interval between the output of the determination result of the count process by the host controller 241 to the GPIO 250 (1HG2) and the transmission of the preprocessing end interrupt signal by the image recognition DSP circuit 242 (1DH1). The output (2IH) of the VSYNC interrupt signal related to the second medal is generated. However, since the storage area of the SRAM 243 for storing the determination results of various processes (counting process, color determination process, engraving determination process, etc.) related to each medal is individually set, no data overwriting occurs. . Such a situation is the same in the processing of the third and subsequent medals.

  It should be noted that the pre-processing and marking determination processing by the image recognition DSP circuit 242 and the image processing by the image recognition accelerator circuit 249 are further accelerated, so that the counting processing, color determination processing, and marking determination processing are performed for all medals inserted. May be performed.

  Various signals relating to the second, third, fourth, fifth, and sixth medals shown in FIG. 32 (the code starts with “2”, “3”, “4”, “5”) , “6” signals) are the same as the various signals related to the first medal described above (only the first symbol is “1”), which is different only in the first digit, and detailed description thereof is omitted. Note that the processing timing of each device in the regular medal discrimination processing of the control LSI 234 shown in FIG. 32 is merely an example. The regular medal determination process can be performed at various processing timings according to the processing capability, processing content, and processing procedure of each device.

  Next, the flow of image processing by the image recognition accelerator circuit 249 will be described in more detail with reference to FIG.

  FIG. 33 is a diagram showing an operation flow of the host controller 241 and the image recognition accelerator circuit 249, and basically corresponds to a part of the processing of FIG. 32 described above. First, when the power of the pachislot 1 is turned on (although omitted in FIG. 32), the host controller 241 performs initial setting of each circuit including the image recognition accelerator circuit 249 (step S0).

  The image recognition accelerator circuit 249 is provided with various setting registers (not shown). In the initial setting, the host controller 241 sets data in various setting registers of the image recognition accelerator circuit 249. For example, the host controller 241 sets the address of the storage area on the SRAM 243 where the target image data 275 is stored in the first setting register, or the SRAM 243 to which the processed image data 277 obtained by the image recognition accelerator circuit 249 is written. Is set in the second setting register, and the image size of the target image data 275 processed by the image recognition accelerator circuit 249 is set in the third setting register.

  Further, in the initial setting of the image recognition accelerator circuit 249, the host controller 241 sets the conversion parameter 280 in the memory 274 of the image recognition accelerator circuit 249. For example, the host controller 241 reads the conversion parameters 280 from the SRAM 243 and writes these conversion parameters 280 into the memory 274. The host controller 241 may create the conversion parameter 280 at the time of initial setting, and write the created conversion parameter 280 into the memory 274 of the image recognition accelerator circuit 249.

  After the initialization is completed, the host controller 241 instructs the image recognition accelerator circuit 249 to start image processing relating to the first target image data 275 (step S1). In response to this instruction, the signal (1HA) shown in FIG. 32 is transmitted to the image recognition accelerator circuit 249. Here, the host controller 241 sets the specific information 290 used in the image processing regarding the first target image data 275 in the register 283 included in the control circuit 282 of the image recognition accelerator circuit 249.

  When the specific information 290 is set in the register 283, the image recognition accelerator circuit 249 starts with the first target image data 275 from the address (address of the SRAM 243) set in the first setting register based on the control of the DMAC 252. Are read by DMA transfer and written to the input frame buffer 271 (step S1-1). The coordinate conversion circuit 272 reads the conversion parameter 280 to be used first from the memory 274 based on the specific information 290 in the register 283, and the target image data 275 stored in the input frame buffer 271 based on the read conversion parameter 280. For the first time (step S1-1). Thereby, the first post-conversion image data 276-1 is obtained. This first converted image data 276-1 is stored in the frame memory 309 of the image processing circuit 273.

  When the coordinate conversion circuit 272 generates the first post-conversion image data 276-1, the coordinate conversion circuit 272 reads the conversion parameter 280 used second from the memory 274 based on the specific information 290, and inputs the conversion parameter 280 based on the read conversion parameter 280. A second coordinate transformation is performed on the target image data 275 stored in the frame buffer 271 (step S1-2). As a result, second converted image data 276-2 is obtained. On the other hand, the image processing circuit 273 performs image processing for adding the second converted image data 276-2 to the first converted image data 276-1 to generate the once processed image data 277-1. (Step S1-2).

  Here, the coordinate conversion circuit 272 outputs the generated pixel data to the image processing circuit 273 each time the pixel data of the converted image data 276 is generated. Further, when the pixel data is input from the coordinate conversion circuit 272, the image processing circuit 273 adds the input pixel data to the pixel data to be added read from the read buffer 307. Therefore, the image recognition accelerator circuit 249 does not generate the once-processed image data 277-1 after the converted image data 276-2 is generated, but the converted image data 276-in the coordinate conversion circuit 272. 2 generation processing and the generation processing of the once-processed image data 277-1 in the image processing circuit 273 are executed in parallel.

  When generating the second converted image data 276-2, the coordinate conversion circuit 272 reads the conversion parameter 280 used third from the memory 274 based on the specific information 290, and based on the read conversion parameter 280, A third coordinate transformation is performed on the target image data 275 stored in the input frame buffer 271. As a result, third converted image data 276-3 is obtained. On the other hand, the image processing circuit 273 performs image processing for adding the third converted image data 276-3 to the once-processed image data 277-1 to generate twice-processed image data 277-2. .

  Thereafter, the image recognition accelerator circuit 249 operates in the same manner, and the coordinate conversion circuit 272 generates N-th converted image data 276-N (step S1-N). On the other hand, the image processing circuit 273 performs image processing for adding the N-th converted image data 276-N to the (N-2) -time processed image data 277- (N-2), and (N− 1) Generate processed image data 277- (N-1), that is, processed image data 277 (step S1-N). Thereafter, the image processing circuit 273 outputs the processed image data 277 to the SRAM 243 under the control of the DMAC 252 (step S1-N).

  The processed image data 277 is written into the storage area of the address set in the second setting register (step S1-N). As described above, since the first read request output unit 301, the write request output unit 302, and the second read request output unit 303 operate independently of each other, the image processing circuit 273 performs addition in the addition processing unit 305. The process and the output process in the output control unit 308 are executed in parallel. Therefore, the image processing circuit 273 does not output the pixel data of the processed image data 277 after all the pixel data constituting the processed image data 277 is generated, but generates the pixel data of the processed image data 277. The pixel data output process of the processed image data 277 is executed in parallel.

  When the image recognition accelerator circuit 249 finishes writing the processed image data 277 to the SRAM 243, the image recognition accelerator circuit 249 notifies the host controller 241 that the image processing for the first target image data 275 has been completed (step S1). -E). For the completion notification from the image recognition accelerator circuit 249 to the host controller 241, for example, an interrupt function of the host controller 241 is used.

  Upon receiving the completion notification, the host controller 241 instructs the image recognition accelerator circuit 249 regarding the second target image data 275 (step S2). Specifically, the host controller 241 sets specific information 290 used in processing for the second target image data 275 in the register 283 included in the control circuit 282 of the image recognition accelerator circuit 249. The image recognition accelerator circuit 249 operates in the same manner as the processing for the first target image data 275, generates the processed image data 277 based on the second target image data 275, and writes the processed image data 277 to the SRAM 243. Thereafter, the image recognition accelerator circuit 249 performs the same processing on the third and subsequent target image data 275.

  Note that the identification information 290 used in the process for the p-th target image data 275 (p is a variable, p ≧ 2) is specified in the process for the (p−1) -th target image data 275. When the information is the same as the information 290, the host controller 241 that has received the completion notification for the (p−1) th target image data 275 registers the specific information 290 used in the process for the pth target image data 275. Instead of setting 283, the image recognition accelerator circuit 249 may be instructed to start processing on the p-th target image data 275.

  In this embodiment, as shown in FIGS. 31 and 32, when the image recognition accelerator circuit 249 completes image processing related to one target image data 275, the image recognition DSP circuit 242 receives an image processing end interrupt signal. (1AD etc.) is output, and when the image recognition DSP circuit 242 detects the image processing end interrupt signal, the image recognition DSP circuit 242 acquires the processed image data 277 stored in the SRAM 243 and then performs the marking determination process. However, the example shown in FIG. 33 is different from such processing. That is, when the image recognition accelerator circuit 249 finishes the image processing, a completion notification is sent to the host controller 241 (step S1-e). As described above, when the image recognition accelerator circuit 249 finishes the image processing related to one target image data 275, the next processing can be started by various operation patterns.

  As described above, the coordinate conversion circuit 272 continuously performs a plurality of coordinate conversions using one target image data 275 based on a plurality of conversion parameters 280. That is, the coordinate conversion circuit 272 generates a plurality of converted image data 276 from one target image data 275 without exchanging data with the host controller 241 based on the plurality of conversion parameters 280. Therefore, each time the coordinate conversion circuit 272 performs the coordinate conversion, the processing time of the plurality of coordinate conversions can be shortened as compared with the case where the conversion parameter 280 used in the coordinate conversion is received from the host controller 241.

  Further, the coordinate conversion circuit 272 generates a plurality of post-conversion image data 276 from one target image data 275 without exchanging data with the host controller 241 based on the plurality of conversion parameters 280, whereby the host controller The processing load of 241 can be reduced. Further, when the host controller 241 and the image recognition accelerator circuit 249 are connected by a bus as in the present embodiment, it is possible to secure a larger band for the bus.

  Furthermore, in this embodiment, the host controller 241 sets the conversion parameter 280 in the memory 274 of the image recognition accelerator circuit 249 when the image recognition accelerator circuit 249 is initially set. After that, the conversion parameter 280 can be read from the memory 274. Therefore, the coordinate conversion circuit 272 does not need to receive the conversion parameter 280 to be used from the host controller 241 every time the conversion parameter 280 is used, and therefore the processing time in the coordinate conversion circuit 272 can be shortened. .

  Note that the SRAM 243 may include only the conversion parameter 280 used by the image recognition accelerator circuit 249 of the control LSI 234. For example, when the coordinate conversion circuit 272 performs coordinate conversion for rotating every 2 ° from 2 ° to 360 ° for any target image data 275, only the conversion parameter 280 having an even rotation angle is stored. It can be constituted as follows. At this time, the SRAM 243 stores conversion parameters 280 relating to all rotation angles, and the conversion parameters 280 that are actually used when the image recognition accelerator circuit 249 is initially set (that is, the conversion parameters 280 having an even rotation angle). ) Only may be stored in the memory 274.

  Furthermore, a common conversion parameter 280 may be stored in each of the plurality of image recognition accelerator circuits 249 that perform different coordinate conversions on the target image data 275. For example, the first image recognition accelerator circuit 249 performs processing of rotating the target image data 275 by 1 ° from 1 ° to 90 °, and the second image recognition accelerator circuit 249 converts the target image data 275 from 91 ° to 180 °. The third image recognition accelerator circuit 249 performs processing of rotating the target image 110 by 1 ° from 181 ° to 270 °, and the fourth image recognition accelerator circuit 249 When the target image data 275 is rotated by 1 ° from 271 ° to 360 °, each of the first to fourth image recognition accelerator circuits 249 has the same conversion parameter 280 (ie, the above example). Similarly, 360 kinds of conversion parameters 280 for rotating the target image data 275 from 1 ° to 360 °) Remember. As a result, it is not necessary to prepare the conversion parameter 280 for each image recognition accelerator circuit 249 individually, so that it is possible to suppress the erroneous conversion parameter 280 from being stored.

  Here, an example in which a common conversion parameter 280 is stored in a plurality of image recognition accelerator circuits 249 has been shown, but the same applies to a plurality of control LSIs 234 and medal selectors 201 that are respectively incorporated in pachislot 1 (different specifications). The common conversion parameter 280 can be stored.

  In the above example, the image processing circuit 273 outputs the processed image data 277 under the control of the DMAC 252, but the converted image data 276 obtained by the coordinate conversion circuit 272 may be output. In this case, the image processing circuit 273 eliminates the addition processing unit 305, the read buffer 307, and the first read request output unit 301. Then, the pixel data of the post-conversion image data 276 output from the coordinate conversion circuit 272 is temporarily stored in the write buffer 306, and the pixel data of the post-conversion image data 276 stored in the write buffer 306 is written into the frame memory 309. . The pixel data stored in the frame memory 309 is output (DMA transfer) from the output control unit 308 to the SRAM 243 under the control of the DMAC 252.

  Further, the conversion parameter 280 may include a conversion parameter for instructing coordinate conversion other than rotation instead of the parameter for specifying the rotation angle or in addition to the parameter for specifying the rotation angle.

  For example, the conversion parameter 280 may include a conversion parameter for enlargement necessary for coordinate conversion for enlarging an image. In this case, the conversion parameter 280 may include a plurality of conversion parameters 280 necessary for a plurality of coordinate conversions having different enlargement ratios. The coordinate conversion circuit 272 performs coordinate conversion on the target image data 275 based on the conversion parameter 280 relating to such image expansion, thereby expanding the target image data 275 at an expansion rate corresponding to the conversion parameter 280. Can do.

  For example, the coordinate conversion circuit 272 performs coordinate conversion on the target image data 275 based on a conversion parameter 280 that instructs to enlarge an image with an enlargement ratio of 1.1 times, thereby enlarging the image to 1.1 times. The converted image data 276 is obtained. Here, the enlargement of the image means enlargement of the image (subject) represented by the target image data 275, and does not increase the number of pixels in the vertical and horizontal directions of the image.

  When the conversion parameter 280 includes a conversion parameter related to image rotation and a conversion parameter related to image enlargement, the coordinate conversion circuit 272 enlarges the rotated image obtained by rotating the target image data 275 and the target image data 275. An enlarged image obtained by doing so can be generated as post-conversion image data 276. The conversion parameter 280 related to image enlargement is similar to the conversion parameter 280 related to image rotation, for example, the coordinates of four pixels in the target image data 275 corresponding to the four corner pixels in the enlarged image (that is, the mapping source). 4 pixel coordinates).

  Further, the conversion parameter 280 may include a conversion parameter for reduction necessary for coordinate conversion for performing image reduction. In this case, the conversion parameter 280 may include a plurality of conversion parameters 280 necessary for a plurality of coordinate conversions having mutually different reduction ratios. The coordinate conversion circuit 272 performs coordinate conversion on the target image data 275 based on the conversion parameter 280 relating to such image reduction, thereby reducing the target image data 275 at a reduction rate according to the conversion parameter 280. Can do.

  For example, the coordinate conversion circuit 272 performs coordinate conversion on the target image data 275 based on a conversion parameter 280 that instructs to reduce an image with a reduction ratio of 0.9, thereby reducing the image by 0.9. The converted image data 276 is obtained. Here, the reduction of the image is a reduction of the image (subject) represented by the target image data 275 and does not reduce the number of vertical and horizontal pixels of the image.

  When the conversion parameter 280 includes a conversion parameter related to image rotation and a conversion parameter 280 related to image reduction, the coordinate conversion circuit 272 outputs a rotated image obtained by rotating the target image data 275 and the target image data 275. A reduced image obtained by reduction can be generated as converted image data 276. The conversion parameter 280 related to image reduction is similar to the conversion parameter 280 related to image rotation, for example, the coordinates of four pixels in the target image data 275 corresponding to the four corner pixels in the reduced image (that is, the mapping source). 4 pixel coordinates).

  Furthermore, the conversion parameter 280 may include a conversion parameter necessary for coordinate conversion for performing parallel movement of the image. In this case, the conversion parameter 280 may include a plurality of conversion parameters 280 necessary for a plurality of coordinate conversions having different movement directions. In addition, the conversion parameter 280 may include a plurality of conversion parameters necessary for each of a plurality of coordinate conversions having different amounts of parallel movement.

  The coordinate conversion circuit 272 moves the target image data 275 in the movement direction according to the conversion parameter 280 by performing coordinate conversion on the target image data 275 based on the conversion parameter 280 regarding such parallel movement. In addition, when the conversion parameter 280 specifies the amount of translation, the target image data 275 can be translated by the designated amount of movement.

  For example, the coordinate conversion circuit 272 performs coordinate conversion on the target image data 275 based on the conversion parameter 280 instructing to perform parallel movement with the movement direction “right” and the movement amount “1 pixel”. Thus, post-conversion image data 276 translated by one pixel to the right is obtained. Here, the parallel movement of the image is a parallel movement of the image (subject) represented by the target image data 275.

  When the conversion parameter 280 includes a conversion parameter related to the rotation of the image and a conversion parameter 280 related to the parallel movement of the image, the coordinate conversion circuit 272 displays the rotated image obtained by rotating the target image data 275 and the target image data 275. Can be generated as converted image data 276. FIG. The conversion parameter 280 for translation is similar to the conversion parameter 280 for rotation of the image, for example, the coordinates of the four pixels in the target image data 275 corresponding to the pixels at the four corners in the translation image (ie, the mapping source). 4 pixel coordinates).

[Detection of illegal medals]
In the gaming machine (pachislot 1) according to the present embodiment, the control LSI 234 of the medal selector 201 performs regular medal discrimination processing including color determination processing, count processing, and stamp determination processing. When an unauthorized device that is not a medal moves on the medal rail 210, it is determined that the color does not match the color of the regular medal in the color determination process, and it is determined that the medal has not passed in the count process. Therefore, it is possible to detect an illegal act of playing a game by misrecognizing that a regular medal is used in the pachislot 1.

  In addition, an illegal medal 310 shown in FIG. 34A (medal having the same diameter and the same color as that of the regular medal 400 (see FIG. 19A), but only a stamp (pattern) applied to the surface of the medal) moves on the medal rail 210. In this case, in the color determination process, it is determined that “matches the color of the regular medal”. However, in the counting process, the imprinted medal image data 312 shown in FIG. 34B is engraved (pattern) in the count area (area 313 surrounded by a dotted line) and the regular medal image data count area (indicated by the dotted line in FIG. 19B). Since the marking (pattern) in the enclosed area 403) is significantly different, it is determined that “the medal has not passed”. Therefore, it is possible to detect an illegal act of playing a game by misrecognizing that a regular medal is used in the pachislot 1.

  Also, on the medal rail 210, there is an unauthorized medal 315 shown in FIG. 35A (other medals having the same diameter and the same color as the regular medal 400 (see FIG. 19A), but differing only in the marking (pattern) applied to the surface of the medal). If it has moved, it is determined in the color determination process that it “matches the color of the regular medal”. In the counting process, the imprinted medal image data 317 shown in FIG. 35B is engraved (pattern) in the count area (area 318 surrounded by a dotted line) and the regular medal image data count area (in FIG. 19B, the dotted line). Since the difference from the stamp (pattern) in the enclosed area 403) is small, it is determined that “the medal has passed”. However, in the engraving determination process, the processed image data 319 for the illegal medal shown in FIG. 35C and the processed image data 405 for the regular medal 400 (see FIG. 20) are significantly different. It is determined that it does not match the stamp. Therefore, it is possible to detect an illegal act of playing a game by misrecognizing that a regular medal is used in the pachislot 1.

  In addition, a medal of the same color as the regular medal 400 (see FIG. 19A) and a different diameter (a diameter slightly smaller or larger than the regular medal and guideable by the select plate 207) moved on the medal rail 210. In this case, in the color determination process, it is determined that “matches the color of the regular medal”. However, in the image data of this medal, if this medal is slightly smaller than the diameter of the regular medal and the count area has a boundary between the outer edge of the medal and the background, the “no medal has passed” in the counting process. It is determined. Even if it is determined that the medal has passed in the counting process, the processed image data of this medal and the processed image data 405 of the regular medal 400 (see FIG. 20) from the difference in diameter between this medal and the regular medal 400. ) Is very different. Therefore, in the marking determination process, it is determined that “the medal stamp (pattern) does not match the stamp of the regular medal”. Therefore, it is possible to detect an illegal act of playing a game by misrecognizing that a regular medal is used in the pachislot 1.

  Further, when a medal having the same diameter and different color as the regular medal 400 (see FIG. 19A) moves on the medal rail 210, it is determined that the color does not match the color of the regular medal in the color determination process. Therefore, it is possible to detect an illegal act of playing a game by misrecognizing that a regular medal is used in the pachislot 1.

  Further, the control LSI 234 outputs the determination results of the color determination process, the count process, and the marking determination process to the main control circuit 91 including the main control board 71 via GPIO. Therefore, it is possible to cause the main control circuit 91 to perform various processes when there is an illegal act. Here, the various processes when there is a fraudulent action are, for example, that the main control circuit 91 forcibly interrupts the game and notifies the fact that the fraudulent act has occurred via the sub-control circuit 101 (for example, , Displaying that the fraud has occurred on the liquid crystal display device 11).

  Further, when an illegal act is detected based on the determination result of the color determination process and the count process, the main control circuit 91 may set the medal solenoid 208 of the medal selector 201 to the OFF state. As a result, the select plate 207 is positioned at the “discharge position”, so that the illegal medal can be guided to the medal chute 202 and discharged from the medal payout opening 32. The main control circuit 91 sets the medal solenoid 208, which has been set to the OFF state by detecting the cheating by the color determination process and the counting process, to the ON state after guiding the cheating medal related to the cheating to the medal chute 202. May be.

  Further, even when an illegal act is detected by the stamp determination process, the main control circuit 91 may set the medal solenoid 208 of the medal selector 201 to the OFF state. In the present embodiment, as shown in FIG. 32, the VSYNC interrupt signal related to the fourth medal after the VSYNC interrupt signal (3IH) related to the third medal is output from the ISP circuit 245 to the main control circuit 91. Until the signal (4IH) is output, the determination result of the marking determination process related to the first medal is output to the main control circuit (1HG3). Therefore, when illegal medals are continuously inserted, the illegal medals inserted after the fourth sheet can be guided to the medal chute 202 and discharged from the medal payout opening 32.

  As a result, the spread of damage caused by fraud can be suppressed. In the case where the imprint act can be detected by the imprint determination process before the medal imaged by the camera unit 209 passes over the after medal pressure 218 or the medal stopper unit 227 by speeding up the imprint determination process. Since the main control circuit 91 immediately sets the medal solenoid 208 to the OFF state, it is possible to prevent damage caused by fraud. In addition, the main control circuit 91 determines that the medal solenoid 208 that has been set to the OFF state by detecting an illegal act by the stamp determination process indicates that the determination result of the next stamp determination process indicates that the medal stamp (pattern) matches the stamp of the regular medal. If “Yes”, it may be set to ON. As a result, since illegal medals were accidentally mixed, if the player inserts illegal medals without intending fraud, and the medal solenoid 208 is set to the OFF state and the game becomes impossible, the player If a medal is inserted, the game can be resumed.

  The gaming machine according to one embodiment of the present invention has been described above including the effects thereof. However, the gaming machine of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention described in the claims.

  For example, in the above description, an example was described in which medals having the same marking (pattern) on both sides were used as game media, but instead of this, different markings were made on one side and the other side of the medal. You may use the given medal. In this case, data relating to each face of the medal may be prepared in advance as data relating to the threshold value in the count process, the color determination process, and the marking determination process.

  Further, as a method for setting data relating to the threshold value, a certain unit game period (for example, 100 games) is set as the data collection period relating to the threshold value, and the camera unit 209 captures images during this unit game period. A method of setting based on the image data of medals may be adopted.

  The gaming machine according to the present embodiment described above can determine a medal or the like through image conversion and image recognition processing performed based on a captured image acquired by the imaging unit 261 including the CMOS image sensor 232 and the like. Therefore, it is possible to determine the difference in patterns such as medals. Further, since the control LSI 234 of the camera unit 209 is configured as an ASIC or the like, the manufacturing cost can be effectively suppressed. Further, since the control LSI 234 is provided in a packaged state such as an ASIC, an illegal act from the outside (for example, invalidate the regular medal discrimination process or steal the processing logic of the regular medal discrimination process) And has a significant security advantage.

<Outline of Configuration of Camera Unit and Regular Medal Discrimination Processing According to this Embodiment>
FIG. 36 is a diagram schematically illustrating an example of a captured image 362A obtained via the imaging device (CMOS image sensor 232) of the camera unit 209 of the present embodiment. The captured image 362A illustrated in FIG. 36 includes the captured image of the medal 410. In addition, the medal rails 351a and 351b as the background are captured, and the images are included in the captured image 362A. The medal rails 351a and 351b correspond to the medal rail 210 described above, but here, the shape of the rails is shown in a simplified manner.

  On one main surface 410a of the medal 410, for example, a pattern of alphabet “A” is shown. This shows a pattern of a regular medal, but other patterns may be used. Moreover, a pattern may be attached | subjected to both the main surfaces of a regular medal.

  In this embodiment, the medal 410 moves along the medal rails 351a and 351b while rotating around the rotation axis along the thickness direction passing through the centers of both main surfaces. The imaging unit 361 described later images the medal 410 from the one main surface 410a side of the medal 410. Therefore, the captured image 362A includes an image of the one main surface 410a of the medal 410. In the present embodiment, the captured image 362A generated by the imaging unit 361 is a color image, but may be a grayscale image.

  FIG. 37 is a functional block diagram of such a camera unit 209, which corresponds to the functional block diagram shown in FIG.

  As shown in FIG. 37, the camera unit 209 according to the present embodiment includes an imaging unit 361, a conversion unit 363, a feature image generation unit 364, a determination unit 365, and an input / output unit 366. Note that the camera unit 209 includes a light emitting unit made of an LED or the like, but is not shown in FIG.

  The imaging unit 361 includes a CMOS image sensor 232, and outputs the image data captured by the CMOS image sensor 232 (performed as necessary) as a captured image 362A.

  The conversion unit 363 (for example, corresponding to the ISP circuit 245) converts the captured image 362A input from the imaging unit 361 from a color image to a grayscale image, and outputs the converted captured image as a captured image 362B.

  The feature image generation unit 364 (for example, corresponding to the image recognition accelerator circuit 249 and the image recognition DSP circuit 242) generates a feature image 362C indicating the features of the medal 410 based on the captured image 362B in which the medal 410 is captured. To do. Based on the feature image 362C generated by the feature image generation unit 364, the determination unit 365 determines that the medal 410 shown in the captured image 362B (that is, the medal 410 corresponding to the image of the medal 410 included in the captured image 362B) is valid. The determination result 368 is output via an input / output unit 366 (for example, corresponding to the GPIO 250).

  The determination unit 365 (for example, corresponding to the image recognition DSP circuit 242) compares the feature image 362C generated from the captured image 362B by the feature image generation unit 364 with the template data (template feature image) 367 indicating the feature of the regular medal. Then, based on the comparison result, it is determined whether or not the medal 410 related to the captured image 362B is genuine. The template data 367 is stored in the SRAM 243 or the flash memory 244.

  FIG. 38 is a diagram showing the configuration of the feature image generation unit 364 in more detail. As illustrated in FIG. 38, the feature image generation unit 364 includes a first image generation unit 370 and a second image generation unit 380. The first image generation unit 370 generates a first image 374 showing the medal 410 based on the captured image 362B. The second image generation unit 380 integrates (synthesizes) a plurality of rotation images (corresponding to the converted image data 276 described above) obtained by rotating the first image 374 generated by the first image generation unit 370. At least a part of the composite image (corresponding to the processed image data 277 described above) is generated as a feature image 362C (second image).

  The first image generation unit 370 includes an extraction unit 371 and an edge image generation unit 372. The extraction unit 371 extracts a medal area 373 where the medal 410 is shown from the captured image 362B. The edge image generation unit 372 performs edge detection on the medal area 373 extracted by the extraction unit 371 and generates an edge image (first image 374).

  In the present embodiment, the first image generation unit 370 is realized by, for example, the image recognition DSP circuit 242, and the second image generation unit 380 is realized by, for example, the image recognition accelerator circuit 249.

  When the gaming machine according to the present embodiment is turned on, the host controller 241 performs initial setting of the image recognition DSP circuit 242 and the image recognition accelerator circuit 249. In the initial setting, as described above, the host controller 241 sets the conversion parameter 280 in the memory 274 of the image recognition accelerator circuit 249. For example, the specific information 290 is set in the register 283 of the coordinate conversion circuit 272 by the host controller 241 for each target image data 275.

  When the initial setting is completed, the imaging unit 361 starts imaging and performs imaging at a predetermined frame rate. The captured image 362A sequentially generated by the imaging unit 361 is stored in the SRAM 243, and based on the captured image 362A read from the SRAM 243, the conversion unit 363, the feature image generation unit 364, and the determination unit 365 determine the regular medal. Processing is performed.

<Flow of regular medal discrimination process in camera unit>
Next, with reference to FIG. 39, a series of operations of the regular medal discrimination process performed by the camera unit 209 in the present embodiment will be described.

  First, the conversion unit 363 reads the captured image 362A stored in the SRAM 243 by the imaging unit 361 from the SRAM 243, converts the read captured image 362A from a color image to a grayscale image, and converts the captured image 362B obtained thereby. The data is stored in the SRAM 243 as a discrimination process target (step S11).

  Next, in step S12, the extraction unit 371 extracts a medal area 373 in which the medal 410 appears from the captured image 362B that is the target of the discrimination process (see FIG. 40). Thereafter, in step S <b> 13, the edge image generation unit 372 performs edge detection on the medal area 373 extracted by the extraction unit 371, and generates an edge image as the first image 374 indicating the medal 410.

  Next, in step S14, the second image generation unit 380 combines a plurality of rotation images obtained by rotating the edge image (first image 374) generated by the edge image generation unit 372 (processing) At least a part of the image data 277) is generated as a feature image 362C.

  Next, in step S15, the determination unit 365 compares the feature image 362C generated by the second image generation unit 380 with the feature image included in the template data 367, and based on the comparison result, It is determined whether or not the medal 410 shown in the captured image 362B is genuine. In other words, the determination unit 365 determines whether the medal 310 shown in the captured image 362A generated by the imaging unit 261 is genuine based on the comparison result between the feature image 362C and the feature image included in the template data 367. Determine whether or not.

  In step S16, the determination unit 365 corresponds to the determination result 368 to the main control circuit (main control circuit 91 in the gaming machine of the above embodiment) via the input / output unit 366 (corresponding to the GPIO 250 of the above embodiment). ). In this way, when the medal 410 shown in the captured image 362A is not legitimate, the main control circuit forcibly interrupts the game, for example, and the sub control circuit (the sub control circuit 101 in the gaming machine of the above embodiment). To the effect that an illegal act has occurred. For example, it is possible to issue a warning to the outside by outputting a warning sound from a speaker or displaying warning information on a display which is a liquid crystal display device.

  Thereafter, when a new captured image 362A is input, the above-described regular medal determination process is executed using the captured image 362B obtained from the captured image 362A as a new determination process target. Thereafter, the same regular medal determination process is executed every time the captured image 362A is input.

<Detailed description of each component of the camera unit>
Next, operations of the extraction unit 371, the edge image generation unit 372, the second image generation unit 380, and the determination unit 365 of the first image generation unit 370 will be described in more detail.

[Extractor]
FIG. 40 is a diagram schematically illustrating an example of the medal area 373 extracted by the extraction unit 371 from the captured image 362B. There are various methods for extracting the medal area 373 from the captured image 362B.

  For example, there is a first extraction method using the fact that the outer shape of the medal 410 is circular. In this first extraction method, first, edge detection is performed on the captured image 362B to generate an edge image. As an edge image generation method, for example, Sobel method, Laplacian method, Canny method and the like are used. Next, a circular area is extracted from the generated edge image. For example, Hough transform is used as a method for extracting a circular region. A circular area in the captured image 362B existing at the same position as the position of the circular area in the edge image is set as a medal area 373.

  As another method, there is a second extraction method for extracting the medal region 373 from the captured image 362B using the background difference method and labeling. In the second extraction method, first, a background difference image indicating a difference between the captured image 362B and a background image (an image showing only the background of the captured image 362B) is generated, and the generated background difference image is binarized. The Then, labeling such as 4-connection is performed on the binary background difference image. A partial area in the captured image 362B existing at the same position as the position of the connected area (independent area) obtained as a result of labeling in the binary background difference image is set as a medal area 373.

  In the present embodiment, the extraction unit 371 extracts the medal area 373 from the captured image 362B by a method different from the above two methods. The operation of the extraction unit 371 according to this embodiment will be described below. Note that the extraction unit 371 may extract the medal area 373 from the captured image 362B using one of the two methods described above.

  First, the extraction unit 371 generates a background difference image indicating a difference between the captured image 362B and the background image 375 (an image showing only the background of the captured image 362B), and binarizes the generated background difference image. FIG. 41 is a diagram schematically showing the background image 375, and FIG. 42 is a diagram schematically showing a binary background difference image 376. Note that, in the binary image schematically shown in FIG. 42 and later-described drawings in the present embodiment, the region having the pixel value “1” (high luminance region) is shown in black and the pixel value is “0”. This region (low luminance region) is shown in white. The background image 375 can be stored in, for example, the SRAM 243 or the like.

  Next, the extraction unit 371 performs template matching on the binary background difference image 376 using a binary outer shape template 377 indicating the outer shape of the medal 410. That is, the extraction unit 371 specifies where in the background difference image 376 a region similar to the outer shape template 377 exists. In other words, the extraction unit 371 specifies where in the background difference image 376 there is an area that matches the outline of the medal 410 indicated by the outline template 377. FIG. 43 is a diagram schematically showing the outer shape template 377. The outline template 377 can be stored in the SRAM 243 or the like, for example.

  In template matching, the extraction unit 371 moves the outline template 377 little by little (for example, one pixel (pixel) at a time) in the raster scan direction on the background difference image 376 as shown in FIG. In other words, the extraction unit 371 raster scans the outline template 377 on the background difference image 376. At this time, the extraction unit 371 generates an AND image of the outline template 377 and a partial region of the background difference image 376 that overlaps the outline template 377 at each position of the outline template 377. Thereby, a plurality of binary AND images are generated. The extraction unit 371 then extracts the background difference image 376 of the outer shape template 377 used in generating the AND image having the largest number of pixels (high luminance pixels) having the pixel value “1” among the plurality of generated AND images. Identify the top position. This position is a position where an area similar to the outline template 377 exists in the background difference image 376.

  Then, as illustrated in FIG. 45, the extraction unit 371 extracts a partial area 378 in the captured image 362B existing at the same position as the identified position as a medal area 373. In other words, the extraction unit 371 extracts, as the medal area 373, the partial area 378 in the captured image 362B that overlaps the external shape template 377 when the external shape template 377 is arranged in the captured image 362B at the same position as the specified position. . At this time, in the partial area 378, a medal area 373 may be obtained by setting the pixel value of each pixel outside the circle indicated by the outer shape template 377 on the partial area 378 to zero. The medal area 373 extracted by the extraction unit 371 is a grayscale image. In the present embodiment, the outer shape of the medal area 373 is a quadrangle, but may be another shape such as a circle.

[Edge image generator]
The edge image generation unit 372 performs edge detection on the medal area 373 extracted by the extraction unit 371 using, for example, the Sobel method, the Laplacian method, the Canny method, and the like, and generates an edge image (first image 374). Generate. In the present embodiment, the edge image generation unit 372 uses, for example, a Sobel method that is light in processing. The edge image is a binary image. FIG. 46 is a diagram schematically showing an edge image.

[Second image generation unit]
The second image generation unit 380 combines, as a feature image 362C, at least a part of a rotation composite image obtained by combining a plurality of rotation images obtained by rotating the first image (edge image) 374 generated by the edge image generation unit 372. Generate. In the present embodiment, the second image generation unit 380 generates, for example, a rotation synthesized image obtained by synthesizing a plurality of rotation images obtained by rotating the first image (edge image) 374 (that is, the processed image data 277 described above). Generated as a feature image 362C. Here, the rotation of the first image (edge image) 374 includes a case where the rotation angle is 0 °. Below, the production | generation method of the said rotation synthetic | combination image is demonstrated.

  FIG. 47 is a diagram for explaining a method by which the second image generation unit 380 generates the rotation composite image 381 and corresponds to the above-described FIG. 20 and FIG. The second image generation unit 380 rotates the first image (edge image) 374 by a predetermined angle α to generate a plurality of rotated images 374a as shown in FIG. Here, the second image generation unit 380 rotates the first image (edge image) 374 by a predetermined angle α. In the present embodiment, for example, the second image generation unit 380 rotates the first image (edge image) 374 by 2 ° as shown in FIG. 26 (α = 2 °), and outputs 180 rotated images 374a. Generate. The angle α described above can be adjusted to various angles such as 1 ° and 4 °.

  Then, the second image generation unit 380 combines the generated plurality of rotation images 374a to generate a rotation combination image 381. Specifically, the second image generation unit 380 adds and averages the plurality of rotated images 374a with their centers coincided with each other, and sets the averaged image obtained thereby as the rotation synthesized image 381. The second image generation unit 380 uses the generated rotation composite image 381 as a feature image 362C indicating the feature of the medal 310 shown in the captured image 362B.

  When the second image generation unit 380 combines the plurality of rotation images 374a, the rotation image 374a having a total rotation angle of 0 ° in each rotation image 374a (that is, the first image that has not been rotated ( It is possible not to use an area protruding from the outer shape of the edge image) 374). Therefore, in this case, the rotation composite image 381 is a gray scale image having the same size as the first image (edge image) 374.

  As described above, the imaging unit 361 images the rotating medal 410 and generates a captured image 362A in which the medal 410 is reflected. Therefore, the rotation angle of the medal 410 (the rotation angle of the pattern attached to the medal 410) of the captured image 362B generated by the conversion unit 363 is not always the same. On the other hand, the rotation composite image 381 is a combination of a plurality of rotation images 374a obtained by rotating the first image (edge image) 374 showing the medal 410 of the captured image 362B, and thus the medal of the captured image 362B. Even if there is a variation in the rotation angle 410, if the medal 410 is genuine, the rotation composite image 381 obtained from the captured image 362B hardly changes. Therefore, it can be said that the rotation composite image 381 is a feature image 362C showing the feature of the medal 410 that is not easily influenced by the rotation angle of the medal 410 of the captured image 362B.

[Determining part]
The determination unit 365 compares the rotation composite image 381 (feature image 362C) generated by the second image generation unit 380 with the feature image of the template data 267 indicating the feature of the regular medal 410, and based on the comparison result. Thus, it is determined whether or not the medal 410 included in the captured image 362B is genuine. As the feature image of the template data 267, the feature image 362C (rotation) indicating the feature of the regular medal 410 generated by the feature image generation unit 364 in the same manner as described above from the captured image 362B including the image of the regular medal 410. A composite image 381) is used.

  The feature image of the template data 367 can be obtained by inserting the medal 310 into the gaming machine. For example, when a regular medal 410 is inserted into a gaming machine equipped with the camera unit 209 of the present embodiment, a captured image 362B (this captured image 362B is referred to as a “standard image 391”) is captured, and then Based on the standard image 391, the feature image generation unit 364 generates a feature image 362C (rotation synthesized image 381) indicating the features of the regular medal 410 included in the standard image 391. This feature image 362C is referred to as a “standard feature image 392”. In the present embodiment, the standard feature image 392 is a feature image of the template data 367. Such template data 367 is stored in the SRAM 243 of the camera unit 209 as described above. Hereinafter, the feature image 362C generated during actual operation of the gaming machine (the feature image 362C generated to determine the regular medal) is referred to as the “target feature image 362C” in order to distinguish it from the standard feature image 392. There is.

  For example, the determination unit 365 obtains a similarity (difference) between the rotation composite image 381 (target feature image 362C) and the feature image of the template data 367, and compares them. In the present embodiment, the determination unit 365 uses, for example, SAD (Sum of Absolute Difference) as a value indicating the similarity. A large SAD means that the similarity is low, and a small SAD means that the similarity is high. Other values such as SSD (Sum of Squared Difference) or NCC (Normalized Correlation Coffiecient) may be used as the value indicating the degree of similarity.

  When the similarity between the rotation composite image 381 and the feature image of the template data 367 is high, the determination unit 365 determines that the medal 410 included in the captured image 362B is authentic, and the similarity is If it is low, it is determined that the medal 410 included in the captured image 362B is not genuine. Specifically, the determination unit 365 determines that the medal 410 of the captured image 362B is genuine when the SAD between the rotation composite image 381 and the feature image of the template data 367 is equal to or less than a threshold value. If the SAD is larger than the threshold value, it is determined that the medal 410 of the captured image 362B is not genuine. Then, the determination unit 365 outputs a determination result 368.

  The threshold value used in the determination unit 365 is determined using a plurality of medals 410, for example. Specifically, when the gaming machine is not actually operating, a plurality of regular medals are sequentially inserted into the gaming machine. Then, a plurality of captured images 362B in which a plurality of inserted regular medals are respectively captured are generated. The determination unit 365 obtains the SAD between the rotation composite image 381 generated by the feature image generation unit 364 from the captured image 362B and the feature image of the template data 367 for each of the generated plurality of captured images 362B. Then, the maximum value among the plurality of SADs obtained by the determination unit 365 is determined as the threshold value. The determined threshold value is stored in, for example, the SRAM 243 or the like.

  Note that the threshold value can be determined by such a gaming machine when a predetermined mode is selected in the gaming machine. Further, the threshold value may be determined in advance by a gaming machine or other device and stored in the SRAM or the like of each gaming machine.

  By determining the threshold value used in the determination unit 365 in this manner, when the type of the regular medal 410 is changed, the changed medal 410 is inserted into a gaming machine that is not actually operating. As a result, a threshold value corresponding to the changed medal 410 is determined. Therefore, even when the type of the medal 410 is changed, it is possible to appropriately determine whether or not the medal 410 inserted into the gaming machine is a genuine one.

  In the above example, the binary first image (edge image) 374 is input to the second image generation unit 380 as the first image 374 indicating the medal 310 of the captured image 362B. An image indicating the region 373 may be input to the second image generation unit 380 as the first image. In this case, a rotation composite image obtained by combining a plurality of rotation images obtained by rotating the medal area 373 is used as the feature image 362C.

  As described above, in the pachislot machine 1 that is a gaming machine according to the present embodiment, at least one of the rotation composite images 381 obtained by combining a plurality of rotation images obtained by rotating the first image (edge image) 374 showing the medal 410. Are generated as the second image (feature image 362C). This feature image 362C is not easily affected by the rotation angle of the medal 410 included in the captured image 362B. Therefore, even when the rotation angle (rotation posture) of the medal 410 included in the captured image 362B varies, the medal 410 included in the captured image 362B using the feature image 362C (target feature image 362C, standard feature image 392). Can be more accurately determined whether or not is genuine, and the determination accuracy is improved.

  In this embodiment, since the binary edge image is the first image 374, the brightness of the imaging region in the imaging unit 361 is compared to the case where the medal region 373 of the grayscale image is the first image 374. It is possible to suppress the first image 374 from being affected by the change in height. Therefore, it is possible to suppress the characteristic image 362C from being affected by the change in the brightness of the imaging area where the medal 410 is imaged, and as a result, the accuracy of determining a regular medal is improved.

  In the present embodiment, the extraction unit 371 uses the template matching to extract the medal area 373 from the captured image 362B. Therefore, the first extraction method using the Hough transform and the labeling are used. Compared with the second extraction method, the extraction process is simplified.

  In the present embodiment, the determination unit 365 compares the feature image 362C generated from the captured image 362B with the feature image of the template data 367 using SAD or the like, and based on the comparison result, the captured image 362B. Since it is determined whether or not the medal 410 according to is genuine, the determination process is simplified.

  Note that the second image generation unit 380 determines the number of rotated images (for example, the value of N shown in FIG. 29) used when generating the feature image 362C (rotated synthesized image 381) as the camera unit 209 of the present embodiment. You may change according to the operation | movement condition of the game machine in which is incorporated. For example, it is assumed that the speed of the medal 410 moving on the medal rail 210 varies depending on the gaming machine or the like. In such a situation, when the moving speed of the medal 410 is fast, the second image generation unit 380 gives priority to the processing time over the determination accuracy, and the number of rotation images used when generating the feature image 362C. It can be configured to reduce For example, the second image generation unit 380 rotates the edge image (first image 374) by 10 ° from 0 ° to 350 °, generates 36 rotated images 374a, and combines these rotated images 374a. Thus, the feature image 362C is generated.

  On the other hand, when the movement speed of the medal 410 is fast, the second image generation unit 380 gives priority to the determination accuracy over the processing time and increases the number of rotation images used when generating the feature image 362C. Can be configured. For example, the second image generation unit 380 rotates the edge image (first image 374) by 1 ° from 0 ° to 359 ° to generate 360 rotated images 374a, and synthesizes these rotated images 374a. Thus, the feature image 362C is generated.

  Also, as shown in FIG. 32, when the host controller 241 detects a reduction end interrupt signal (2SH, 4SH, etc.) indicating the end of fisheye correction processing by the fisheye correction scaler circuit 248, the image recognition DSP circuit. 242 or the image recognition accelerator circuit 249 is being processed (busy state), and even when a situation in which the marking determination process (regular medal determination process) is skipped occurs, the regular medals are determined for more medals 410. The processing time can be shortened by reducing the number of rotated images used when generating the feature image 362C so that processing can be performed.

  In the gaming machine in which the camera unit 209 of the present embodiment is incorporated, when the medal 410 is inserted into the gaming machine by moving on the medal rail 210 without changing its posture, the captured image 362B is displayed. Although the posture of the medal 410 shown is constant, the position of the medal 410 shown in the right and left direction may vary. For example, in one captured image 362B, the medal 410 may appear on the left side, in another captured image 362B, the medal 410 may appear in the center, and in another captured image 362B, the medal 410 may appear on the right side.

  In such a case, the conversion parameter 280 includes a plurality of parallel movement parameters (the conversion parameter 280 related to parallel movement described above), and the captured image 362B or the like is not the edge image (first image 374) but the second image. The data is input to the generation unit 380. Therefore, the second image generation unit 380 individually performs coordinate conversion on the captured image 362B and the like based on the plurality of parallel movement parameters, and generates a plurality of parallel movement images. For example, the second image generation unit 380 generates a plurality of right-translated images obtained by moving the captured image 362B by two pixels in the right direction, and moves the captured image 362B by two pixels in the left direction. A plurality of left translation images are generated. Then, the second image generation unit 380 generates a composite image by synthesizing the plurality of parallel movement images including the plurality of right translation images and the plurality of left translation images generated in this way. Moreover, it is also possible to generate a plurality of such parallel movement images for the edge image (first image 374) and combine these parallel movement images to generate a composite image.

  The determination unit 365 determines whether or not the medal 410 is a regular medal using the composite image as a feature image. Thereby, even if the position of the medal 410 shown in the left and right direction varies in the captured image 362B, it is possible to appropriately determine whether or not the medal 410 is a regular medal.

  In addition, in the gaming machine in which the camera unit 209 of this embodiment is incorporated, when the medal 410 is captured, the size of the medal 410 shown in the captured image 362B may vary. For example, when the distance between the medal 410 and the CMOS image sensor 232 is not kept constant due to a slight allowance of the passage route of the medal 410, the size of the medal 410 shown in the captured image 362B varies somewhat. Sometimes.

  In such a case, the conversion parameter 280 includes a plurality of enlargement parameters (the conversion parameter 280 related to image enlargement described above) and a plurality of reduction parameters (the conversion parameter 280 related to image reduction described above). Then, the second image generating unit 380 individually performs a plurality of coordinate transformations on the edge image (first image 374) based on the plurality of enlargement parameters, and generates a plurality of enlarged images. Further, the second image generation unit 380 individually performs a plurality of coordinate transformations on the edge image (first image 374) based on the plurality of reduction parameters, and generates a plurality of reduced images. Then, the second image generation unit 380 generates a composite image by combining a plurality of images including a plurality of enlarged images and a plurality of reduced images.

  The determination unit 365 determines whether or not the medal 410 is a regular medal using the composite image as a feature image. Thereby, even when the size of the medal 410 shown in the captured image 362B varies, it can be appropriately determined whether or not the medal 410 is a regular medal.

  Further, in the gaming machine in which the camera unit 209 of the present embodiment is incorporated, when a plurality of types of medals 410 are used, a plurality of conversions used in the second image generation unit 380 depending on the type of the medals 410. The set of parameters 280 may be changed. For example, when a certain type of medal 410 is used and captured by the CMOS image sensor 232, the second image generation unit 380 uses a plurality of rotation parameters included in the conversion parameter 280 to generate an edge image (first image). 374) etc., a plurality of coordinate transformations are performed individually. On the other hand, when another type of medal 410 is used, the second image generation unit 380 uses a plurality of parallel movement parameters included in the conversion parameter 280 to perform an edge image (first image 374) or the like. Multiple coordinate transformations individually.

<Modification of this embodiment>
Hereinafter, various modifications related to the camera unit 209 (particularly, the image recognition accelerator circuit 249) according to an embodiment of the present invention will be described.

[Modification 1]
FIG. 48 is a diagram showing the configuration of the image recognition accelerator circuit 449 according to this modification. The image recognition accelerator circuit 449 corresponds to the image recognition accelerator circuit 249 shown in FIG. 23, and at least the coordinate conversion circuit 272 is changed to the coordinate conversion circuit 472. The input frame buffer 471 corresponds to the input frame buffer 271 in FIG. 23, the image processing circuit 473 corresponds to the image processing circuit 273 in FIG. 23, and the memory 474 corresponds to the memory 274 in FIG.

  When the first image (edge image) 374 shown in FIG. 47 is rotated to obtain a rotated image (374a), the coordinate conversion circuit 472 selects a specific subject among the subjects included in the first image (edge image) 374. (Hereinafter referred to as “specific subject”) can be adjusted. Hereinafter, the coordinate conversion circuit 472 according to this modification will be described focusing on differences from the coordinate conversion circuit 272 shown in FIG.

  A coordinate conversion circuit 472 according to this modification includes a conversion circuit 481 that performs coordinate conversion, a control circuit 482, and an addition circuit 485. Compared with the control circuit 282 shown in FIG. 23, the control circuit 482 includes a register 483 corresponding to the register 283, and stores therein the specific information 490 corresponding to the specific information 290 therein. The adder circuit 485 adds the parameter offset 495 to the conversion parameter 280 read from the memory 474 of the image recognition accelerator circuit 449 by the control circuit 482. Then, the addition circuit 485 outputs the conversion parameter 280 added with the parameter offset 495 to the conversion circuit 481.

  The parameter offset 495 is stored in the register 483 of the control circuit 482. The parameter offset 495 is represented in the first image (edge image) 374 with respect to the position of the center of gravity of the quadrilateral image represented by the first image (edge image) 374 (that is, the intersection of the diagonal lines of the quadrilateral), for example. The deviation amount of the position of the center of gravity of the specific subject is shown. In the case of the gaming machine according to the present embodiment, the specific subject is the medal 410 represented by the first image (edge image) 374. In this case, the center of gravity of the specific subject is the center of gravity of the medal 410, that is, the center of the circular medal 410.

  The parameter offset 495 is the x-direction of the position of the center of gravity of the specific subject represented by the first image (edge image) 374 with respect to the position of the center of gravity of the square represented by the first image (edge image) 374 (for example, left and right of the image). Direction) shift amount xoff and the position of the center of gravity of the specific subject represented by the first image (edge image) 374 with respect to the position of the center of gravity of the square represented by the first image (edge image) 374 (for example, And the amount of deviation yoff in the vertical direction of the image). Hereinafter, the shift amount xoff is referred to as “x offset xoff”. The shift amount yoff is referred to as “y offset yoff”.

  Here, the coordinates of the center of gravity of the quadrangle represented by the first image (edge image) 374 are (x1, y1), and the coordinates of the center of gravity of the specific subject represented by the first image (edge image) 374 are (x2, y2). At this time, x offset xoff = x2-x1, and y offset yoff = y2-y1. In the example of the first image (edge image) 374 shown in FIG. 46, each side of the quadrangle represented by the first image (edge image) 374 is in contact with the circumference of the medal 410 that is a perfect circle. , Xoff = 0, and yoff = 0.

  When the addition circuit 485 adds the parameter offset 495 to the conversion parameter 280, the addition circuit 485 adds the x offset xoff of the parameter offset 495 to the respective x coordinates of the four coordinates constituting the conversion parameter 280. Then, the adding circuit 485 adds the y offset yoff of the parameter offset 495 to each y coordinate of the four coordinates constituting the conversion parameter 280.

  The conversion circuit 481 performs coordinate conversion on the target image data 275 (first image 374) based on the conversion parameter 280 to which the parameter offset 495 is added. When the conversion parameter 280 is a conversion parameter 280 related to image rotation, the conversion circuit 481 performs coordinate conversion of the target image data 275 based on the conversion parameter 280 to which the parameter offset 495 is added. Thus, even when the position of the center of gravity of the specific subject represented by the target image data 275 is deviated from the position of the center of gravity of the quadrangle represented by the target image data 275, the positions of the centers of gravity of both coincide with each other. It becomes like this. In the gaming machine according to the present embodiment, the position of the center of gravity of the medal 410 represented by the first image (edge image) 374 that is the target image data 275 is determined from the position of the center of gravity of the quadrangle represented by the first image 374. Even if they are misaligned, the positions of the centers of gravity of both coincide.

  The parameter offset 495 is set by the host controller 241 when the host controller 241 instructs the image recognition accelerator circuit 449 to start image processing (rotation integration processing) related to the target image data 275 (step S1 in FIG. 33, etc.). And the specific information 290 are set in the register 483 of the control circuit 482. The host controller 241 reads the specific information 290 and the parameter offset 495 corresponding to the target image data 275 for each target image data 275 to be processed from the SRAM 243 and the like to the image recognition accelerator circuit 249. 290 and parameter offset 495 are set in the register 483 of the control circuit 482.

  The control circuit 482 outputs the parameter offset 495 stored in the register 483 to the addition circuit 485 and reads the conversion parameter 280 from the memory 274 based on the specific information 290 stored in the register 483. The addition circuit 485 adds the parameter offset 495 to the conversion parameter 280 read from the memory 274, and the conversion parameter 280 added with the parameter offset 495 is provided to the conversion circuit 481.

  In the gaming machine according to the present embodiment, the parameter offset 495 is generated by, for example, the image recognition DSP circuit 242 that functions as the first image generation unit 370. The first image generation unit 370 can generate the parameter offset 495 when generating the first image (edge image) 374 based on the captured image 362B.

  The first image generation unit 370 stores the parameter offset 495 obtained when generating the first image (edge image) 374 in the SRAM 243 in association with the first image 374.

  As described above, in the coordinate conversion circuit 472 according to this modification, the conversion circuit 481 performs coordinate conversion on the first image (edge image) 374 based on the conversion parameter 280 to which the parameter offset 495 is added. Therefore, by adjusting the parameter offset 495 for each first image (edge image) 374, the rotation image 374a (post-conversion image data 276) obtained by the conversion circuit 481 or the feature image 362C (processed image data 277) is obtained. The position of the specific subject is adjusted.

  In the gaming machine according to the present embodiment, when the position of the medal 410 in the rotation image 374a varies, the composite image varies, and as a result, the feature image 362C varies. If the feature image 362C varies, even if the medal 410 inserted into the gaming machine is a regular medal, there is a possibility that it is greatly different from the template data 367, and as a result, the determination accuracy in the determination unit 365 may decrease. is there. Therefore, the feature image is obtained by matching the position of the center of gravity of the medal 410 represented by the first image (edge image) 374 with the position of the center of gravity of the quadrangle represented by the first image 374 as in this modification. As a result, the determination accuracy in the determination unit 365 can be improved.

[Modification 2]
In the present modification, as shown in FIG. 49, the image recognition accelerator circuit 549 performs coordinate transformation on the target image data 575 stored in the input frame buffer a plurality of times to generate one processed image data 577. To do.

  FIG. 50 is a diagram illustrating a configuration of an image recognition accelerator circuit 549 according to the present modification. The image recognition accelerator circuit 549 corresponds to the image recognition accelerator circuit 249 shown in FIG. 23. At least the coordinate conversion circuit 272 is changed to the coordinate conversion circuit 572, and the image processing circuit 273 is changed to the image processing circuit 573. Has been. The input frame buffer 571 corresponds to the input frame buffer 271 in FIG. 23, and the memory 574 corresponds to the memory 274 in FIG.

  FIG. 51 is a diagram showing a configuration of an image processing circuit 573 according to the present modification. As shown in FIG. 51, the image processing circuit 573 according to the present modification does not include an addition processing unit as compared with the image processing circuit 273 shown in FIG. In addition, the image processing circuit 573 has a first read request output unit 601 corresponding to the first read request output unit 301 and a write request output unit 602 corresponding to the write request output unit 302 as compared with the image processing circuit 273. The storage control unit 600 includes a second read request output unit 603 corresponding to the second read request output unit 303. 51 includes an arbitration unit 604 corresponding to the arbitration unit 304 of the image processing circuit 273, and further includes a write buffer 606 corresponding to the write buffer 306, a read buffer 607 corresponding to the read buffer 307, A frame memory 609 corresponding to the frame memory 309 is provided. The converted image data 576 is output from the coordinate conversion circuit 572 described above to the write buffer 606.

  In such an image processing circuit 573, the pixel data (of the converted image data 576) output from the conversion circuit 581 of the coordinate conversion circuit 572 of the image recognition accelerator circuit 549 is written in the write buffer 606 as it is. Further, the pixel data stored in the read buffer 607 is output to the selection circuit 585 of the coordinate conversion circuit 572.

  As shown in FIG. 50, the coordinate conversion circuit 572 according to the present modification further includes a selection circuit 585 as compared to the coordinate conversion circuit 272 shown in FIG. The selection circuit 585 selects either the output of the input frame buffer 571 or the output of the image processing circuit 573 based on the control signal CNT1 output from the control circuit 582, and the selected output is input to the conversion circuit 581. In this way, the converter circuit 581 is connected.

  In the present modification, the selection circuit 585 selects the output of the input frame buffer 571 when the control signal CNT1 output from the control circuit 582 is in the first state (for example, indicates “1”). When the selection circuit 585 selects the output of the input frame buffer 571, the conversion circuit 581 can access the target image data 575 stored in the input frame buffer 571.

  On the other hand, when the control signal CNT1 output from the control circuit 582 is in the second state (for example, indicating “0”), the selection circuit 585 selects the output of the image processing circuit 573. When the selection circuit 585 selects the output of the image processing circuit 573, the conversion circuit 581 is connected to the read buffer 607 of the image processing circuit 573 and can read pixel data from the read buffer 607.

  FIG. 52 is a diagram showing an example of the conversion parameter 580 according to the present modification. In the conversion parameter 580 according to this modification, a unique parameter number (identification information) is associated with each of the plurality of conversion parameters 580. In the example shown in FIG. 52, the conversion parameters associated with the parameter numbers “1” to “360” are the conversion parameters (580-1 to 580-360) related to image rotation. 360 conversion parameters 580 for rotating from ° to 360 °. Also, the conversion parameters associated with the parameter numbers “361” to “360” are conversion parameters (580-361 to 580-390) related to image enlargement, and these images are converted from 1.1 times to 4 times. 30 conversion parameters 580 for enlarging to 0 times.

  Furthermore, the conversion parameters associated with the parameter numbers “391” to “399” are conversion parameters (580-391 to 580-399) related to image reduction, and these convert the image from 0.9 times to 0. 9 conversion parameters 580 for reduction to 1 times. Also, the conversion parameters associated with the parameter numbers “400” and “401” are the conversion parameters (580-400 to 580-401) related to the parallel movement of the image, and each of these is an image one pixel to the right. This corresponds to a conversion parameter 580 for moving in parallel and a conversion parameter 580 for moving the image to the right by two pixels.

  FIG. 53 is a diagram showing an example of the specific information 590 according to the present modification. As shown in FIG. 53, the specific information 590 according to this modification includes reference mode information 591 and a lookup table (LUT) 592.

  The reference mode information 591 includes a reference count 591a, a reference start position 591b, and a reference interval 591c. The reference count 591a indicates the number of times the parameter number stored in the LUT 592 is referred to. The reference start position 591b indicates the position of the parameter number to be referred to first in the LUT 592. The reference interval 591c indicates how many conversion parameters 580 are referred to from the previously referred conversion parameter 580 in the LUT 592 when the conversion parameter 580 is referred to at a certain timing.

  A plurality of parameter numbers are described in the LUT 592. The reference mode information 591 is information indicating how to refer to a plurality of parameter numbers described in the LUT 592 as described above. The control circuit 582 refers to the parameter numbers of the LUT 592 one by one in accordance with the reference mode information 591 and reads the conversion parameter 580 corresponding to the referenced parameter number each time the parameter number is referenced. The read conversion parameter 580 is input to the conversion circuit 581.

  The control circuit 582 sequentially references a plurality of parameter numbers of the LUT 592 from the head side to the tail side of the LUT 592 (for example, from the head storage position (head address) to the last storage position (final address) of the storage area constituting the LUT 592). To do. When M (≧ 2) coordinate transformations are performed on the target image data 575 in the coordinate transformation circuit 572, the control circuit 582 first determines the LUT 592 based on the reference start position 591b of the reference mode information 591. The parameter number of the corresponding reference start position is referred to. Next, the control circuit 582 reads the conversion parameter 580 corresponding to the referenced parameter number from the memory 574 and inputs it to the conversion circuit 581.

  Next, based on the reference interval 591c of the reference mode information 591, the control circuit 582 refers to the parameter number separated from the last referenced parameter number by the number indicated by the reference interval 591c in the LUT 592. Then, the control circuit 582 reads the conversion parameter 580 corresponding to the referenced parameter number from the memory 574 and inputs it to the conversion circuit 581.

  Thereafter, the control circuit 582 repeats the same operation, refers to the parameter number for the number of times (M times) indicated by the reference count 591a of the reference mode information 591, and stores the conversion parameter 580 corresponding to the referred parameter number in the memory 574, respectively. Is input to the conversion circuit 581. As a result, among the plurality of conversion parameters 580 stored in the memory 574, M conversion parameters 580 used by the conversion circuit 581 in the coordinate conversion for the target image data 575 stored in the input frame buffer 571 are converted in order. It is input to the circuit 581.

  52 and 53, for example, when the reference count 591a of the reference mode information 591 is “3”, the reference start position 591b is “0000h” indicating the head address, and the reference interval 591c is “1”. The circuit 582 sequentially refers to “1”, “361”, and “400” among the plurality of parameter numbers stored in the LUT 592. As a result, the conversion circuit 581 stores the conversion parameter 580-1 corresponding to the rotation for rotating the image by 1 ° corresponding to the parameter number = “1” and the image corresponding to the parameter number = “361” in the order of 1.. Conversion parameters 580 to 361 relating to enlargement for enlarging the image by one time, and conversion parameters 580 to 400 relating to parallel movement for translating the image by one pixel in the right direction corresponding to parameter number = “400”. They are entered in order.

[Operation of Image Recognition Accelerator Circuit in Modification 2]
FIG. 54 is a diagram for explaining the operation of the image recognition accelerator circuit 549 according to the present modification. When the target image data 575 is written into the input frame buffer 571, the control circuit 582 sets the control signal CNT1 to the first state, whereby the target image data 575 in the input frame buffer 571 is passed through the selection circuit 585. This is input to the conversion circuit 581. Further, the control circuit 582 reads the conversion parameter 580 that is used first from the memory 574 together with the setting of the control signal CNT1, and outputs the conversion parameter 580 to the conversion circuit 581. The conversion circuit 581 performs coordinate conversion on the target image data 575 stored in the input frame buffer 571 based on the input conversion parameter 580 to generate first converted image data 576-1. When the conversion circuit 581 generates the first converted image data 576-1, the control circuit 582 sets the control signal CNT1 to the second state. As a result, the read buffer 607 of the image processing circuit 573 is connected to the conversion circuit 581 via the selection circuit 585.

  When the conversion circuit 581 performs coordinate conversion on the target image data 575 based on the conversion parameter 580, the conversion circuit 581 writes the pixel data of the first converted image data 576-1 into the write buffer 606 of the image processing circuit 573. Pixel data written to the write buffer 606 is written to the frame memory 609. As a result, the first converted image data 576-1 is stored in the frame memory 609.

  The image processing circuit 573 writes the pixel data of the first converted image data 576-1 stored in the frame memory 609 to the read buffer 607. Here, the conversion circuit 581 reads out the pixel data of the first converted image data 576-1 from the read buffer 607, whereby the conversion circuit 581 receives the first converted image data 576-1 from the image processing circuit 573. Is entered.

  Next, the conversion circuit 581 performs coordinate conversion on the first converted image data 576-1 based on the conversion parameter 580 used secondly read from the memory 574 by the control circuit 582, and Second converted image data 576-2 is generated. The conversion circuit 581 writes the pixel data of the second converted image data 576-2 into the write buffer 606 of the image processing circuit 573, and thus the pixel data written into the write buffer 606 is written into the frame memory 609. As a result, the second converted image data 576-2 is stored in the frame memory 609.

  The image processing circuit 573 writes the pixel data of the second converted image data 576-2 stored in the frame memory 609 to the read buffer 607, and the conversion circuit 581 receives the second converted image data 576- from the read buffer 607. 2 pixel data is read out. As a result, the second converted image data 576-2 is input to the conversion circuit 581 from the image processing circuit 573. The conversion circuit 581 performs coordinate conversion on the second converted image data 576-2 based on the third used conversion parameter 580 read from the memory 574 by the control circuit 582, and performs the third conversion. After image data 576-3 is generated. The conversion circuit 581 writes the pixel data of the third converted image data 576-3 into the write buffer 606 of the image processing circuit 573, and the pixel data of the write buffer 606 thus written is written into the frame memory 609. As a result, the third converted image data 576-3 is stored in the frame memory 609.

  Thereafter, the image recognition accelerator circuit 549 repeats the same operation, and the conversion circuit 581 of the coordinate conversion circuit 572 causes the control circuit 582 to process the (M−1) -th converted image data 576- (M−1). Coordinate conversion is performed based on the M-th conversion parameter 580 read from the memory 574, and M-th converted image data 576-M is generated. The M-th converted image data 576-M is written in the frame memory 609 as processed image data 577.

  52 and 53, for example, the reference count 591a in the reference mode information 591 of the specific information 590 is "3", the reference start position 591b is "0000h" indicating the head address, and the reference interval 591c is "1". In the case shown, by referring to the LUT 592 as described above, the conversion circuit 581 causes the conversion parameter 580-1 for rotation for rotating the image by 1 ° and the image for enlarging the image by 1.1 times. Conversion parameters 580 to 361 relating to enlargement and conversion parameters 580 to 400 relating to translation for translating the image by one pixel in the right direction are sequentially input. Therefore, in this case, the conversion circuit 581 converts the coordinate conversion for rotating the image by 1 °, the coordinate conversion for enlarging the image by 1.1 times, and the image for one target image data 575. Coordinate conversion is performed in this order in order to translate one pixel in the right direction. In other words, the conversion circuit 581 rotates an image related to one target image data 575 by 1 °, enlarges the rotation image obtained thereby by 1.1 times, and obtains the enlarged image obtained thereby by 1 in the right direction. One processed image data 577 is generated by moving in parallel by the amount of pixels.

  The output control unit 608 of the image processing circuit 573 outputs the processed image data 577 as an output image to the SRAM 243 by DMA transfer as described above. Further, when the storage control unit 600 controls the frame memory 609, the output control unit 608 reads out the four pixel data of the final processed image data 577 from the frame memory 609. Minute pixel data is output to the SRAM 243 by DMA transfer. The DMAC 252 controls the processed image data 577 to be DMA-transferred from the frame memory 609 to the SRAM 243.

  When the DMAC 252 includes a buffer, the output control unit 608 reads out the pixel data for four pixels of the final processed image data 577 from the frame memory 609, and uses the read pixel data for the four pixels as a buffer of the DMAC 252. After that, the host controller 241 writes the pixel data for four pixels or the entire processed image data 577 into the SRAM 243.

  Each time the conversion circuit 581 generates pixel data, the conversion circuit 581 writes the generated pixel data to the write buffer 606, and the write request output unit 602 and the second read request output unit 603 operate independently. Therefore, after the processed image data 577 is generated, the entire data is not output to the SRAM 243 and the DMAC 252, but the conversion circuit 581 performs coordinate conversion in units of pixel data for generating the processed image data 577. The process and the output process of the pixel data of the processed image data 577 in the output control unit 608 are executed in parallel.

  As described above, the coordinate conversion circuit 572 according to the present modification superimposes a plurality of coordinate conversions on one target image data 575 based on the plurality of conversion parameters 580 without exchanging data with the host controller 241. Do it. Therefore, in the same manner as described above, each time the coordinate conversion circuit 572 performs coordinate conversion, the processing time of a plurality of coordinate conversions is shortened as compared with the case where the conversion parameter 580 used in the coordinate conversion is received from the host controller 241. be able to.

  Similarly to the above, in the storage control unit 600, when at least two requests of the first read request, the write request, and the second read request conflict, the arbitration unit 604 sends the at least two requests. Mediated. Therefore, the first read request output unit 601, the write request output unit 602, and the second read request output unit 603 can operate independently of each other, and the first read request output unit 601 and the write request output unit It is possible to prevent the processing at a certain output unit from among 602 and the second read request output unit 603 from becoming a bottleneck. As a result, the processing speed of the entire image recognition accelerator circuit 549 can be improved.

  In this modification, the specific information 590 includes an LUT 592 in which a parameter number corresponding to the conversion parameter 580 is described, and reference mode information 591 indicating how to refer to a plurality of parameter numbers described in the LUT 592. It consists of For this reason, the conversion parameter 580 used in the conversion circuit 581 is specified by the parameter number. Therefore, the conversion parameter 580 used in the conversion circuit 581 can be specified regardless of the position and order in which the plurality of conversion parameters 580 are stored in the memory 574.

  For example, consider the case where conversion parameters 280 relating to a plurality of rotations are stored in the memory 574 as shown in FIG. Here, as shown in FIG. 25 described above, when the specific information 290 includes the number of used parameters 291, the use start position 292, and the use interval 293, the image is rotated by 1 ° based on the specific information 290. Conversion parameter 280-1, a rotation parameter 280-2 for rotating the image by 2 °, a conversion parameter 280-4 for rotating the image by 4 °, and a conversion parameter 280-7 for rotating the image by 7 ° Only (not shown) cannot be specified.

  On the other hand, in this modification, the LUT 592 has a parameter number corresponding to the conversion parameter 580-1 for rotating the image by 1 °, and a parameter number corresponding to the conversion parameter 580-2 for rotating the image by 2 °. These conversions are described by individually describing the parameter number corresponding to the conversion parameter 580-4 for rotating the image by 4 ° and the parameter number corresponding to the conversion parameter 580-7 for rotating the image by 7 °. The parameter 580 can be specified.

  Note that the specific information 590 includes the reference mode information 591 and the LUT 592, but may include only the LUT 592. In this case, the control circuit 582 refers to the plurality of parameter numbers stored in the LUT 592 in order from the top of the LUT 592, for example. Even in such a case, since the conversion parameter 580 used in the conversion circuit 581 is specified by the parameter number, the plurality of conversion parameters 580 are stored in the memory 574 in any way. The conversion parameter 580 used in the conversion circuit 581 can be freely specified from the conversion parameter 580. Further, in the image recognition accelerator circuit 549 according to this modification, the specific information 290 shown in FIG. 25 described above may be used.

  As shown in FIG. 51, the image processing circuit 573 does not include an addition processing unit, and exchanges post-conversion image data 576 with the coordinate conversion circuit 572 shown in FIG. Data 577 is generated (see FIG. 54). In this specification, such processing in the image processing circuit 573 (data handling) is also regarded as a form of image processing.

[Modification 3]
The image recognition accelerator circuit 749 according to the present modification example has an individual conversion processing mode in which individual conversion processing is performed on each target image data 775 and a composite image is generated as an operation mode, and one target image data 775. A plurality of conversion processing modes for performing conversion processing a plurality of times. FIGS. 55 and 56 are diagrams showing configurations of an image recognition accelerator circuit 749 and an image processing circuit 773 according to this modification, respectively.

  FIG. 55 is a diagram showing a configuration of an image recognition accelerator circuit 749 according to this modification. The image recognition accelerator circuit 749 corresponds to the image recognition accelerator circuit 549 shown in FIG. 50. At least the coordinate conversion circuit 572 is changed to the coordinate conversion circuit 772, and the image processing circuit 573 is changed to the image processing circuit 773. Has been. The input frame buffer 771 corresponds to the input frame buffer 771 in FIG. 50, and the memory 774 corresponds to the memory 774 in FIG. 55, the selection circuit 785 corresponds to the selection circuit 585 of the coordinate conversion circuit 572 of FIG. 50, the conversion circuit 781 corresponds to the conversion circuit 581 of the coordinate conversion circuit 572, and the control circuit 782 is the coordinate conversion circuit. This corresponds to the control circuit 582 of the circuit 572.

  As shown in FIG. 55, the coordinate conversion circuit 772 according to this modification has a similar configuration to the coordinate conversion circuit 572 shown in FIG. 50 described above, but in this modification, the register 783 of the control circuit 782 is used. The operation mode information 795 indicating the operation mode in which the image recognition accelerator circuit 749 should operate is stored, and the control signal CNT2 is provided to the image processing circuit 773 based on the operation mode information 795.

  For example, the operation mode information 795 is set in the register 783 by the host controller 241. When the host controller 241 sets the specific information 790 in the register 783, the host controller 241 also sets the operation mode information 795 in the register 783.

  The control circuit 782 controls the control signal CNT1 based on the operation mode information 795. In addition, the control circuit 782 outputs a control signal CNT2 for controlling a selection circuit 806, which will be described later, included in the image processing circuit 773. Such a control signal CNT2 is determined based on the operation mode information 795.

  As shown in FIG. 56, the image processing circuit 773 according to the present modification further includes a selection circuit 806 as compared with the image processing circuit 273 shown in FIG. 30 described above. In addition, the image processing circuit 773 according to the present modification has a document corresponding to the first read request output unit 801 and the write request output unit 302 corresponding to the first read request output unit 301, as compared with the image processing circuit 273. The storage control unit 800 includes a read request output unit 802 and a second read request output unit 803 corresponding to the second read request output unit 303. 56 includes an arbitration unit 804 corresponding to the arbitration unit 304 of the image processing circuit 273, an addition processing unit 805 corresponding to the addition processing unit 305, and a write buffer corresponding to the write buffer 306. 706, a read buffer 707 corresponding to the read buffer 307, a frame memory 709 corresponding to the frame memory 309, and an output control unit 708 corresponding to the output control unit 308. The converted image data 776 is output from the coordinate conversion circuit 772 to the addition processing unit 805.

  Here, the selection circuit 806 receives the control signal CNT2 from the control circuit 782 of the coordinate conversion circuit 772 of the image recognition accelerator circuit 749, and based on this control signal CNT2, outputs the conversion circuit 781 of the coordinate conversion circuit 772 and One of the outputs obtained as a result of the output of the conversion circuit 781 of the coordinate conversion circuit 772 being input to the addition processing unit 805 is selected, and the selected output is output to the write buffer 706. In the present modification, when the control signal CNT2 is in the first state (for example, a state indicating “1”), the selection circuit 806 selects the output of the addition processing unit 805 and writes the selected output (pixel data) to the write buffer. Output to 706. On the other hand, when the control signal CNT2 is in the second state (for example, a state indicating “0”), the selection circuit 806 selects the output of the conversion circuit 781 and outputs the selected output (pixel data) to the write buffer 706. .

[Operation of Image Recognition Accelerator Circuit in Modification 3]
When the operation mode information 795 indicates the individual conversion processing mode, the control circuit 782 sets both the control signal CNT1 and the control signal CNT2 to the first state. As a result, the operation mode of the image recognition accelerator circuit 749 according to the present modification becomes the individual conversion processing mode, and the configuration thereof is the same as that of the image recognition accelerator circuit 249 shown in FIG. 23 and the image processing circuit 273 shown in FIG. The operation of the image recognition accelerator circuit 749 in the individual conversion processing mode is the same as that of these circuits.

  In the individual conversion processing mode, for example, 360 pieces of converted image data 776 (for 360 degrees) generated by rotating by one degree based on the conversion parameter 780 are integrated for one target image data 775, and One piece of processed image data 777 is generated (see FIG. 29).

  On the other hand, the control circuit 782 sets the control signal CNT2 to the second state when the operation mode information 795 indicates the multiple conversion processing mode. As a result, the operation mode of the image recognition accelerator circuit 749 according to the present modification becomes the multiple conversion processing mode, and the configuration thereof is the image recognition accelerator circuit 549 shown in FIG. 50 and the image processing circuit 573 shown in FIG. The configuration is the same, and the operation of the image recognition accelerator circuit 749 in the multiple conversion processing mode is the same operation as these circuits.

  In the multiple conversion processing mode, for example, coordinate conversion based on the conversion parameter 780 is performed on one target image data 775, and then coordinate conversion based on the conversion parameter 780 is sequentially performed on the generated converted image data 776. Then, one processed image data 777 is generated (see FIG. 54).

  After the camera unit 209 including the image recognition accelerator circuit 749 according to this modification is activated, the host controller 241 makes the qth (q is a variable and q ≧ 1) target image with respect to the image recognition accelerator circuit 749. When setting the data 775 (settings in step S1, step S2, etc. in FIG. 33 described above), the host controller 241 uses the specific information 790 used in the process for the q-th target image data 775 and the q-th data. The operation mode information 795 indicating the operation mode of the image recognition accelerator circuit 749 related to the processing for the target image data 775 is set in the register 783 included in the control circuit 782 of the image recognition accelerator circuit 749.

  In the image recognition accelerator circuit 749, when the specific information 790 and the operation mode information 795 are set in the register 783, the q-th target image data 775 is written from the SRAM 243 to the input frame buffer 771 by DMA transfer. In the coordinate conversion circuit 772, the control circuit 782 controls the control signal CNT1 and the control signal CNT2 to set the operation mode of the image recognition accelerator circuit 749 to the operation mode indicated by the operation mode information 795 of the register 783. . Then, the image recognition accelerator circuit 749 performs processing according to the set operation mode on the q-th target image data 775 stored in the input frame buffer 771.

  When the host controller 241 sets the (q + 1) -th target image data 775 for the image recognition accelerator circuit 749, it is used in the process for the (q + 1) -th target image data 775 in the same manner. Specific information 790 and operation mode information 795 indicating the operation mode of the image recognition accelerator circuit 749 related to the processing for the (q + 1) th target image data 775 are set in the register 783 included in the control circuit 782 of the image recognition accelerator circuit 749. To do.

  As described above, the image recognition accelerator circuit 749 according to the present modification includes the individual conversion processing mode and the multiple conversion processing mode as the operation modes, and therefore, in one camera unit 209, two processes, that is, Both the individual conversion process and the multiple conversion process can be executed.

  In addition, two camera units 209 and gaming machines having the same configuration may be configured such that only individual conversion processing is executed on the one hand and only multiple conversion processing is executed on the other hand.

[Modification 4]
The configuration of the image recognition accelerator circuit 949 (not shown) according to this modification corresponds to the image recognition accelerator circuit 249 shown in FIG. 23, and at least the image processing circuit 273 is changed to the image processing circuit 973. . In addition, the image recognition accelerator circuit 949 includes an input frame buffer 971 corresponding to the input frame buffer 271 of the image recognition accelerator circuit 249 shown in FIG. 23, a coordinate conversion circuit 972 corresponding to the coordinate conversion circuit 272, and a memory corresponding to the memory 274. 974.

  FIG. 57 is a diagram showing a configuration of the image processing circuit 973 of the image recognition accelerator circuit 949 according to this modification. Compared with the image processing circuit 273 shown in FIG. 30 described above, the image processing circuit 973 according to the present modification includes a first read request output unit 1001 corresponding to the first read request output unit 301, and a write request output unit. The storage control unit 1000 includes the write request output unit 1002 corresponding to 302, but does not include the second read request output unit. The image processing circuit 973 in FIG. 57 includes an arbitration unit 1004 corresponding to the arbitration unit 304 of the image processing circuit 273, and the arbitration unit 1004 receives the first read request output from the first read request output unit 1001. The write request output from the write request output unit 1002 is arbitrated, and either the first read request or the write request is selected, and processing corresponding to the selected request is performed.

  Further, the image processing circuit 973 in FIG. 57 includes an addition processing unit 1005 corresponding to the addition processing unit 305, a write buffer 1006 corresponding to the write buffer 306, and a read buffer 307, as compared with the image processing circuit 273 shown in FIG. A corresponding read buffer 1007 and a frame memory 909 corresponding to the frame memory 309 are provided. The addition processing unit 1005 outputs post-conversion image data 976 from the coordinate conversion circuit 972 described above.

  In addition, the image processing circuit 973 according to the present modification includes an output control unit 1008. The output control unit 1008 is read from the frame memory 909, unlike the output control unit 308 of the image processing circuit 273 shown in FIG. Instead of outputting the pixel data of the processed image data 977, the pixel data of the processed image data 977 stored in the write buffer 1006 is output. When the pixel data for four pixels of the processed image data 977, which is the image data to be output, is stored in the write buffer 1006, the output control unit 1008 reads the pixel data for four pixels from the write buffer 1006 and performs DMA transfer. Is output to the SRAM 243. The DMAC 252 controls the processed image data 977 to be DMA transferred from the write buffer 1006 to the SRAM 243.

  When the DMAC 252 includes a buffer, the output control unit 1008 reads the pixel data for four pixels of the processed image data 977 from the write buffer 1006, and the read pixel data for four pixels is stored in the buffer of the DMAC 252. After that, the host controller 241 writes the pixel data for four pixels or the entire processed image data 577 into the SRAM 243.

  In this modification, the write request output unit 1002 exceptionally issues a write request even when the write buffer 1006 is full when the pixel data of the processed image data 977 to be output is stored in the write buffer 1006. Do not output.

  In this way, in the image processing circuit 973 according to the present modification, when the first read request and the write request conflict, the two requests are arbitrated, and therefore the first read request output unit 1001 and The write request output units 1002 can operate independently of each other. Therefore, it is possible to suppress the processing at one of the first read request output unit 1001 and the write request output unit 1002 from becoming a bottleneck. As a result, the overall processing speed of the image recognition accelerator circuit 949 can be improved.

  Further, the output control unit 1008 outputs pixel data of the processed image data 977 that has not been written in the frame memory 909 to the SRAM 243 by DMA transfer. Therefore, compared to the case where the output control unit 1008 outputs the pixel data of the processed image data 977 read from the frame memory 909, the DMAC 252 outputs the output target data (processed image data) output from the addition processing unit 1005. 977) can be received immediately. Therefore, it is possible to reduce the time from when this output target data is generated until it is written to the SRAM 243.

[Other variations]
In the above example, the coordinate conversion circuit 272 and the like have performed a plurality of coordinate conversions using one (one frame) target image data, but only one coordinate conversion is performed on one target image 110. May be performed. Further, the coordinate conversion circuit 272 or the like may repeatedly perform one coordinate conversion on one target image data. For example, in Modification 2 described above, the coordinate conversion circuit 472 performs coordinate conversion on one target image data 475 based on the conversion parameter 480 for rotating the image by 2 °, and then performs the coordinate conversion ( That is, an image obtained by rotating the target image data 475 by 180 ° is obtained as the converted image data 476 by performing 89 times of coordinate conversion with a rotation angle of 2 °.

  Further, all or some of the functions of the coordinate conversion circuit 272 and the like may be realized by a processor (CPU or DSP). Further, all or part of the functions of the image processing circuit 273 and the like may be realized by a processor.

  Further, the image recognition accelerator circuit 249 or the like may not include the image processing circuit 273 or the like. In this case, data output from the coordinate conversion circuit 272 or the like is written into the SRAM 243 by DMA transfer. Further, the image processing circuit 273 may process data other than image data. In the image processing circuit 273 and the like, a processing unit that performs processing other than the addition processing may be provided instead of the addition processing unit.

  As described above, the image recognition accelerator circuit 249 of the camera unit 209 and the modification thereof have been described in detail. However, the above description is merely an example, and the present invention is not limited to such an exemplary configuration. Absent. Further, the various modifications described above can be applied in combination with each other as long as they do not contradict each other.

  Further, in the above-described embodiment and modifications, a pachislot machine has been described as an example of a gaming machine. However, the present invention is not limited to this, and the present invention can also be applied to a gaming machine called “pachinko”. The effect is obtained.

  Heretofore, the gaming machine according to one embodiment of the present invention and the modifications thereof have been described. It is disclosed as an additional note that the gaming machine described above basically has the following characteristics and operational effects.

[Appendix 1-1]
In Embodiment 1-1 of the present invention, a gaming machine having the following configuration is provided.
An insertion slot (for example, medal insertion slot 21) into which a game medium (for example, a medal) is inserted;
Game medium detection means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the insertion slot,
The game medium detection means includes
A game medium passage portion (for example, medal rail 210) serving as a passage through which the game medium passes;
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object that is an object passing through the passage;
By performing image processing based on image data obtained through the imaging means (for example, a captured image 362A acquired by the imaging unit 361), it is determined whether or not the game medium is genuine. Game medium determination means (for example, control LSI 234),
The game medium determining means is
It is configured as a dedicated integrated circuit for determining the game medium,
Direct transfer control means (eg, DMAC 252) for controlling direct transfer of data;
First storage means for storing data (for example, SRAM 243);
The image data obtained via the imaging means is subjected to a predetermined format conversion, and the image data after the format conversion (for example, target image data 275, captured image 362B) is transferred to the first storage means by the direct transfer. Conversion means for storing (for example, conversion unit 363, ISP circuit 245, etc.);
Feature image generation means (for example, a feature image generation unit 364, an image recognition accelerator circuit 249, etc.) for generating a feature image indicating the characteristics of the game medium based on the image data after the format conversion,
The feature image generation means includes
Image data relating to the image data after the format conversion is acquired from the first storage means, image processing including coordinate conversion is performed on the acquired image data (for example, rotation processing of a figure), and the image processing The subsequent image data (for example, processed image data 277, feature image 362C) is stored in the first storage means by the direct transfer.

  With such a configuration of the present invention, the regular medal discrimination process can be executed using the image data acquired by the imaging means. Since each process of image conversion and image recognition performed based on the captured image makes it possible to determine a medal or the like, it is possible to determine a difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, an illegal act from the outside (for example, invalidating the regular medal discrimination process or setting the processing logic of the regular medal discrimination process) (The act of trying to steal)) and has a significant security advantage. In addition, since the writing and reading of image data with respect to the storage means (SRAM, etc.) of the game medium determination means are realized by the direct transfer control means for controlling the direct transfer of data, the host controller ( (Processor) is not involved and each circuit (hardware) included in the game medium determination means can be processed in parallel. As a result, the processing efficiency is improved and the processing time for determining the game medium is shortened.

[Appendix 1-2]
Embodiment 1-2 of the present invention has the following configuration in embodiment 1-1.
The feature image generation means includes
It is configured as a circuit in the game medium determination means,
Second storage means (for example, memory 274) for storing the conversion parameters (for example, conversion parameters 280);
The coordinate conversion is performed based on the conversion parameter acquired from the second storage unit.

  With such a configuration of the present invention, it is possible to appropriately change the content of the coordinate conversion process by changing the conversion parameter. In addition, when performing image processing including coordinate conversion in the feature image generation means, it is possible to obtain conversion parameters by accessing the memory in the circuit, avoiding access via the bus, securing the bus bandwidth, Processing efficiency can be further improved.

[Appendix 1-3]
Embodiment 1-3 of the present invention has the following configuration in Embodiment 1-2.
The feature image generation means includes
Third storage means (for example, register 283) for storing specific information (for example, specific information 290) is provided,
The conversion parameter used for the coordinate conversion is specified based on the specifying information acquired from the third storage unit.

  With such a configuration of the present invention, by changing the specific information, the conversion parameter used for coordinate conversion can be changed as appropriate, and as a result, the processing content of coordinate conversion can be changed.

[Appendix 2-1]
Embodiment 2-1 of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, medal insertion slot 21) into which a game medium (for example, a medal) is inserted;
Game medium detection means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the insertion slot,
The game medium detection means includes
A game medium passage portion (for example, medal rail 210) serving as a passage through which the game medium passes;
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object that is an object passing through the passage;
By performing image processing based on image data obtained through the imaging means (for example, a captured image 362A acquired by the imaging unit 361), it is determined whether or not the game medium is genuine. Game medium determination means (for example, control LSI 234),
The game medium determining means is
It is configured as a dedicated integrated circuit for determining the game medium,
First storage means for storing data (for example, SRAM 243);
Conversion means for performing a predetermined format conversion on the image data obtained via the image pickup means, and storing the image data after the format conversion (for example, target image data 775 and picked-up image 362B) in the first storage means. (For example, the conversion unit 363, the ISP circuit 245, etc.)
Feature image generation means (for example, a feature image generation unit 364, an image recognition accelerator circuit 749, etc.) for generating a feature image indicating the characteristics of the game medium based on the image data after the format conversion,
The feature image generation means includes
Image data related to the image data after the format conversion is acquired from the first storage means, image processing including coordinate conversion is performed on the acquired one image data (for example, rotation processing of a figure), and Image data after image processing (for example, processed image data 777, feature image 362C) is stored in the first storage means,
Including at least two conversion processing modes for the image processing;
In the first conversion processing mode, a plurality of converted image data are generated by individually performing different coordinate conversions on the one image data, and the processed image data is synthesized by combining the plurality of converted image data. It is a conversion processing mode that performs image processing to obtain data,
The second conversion processing mode is a conversion processing mode in which a plurality of coordinate conversions are sequentially and sequentially superimposed on the one image data to perform image processing to obtain one processed image data.
The game medium determination means further includes
Direct transfer control means for controlling direct transfer of data (for example, DMAC 252),
At least one of storage in the first storage unit of the image data after the format conversion in the conversion unit, and storage in the first storage unit of the image data after the image processing in the feature image generation unit, This is done by the direct transfer.

  With such a configuration of the present invention, the regular medal discrimination process can be executed using the image data acquired by the imaging means. Since each process of image conversion and image recognition performed based on the captured image makes it possible to determine a medal or the like, it is possible to determine a difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, an illegal act from the outside (for example, invalidating the regular medal discrimination process or setting the processing logic of the regular medal discrimination process) (The act of trying to steal)) and has a significant security advantage. In addition, since there are at least two conversion processing modes for image processing for generating a characteristic image of a game medium used for determination of the game medium, the conversion processing mode can be switched according to the characteristics and situation of the game medium. it can. Furthermore, since the writing and reading of the image data with respect to the storage means (SRAM or the like) of the game medium determination means is realized by the direct transfer control means that controls the direct transfer of data, the host controller ( (Processor) is not involved and each circuit (hardware) included in the game medium determination means can be processed in parallel. As a result, the processing efficiency is improved and the processing time for determining the game medium is shortened.

[Appendix 2-2]
Embodiment 2-2 of the present invention has the following configuration in Embodiment 2-1.
The feature image generation means includes
It is configured as a circuit in the game medium determination means,
Second storage means (for example, memory 774) for storing the conversion parameters (for example, conversion parameters 780);
The coordinate conversion is performed based on the conversion parameter acquired from the second storage unit.

  With such a configuration of the present invention, it is possible to appropriately change the content of the coordinate conversion process by changing the conversion parameter. In addition, when performing image processing including coordinate conversion in the feature image generation means, it is possible to obtain conversion parameters by accessing the memory in the circuit, avoiding access via the bus, securing the bus bandwidth, Processing efficiency can be further improved.

[Appendix 2-3]
Embodiment 2-3 of the present invention has the following configuration in Embodiment 2-2.
The conversion parameter is configured to be a parameter that specifies coordinate conversion related to rotation at a predetermined angle.

  With such a configuration of the present invention, it is possible to set so that the figure represented by the image data is rotated by a predetermined angle by the conversion parameter.

[Appendix 2-4]
Embodiment 2-4 of the present invention has the following configuration in any of Embodiment 2-1 to Embodiment 2-3.
The feature image generation means includes
It is configured as a circuit in the game medium determination means,
Third storage means (for example, memory 774) for storing operation mode information (for example, operation mode information 795) is provided,
The conversion processing mode is configured to be determined based on the operation mode information.

  With such a configuration of the present invention, the conversion processing mode can be switched by changing the operation mode information.

[Appendix 2-5]
Embodiment 2-5 of the present invention has the following configuration in Embodiment 2-4.
The operation mode information is configured to be set for each of the image data obtained via the imaging unit.

  With such a configuration of the present invention, the conversion processing mode can be switched for each captured image of the game medium, and a characteristic image corresponding to the situation can be obtained.

[Appendix 3-1]
Embodiment 3-1 of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, medal insertion slot 21) into which a game medium (for example, a medal) is inserted;
Game medium detection means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the insertion slot,
The game medium detection means includes
A game medium passage portion (for example, medal rail 210) serving as a passage through which the game medium passes;
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object that is an object passing through the passage;
By performing image processing based on image data obtained through the imaging means (for example, a captured image 362A acquired by the imaging unit 361), it is determined whether or not the game medium is genuine. Game medium determination means (for example, control LSI 234),
The game medium determining means is
It is configured as a dedicated integrated circuit for determining the game medium,
First storage means for storing data (for example, SRAM 243);
A conversion unit that performs a predetermined format conversion on the image data obtained through the imaging unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.)
Feature image generation means (for example, a feature image generation unit 364, an image recognition accelerator circuit 249, etc.) for generating a feature image indicating the characteristics of the game medium based on the image data after the format conversion,
The feature image generation means includes
Image data relating to the image data after the format conversion is acquired from the first storage means, image processing including coordinate conversion is performed on the acquired image data, and the image data after the image processing is converted into the first data. Memorize it in the memory means,
The processing content of the coordinate transformation is specified by a transformation parameter (for example, transformation parameter 280),
The game medium determination means further includes
Direct transfer control means for controlling direct transfer of data (for example, DMAC 252),
At least one of storage in the first storage unit of the image data after the format conversion in the conversion unit, and storage in the first storage unit of the image data after the image processing in the feature image generation unit, This is done by the direct transfer.

  With such a configuration of the present invention, the regular medal discrimination process can be executed using the image data acquired by the imaging means. Since each process of image conversion and image recognition performed based on the captured image makes it possible to determine a medal or the like, it is possible to determine a difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, an illegal act from the outside (for example, invalidating the regular medal discrimination process or setting the processing logic of the regular medal discrimination process) (The act of trying to steal)) and has a significant security advantage. In addition, by changing the conversion parameter, the content of the coordinate conversion process can be changed as appropriate. Furthermore, since the writing and reading of the image data with respect to the storage means (SRAM or the like) of the game medium determination means is realized by the direct transfer control means that controls the direct transfer of data, the host controller ( (Processor) is not involved and each circuit (hardware) included in the game medium determination means can be processed in parallel. As a result, the processing efficiency is improved and the processing time for determining the game medium is shortened.

[Appendix 3-2]
Embodiment 3-2 of the present invention has the following configuration in Embodiment 3-1.
The feature image generation means includes
It is configured as a circuit in the game medium determination means,
Second storage means (for example, a memory 274) for storing the conversion parameter;
The coordinate conversion is performed based on the conversion parameter acquired from the second storage unit.

  With such a configuration of the present invention, when image processing including coordinate conversion is performed in the feature image generation means, conversion parameters can be acquired by accessing the memory in the circuit, and access via the bus is avoided. Thus, the bus bandwidth can be secured and the processing efficiency can be further improved.

[Appendix 3-3]
Embodiment 3-3 of the present invention has the following configuration in Embodiment 3-1 or Embodiment 3-2.
The conversion parameter is configured to indicate at least one of coordinate conversion related to rotation, coordinate conversion related to enlargement, coordinate conversion related to reduction, and coordinate conversion related to parallel movement.

  According to such a configuration of the present invention, it is possible to instruct coordinate conversion related to rotation, coordinate conversion related to enlargement, coordinate conversion related to reduction, and coordinate conversion related to parallel movement by the conversion parameter.

[Appendix 4-1]
In Embodiment 4-1 of the present invention, a gaming machine having the following configuration is provided.
An insertion slot (for example, medal insertion slot 21) into which a game medium (for example, a medal) is inserted;
Game medium detection means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the insertion slot,
The game medium detection means includes
A game medium passage portion (for example, medal rail 210) serving as a passage through which the game medium passes;
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object that is an object passing through the passage;
By performing image processing based on image data obtained through the imaging means (for example, a captured image 362A acquired by the imaging unit 361), it is determined whether or not the game medium is genuine. Game medium determination means (for example, control LSI 234),
The game medium determining means is
It is configured as a dedicated integrated circuit for determining the game medium,
First storage means for storing data (for example, SRAM 243);
A conversion unit that performs a predetermined format conversion on the image data obtained through the imaging unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.)
Feature image generation means (for example, a feature image generation unit 364, an image recognition accelerator circuit 449, etc.) for generating a feature image indicating the characteristics of the game medium based on the image data after the format conversion,
The feature image generation means includes
It is configured as a circuit in the game medium determination means,
Second storage means (eg, memory 474) for storing conversion parameters (eg, conversion parameters 480);
A conversion circuit (for example, a conversion circuit 481) that acquires image data related to the image data after the format conversion from the first storage unit, and performs image processing including coordinate conversion on the acquired image data;
A control circuit (eg, control circuit 482) that stores a parameter offset (eg, parameter offset 495);
An addition circuit (for example, an addition circuit 485) that adds the conversion parameter and the parameter offset under the control of the control circuit and outputs the addition result to the conversion circuit;
The conversion circuit performs the coordinate conversion based on the addition result by the addition circuit,
The game medium determination means further includes
Direct transfer control means for controlling direct transfer of data (for example, DMAC 252),
Storage of the image data after the format conversion in the conversion means in the first storage means, and storage of the image data related to the image data after the image processing obtained by the conversion circuit in the first storage means. At least one of them is performed by the direct transfer.

  With such a configuration of the present invention, the regular medal discrimination process can be executed using the image data acquired by the imaging means. Since each process of image conversion and image recognition performed based on the captured image makes it possible to determine a medal or the like, it is possible to determine a difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, an illegal act from the outside (for example, invalidating the regular medal discrimination process or setting the processing logic of the regular medal discrimination process) (The act of trying to steal)) and has a significant security advantage. Also, by adding the conversion parameter and the parameter offset, the coordinate conversion performed based on the conversion parameter can be changed in consideration of the content of the parameter offset. Furthermore, since the writing and reading of the image data with respect to the storage means (SRAM or the like) of the game medium determination means is realized by the direct transfer control means that controls the direct transfer of data, the host controller ( (Processor) is not involved and each circuit (hardware) included in the game medium determination means can be processed in parallel. As a result, the processing efficiency is improved and the processing time for determining the game medium is shortened.

[Appendix 4-2]
Embodiment 4-2 of the present invention has the following configuration in embodiment 4-1.
The conversion parameter includes a plurality of coordinates before conversion corresponding to predetermined coordinates after conversion,
The parameter offset is configured to include offsets for a plurality of coordinates before the conversion.

  With such a configuration of the present invention, by adding the conversion parameter and the parameter offset, the coordinate conversion performed based on the conversion parameter can be controlled to be shifted by the amount specified by the parameter offset.

[Appendix 5-1]
Embodiment 5-1 of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, medal insertion slot 21) into which a game medium (for example, a medal) is inserted;
Game medium detection means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the insertion slot,
The game medium detection means includes
A game medium passage portion (for example, medal rail 210) serving as a passage through which the game medium passes;
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object that is an object passing through the passage;
By performing image processing based on image data obtained through the imaging means (for example, a captured image 362A acquired by the imaging unit 361), it is determined whether or not the game medium is genuine. Game medium determination means (for example, control LSI 234),
The game medium determining means is
It is configured as a dedicated integrated circuit for determining the game medium,
A processor (eg, host controller 241);
First storage means for storing data (for example, SRAM 243);
A conversion unit that performs a predetermined format conversion on the image data obtained through the imaging unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.)
Feature image generation means (for example, a feature image generation unit 364, an image recognition accelerator circuit 249, etc.) for generating a feature image indicating the characteristics of the game medium based on the image data after the format conversion,
The feature image generation means includes
It is configured as a circuit in the game medium determination means,
Second storage means (eg, memory 274) for storing conversion parameters (eg, conversion parameters 280);
A conversion circuit (for example, a conversion circuit 281) that acquires image data related to the image data after the format conversion from the first storage unit, and performs image processing including coordinate conversion on the acquired image data;
A control circuit (e.g., control circuit 282) that controls to obtain the conversion parameter from the second storage means and output it to the conversion circuit;
The conversion circuit performs the coordinate conversion based on the conversion parameter,
The processor controls the conversion parameter to be stored in the second storage unit at a predetermined timing;
The game medium determination means further includes
Direct transfer control means for controlling direct transfer of data (for example, DMAC 252),
At least one of storage of the image data after the format conversion in the conversion unit in the first storage unit and storage of image data related to the image data after the image processing in the conversion circuit in the first storage unit. Is performed by the direct transfer.

  With such a configuration of the present invention, the regular medal discrimination process can be executed using the image data acquired by the imaging means. Since each process of image conversion and image recognition performed based on the captured image makes it possible to determine a medal or the like, it is possible to determine a difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, an illegal act from the outside (for example, invalidating the regular medal discrimination process or setting the processing logic of the regular medal discrimination process) (The act of trying to steal)) and has a significant security advantage. In addition, by storing the conversion parameters in the circuit of the feature image generation unit and changing the conversion parameters, the processing content of the coordinate conversion can be changed as appropriate. Furthermore, since the writing and reading of the image data with respect to the storage means (SRAM or the like) of the game medium determination means is realized by the direct transfer control means that controls the direct transfer of data, the host controller ( (Processor) is not involved and each circuit (hardware) included in the game medium determination means can be processed in parallel. As a result, the processing efficiency is improved and the processing time for determining the game medium is shortened.

[Appendix 5-2]
Embodiment 5-2 of the present invention has the following configuration in embodiment 5-1.
The predetermined timing is configured to be an initial setting timing of the game medium determination means.

  With such a configuration of the present invention, when the conversion parameter is copied into the circuit at a predetermined timing and the conversion parameter is referred to at the time of coordinate conversion, access to the bus is suppressed.

[Appendix 5-3]
Embodiment 5-3 of the present invention has the following configuration in Embodiment 5-1 or Embodiment 5-2.
The processor is configured to copy only the conversion parameters used for coordinate conversion in the feature image generation means from among the conversion parameters stored in the first storage means and store them in the second storage means. Is done.

  With this configuration of the present invention, common conversion parameters are prepared in the first storage means, and only necessary conversion parameters are copied to the memory in the circuit, so that the control LSI can be manufactured in common. The memory in the circuit can be used effectively.

[Appendix 6-1]
In Embodiment 6-1 of the present invention, a gaming machine having the following configuration is provided.
An insertion slot (for example, medal insertion slot 21) into which a game medium (for example, a medal) is inserted;
Game medium detection means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the insertion slot,
The game medium detection means includes
A game medium passage portion (for example, medal rail 210) serving as a passage through which the game medium passes;
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object that is an object passing through the passage;
By performing image processing based on image data obtained through the imaging means (for example, a captured image 362A acquired by the imaging unit 361), it is determined whether or not the game medium is genuine. Game medium determination means (for example, control LSI 234),
The game medium determining means is
It is configured as a dedicated integrated circuit for determining the game medium,
First storage means for storing data (for example, SRAM 243);
A conversion unit that performs a predetermined format conversion on the image data obtained through the imaging unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.)
Feature image generation means (for example, feature image generation unit 364, image recognition accelerator circuit 249, etc.) that generates a feature image (for example, feature image 362C) indicating the feature of the game medium based on the image data after the format conversion. And comprising
The feature image generation means includes
It is configured as a circuit in the game medium determination means,
Second storage means (eg, memory 274) for storing conversion parameters (eg, conversion parameters 280);
A conversion circuit (for example, a conversion circuit 281) that performs coordinate conversion on the image data related to the image data after the format conversion acquired from the first storage unit;
A control circuit (for example, control circuit 282) that controls to obtain the conversion parameter from the second storage means and output the conversion parameter to the conversion circuit;
An image processing circuit (for example, image processing) that acquires image data after the coordinate conversion from the conversion circuit, performs image processing, and stores image data to be output (for example, processed image data 277) in the first storage unit. Circuit 273),
The conversion circuit performs the coordinate conversion based on the conversion parameter,
The image processing circuit includes:
A third storage unit (for example, a frame memory 309) that temporarily stores image data related to the image data after the coordinate conversion for the image processing;
A first read request output unit (for example, a first read request output unit 301) that outputs a request to read image data to be subjected to image processing from the third storage unit;
A write request output unit (for example, a write request output unit 302) that outputs a request to write the image data after the image processing into the third storage unit;
When the image data after the image processing is the output target image data, a second read request output unit (for example, a second read request output unit) that outputs a request to read the image data after the image processing from the third storage unit A read request output unit 303);
An arbitration unit (for example, an arbitration unit 304) that performs arbitration so that the requests output from the first read request output unit, the write request output unit, and the second read request output unit do not compete with each other; Prepare.

  With such a configuration of the present invention, the regular medal discrimination process can be executed using the image data acquired by the imaging means. Since each process of image conversion and image recognition performed based on the captured image makes it possible to determine a medal or the like, it is possible to determine a difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, an illegal act from the outside (for example, invalidating the regular medal discrimination process or setting the processing logic of the regular medal discrimination process) (The act of trying to steal)) and has a significant security advantage. In addition, by providing the arbitration unit, it is possible to avoid contention of access requests for the third storage unit for image processing.

[Appendix 6-2]
Embodiment 6-2 of the present invention has the following configuration in embodiment 6-1.
The game medium determining means further includes direct transfer control means (for example, DMAC 252) for controlling direct transfer of data,
At least one of storage of the image data after the format conversion in the conversion unit in the first storage unit and storage of the image data to be output in the image processing circuit in the first storage unit is the direct Configured to be done by transfer.

  With such a configuration of the present invention, writing and reading of image data to and from the storage means (SRAM or the like) of the game medium determination means is realized by the direct transfer control means that controls the direct transfer of data. The host controller (processor) of the medium determination means is not involved, and the parallel processing of each circuit (hardware) included in the game medium determination means is possible. As a result, the processing efficiency is improved and the processing time relating to the determination of the game medium Is shortened.

[Appendix 7-1]
In Embodiment 7-1 of the present invention, a gaming machine having the following configuration is provided.
An insertion slot (for example, medal insertion slot 21) into which a game medium (for example, a medal) is inserted;
Game medium detection means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the insertion slot,
The game medium detection means includes
A game medium passage portion (for example, medal rail 210) serving as a passage through which the game medium passes;
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object that is an object passing through the passage;
By performing image processing based on image data obtained through the imaging means (for example, a captured image 362A acquired by the imaging unit 361), it is determined whether or not the game medium is genuine. Game medium determination means (for example, control LSI 234),
The game medium determining means is
It is configured as a dedicated integrated circuit for determining the game medium,
First storage means for storing data (for example, SRAM 243);
A conversion unit that performs a predetermined format conversion on the image data obtained through the imaging unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.)
Feature image generation means (for example, feature image generation unit 364, image recognition accelerator circuit 949, etc.) that generates a feature image (for example, feature image 362C) indicating the feature of the game medium based on the image data after the format conversion. And comprising
The feature image generation means includes
It is configured as a circuit in the game medium determination means,
Second storage means (eg, memory 274) for storing conversion parameters (eg, conversion parameters 280);
A conversion circuit (for example, a conversion circuit 281) that performs coordinate conversion on the image data related to the image data after the format conversion acquired from the first storage unit;
A control circuit (for example, control circuit 282) that controls to obtain the conversion parameter from the second storage means and output the conversion parameter to the conversion circuit;
An image processing circuit (for example, image processing) that acquires image data after the coordinate conversion from the conversion circuit, performs image processing, and stores output target image data (for example, processed image data 977) in the first storage means. Circuit 973), and
The conversion circuit performs the coordinate conversion based on the conversion parameter,
The image processing circuit includes:
A third storage unit (for example, a frame memory 909) for temporarily storing image data related to the image data after the coordinate conversion for the image processing;
A first read request output unit (for example, a first read request output unit 1001) that outputs a request to read image data to be subjected to image processing from the third storage unit;
A write request output unit (for example, a write request output unit 1002) that outputs a request to write the image data after the image processing into the third storage unit;
An arbitration unit (for example, an arbitration unit 1004) that performs arbitration so that the requests output from the first read request output unit and the write request output unit do not compete with each other;
When the image data after the image processing is the image data to be output, an output control unit (for example, an output control unit 1008) that controls to store the image data after the image processing in the first storage unit And comprising.

  With such a configuration of the present invention, the regular medal discrimination process can be executed using the image data acquired by the imaging means. Since each process of image conversion and image recognition performed based on the captured image makes it possible to determine a medal or the like, it is possible to determine a difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, an illegal act from the outside (for example, invalidating the regular medal discrimination process or setting the processing logic of the regular medal discrimination process) (The act of trying to steal)) and has a significant security advantage. In addition, by providing the arbitration unit, it is possible to avoid contention of access requests for the third storage unit for image processing.

[Appendix 7-2]
Embodiment 7-2 of the present invention has the following configuration in Embodiment 7-1.
The game medium determining means further includes direct transfer control means (for example, DMAC 252) for controlling direct transfer of data,
At least one of storage of the image data after the format conversion in the conversion unit in the first storage unit and storage of the image data after the image processing in the output control unit in the first storage unit is Configured to be done by direct transfer.

  With such a configuration of the present invention, writing and reading of image data to and from the storage means (SRAM or the like) of the game medium determination means is realized by the direct transfer control means that controls the direct transfer of data. The host controller (processor) of the medium determination means is not involved, and the parallel processing of each circuit (hardware) included in the game medium determination means is possible. As a result, the processing efficiency is improved and the processing time relating to the determination of the game medium Is shortened.

[Appendix 8-1]
In Embodiment 8-1 of the present invention, a gaming machine having the following configuration is provided.
An insertion slot (for example, medal insertion slot 21) into which a game medium (for example, a medal) is inserted;
Game medium detection means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the insertion slot,
The game medium detection means includes
A game medium passage portion (for example, medal rail 210) serving as a passage through which the game medium passes;
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object that is an object passing through the passage;
By performing image processing based on image data obtained through the imaging means (for example, a captured image 362A acquired by the imaging unit 361), it is determined whether or not the game medium is genuine. Game medium determination means (for example, control LSI 234),
The game medium determining means is
It is configured as a dedicated integrated circuit for determining the game medium,
First storage means for storing data (for example, SRAM 243);
A conversion unit that performs a predetermined format conversion on the image data obtained through the imaging unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.)
Feature image generation means (for example, feature image generation unit 364, image recognition accelerator circuit 249, etc.) that generates a feature image (for example, feature image 362C) indicating the feature of the game medium based on the image data after the format conversion. And comprising
The feature image generation means includes
It is configured as a circuit in the game medium determination means,
Second storage means (eg, memory 274) for storing conversion parameters (eg, conversion parameters 280);
A conversion circuit (for example, a conversion circuit 281) that performs coordinate conversion on the image data related to the image data after the format conversion acquired from the first storage unit;
A control circuit (for example, control circuit 282) that controls to obtain the conversion parameter from the second storage means and output the conversion parameter to the conversion circuit;
An image processing circuit (for example, image processing) that acquires image data after the coordinate conversion from the conversion circuit, performs image processing, and stores image data to be output (for example, processed image data 277) in the first storage unit. Circuit 273),
The conversion circuit performs the coordinate conversion based on the conversion parameter,
The image processing circuit includes:
A third storage unit (for example, a frame memory 309) that temporarily stores image data related to the image data after the coordinate conversion for the image processing;
A first read request output unit (for example, a first read request output unit 301) that outputs a request to read image data to be subjected to image processing from the third storage unit;
A write request output unit (for example, a write request output unit 302) that outputs a request to write the image data after the image processing into the third storage unit;
When the image data after the image processing is the output target image data, a second read request output unit (for example, a second read request output unit) that outputs a request to read the image data after the image processing from the third storage unit A read request output unit 303);
An arbitration unit (for example, an arbitration unit 304) that performs arbitration so that the requests output from the first read request output unit, the write request output unit, and the second read request output unit do not compete with each other; Prepared,
The arbitration unit is related to each output unit of the first read request output unit, the write request output unit, and the second read request output unit, or the first read request output unit and the write request output unit. , And the priority assigned to each request output from the second read request output unit.

  With such a configuration of the present invention, the regular medal discrimination process can be executed using the image data acquired by the imaging means. Since each process of image conversion and image recognition performed based on the captured image makes it possible to determine a medal or the like, it is possible to determine a difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, an illegal act from the outside (for example, invalidating the regular medal discrimination process or setting the processing logic of the regular medal discrimination process) (The act of trying to steal)) and has a significant security advantage. Further, by providing an arbitration unit, it is possible to avoid contention for access requests to the third storage unit for image processing, and arbitration by the arbitration unit is performed based on priority.

[Appendix 8-2]
Embodiment 8-2 of the present invention has the following configuration in Embodiment 8-1.
The game medium determining means further includes direct transfer control means (for example, DMAC 252) for controlling direct transfer of data,
At least one of storage of the image data after the format conversion in the conversion unit in the first storage unit and storage of the image data to be output in the image processing circuit in the first storage unit is the direct Configured to be done by transfer.

  With such a configuration of the present invention, writing and reading of image data to and from the storage means (SRAM or the like) of the game medium determination means is realized by the direct transfer control means that controls the direct transfer of data. The host controller (processor) of the medium determination means is not involved, and the parallel processing of each circuit (hardware) included in the game medium determination means is possible. As a result, the processing efficiency is improved and the processing time relating to the determination of the game medium Is shortened.

[Appendix 8-3]
Embodiment 8-3 of the present invention has the following configuration in Embodiment 8-1 or Embodiment 8-2.
The priority is configured to be changed by a user's operation or according to an operation state of the game medium determination unit.

  With such a configuration of the present invention, the priority can be set in accordance with, for example, the setting of the user, or set in accordance with the bus usage rate of the game medium determining means. The processing time relating to the determination of the game medium is effectively shortened by the priority.

[Appendix 9-1]
In Embodiment 9-1 of the present invention, a gaming machine having the following configuration is provided.
An insertion slot (for example, medal insertion slot 21) into which a game medium (for example, a medal) is inserted;
Game medium detection means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the insertion slot,
The game medium detection means includes
A game medium passage portion (for example, medal rail 210) serving as a passage through which the game medium passes;
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object that is an object passing through the passage;
By performing image processing based on image data obtained through the imaging means (for example, a captured image 362A acquired by the imaging unit 361), it is determined whether or not the game medium is genuine. Game medium determination means (for example, control LSI 234),
The game medium determining means is
It is configured as a dedicated integrated circuit for determining the game medium,
First storage means for storing data (for example, SRAM 243);
A conversion unit that performs a predetermined format conversion on the image data obtained through the imaging unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.)
Feature image generation means (for example, feature image generation unit 364, image recognition accelerator circuit 249, etc.) that generates a feature image (for example, feature image 362C) indicating the feature of the game medium based on the image data after the format conversion. And comprising
The feature image generation means includes
It is configured as a circuit in the game medium determination means,
Second storage means (eg, memory 274) for storing conversion parameters (eg, conversion parameters 280);
A conversion circuit (for example, a conversion circuit 281) that performs coordinate conversion on the image data related to the image data after the format conversion acquired from the first storage unit;
A control circuit (for example, control circuit 282) that controls to obtain the conversion parameter from the second storage means and output the conversion parameter to the conversion circuit;
An image processing circuit (for example, image processing) that acquires image data after the coordinate conversion from the conversion circuit, performs image processing, and stores image data to be output (for example, processed image data 277) in the first storage unit. Circuit 273),
The conversion circuit performs the coordinate conversion based on the conversion parameter,
The image processing circuit includes:
A third storage unit (for example, a frame memory 309) that temporarily stores image data related to the image data after the coordinate conversion for the image processing;
A first read request output unit (for example, a first read request output unit 301) that outputs a request to read image data to be subjected to image processing from the third storage unit;
A write request output unit (for example, a write request output unit 302) that outputs a request to write the image data after the image processing into the third storage unit;
When the image data after the image processing is the output target image data, a second read request output unit (for example, a second read request output unit) that outputs a request to read the image data after the image processing from the third storage unit A read request output unit 303),
The third storage means is a one-port memory;
The image data after the image processing is written in a predetermined position of the third storage unit based on a request by the write request output unit,
The third storage means in which the predetermined position is image data read based on a request from the first read request output unit, and image data corresponding to the image data after the image processing is stored. Position.

  With such a configuration of the present invention, the regular medal discrimination process can be executed using the image data acquired by the imaging means. Since each process of image conversion and image recognition performed based on the captured image makes it possible to determine a medal or the like, it is possible to determine a difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, an illegal act from the outside (for example, invalidating the regular medal discrimination process or setting the processing logic of the regular medal discrimination process) (The act of trying to steal)) and has a significant security advantage. Further, when image data after image processing is written to the third storage means, the pixel data of the processed image data is stored in the same position as the storage position of the third storage means stored before the image processing (Read Modify). Therefore, the circuit scale of the third storage means can be reduced.

[Appendix 9-2]
Embodiment 9-2 of the present invention has the following configuration in Embodiment 9-1.
The game medium determining means further includes direct transfer control means (for example, DMAC 252) for controlling direct transfer of data,
At least one of storage of the image data after the format conversion in the conversion unit in the first storage unit and storage of the image data to be output in the image processing circuit in the first storage unit is the direct Configured to be done by transfer.

  With such a configuration of the present invention, writing and reading of image data to and from the storage means (SRAM or the like) of the game medium determination means is realized by the direct transfer control means that controls the direct transfer of data. The host controller (processor) of the medium determination means is not involved, and the parallel processing of each circuit (hardware) included in the game medium determination means is possible. As a result, the processing efficiency is improved and the processing time relating to the determination of the game medium Is shortened.

[Appendix 9-3]
Embodiment 9-3 of the present invention has the following configuration in Embodiment 9-1 or Embodiment 9-2.
The image data after the image processing written in the third storage unit based on the request from the write request output unit is an image to be subjected to the image processing based on the request from the first read request output unit. Data is read from the third storage means.

  With such a configuration of the present invention, the image data after image processing written in the third storage means is read again from the third storage means as the object of image processing, so the circuit scale of the third storage means is reduced. can do.

[Appendix 10-1]
In the embodiment 10-1 of the present invention, a gaming machine having the following configuration is provided.
An insertion slot (for example, medal insertion slot 21) into which a game medium (for example, a medal) is inserted;
Game medium detection means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the insertion slot,
The game medium detection means includes
A game medium passage portion (for example, medal rail 210) serving as a passage through which the game medium passes;
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object that is an object passing through the passage;
By performing image processing based on image data obtained through the imaging means (for example, a captured image 362A acquired by the imaging unit 361), it is determined whether or not the game medium is genuine. Game medium determination means (for example, control LSI 234),
The game medium determining means is
It is configured as a dedicated integrated circuit for determining the game medium,
First storage means for storing data (for example, SRAM 243);
A conversion unit that performs a predetermined format conversion on the image data obtained through the imaging unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.)
Feature image generation means (for example, feature image generation unit 364, image recognition accelerator circuit 249, etc.) that generates a feature image (for example, feature image 362C) indicating the feature of the game medium based on the image data after the format conversion. And comprising
The feature image generation means includes
It is configured as a circuit in the game medium determination means,
Second storage means (eg, memory 274) for storing conversion parameters (eg, conversion parameters 280);
A conversion circuit (for example, a conversion circuit 281) that performs coordinate conversion on the image data related to the image data after the format conversion acquired from the first storage unit;
A control circuit (for example, control circuit 282) that controls to obtain the conversion parameter from the second storage means and output the conversion parameter to the conversion circuit;
An image processing circuit (for example, image processing) that acquires image data after the coordinate conversion from the conversion circuit, performs image processing, and stores image data to be output (for example, processed image data 277) in the first storage unit. Circuit 273),
The conversion circuit performs the coordinate conversion based on the conversion parameter,
The image processing circuit includes:
A third storage unit (for example, a frame memory 309) that temporarily stores image data related to the image data after the coordinate conversion for the image processing;
A first read request output unit (for example, a first read request output unit 301) that outputs a request to read image data to be subjected to image processing from the third storage unit;
A write request output unit (for example, a write request output unit 302) that outputs a request to write the image data after the image processing into the third storage unit;
When the image data after the image processing is the output target image data, a second read request output unit (for example, a second read request output unit) that outputs a request to read the image data after the image processing from the third storage unit A read request output unit 303);
A buffer (for example, a read buffer 307) that temporarily stores image data to be subjected to the image processing read from the third storage unit based on a request from the first read request output unit;
The first read request output unit outputs a request to read image data to be subjected to the image processing from the third storage unit when the buffer is empty.

  With such a configuration of the present invention, the regular medal discrimination process can be executed using the image data acquired by the imaging means. Since each process of image conversion and image recognition performed based on the captured image makes it possible to determine a medal or the like, it is possible to determine a difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, an illegal act from the outside (for example, invalidating the regular medal discrimination process or setting the processing logic of the regular medal discrimination process) (The act of trying to steal)) and has a significant security advantage. In addition, since the first read request output unit outputs a request to read image data to be subjected to image processing from the third storage unit when the read buffer is empty, the circuit scale of the read buffer can be reduced. The reading timing of the image data is determined by an independent and effective standard.

[Appendix 10-2]
Embodiment 10-2 of the present invention has the following configuration in Embodiment 10-1.
The game medium determining means further includes direct transfer control means (for example, DMAC 252) for controlling direct transfer of data,
At least one of storage of the image data after the format conversion in the conversion unit in the first storage unit and storage of the image data to be output in the image processing circuit in the first storage unit is the direct Configured to be done by transfer.

  With such a configuration of the present invention, writing and reading of image data to and from the storage means (SRAM or the like) of the game medium determination means is realized by the direct transfer control means that controls the direct transfer of data. The host controller (processor) of the medium determination means is not involved, and the parallel processing of each circuit (hardware) included in the game medium determination means is possible. As a result, the processing efficiency is improved and the processing time relating to the determination of the game medium Is shortened.

[Appendix 10-3]
Embodiment 10-3 of the present invention has the following configuration in Embodiment 10-1 or Embodiment 10-2.
When the image data targeted for image processing stored in the buffer is read out for the image processing, the image data targeted for image processing is erased from the buffer.

  With this configuration of the present invention, when image data to be subjected to image processing is read out for image processing, the image data is erased from the read buffer, so that the image data is read out immediately. In addition, a request from the first read request output unit can be made, and as a result, the image data is efficiently read into the read buffer.

[Appendix 11-1]
In the embodiment 11-1 of the present invention, a gaming machine having the following configuration is provided.
An insertion slot (for example, medal insertion slot 21) into which a game medium (for example, a medal) is inserted;
Game medium detection means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the insertion slot,
The game medium detection means includes
A game medium passage portion (for example, medal rail 210) serving as a passage through which the game medium passes;
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object that is an object passing through the passage;
By performing image processing based on image data obtained through the imaging means (for example, a captured image 362A acquired by the imaging unit 361), it is determined whether or not the game medium is genuine. Game medium determination means (for example, control LSI 234),
The game medium determining means is
It is configured as a dedicated integrated circuit for determining the game medium,
First storage means for storing data (for example, SRAM 243);
A conversion unit that performs a predetermined format conversion on the image data obtained through the imaging unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.)
Feature image generation means (for example, feature image generation unit 364, image recognition accelerator circuit 249, etc.) that generates a feature image (for example, feature image 362C) indicating the feature of the game medium based on the image data after the format conversion. And comprising
The feature image generation means includes
It is configured as a circuit in the game medium determination means,
Second storage means (eg, memory 274) for storing conversion parameters (eg, conversion parameters 280);
A conversion circuit (for example, a conversion circuit 281) that performs coordinate conversion on the image data related to the image data after the format conversion acquired from the first storage unit;
A control circuit (for example, control circuit 282) that controls to obtain the conversion parameter from the second storage means and output the conversion parameter to the conversion circuit;
An image processing circuit (for example, image processing) that acquires image data after the coordinate conversion from the conversion circuit, performs image processing, and stores image data to be output (for example, processed image data 277) in the first storage unit. Circuit 273),
The conversion circuit performs the coordinate conversion based on the conversion parameter,
The image processing circuit includes:
A third storage unit (for example, a frame memory 309) that temporarily stores image data related to the image data after the coordinate conversion for the image processing;
A first read request output unit (for example, a first read request output unit 301) that outputs a request to read image data to be subjected to image processing from the third storage unit;
A write request output unit (for example, a write request output unit 302) that outputs a request to write the image data after the image processing into the third storage unit;
When the image data after the image processing is the output target image data, a second read request output unit (for example, a second read request output unit) that outputs a request to read the image data after the image processing from the third storage unit A read request output unit 303);
A buffer (for example, a write buffer 306) that temporarily stores the image data after the image processing,
The write request output unit reads the image data after the image processing from the buffer when the predetermined amount of image data is stored in the buffer (for example, when the write buffer 306 is full). A request to write to the storage means is output.

  With such a configuration of the present invention, the regular medal discrimination process can be executed using the image data acquired by the imaging means. Since each process of image conversion and image recognition performed based on the captured image makes it possible to determine a medal or the like, it is possible to determine a difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, an illegal act from the outside (for example, invalidating the regular medal discrimination process or setting the processing logic of the regular medal discrimination process) (The act of trying to steal)) and has a significant security advantage. Further, since the write request output unit outputs a request to write the image data after image processing to the third storage means when the write buffer is full, the circuit scale of the write buffer can be reduced. The writing timing of the image data is determined by an independent and effective standard.

[Appendix 11-2]
Embodiment 11-2 of the present invention has the following configuration in Embodiment 11-1.
The game medium determining means further includes direct transfer control means (for example, DMAC 252) for controlling direct transfer of data,
At least one of storage of the image data after the format conversion in the conversion unit in the first storage unit and storage of the image data to be output in the image processing circuit in the first storage unit is the direct Configured to be done by transfer.

  With such a configuration of the present invention, writing and reading of image data to and from the storage means (SRAM or the like) of the game medium determination means is realized by the direct transfer control means that controls the direct transfer of data. The host controller (processor) of the medium determination means is not involved, and the parallel processing of each circuit (hardware) included in the game medium determination means is possible. As a result, the processing efficiency is improved and the processing time relating to the determination of the game medium Is shortened.

[Appendix 11-3]
Embodiment 11-3 of the present invention has the following configuration in Embodiment 11-1 or Embodiment 11-2.
The image data after the image processing is erased from the buffer when the image data after the image processing stored in the buffer is written in the third storage means.

  With such a configuration of the present invention, when image data to be subjected to image processing is written in the third storage means, the image data is erased from the write buffer, so immediately after the image data is written, Requests from the write request output unit can be made, and as a result, efficient writing of image data to the write buffer is sequentially performed.

DESCRIPTION OF SYMBOLS 1 Pachi slot 3L Left reel 3C Middle reel 3R Right reel 4 Reel display window 21 Medal slot 23 Start lever 32 Medal payout 51 Hopper device 71 Main control board 72 Sub control board 79 Start switch 80 Stop switch board 91 Main control circuit 101 Sub Control circuit 201 Medal selector 202 Medal chute 203 Slope 204 Base plate part 205 Sub plate 206 Cancel shooter 207 Select plate 208 Medal solenoid 209 Camera unit 210 Medal rail 211 Medal inlet part 212 Central hole 213 Medal pressure 217 Magnet 218 After medal pressure 227 Medal Stopper portion 230 First substrate 231 Second substrate 232 CMOS image sensor 233 LED
234 Control LSI
235 Leg 241 Host controller 242 Image recognition DSP circuit 243 SRAM
244 Flash memory 245 ISP circuit 246 Medal count circuit 247 Color recognition circuit 248 Fisheye correction scaler circuit 249, 449, 549, 749, 949 Image recognition accelerator circuit 250 GPIO
251 ISI circuit 252 DMAC
261,361 Imaging unit 262,362A Captured image 362B Captured image 362C Feature image 263,363 Conversion unit 264,364 Feature image generation unit 265,365 Determination unit 266,366 Input / output unit 267,367 Template data 268,368 Determination result 271 , 471, 571, 771, 971 Input frame buffer 272, 472, 572, 772, 972 Coordinate conversion circuit 273, 473, 573, 773, 973 Image processing circuit 274, 474, 574, 774, 974 Memory 275, 475, 575 , 775 Target image data 276,476,576,776,976 Converted image data 277,577,777,977 Processed image data 280,480,580,780 Conversion parameters 281,481,581,781 Circuit 282, 482, 582, 782 Control circuit 283, 483, 583, 783 Register 290, 490, 590, 790 Specific information 300, 600, 800, 1000 Storage controller 301, 601, 801, 1001 First read request output unit 302, 602, 802, 1002 Write request output unit 303, 603, 803 Second read request output unit 304, 604, 804, 1004 Arbitration unit 305, 805, 1005 Addition processing unit 306, 606, 706, 1006 Write buffer 307 , 607, 707, 1007 Read buffer 308, 608, 708, 1008 Output control unit 309, 609, 709, 909 Frame memory 370 First image generation unit 371 Extraction unit 372 Edge image generation unit 374 First image 380 Second image generation Part 400 Tadashi Medals 310, 410 Medals 485 adder circuit 495 parameter offset 585,785 selecting circuit 795 operation mode information 806 selection circuit

Claims (3)

A slot for gaming media;
A game medium detecting means for detecting a game medium thrown from the slot,
The game medium detection means includes
A game medium passage section serving as a passage through which the game medium passes;
Imaging means for imaging a passing object that is an object passing through the passage;
Game medium determination means for determining whether or not the game medium is legitimate by performing image processing based on image data obtained via the imaging means,
The game medium determining means is
It is configured as a dedicated integrated circuit for determining the game medium,
First storage means for storing data;
Conversion means for performing a predetermined format conversion on the image data obtained via the imaging means, and storing the image data after the format conversion in the first storage means;
Feature image generation means for generating a feature image indicating the characteristics of the game medium based on the image data after the format conversion,
The feature image generation means includes
Image data relating to the image data after the format conversion is acquired from the first storage means, image processing including coordinate conversion is performed on the acquired image data, and the image data after the image processing is converted into the first data. Memorize it in the memory means,
The processing content of the coordinate transformation is specified by a transformation parameter,
The game medium determination means further includes
Direct transfer control means for controlling the direct transfer of data,
At least one of storage in the first storage unit of the image data after the format conversion in the conversion unit, and storage in the first storage unit of the image data after the image processing in the feature image generation unit, A gaming machine, which is performed by the direct transfer. The feature image generation means includes
It is configured as a circuit in the game medium determination means,
Second storage means for storing the conversion parameter;
The gaming machine according to claim 1, wherein the coordinate transformation is performed based on the transformation parameter acquired from the second storage unit.   3. The parameter according to claim 1, wherein the conversion parameter is a parameter that indicates at least one of coordinate conversion related to rotation, coordinate conversion related to enlargement, coordinate conversion related to reduction, and coordinate conversion related to parallel movement. Gaming machine.

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