JP2017183519A - Circuit arrangement - Google Patents

Circuit arrangement Download PDF

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JP2017183519A
JP2017183519A JP2016068594A JP2016068594A JP2017183519A JP 2017183519 A JP2017183519 A JP 2017183519A JP 2016068594 A JP2016068594 A JP 2016068594A JP 2016068594 A JP2016068594 A JP 2016068594A JP 2017183519 A JP2017183519 A JP 2017183519A
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substrate
edge connector
pattern
core layer
layer
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JP6267738B2 (en
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禎夫 久保木
Sadao Kuboki
禎夫 久保木
秀一 滝岡
Shuichi Takioka
秀一 滝岡
堀越　崇
Takashi Horikoshi
崇 堀越
昌龍 許
chang long Xu
昌龍 許
朋宜 湯山
Tomonobu Yuyama
朋宜 湯山
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Keihin Corp
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Keihin Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a circuit arrangement capable of preventing an edge connector from being warped by heat, simplifying a structure and reducing component cost.SOLUTION: The present invention relates to a circuit arrangement 10 including a substrate 30 on which an edge connector 20 is formed, and a resin part 40 which is integrally formed on the substrate 30 so as to expose the edge connector 20. The substrate 30 includes a core layer 32 and pattern layers 33a and 33b that are disposed along both surfaces of the core layer 32. The pattern layers 33a and 33b are formed so as to be spread over a portion of the edge connector 20 and the resin part 40.EFFECT: Since the pattern layer is a so-called flat pattern that is formed to be spread over the edge connector portion and the resin part, amounts of elongation due to thermal expansion of the pattern layers become equal on an upper surface and a lower surface of the core layer, thereby preventing the edge connector from being warped.SELECTED DRAWING: Figure 3

Description

本発明は、エッジコネクタが形成された基板を樹脂で封止する回路装置に関する。   The present invention relates to a circuit device for sealing a substrate on which an edge connector is formed with a resin.

乗用車や自動二輪車に代表される車両には、基板を備える回路装置が搭載されている。回路装置では、基板への水等の浸入を防ぐために、基板の周囲を樹脂で中実になるように封止する技術が実用化されている。このような回路装置において、加熱ポットから溶融した樹脂を基板が配置されたキャビティに充填する、トランスファーモールドの技術が知られている（例えば、特許文献１（図２）参照。）。   A vehicle represented by a passenger car or a motorcycle is equipped with a circuit device including a substrate. In the circuit device, in order to prevent water and the like from entering the substrate, a technique for sealing the periphery of the substrate so as to be solid with resin has been put into practical use. In such a circuit device, a transfer molding technique is known in which a resin melted from a heating pot is filled in a cavity in which a substrate is arranged (see, for example, Patent Document 1 (FIG. 2)).

特許文献１に開示されている技術の基本原理を図４（ａ）に基づいて説明する。
図４（ａ）に示すように、回路装置１００は、トランスファーモールドによって基板１０１が樹脂１０２で封止されている。基板１０１の上面には表面電子部品１０３、表面金属配線１０４及び端子１０５が設けられ、基板１０１の下面には裏面電子部品１０６、裏面金属配線１０７及び端子１０８が設けられている。樹脂１０２から露出する部分が、エッジコネクタ１０９を形成している。 The basic principle of the technique disclosed in Patent Document 1 will be described with reference to FIG.
As shown in FIG. 4A, in the circuit device 100, the substrate 101 is sealed with a resin 102 by transfer molding. A front surface electronic component 103, a front surface metal wiring 104 and a terminal 105 are provided on the upper surface of the substrate 101, and a back surface electronic component 106, a back surface metal wiring 107 and a terminal 108 are provided on the lower surface of the substrate 101. A portion exposed from the resin 102 forms an edge connector 109.

電子部品及び金属配線は熱を帯びるが、金属配線は熱によって膨張する。基板１０１の上面に配置された表面電子部品１０３及び表面金属配線１０４は、基板１０１の下面に配置された裏面電子部品１０６及び裏面金属配線１０７とは数や形状等が異なるため、基板１０１の上面と下面とでは膨張量が異なり、いわゆるバイメタル効果によって基板１０１が反り返ることがある。基板１０１の反り返りによって、エッジコネクタ１０９を相手方のコネクタ部に接続し難くなる。この対策の一つとして、特許文献２の技術が知られている（例えば、特許文献２（図５）参照。）。   Electronic parts and metal wiring are heated, but metal wiring expands due to heat. The front surface electronic component 103 and the front surface metal wiring 104 arranged on the upper surface of the substrate 101 are different in number and shape from the back surface electronic component 106 and the back surface metal wiring 107 disposed on the lower surface of the substrate 101. And the lower surface have different expansion amounts, and the substrate 101 may warp due to the so-called bimetal effect. Due to the warping of the substrate 101, it becomes difficult to connect the edge connector 109 to the mating connector portion. As one of countermeasures, the technique of Patent Document 2 is known (see, for example, Patent Document 2 (FIG. 5)).

特許文献２に開示されている技術の基本原理を図４（ｂ）に基づいて説明する。
図４（ｂ）に示すように、エッジコネクタ１１０は、基板１１１に弾性接触片１１２を有し、この弾性接触片１１２の先端に端子金具１１３が設けられている。これらの基板１１１、弾性接触片１１２及び金属端子１１３は、コネクタハウジング１１４で覆われており、コネクタハウジング１１４の表面には複数の溝部１１５が形成されている。コネクタハウジング１１４は溝部１１５によって曲がり易いため、基板１１１が熱により反り返ると、コネクタハウジング１１４も追従して曲がる。 The basic principle of the technique disclosed in Patent Document 2 will be described with reference to FIG.
As shown in FIG. 4B, the edge connector 110 has an elastic contact piece 112 on a substrate 111, and a terminal fitting 113 is provided at the tip of the elastic contact piece 112. These substrate 111, elastic contact piece 112 and metal terminal 113 are covered with a connector housing 114, and a plurality of groove portions 115 are formed on the surface of the connector housing 114. Since the connector housing 114 is easily bent by the groove 115, when the board 111 is warped by heat, the connector housing 114 is also bent.

しかし、コネクタハウジング１１４に溝部１１５を設けていたのでは、構造が複雑になりエッジコネクタ１１０のコストが高くなる。また、コネクタハウジング１１４の剛性が低下することから、端子金具１１３の位置精度が低下し、接続信頼性の低下のおそれが生じる。   However, if the groove 115 is provided in the connector housing 114, the structure becomes complicated and the cost of the edge connector 110 increases. Further, since the rigidity of the connector housing 114 is lowered, the positional accuracy of the terminal fitting 113 is lowered, and the connection reliability may be lowered.

特許第４４７８００７号公報Japanese Patent No. 4478007 特開２００８−９１１０８号公報JP 2008-91108 A

本発明は、エッジコネクタの熱による反り返りを防止するとともに、構造が簡単で部品コストを低減することができる回路装置を提供することを課題とする。   It is an object of the present invention to provide a circuit device that prevents warping of an edge connector due to heat and that has a simple structure and can reduce component costs.

請求項１に係る発明では、エッジコネクタが形成された基板と、この基板に前記エッジコネクタを露出させるように一体に形成された樹脂部とを含む回路装置であって、前記基板は、コア層及びこのコア層の両面に沿って配置するパターン層を有し、前記パターン層は、前記エッジコネクタ部分と樹脂部にわたり広がるように形成されていることを特徴とする。   The invention according to claim 1 is a circuit device including a substrate on which an edge connector is formed and a resin portion integrally formed on the substrate so as to expose the edge connector, wherein the substrate includes a core layer And a pattern layer disposed along both surfaces of the core layer, wherein the pattern layer is formed so as to spread over the edge connector portion and the resin portion.

請求項２に係る発明では、パターン層は、コア層を挟んで対称に形成されていることを特徴とする。   The invention according to claim 2 is characterized in that the pattern layer is formed symmetrically across the core layer.

請求項３に係る発明では、パターン層は、基板の全面に形成されていることを特徴とする。   The invention according to claim 3 is characterized in that the pattern layer is formed on the entire surface of the substrate.

請求項１に係る発明では、回路装置は、エッジコネクタが形成された基板と、この基板にエッジコネクタを露出させるように一体に形成された樹脂部とを含み、基板は、コア層及びこのコア層の両面に沿って配置するパターン層を有する。パターン層は、エッジコネクタ部分と樹脂部にわたり広がるように形成されたいわゆるベタパターンであるので、コア層の上面と下面におけるパターン層の熱膨張による伸び量が同等になり、エッジコネクタの反り返りを防止することができる。   In the invention according to claim 1, the circuit device includes a substrate on which the edge connector is formed, and a resin portion integrally formed so as to expose the edge connector on the substrate, and the substrate includes the core layer and the core. It has a pattern layer arranged along both sides of the layer. Since the pattern layer is a so-called solid pattern that is formed so as to spread over the edge connector part and the resin part, the amount of elongation due to the thermal expansion of the pattern layer on the upper surface and the lower surface of the core layer is equal, preventing the edge connector from warping can do.

さらに、パターン層はコア層と表層の間にあって、端子の下（コア層側）にあるため、基板の配線パターンの一部として兼用することができる。さらに、従来技術のような特殊なコネクタハウジングが不要であり、パターン層をエッジコネクタ部分と樹脂部にわたり形成しただけであるので、構造が簡単で部品コストを低減することができる。   Furthermore, since the pattern layer is located between the core layer and the surface layer and under the terminal (on the core layer side), it can also be used as a part of the wiring pattern of the substrate. Further, since a special connector housing as in the prior art is unnecessary and the pattern layer is only formed over the edge connector portion and the resin portion, the structure is simple and the component cost can be reduced.

請求項２に係る発明では、パターン層は、コア層を挟んで対称に形成されているので、コア層の上面と下面におけるパターン層の熱膨張に伸び量を同一にし、エッジコネクタの反り返りを一層抑制することができる。   In the invention according to claim 2, since the pattern layer is formed symmetrically with the core layer in between, the elongation amount is made equal to the thermal expansion of the pattern layer on the upper surface and the lower surface of the core layer, and the edge connector is further warped. Can be suppressed.

請求項３に係る発明では、パターン層は、基板の全面に形成されているので、基板の端部まで、コア層の上面と下面におけるパターン層の熱膨張による伸び量を同一にすることができる。   In the invention according to claim 3, since the pattern layer is formed on the entire surface of the substrate, the amount of elongation due to the thermal expansion of the pattern layer on the upper surface and the lower surface of the core layer can be made the same up to the edge of the substrate. .

本発明の実施例に係る回路装置の斜視図である。1 is a perspective view of a circuit device according to an embodiment of the present invention. 基板等の層の分解斜視図である。It is a disassembled perspective view of layers, such as a board | substrate. 回路装置の作用図である。It is an effect | action figure of a circuit apparatus. 従来技術の基本原理を説明する図である。It is a figure explaining the basic principle of a prior art.

本発明の実施の形態を添付図に基づいて以下に説明する。   Embodiments of the present invention will be described below with reference to the accompanying drawings.

まず、本発明の実施例１を図面に基づいて説明する。
図１に示すように、回路装置１０は、端部にエッジコネクタ２０が形成された基板３０と、この基板３０にエッジコネクタ２０を露出させるように一体に形成された樹脂部４０とを含んでいる。基板３０の大部分は、樹脂部４０によって封止されている。 First, Embodiment 1 of the present invention will be described with reference to the drawings.
As shown in FIG. 1, the circuit device 10 includes a substrate 30 having an edge connector 20 formed at an end thereof, and a resin portion 40 integrally formed so as to expose the edge connector 20 on the substrate 30. Yes. Most of the substrate 30 is sealed by the resin portion 40.

エッジコネクタ２０は、いわゆる雄コネクタであり、基板３０の端部に複数の端子３１ａが露出するように設けられている。端子３１ａは、基板３０の上面３０ａ及び下面３０ｂに設けられており、端子３１ａの先端は、基板３０の先端よりも若干後退した位置にある。   The edge connector 20 is a so-called male connector, and is provided so that a plurality of terminals 31 a are exposed at the end of the substrate 30. The terminal 31 a is provided on the upper surface 30 a and the lower surface 30 b of the substrate 30, and the tip of the terminal 31 a is at a position slightly retracted from the tip of the substrate 30.

図２に示すように、基板３０は、エッジコネクタ２０において複数の層が積層された状態であり、層の中心位置する平板状のコア層３２と、このコア層３２の上面及び下面に沿って配置されるパターン層３３ａ、３３ｂと、これらのパターン層３３ａ、３３ｂの外側に沿って配置される表層３４ａ、３４ｂと、これらの表層３４ａ、３４ｂの外側に沿って配置される端子３１ａ、３１ｂとを備えている。   As shown in FIG. 2, the substrate 30 is a state in which a plurality of layers are stacked in the edge connector 20, and a flat core layer 32 positioned at the center of the layer and along the upper and lower surfaces of the core layer 32. Pattern layers 33a and 33b to be arranged, surface layers 34a and 34b arranged along the outside of these pattern layers 33a and 33b, and terminals 31a and 31b arranged along the outside of these surface layers 34a and 34b It has.

基板３０は、樹脂部４０（図１参照）の内部においても積層された状態である。コア層３２及び表層３４ａ、３４ｂは、例えばガラス・エポキシ製である。パターン層３３ａ、３３ｂは銅製の配線パターンであり、樹脂部４０においてはいわゆるベタパターンの配線を形成し、エッジコネクタ２０部分においては平面状に広がるように形成されている。なお、基板３０の積層数はこれに限定されず、ベタパターンを形成するパターン層は、基板の表層以外の内層のうちいずれかの内層であればよい。また、実施例ではコア層３２及び表層３４ａ、３４ｂを、ガラス・エポキシ製としたが、これに限定されず、他の一般的な基板の材料であってもよい。   The board | substrate 30 is the state laminated | stacked also inside the resin part 40 (refer FIG. 1). The core layer 32 and the surface layers 34a and 34b are made of, for example, glass epoxy. The pattern layers 33a and 33b are copper wiring patterns, and so-called solid pattern wiring is formed in the resin portion 40, and the edge connector 20 is formed so as to spread in a planar shape. Note that the number of stacked layers of the substrate 30 is not limited to this, and the pattern layer forming the solid pattern may be any one of the inner layers other than the surface layer of the substrate. In the embodiment, the core layer 32 and the surface layers 34a and 34b are made of glass / epoxy. However, the present invention is not limited to this, and other general substrate materials may be used.

端子３１ａ、３１ｂは、銅製であり、エッジコネクタ２０部分から樹脂部４０内へ伸びている。図は省略するが、パターン層３３ａ、３３ｂ及び端子３１ａ、３１ｂは、銅製のスルーホールで接続され、さらに電子部品にも適宜接続されている。   The terminals 31 a and 31 b are made of copper and extend from the edge connector 20 portion into the resin portion 40. Although illustration is omitted, the pattern layers 33a and 33b and the terminals 31a and 31b are connected by copper through holes, and further appropriately connected to electronic components.

以上に述べた回路装置１０の作用について次に説明する。
図３（ａ）は実施例の回路装置１０の断面図であり、パターン層３３ａ、３３ｂは、エッジコネクタ２０部分と樹脂部４０にわたり広がるように形成されている。パターン層３３ａ、３３ｂは、いわゆるベタパターンであるので、コア層３２の上面のパターン層３３ａと下面のパターン層３３ｂの熱膨張による伸び量が同等になり、エッジコネクタ２０の反り返りを防止することができる。 Next, the operation of the circuit device 10 described above will be described.
FIG. 3A is a cross-sectional view of the circuit device 10 of the embodiment, and the pattern layers 33 a and 33 b are formed so as to spread over the edge connector 20 portion and the resin portion 40. Since the pattern layers 33a and 33b are so-called solid patterns, the amount of elongation due to thermal expansion of the pattern layer 33a on the upper surface of the core layer 32 and the pattern layer 33b on the lower surface becomes equal, and the edge connector 20 can be prevented from warping. it can.

このため、雄コネクタとしてのエッジコネクタ２０は、雌コネクタ５０に対して直線状に伸びており、矢印（１）のように、エッジコネクタ２０を雌コネクタ５０に容易に差し込むことができる。   For this reason, the edge connector 20 as a male connector extends linearly with respect to the female connector 50, and the edge connector 20 can be easily inserted into the female connector 50 as indicated by an arrow (1).

さらに、パターン層３３ａ、３３ｂはコア層３２と表層３４ａ、３４ｂの間にあって、端子３１ａ、３１ｂの下（コア層側）にあるため、基板３０の配線パターンの一部として兼用することができる。さらに、従来技術のような特殊なコネクタハウジングが不要であり、パターン層３３ａ、３３ｂをエッジコネクタ２０部分と樹脂部４０にわたり形成しただけであるので、構造が簡単で部品コストを低減することができる。   Furthermore, since the pattern layers 33a and 33b are located between the core layer 32 and the surface layers 34a and 34b and under the terminals 31a and 31b (on the core layer side), they can also be used as a part of the wiring pattern of the substrate 30. Further, a special connector housing as in the prior art is not required, and the pattern layers 33a and 33b are simply formed over the edge connector 20 portion and the resin portion 40. Therefore, the structure is simple and the component cost can be reduced. .

また、パターン層３３ａ、３３ｂは、コア層３２を挟んで対称に形成されている。このため、コア層３２の上面と下面におけるパターン層３３ａ、３３ｂの熱膨張に伸び量を同一にし、エッジコネクタ２０の反り返りを一層抑制することができる。   The pattern layers 33a and 33b are formed symmetrically with the core layer 32 in between. For this reason, it is possible to make the elongation amount the same as the thermal expansion of the pattern layers 33 a and 33 b on the upper surface and the lower surface of the core layer 32, and to further suppress the warping of the edge connector 20.

また、パターン層３３ａ、３３ｂは、基板３０の全面に形成されている。このため、基板３０の端部まで、コア層３２の上面と下面におけるパターン層３３ａ、３３ｂの熱膨張による伸び量を同一にすることができる。   Further, the pattern layers 33 a and 33 b are formed on the entire surface of the substrate 30. For this reason, the amount of elongation due to thermal expansion of the pattern layers 33 a and 33 b on the upper surface and the lower surface of the core layer 32 can be made the same up to the end of the substrate 30.

さらに、端子３１ａ、３１ｂの先端は、基板３０の先端よりも若干後退した位置にあるので、小エッジコネクタ２０の先端は先細りとなる。このため、エッジコネクタ２０を雌コネクタ５０に容易に差し込むことができる。   Furthermore, since the tips of the terminals 31a and 31b are located slightly behind the tip of the substrate 30, the tip of the small edge connector 20 is tapered. For this reason, the edge connector 20 can be easily inserted into the female connector 50.

図３（ｂ）は比較例の回路装置１２０の断面図であり、基板１２１は、コア層１２２の上面に沿って表層１２４ａが積層され、表層１２４ａの上面に端子１２５ａが配置され、コア層１２２の下面に沿ってパターン層１２３ｂが積層され、パターン層１２３ｂの下面に表層１２４ｂが積層され、表層１２４ｂの下面に端子１２５ｂが配置されている。   FIG. 3B is a cross-sectional view of the circuit device 120 of the comparative example. The substrate 121 has a surface layer 124 a laminated along the upper surface of the core layer 122, a terminal 125 a is disposed on the upper surface of the surface layer 124 a, and the core layer 122. The pattern layer 123b is stacked along the lower surface of the pattern layer, the surface layer 124b is stacked on the lower surface of the pattern layer 123b, and the terminal 125b is disposed on the lower surface of the surface layer 124b.

比較例では、パターン層１２３ｂがコア層１２２の下側にのみ配置されているか、又はコア層１２２の下側のパターン層１２３ｂの面積が上側のパターン層の面積よりも大きくなるように配置されている。パターン層１２３ｂの熱膨張により、エッジコネクタ１２５は上側に反り返っており、矢印（２）のように、雄コネクタとしてのエッジコネクタ１２５が、雌コネクタ１２６の差し込み口１２７からＨ１だけ位置ずれして差し込み難い。また、エッジコネクタ１２５を雌コネクタ１２６に無理に差し込んでも、端子１２５ａ、１２５ｂの位置精度が低下しているため、接続信頼性が低下する。   In the comparative example, the pattern layer 123b is disposed only on the lower side of the core layer 122, or is disposed so that the area of the pattern layer 123b on the lower side of the core layer 122 is larger than the area of the upper pattern layer. Yes. The edge connector 125 warps upward due to the thermal expansion of the pattern layer 123b, and the edge connector 125 as a male connector is displaced from the insertion port 127 of the female connector 126 by H1 as shown by the arrow (2). hard. Moreover, even if the edge connector 125 is forcibly inserted into the female connector 126, the positional accuracy of the terminals 125a and 125b is lowered, so that the connection reliability is lowered.

この点、本実施例では図３（ａ）に示すように、エッジコネクタ２０が直線状に伸びているので、エッジコネクタ２０を雌コネクタ５０に差し込んだ際の、端子３１ａ、３１ｂの位置精度を高い状態にでき、接続信頼性を向上させることができる。   In this regard, in this embodiment, as shown in FIG. 3A, the edge connector 20 extends linearly, so that the positional accuracy of the terminals 31a and 31b when the edge connector 20 is inserted into the female connector 50 is improved. A high state can be achieved, and the connection reliability can be improved.

尚、本発明は上記実施形態に限定されるものではなく、その要旨を逸脱しない範囲で種々の設計変更が可能である。また、実施例では、端子３１ａ、３１ｂを基板３０の両面に設けたが、これに限定されず、端子３１ａを基板３０の一方の面にのみ設けても差し支えない。また、端子３１ａ，３１ｂの数は実施例に限定されず、４本、８本、１０本など同じ方向に複数並んで配置されていれば差し支えない。   In addition, this invention is not limited to the said embodiment, A various design change is possible in the range which does not deviate from the summary. In the embodiment, the terminals 31 a and 31 b are provided on both surfaces of the substrate 30. However, the present invention is not limited to this, and the terminals 31 a may be provided only on one surface of the substrate 30. The number of terminals 31a and 31b is not limited to the embodiment, and a plurality of terminals 31a and 31b may be arranged in the same direction, such as four, eight, and ten.

本発明は、エッジコネクタが形成された基板を樹脂で封止する回路装置に好適である。   The present invention is suitable for a circuit device that seals a substrate on which an edge connector is formed with a resin.

１０...回路装置、２０...エッジコネクタ、３０...基板、３２...コア層、３３ａ、３３ｂ...パターン層、４０...樹脂部。   DESCRIPTION OF SYMBOLS 10 ... Circuit apparatus, 20 ... Edge connector, 30 ... Board | substrate, 32 ... Core layer, 33a, 33b ... Pattern layer, 40 ... Resin part.

Claims (3)

エッジコネクタが形成された基板と、この基板に前記エッジコネクタを露出させるように一体に形成された樹脂部とを含む回路装置であって、
前記基板は、コア層及びこのコア層の両面に沿って配置するパターン層を有し、
前記パターン層は、前記エッジコネクタ部分と樹脂部にわたり広がるように形成されていることを特徴とする回路装置。 A circuit device including a substrate on which an edge connector is formed, and a resin portion integrally formed to expose the edge connector on the substrate,
The substrate has a core layer and a pattern layer disposed along both sides of the core layer,
The circuit device is characterized in that the pattern layer is formed so as to spread over the edge connector portion and the resin portion. 前記パターン層は、前記コア層を挟んで対称に形成されていることを特徴とする請求項１記載の回路装置。   The circuit device according to claim 1, wherein the pattern layer is formed symmetrically across the core layer. 前記パターン層は、前記基板の全面に形成されていることを特徴とする請求項１又は請求項２記載の回路装置。   The circuit device according to claim 1, wherein the pattern layer is formed on an entire surface of the substrate.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002100841A (en) * 2000-09-25 2002-04-05 Taiyo Yuden Co Ltd Multilayer circuit board
JP2007128959A (en) * 2005-11-01 2007-05-24 Toshiba Corp Semiconductor memory card and circuit board
JP2015125951A (en) * 2013-12-27 2015-07-06 日立オートモティブシステムズ株式会社 On-vehicle electronic module
JP2016025232A (en) * 2014-07-22 2016-02-08 株式会社フジクラ Printed wiring board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002100841A (en) * 2000-09-25 2002-04-05 Taiyo Yuden Co Ltd Multilayer circuit board
JP2007128959A (en) * 2005-11-01 2007-05-24 Toshiba Corp Semiconductor memory card and circuit board
JP2015125951A (en) * 2013-12-27 2015-07-06 日立オートモティブシステムズ株式会社 On-vehicle electronic module
JP2016025232A (en) * 2014-07-22 2016-02-08 株式会社フジクラ Printed wiring board

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