JP2017168875A - Electronic apparatus and method for detecting communication error between programmable devices - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of communication between programmable devices.SOLUTION: An electronic apparatus is loaded with programmable devices connected with each other via a plurality of signal lines. Each of the programmable devices includes: a detection unit for detecting the number of normal signal lines among the plurality of signal lines on the basis of test data communicated via the signal lines more than the bit number of the data communicated between the programmable devices; and a selection unit for selecting a method for detecting an error of the data depending on the number of normal signal lines.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic device and an error detection method.

  A Field Programmable Gate Array (FPGA) is a programmable device that can change the function of a logic circuit, and is mounted on an electronic device such as a communication device or a video device. In recent years, electronic devices equipped with a plurality of FPGAs have been used. The FPGAs are connected to each other via a bus, and communication is performed between the FPGAs via the bus.

  As a related technique, there has been proposed a connection monitoring device for connecting two programmable devices for monitoring a connection state between a main control board and a peripheral control boat (see, for example, Patent Document 1).

JP 2009-187284 A

  When data is communicated between FPGAs via a bus, data may not be communicated normally. For example, when a steady failure occurs in the signal line itself included in the bus, or when a transient failure such as a software error occurs during communication, an error occurs in one or more bits of the data. Sometimes.

  For this reason, error detection is performed for each bit of data. Data errors are detected in the FPGA on the data receiving side. In this case, an error detection bit is added to the data, and error detection is performed in the receiving side FPGA using the error detection bit.

  There are several methods for error detection, and the number of bits used for error detection differs depending on the error detection method. Since the number of bits that can be used on the bus varies depending on the failure status and the like, the number of bits allocated for error detection also varies depending on the failure status and the like.

  Depending on the number of bits allocated for error detection, how error detection is performed also varies. In this case, an appropriate error detection method may not be selected, and the reliability of communication between programmable devices decreases.

  As one aspect, the present invention aims to improve the reliability of communication between programmable devices.

  In one aspect, an electronic device is an electronic device equipped with programmable devices connected to each other by a plurality of signal lines, and the number of programmable devices is greater than the number of bits of data communicated between the programmable devices. Based on test data communicated through the plurality of signal lines, a detection unit that detects the number of normal signal lines among the plurality of signal lines, and according to the number of normal signal lines, And a selection unit that selects a method for detecting a data error.

  According to one aspect, the reliability of communication between programmable devices can be improved.

FIG. 3 illustrates an example of an electronic apparatus (part 1); It is a figure which shows an example at the time of representing a bus with a signal line. It is FIG. (2) which shows an example of an electronic device. FIG. 3 is a diagram (part 3) illustrating an example of an electronic apparatus. It is a figure (the 1) which shows an example of an allocation table. It is FIG. (2) which shows an example of an allocation table. FIG. 6 is a diagram (part 4) illustrating an example of an electronic apparatus. It is a figure (the 1) which shows the example of application of an allocation table. It is FIG. (2) which shows an example of an allocation table. FIG. 10 illustrates an example of an allocation table (part 3); FIG. 10 is a diagram illustrating an example of an electronic apparatus (part 5); FIG. 6 is a sixth diagram illustrating an example of an electronic apparatus. FIG. 11 is a diagram illustrating an example of an electronic apparatus (part 7); It is a sequence chart which shows an example of the flow of processing of an embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 shows an example of an electronic device 1. An arbitrary device such as a communication device or a video device may be applied to the electronic device 1. The electronic device 1 is equipped with a plurality of FPGAs.

  An FPGA is an example of a programmable device that can change the function of a logic circuit. For example, by changing the Look Up Table (LUT) of the FPGA, the logic circuit can function as an arbitrary logic circuit such as an AND circuit or an OR circuit.

  In the examples after FIG. 1, the electronic device 1 is assumed to be equipped with two FPGAs, a first FPGA 11 and a second FPGA 12. However, the number of FPGAs mounted on the electronic device 1 may be three or more.

  The first FPGA 11 is an FPGA that transmits data. The second FPGA 12 is an FPGA that receives data. However, the first FPGA 11 may be a data reception side FPGA, and the second FPGA 12 may be a data transmission side FPGA.

  Therefore, the first FPGA 11 and the second FPGA 12 have the same function. However, the first FPGA 11 and the second FPGA 12 may have functions other than those shown in the example of FIG.

  The first FPGA 11 and the second FPGA 12 are connected by a bus 13. The first FPGA 11 transmits data to the second FPGA 12 via the bus 13. The bus 13 includes a plurality of signal lines.

  Next, the first FPGA 11 and the second FPGA 12 will be described. As described above, the first FPGA 11 and the second FPGA 12 have equivalent functions. Therefore, in FIG. 1 and after, each part of the first FPGA 11 is denoted by “A” and each part of the second FPGA 12 is denoted by “B”.

  Hereinafter, the first FPGA 11 and the second FPGA 12 may be collectively referred to simply as an FPGA. The FPGA includes an Identification (ID) adding unit 21, a test data generating unit 22, a ring buffer 23, a multiplexer 24, a selecting unit 25, a detecting unit 26, a normal bit information generating unit 27, a normal bit information holding unit 28, and an error processing unit 29. And a retransmission request unit 30.

  In the embodiment, each part of the FPGA is realized by a predetermined circuit. The FPGA may have functions other than those described above. The ID assigning unit 21 assigns an ID to data (transmission data) transmitted from the transmission source FPGA (first FPGA 11) to the transmission destination FPGA (second FPGA 12).

  The ID is information that identifies transmission data. In the embodiment, it is assumed that the transmission data is 64-bit data. However, the number of bits of transmission data is not limited to 64 bits.

  In the embodiment, when the electronic device 1 is powered on (when the power is turned on), the test data generation unit 22 generates test data. However, the test data may be generated at an arbitrary timing. The test data is data for inspecting whether there is a failure in communication via the bus 13.

  One bit is assigned to one signal line of the bus 13. In the embodiment, it is assumed that the number of signal lines of the bus 13 is 82. However, the number of signal lines of the bus 13 is not limited to 82.

  Since the test data is data for checking the communication on the bus 13, the number of bits of the test data is the same as the number of signal lines of the bus 13. In the case of the embodiment, since the number of signal lines of the bus 13 is 82, the test data is 82 bits.

  Further, the number of signal lines (= 82) of the bus 13 is larger than the number of bits of transmission data transmitted from the first FPGA 11 to the second FPGA 12. In the case of the embodiment, the transmission data is assumed to be 64 bits.

  The ring buffer 23 stores transmission data to which an ID is assigned. The ring buffer 23 is an example of a storage unit. The transmission data to which the ID is assigned may be stored in a storage unit other than the ring buffer. For example, the transmission data may be stored in a buffer other than the ring buffer.

  The multiplexer 24 inputs transmission data and test data. The multiplexer 24 assigns each bit of data communicated via the bus 13 to each signal line included in the bus 13 based on the control of the selection unit 25.

  The detection unit 26 compares the test data received from the other party's FPGA via the bus 13 with the test data held by itself, and detects whether the communication using each signal line of the bus 13 is normal. To do.

  For this reason, the detection unit 26 holds the same test data as the test data transmitted by the counterpart FPGA. The detection unit 26 compares the test data received from the other party's FPGA with the test data held by itself one bit at a time, and if the value is the same, the bit is normal, and if the value is different, the bit is Detect that it is not normal.

  The normal bit information generation unit 27 generates normal bit information based on the detection result. The generated normal bit information is assigned by the normal bit information generation unit 27 to each bit detected to be normal.

  The normal bit information holding unit 28 receives and holds the normal bit information generated by the normal bit information generating unit 27 of the counterpart FPGA. The normal bit information held by the normal bit information holding unit 28 is input to the selection unit 25.

  The error processing unit 29 performs error processing on the received transmission data. The error processing unit 29 may perform error detection, may perform error correction, or may perform both error detection and error correction.

  In the embodiment, it is assumed that the error detection method is either a parity method or an error checking and correcting (ECC) method. The parity method is a method of performing error detection of a plurality of bits using 1 bit. The parity method is an example of a first method.

  The ECC method is a method of performing error detection of a plurality of bits using a plurality of bits. The ECC method is also a method that can correct a detected error. The ECC method is an example of a second method. The method for performing error detection may be any method other than the parity method and the ECC method.

  When error correction is not performed by the error processing unit 29A, the retransmission request unit 30 transmits a retransmission request for requesting retransmission of transmission data stored in the ring buffer 23 of the counterpart FPGA to the counterpart FPGA.

  For example, it is assumed that the error processing unit 29A detects a 2-bit error as a result of error detection by the ECC method. In this case, since error correction cannot be performed, the error processing unit 29A does not perform error correction.

  FIG. 2 shows an example when the bus 13 is represented by a signal line. In the example of FIG. 2, the first FPGA 11 and the second FPGA 12 are connected by 82 signal lines. As described above, since the number of bits of transmission data is 64 bits, the number of signal lines of the bus 13 is 18 more than the number of signal lines used for communication of transmission data.

  The operation of the embodiment will be described after FIG. As described above, it is assumed that the first FPGA 11 is a transmission side and the second FPGA 12 is a reception side. From FIG. 3 onward, the alternate long and short dash line indicates the flow of data and information.

  When the electronic device 1 is powered on, the test data generation unit 22A generates 82-bit test data. The generated test data is input to the multiplexer 24A. In the embodiment, 82 bits of test data are assigned to each signal line included in the bus 13.

  The multiplexer 24A transmits each bit of the test data to the corresponding signal line of the bus 13. Thereby, the second FPGA 12 receives the test data. The test data received by the second FPGA 12 is input to the detection unit 26B.

  The detection unit 26B holds the same test data as the test data generated by the test data generation unit 22A. Then, the detection unit 26B compares the input test data with the held test data bit by bit.

  For example, if the values of all bits of the input test data and the test data held by the detection unit 26B are the same, the detection unit 26B has normal communication using all the signal lines included in the bus 13. Detect that.

  For example, when the value of the 75th bit of the input test data is “1” and the value of the held test data is “0”, the detection unit 26B detects the 75th bit signal line of the bus 13 It is detected that the communication by is not normal and the other is normal.

  As a result of the comparison by the detection unit 26B, there may be a plurality of bits having different values between the input test data and the test data held by the detection unit 26B. In this case, the detection unit 26B detects that communication using a plurality of signal lines among the signal lines of the bus 13 is not normal.

  As a result of detection by the detection unit 26B, the normal bit information generation unit 27B generates normal bit information indicating normal bits for each bit of the 82-bit bus 13. The normal bit information is information from which bits detected to be abnormal are excluded.

  For example, as described above, when it is detected that the 75th bit signal line of the bus 13 is not normal, the normal bit information generation unit 27B generates normal bit information excluding the 75th bit signal line. .

  In this case, the normal bit information indicates information about 81 bits. The normal bit information generation unit 27B allocates predetermined bits of the 81-bit signal line indicating normality to transmission data, a retransmission request, and a control signal, respectively.

  The normal bit information generation unit 27B preferentially assigns transmission data bits to signal lines indicating normality. In the case described above, the normal bit information generation unit 27B preferentially allocates a 64-bit signal line among the 81-bit signal lines indicating normality for transmission data.

  The normal bit information generation unit 27B allocates a signal line for requesting retransmission among the remaining 17-bit signal lines. In the embodiment, it is assumed that 2 bits are used to make a retransmission request. Therefore, the normal bit information generation unit 27B allocates two signal lines to the retransmission request bits.

  The normal bit information generation unit 27B allocates the remaining 15-bit signal lines to control signal bits. The control signal is a signal for error detection. When error correction is performed, the control signal is also used for error correction.

  In this case, in the embodiment, transmission data error detection (and error correction) is performed using 15 bits. As described above, the normal bit information generation unit 27B assigns signal lines to each signal line indicating normality in the order of priority of transmission data, retransmission request, and control signal.

  For this reason, when the number of abnormal signal lines in the bus 13 increases, the number of signal lines allocated to the control signal decreases. That is, the number of signal lines (bits) allocated for error detection and error correction is reduced.

  As illustrated in the example of FIG. 4, the normal bit information generation unit 27 </ b> B transmits the generated normal bit information to the first FPGA 11 via the bus 13. The normal bit information received by the first FPGA 11 is input to the normal bit information holding unit 28A. Thus, the normal bit information holding unit 28A holds the normal bit information generated by the normal bit information generation unit 27A.

  Next, the allocation table held by the selection unit 25A will be described with reference to the examples of FIGS. The allocation table is a table for allocating each bit of transmission data, retransmission request, and control signal to each signal line of the bus 13. In FIG. 5 and subsequent figures, “bit” may be expressed as “bit”.

  The allocation table includes items of connection pattern, normal bit number, transmission data bit number, retransmission request bit number, control signal bit number, error processing method, and bit allocation. The connection pattern is a number indicating a pattern corresponding to the number of normal bits. The number of normal bits is the number of normal bits indicated by the normal bit information held by the normal bit information holding unit 28A.

  The transmission data bit number indicates the bit number of transmission data. As described above, signal lines corresponding to the number of bits of transmission data among the signal lines of the bus 13 are preferentially assigned to transmission data.

  When the transmission data is 64 bits, the signal lines for 64 bits among the signal lines of the bus 13 are assigned to the transmission data. Therefore, as shown in the example of FIG. 5, the number of transmission data bits is constant at 64 bits in any pattern.

  The number of bits of the retransmission request is used to specify the ID of the transmission data that is the target of the retransmission request in order to request retransmission of the transmission data stored in the ring buffer 23 of the counterpart FPGA.

  As described above, among the signal lines of the bus 13, signal lines corresponding to the number of retransmission request bits are preferentially assigned next to transmission data. When the retransmission request is 2 bits, signal lines for 2 bits are assigned to the retransmission request. Therefore, the number of bits in the retransmission request is 2 bits regardless of the pattern.

  The number of control signal bits is the number of bits used for error processing. Of the signal lines of the bus 13, signal lines other than transmission data and retransmission requests are assigned to the control signal. If a failure occurs in communication using one or more signal lines among the signal lines of the bus 13, the number of normal bits decreases. When the number of normal bits is decreased by 1, the number of control signal bits is also decreased by 1.

  The error processing method includes items of a method, an error correction bit number, and an error detection bit number. The method indicates whether to make a retransmission request and the error detection method to be applied. In the embodiment, one or both of the parity method and the ECC method are applied to the error detection method.

  The number of error correction bits indicates the number of bits for which error correction is performed. For example, in the case of connection pattern 2, it indicates that 1-bit error correction is performed on 64-bit transmission data (indicated as “1bit / 64bit”).

  In the case of connection pattern 1, it indicates that 1-bit error correction is performed on 32 bits of 64-bit transmission data, and 1-bit error correction is performed on the remaining 32 bits (“1 bit / 32bit ").

  The number of error detection bits indicates the number of bits for which error detection is performed. For example, in the case of connection pattern 1, only the ECC method is selected. This indicates that 2-bit error detection is performed on 32 bits of 64-bit transmission data (indicated as “2 bits / 32 bits”).

  In the case of connection pattern 2, the ECC method and the parity method are selected. In this case, error detection by the ECC method and error detection by the parity method are applied to 64-bit transmission data. That is, double error detection is applied to 64-bit transmission data.

  In this case, it indicates that 1-bit error detection is performed on 64-bit transmission data for the ECC method (indicated as “1 bit / 64 bit”). In addition, for the parity method, 10 bits of 64-bit transmission data are set as one group, and 1-bit error detection is performed for each group (denoted as “1 bit / 10 bit”).

  The bit allocation includes items of a method, a control signal bit, and a transmission data charge bit. The method indicates an ECC method or a parity method. The control signal bit indicates a bit for performing error processing of a predetermined bit in the transmission data.

  For example, in the case of connection pattern 1, a total of 32 bits from bit 0 to bit 31 are in charge of transmission data, and a total of 8 bits from bit 0 to bit 7 are in charge of control signal bits.

  Similarly, a total of 32 bits from bit 32 to bit 63 in the transmission data are handled by a total of 8 bits from bit 8 to bit 15 in the control bit.

  The control signal is a signal for performing error processing, and 32 bits of the transmission data are subjected to ECC error processing by 8 bits of the control signal, and the remaining 32 bits are ECC processing by 8 bits of the control signal. Error handling is performed.

  The ECC method has higher error detection accuracy than the parity method, and the ECC method can correct errors. In the case of connection pattern 1 having 16 control signal bits, as described above, it is preferable to apply the ECC method to 32 bits of transmission data and to apply the ECC method to the remaining 32 bits. Thereby, appropriate error detection with high reliability is performed.

  In the case of connection pattern 2, the number of control signal bits is 15. This is because a communication failure has occurred in one of the signal lines of the bus 13. In the case of the connection pattern 1 described above, since the control signal is 16 bits, an 8-bit control signal can be allocated for each 32 bits of transmission data.

  However, in the case of connection pattern 2, the control signal bit is 15, and the control signal bit (= 16 bits) used in connection pattern 1 is less than 1 bit. For this reason, in the case of connection pattern 2, a total of 8 bits from bit 0 to bit 7 are assigned to 64-bit transmission data.

  Thereby, an ECC method using an 8-bit control signal is applied to 64-bit transmission data. There are remaining 7 bits in the control signal bits. In the embodiment, a 1-bit control signal is assigned to a group in which 64-bit transmission data is equalized.

  In the case of connection pattern 2, since the remaining control signal bits are 7 bits, the number of bits of transmission data belonging to one group is 10 bits. Therefore, one bit of the control signal is assigned every 10 bits of the transmission data.

  As a result, a parity scheme in which 1 bit for error detection is assigned to 10 bits targeted for error detection is applied. The parity method has lower error detection accuracy than the ECC method, but error detection is performed with high accuracy if the number of bits subject to error detection is small.

  Therefore, according to the number of unused bits in the control signal bits, the bits of the transmission data in charge are grouped so as to be equal. This reduces the number of bits belonging to one group. If the number of bits belonging to one group is small, error detection is performed with high accuracy even in the parity method.

  In the case of connection pattern 2, two error detections of the ECC method and the parity method are performed on the transmission data. Accordingly, double error detection is performed on the same transmission data, so that the accuracy of error detection is improved.

  In the case of connection pattern 1, an ECC method in which 8 bits are assigned to 32 bits of 64-bit transmission data is applied. Therefore, the ECC method of connection pattern 1 has higher error detection accuracy than the ECC method of connection pattern 2. However, double error detection is not performed for the same transmission data.

  In the case of the connection pattern 8, the number of control signal bits is 9, and 8 bits are used for the ECC system, so the control signal assigned to the parity system is 1 bit. Therefore, in the case of the connection pattern 8, the number of groups is one. For this reason, error detection is performed using 64-bit transmission data using 1-bit error detection bits.

  FIG. 6 shows an example of the allocation table after the connection pattern 9. In the case of connection pattern 9, the number of normal bits is 74, so the number of control signal bits is 8. In the ECC method, when the error detection target is 64 bits, 8 bits are used for the error detection bit.

  Therefore, in the case of connection pattern 9, ECC method error detection using 8-bit control signals is performed on 64-bit transmission data. In the case of connection pattern 9, since the ECC method is applied, transmission data error correction is possible.

  In the case of the connection pattern 10, since the number of normal bits is 73, the number of control signal bits is 7. As described above, in the ECC method, when the error detection target is 64 bits, 8 error detection bits are used. Therefore, in the case of the connection pattern 10, one control signal bit number is insufficient.

  Therefore, in the case of the connection pattern 10, the ECC method is not applied. In the case of the connection pattern 10, 64-bit transmission data is grouped into seven groups. The number of bits belonging to one group is 10 bits.

  A 1-bit control signal is assigned to one group. As a result, error detection using one error detection bit is performed on 10 bits that are the object of error detection.

  In the case of the connection pattern 17, the number of control signal bits is zero. Therefore, error detection is not performed. In the case of the connection pattern 18, the number of bits (= 1 bit) obtained by subtracting the number of transmission data bits from the number of normal bits is less than 2 bits used for the retransmission request.

  In this case, no retransmission request is made. On the other hand, since 1 bit can be assigned to the control signal, a 1-bit control signal is assigned to 64-bit transmission data. In the case of the connection pattern 19, when the number of transmission data bits is subtracted from the number of normal bits, it becomes zero. In this case, retransmission request and error detection are not performed.

  Next, an example in which the first FPGA 11 transmits transmission data to the second FPGA 12 will be described with reference to the example of FIG. The transmission data is given an ID by the ID giving unit 21A. The transmission data to which the ID is assigned is stored in the ring buffer 23A.

  The transmission data to which the ID is assigned is input to the multiplexer 24A. The selection unit 25A performs bit allocation of transmission data to each signal line of the bus 13 based on the normal bit information held by the normal bit information holding unit 28A and the above-described allocation table.

  For example, when a communication failure has occurred in one of the 82 signal lines of the bus 13, the normal bit number indicated by the normal bit information is 81. In this case, the selection unit 25A selects the connection pattern 2 from the allocation table.

  Next, a case where a communication failure has occurred in one of the signal lines of the bus 13 will be described. In this case, since the number of normal bits is 81, the selection unit 25A selects the connection pattern 2 from the allocation table as shown in the example of FIG.

  In connection pattern 2, the ECC method and the parity method are used together. The selection unit 25A controls the multiplexer 24A so that 1 bit is allocated to each of the normal 81 signal lines among the 82 signal lines of the bus 13.

  The selection unit 25A assigns each bit of the transmission data input to the multiplexer 24A to each signal line of the bus 13. In the case of connection pattern 2, a total of 64 bits from bit 0 to bit 63 are allocated to 64 signal lines out of 81 signal lines.

  Further, a 2-bit retransmission request is assigned to two of the remaining 17 signal lines. Then, control signal bits are assigned to the remaining 15 signal lines. Based on the bit assignment of the connection pattern 2, the selection unit 25A controls the multiplexer 24A so that the control signal bits are assigned to the remaining 15 signal lines.

  Therefore, a 15-bit control signal is assigned to 64-bit transmission data. Thereby, error detection by the ECC method using an 8-bit control signal is performed on 64-bit transmission data. In the case of the ECC method, error correction can be performed on transmission data.

  The selection unit 25A controls the multiplexer 24A using the remaining seven signal lines so that error detection is performed on the transmission data by the parity method. In the case of connection pattern 2, 64-bit transmission data is grouped according to the number of remaining signal lines.

  In the case of connection pattern 2, since the number of remaining signal lines is 7, 64-bit transmission data is grouped into 7 groups. The number of bits belonging to each group is grouped so as to be equal. This reduces the number of bits belonging to one group.

  However, the number of bits belonging to one group out of each group is different from the number of bits belonging to other groups. In the case of connection pattern 2 in the example of FIG. 8, the number of bits belonging to 6 groups out of 7 groups is 10. In this case, the total number of bits belonging to the six groups is 60.

  Therefore, in this case, 4 bits from bit 60 to bit 63 are redundant. As shown in connection pattern 2 of the allocation table in the example of FIG. 8, in this case, a 1-bit control signal is allocated to the extra 4 bits.

  As described above, the selection unit 25A selects the connection pattern corresponding to the number of normal bits from the allocation table, and controls the multiplexer 24A so as to perform bit allocation of the control signal based on the selected connection pattern.

  In the case of connection pattern 2, the selection unit 25A selects an ECC method and a parity method. Thereby, when 63 signal lines out of 64 signal lines of the bus 13 are normal, the ECC method and the parity method are used together, and the accuracy of error detection of transmission data can be improved.

  In the case of connection pattern 2, since the number of normal signal lines is large, the number of bits belonging to one group of the parity scheme is reduced. For this reason, the accuracy of error detection by the parity method is also improved.

  As a result, error detection of an appropriate method according to the number of normal signal lines among the signal lines of the bus 13 is performed. For this reason, the reliability of error detection is improved. In the case of connection pattern 2, since the ECC method is selected, transmission data error correction is also performed.

  Next, a case where communication failure has occurred in eight signal lines among the signal lines of the bus 13 will be described. In this case, since the number of normal bits is 74, as illustrated in the example of FIG. 9, the selection unit 25A selects the connection pattern 9 from the allocation table.

  The selection unit 25A assigns each bit of the transmission data to 74 signal lines of the bus 13 excluding the 8 signal lines causing the communication failure. Since two signal lines are allocated for the retransmission request, the number of remaining signal lines is eight.

  When ECC error detection is applied to 64-bit transmission data, 8-bit error detection bits are used. Therefore, in the case of the connection pattern 9, the remaining eight signal lines are all assigned as control signal bits used in the ECC system.

  In this case, there is no signal line assigned to the parity method. Therefore, the selection unit 25A selects only the ECC method based on the connection pattern 9 in the allocation table, and controls the multiplexer 24A so that error detection and error correction of the ECC method are performed.

  Therefore, in the case of the connection pattern 9, since the error detection of the ECC method is performed, the accuracy of error detection is improved. Thereby, appropriate error detection according to the number of normal signal lines among the signal lines of the bus 13 is performed. For this reason, the reliability of error detection is improved. In the case of connection pattern 9, since the ECC method is selected, transmission data error correction is also performed.

  Next, a case where a communication failure has occurred in nine signal lines among the signal lines of the bus 13 will be described. In this case, since the number of normal bits is 73, as illustrated in the example of FIG. 10, the selection unit 25A selects the connection pattern 10 from the allocation table.

  The selection unit 25A assigns each bit of the transmission data to 73 signal lines of the bus 13 excluding 9 signal lines that cause a communication failure. Since two signal lines are allocated for the retransmission request, the number of remaining signal lines is seven.

  As described above, when ECC error detection is applied to 64-bit transmission data, 8-bit error detection bits are used. In the case of the connection pattern 10, the remaining signal lines are seven (7 bits), which is less than the number of bits used for error detection in the ECC method.

  For this reason, the selection unit 25A selects only the parity method based on the connection pattern 10 in the allocation table. Then, the selection unit 25A groups the 64-bit signal lines, and controls the multiplexer 24A so that a 1-bit control signal is assigned to each group.

  As described above, the number of bits belonging to six groups out of the seven groups is nine. The number of bits belonging to the remaining one group is 10. As a result, the number of bits of transmission data handled by one bit for error detection by the parity method is reduced.

  This increases the accuracy of data error detection. Accordingly, appropriate error detection is performed according to the number of normal signal lines among the signal lines of the bus 13. For this reason, the reliability of error detection is improved.

  As described above, an appropriate error detection method corresponding to the number of normal signal lines among the signal lines of the bus 13 is selected by the selection unit 25A, and transmission data bits are allocated according to the selected method. Multiplexer 24A is controlled to do so.

  The transmission data to which bits are assigned by the multiplexer 24A is transmitted to the second FPGA 12 via the bus 13, as shown in the example of FIG. At this time, the ID and control signal attached to the transmission data are also transmitted to the second FPGA 12 together with the transmission data.

  The transmission data, ID, and control signal received by the second FPGA 12 are also output to the error processing unit 29B. The error processing unit 29B performs transmission data error detection using the input control signal.

  One bit of transmission data and control signal is assigned to each normal signal line in the bus 13. For example, in the case of connection pattern 2, among the control signal bits, a total of 8 bits from bit 0 to bit 7 are assigned as error detection bits according to the ECC method for 64-bit transmission data.

  The error processing unit 29B uses the 8-bit error detection bit (control signal bit) to perform error detection by the ECC method on 64-bit transmission data. Further, the error processing unit 29B performs error correction of transmission data using 1 bit.

  In the connection pattern 2 of the embodiment, the error processing unit 29B uses a 7-bit error detection bit (control signal) to perform error detection using a parity method on 64-bit transmission data.

  As described above, the 64-bit transmission data is grouped, and the error processing unit 29B performs error detection on the 64-bit transmission data using the parity method by using one error detection bit for each group. .

  Further, for example, in the case of the connection pattern 10, since the control signal bits are 7 bits, the number of bits is less than 8 bits for performing error detection by the ECC method for 64-bit transmission data.

  Therefore, the error processing unit 29B performs error detection of transmission data by the parity method using the input control signal. Since the ECC method is not applied to error processing for transmission data, the error processing unit 29B does not perform error correction.

  As described above, for example, it is assumed that the error processing unit 29B detects a 2-bit error by the ECC method. In this case, error correction of transmission data by the ECC method cannot be performed. As described above, when the error correction for the transmission data is not performed, the retransmission request unit 30B makes a retransmission request for the transmission data via the bus 13, as illustrated in the example of FIG.

  As described above, the transmission data, ID, and control signal transmitted from the first FPGA 11 are input to the error processing unit 29B. The retransmission request unit 30B outputs an ID for specifying transmission data for which retransmission is requested. This ID is transmitted to the first FPGA 11 via the two signal lines of the bus 13 assigned for retransmission request.

  The ring buffer 23A of the first FPGA 11 inputs the received ID, and the transmission data corresponding to the received ID is extracted from the ring buffer 23A. At this time, the extracted transmission data may be stored again in the ring buffer 23A.

  As shown in the example of FIG. 13, the transmission data extracted from the ring buffer 23A is input to the multiplexer 24A. The transmission data is bit-allocated by the multiplexer 24A based on the control of the selection unit 25A. Then, the transmission data is transmitted from the first FPGA 11 to the second FPGA 12.

  The error processing unit 29B receives the transmission data received by the second FPGA 12 and performs error detection. For example, in the first error detection, even if a 2-bit error is detected by the ECC method due to a software error or the like, the situation is improved and the error detection by the second ECC method is performed. A 1-bit error may be detected.

  In this case, the error processing unit 29B performs error correction by the ECC method. In the case of the connection patterns 10 to 20 described above, the ECC method is not applied, and only the parity method is applied, so that error correction is not performed.

  Further, it is assumed that the error processing unit 29B detects a 2-bit error even in the second error detection. In this case, the retransmission request unit 30B may make a retransmission request to the first FPGA 11 again.

  Next, an example of the processing flow of the embodiment will be described with reference to the sequence chart of the example of FIG. The test data generation unit 22A of the first FPGA 11 generates test data. The generated transmission data is transmitted to the second FPGA 12 via the bus 13 (step S1).

  The detection unit 26B of the second FPGA 12 compares the test data and detects a normal bit that does not cause a communication failure (step S2). Then, the normal bit information generation unit 27B generates normal bit information indicating normal bits, and transmits the generated normal bit information to the first FPGA 11 (step S3).

  The normal bit information holding unit 28A of the first FPGA 11 holds the received normal bit information (step S4). Thereby, the same normal bit information is shared by the first FPGA 11 and the second FPGA 12.

  Transmission data with an ID is input to the multiplexer 24A. The selection unit 25A selects an error detection method based on the normal bit information and the allocation table (step S5).

  The error detection method selected differs depending on the number of normal bits. If the number of normal bits is large, two methods of a parity method and an ECC method are selected. Depending on the number of normal bits, either the parity method or the ECC method is selected.

  The multiplexer 24A assigns each bit of transmission data, ID, and control signal to a normal signal line in the bus 13 under the control of the selection unit 25A (step S6). Then, each bit of the transmission data, ID, and control signal is transmitted to the second FPGA 12 via the bus 13.

  The error processing unit 29B performs error detection based on the transmission data and the control signal (step S7). Then, the error processing unit 29B determines whether error correction is possible (step S8). If error correction is possible (YES in step S8), the process proceeds to step S11. On the other hand, if error correction is not possible (NO in step S8), the process proceeds to step S9.

  For example, if a 2-bit error is detected as a result of error detection by the ECC method, the retransmission request unit 30B makes a retransmission request for the transmission data specified by the ID to the first FPGA 11 (step S9). ).

  The first FPGA 11 extracts the transmission data specified by the ID indicated by the retransmission request from the ring buffer 23A, and retransmits the transmission data from the multiplexer 24 (step S10).

  The error processing unit 29B of the second FPGA 12 performs error correction if error correction is possible based on the received transmission data and the control signal (step S11). For example, when the error detected by the error processing unit 29B is 1 bit, the error processing unit 29B performs error correction by the ECC method.

  In the embodiment, an appropriate error detection method is selected in order to select a method for detecting an error in transmission data transmitted from the first FPGA 11 to the second FPGA 12 according to the number of normal signal lines in the bus 13. Thereby, the reliability of communication between the first FPGA 11 and the second FPGA 12 is improved.

<Others>
The present embodiment is not limited to the above-described embodiment, and various configurations or embodiments can be taken without departing from the gist of the present embodiment.

1 Electronic device 11 1st FPGA
12 Second FPGA
13 Bus 21 ID assignment unit 22 Test data generation unit 23 Ring buffer 24 Multiplexer 25 Selection unit 26 Detection unit 27 Normal bit information generation unit 28 Normal bit information holding unit 29 Error processing unit 30 Retransmission request unit

Claims (8)

An electronic device having programmable devices connected to each other by a plurality of signal lines,
The programmable device is:
Detection for detecting the number of normal signal lines among the plurality of signal lines based on test data communicated through the plurality of signal lines in a number larger than the number of bits of data communicated between the programmable devices. And
A selection unit that selects a method of detecting an error in the data according to the number of the normal signal lines;
An electronic device comprising: The method for detecting the error is a first method using one bit to detect the error, or a second method using a plurality of bits.
The selection unit selects either the first method or the second method according to the number of the normal signal lines, or selects both the first method and the second method.
The electronic device according to claim 1. 1 bit of the data is assigned to each of the normal signal lines,
The selection unit uses a predetermined number of signal lines out of the normal signal lines not assigned to the data as control signal lines, and the number of control signal lines is the number of bits used in the second method. If not, select the first method,
Error detection by the first method is performed on the data;
The electronic device according to claim 2. When the number of the control signal lines is larger than the number of bits used in the second method, the selection unit selects both the first method and the second method,
Error detection by the first method and error detection by the second method are performed on the data.
The electronic device according to claim 3. The selection unit allocates a plurality of bits used in the second method to the control signal lines, groups the bits of the data based on the number of remaining control signal lines, and Allocating 1 bit used for the first method,
The electronic device according to claim 4, wherein: The selection unit groups each bit of the data so that the number of bits of the data belonging to the one group is equal;
6. The electronic apparatus according to claim 5, wherein The programmable device is:
A storage unit for storing the transmitted data;
When an error is detected in the data and the error is not corrected, a retransmission request unit that makes a retransmission request for the data stored in the storage unit to the transmission source of the data;
The electronic apparatus according to claim 1, further comprising: A communication error detection method between programmable devices for detecting an error in data communicated between programmable devices connected to each other by a plurality of signal lines,
Based on test data communicated through the plurality of signal lines in a number greater than the number of bits of data communicated between the programmable devices, the number of normal signal lines among the plurality of signal lines is detected,
According to the number of normal signal lines, a method for detecting an error in the data is selected.
A communication error detection method between programmable devices.

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