JP2017168653A - Semiconductor device and manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which the decrease in reliability is suppressed.SOLUTION: A semiconductor device includes: a first substrate including an insulating layer having a first opening which exposes at least a part of a first conductive pad and in which an exposure area of the first conductive pad is a first area, a second opening which exposes at least a part of a second conductive pad and in which an exposure area of the second conductive pad is a second area different from the first area, and a third opening which exposes at least a part of a third conductive pad and in which an exposure area of the third conductive pad is a third area that is a value between the first area and the second area; a second substrate including fourth to sixth conductive pads; a first bump electrically connecting between the first and fourth conductive pads; a second bump electrically connecting between the second and fifth conductive pads; and a third bump electrically connecting between the third and sixth conductive pads.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In recent years, with the development of communication technology and information processing technology, there is a demand for downsizing and speeding up of semiconductor devices. In order to cope with this, in a semiconductor device, three-dimensional mounting by laminating a plurality of semiconductor chips shortens the length of wiring between components to cope with an increase in operating frequency and increase mounting area efficiency. Development of targeted semiconductor packages is underway.

  In the manufacture of a semiconductor device having a three-dimensional mounting structure, flip chip bonding is performed on a mounting substrate or a semiconductor chip via a bump such as a solder ball, and the mounting substrate or the semiconductor chip and other semiconductors are formed using an underfill resin. Seal between the chip.

  In a semiconductor device having a three-dimensional mounting structure, a semiconductor chip is very thin and easily deformed for downsizing and thinning. For this reason, the warp of the semiconductor chip is likely to occur. When the warpage of the semiconductor chip occurs, a bump that is not connected between the mounting substrate or the semiconductor chip and another semiconductor chip may occur, resulting in poor connection. As described above, the semiconductor device having the three-dimensional mounting structure has a problem that the reliability is lowered due to warpage of the semiconductor chip.

US Pat. No. 8,703,600

  The problem to be solved by the invention of the embodiment is to suppress a decrease in reliability of the semiconductor device.

  In the semiconductor device of the embodiment, the first to third conductive pads and at least a part of the first conductive pad are exposed, and the exposed area of the exposed first conductive pad is the first area. A first opening having a second area that exposes at least a portion of the first opening and the second conductive pad, and has an exposed area of the exposed second conductive pad that is different from the first area. The third opening that exposes at least a portion of the second opening and the third conductive pad, and the exposed area of the exposed third conductive pad is a value between the first area and the second area. And a fourth substrate that is provided so as to face the first substrate and overlaps with the first conductive pad. A pad, a fifth conductive pad overlying the second conductive pad, and a third conductive pad. A second substrate comprising: a sixth conductive pad overlapping with the first conductive pad; a first bump electrically connecting the first conductive pad and the fourth conductive pad; A second bump electrically connecting between the conductive pad and the fifth conductive pad; and a third bump electrically connecting between the third conductive pad and the sixth conductive pad. And a bump. The second conductive pad is closer to the geometric center of the first substrate than the first conductive pad. The third conductive pad is closer to the geometric center of the first substrate than the first conductive pad and farther from the geometric center of the first substrate than the second conductive pad.

It is a cross-sectional schematic diagram for demonstrating the example of the manufacturing method of a semiconductor device. It is a cross-sectional schematic diagram which shows the structural example of the semiconductor device after a joining process. It is a cross-sectional schematic diagram which shows the other structural example of a semiconductor device. It is a cross-sectional schematic diagram which shows the other structural example of a semiconductor device. It is a plane schematic diagram which shows the structural example of a semiconductor device. It is a cross-sectional schematic diagram which shows the structural example of a semiconductor device. It is a cross-sectional schematic diagram which shows the example of a structure of a part of connection part between a wiring board and a chip laminated body.

  Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic, and for example, the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like may be different from the actual ones. In the embodiments, substantially the same constituent elements are denoted by the same reference numerals and description thereof is omitted.

  FIG. 1 is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device. In an example of a method for manufacturing a semiconductor device, a substrate 1 including conductive pads 11a to 11c and an insulating layer 12 and a substrate 2 including conductive pads 21a to 21c are electrically conductive with the conductive pads 21a sandwiching bumps 31a. The conductive pad 21b is superimposed on the pad 11a, the conductive pad 21b is superimposed on the conductive pad 11b with the bump 31b interposed therebetween, and the conductive pad 21c is joined so as to be superimposed on the conductive pad 11c with the bump 31c interposed therebetween. The numbers of conductive pads and bumps are not limited to the numbers shown in FIG.

  The substrate 1 has, for example, a rectangular planar shape. As the substrate 1, for example, a wiring substrate is used. The wiring board only needs to be capable of mounting a semiconductor element and have a wiring network. The wiring board may include a semiconductor substrate such as a silicon substrate, a glass substrate, a resin substrate, or a metal substrate, for example.

  The conductive pad 11b is closer to the geometric center of the substrate 1 (hereinafter referred to as the center) than the conductive pad 11a. The center of the substrate 1 is, for example, the center of the planar shape of the substrate 1. Further, as shown in FIG. 1, the conductive pad 11c is closer to the center of the substrate 1 than the conductive pad 11a and farther from the center of the substrate 1 than the conductive pad 11b. As the conductive pads 11a to 11c, for example, a single layer or a stacked layer of aluminum, copper, titanium, titanium nitride, chromium, nickel, gold, palladium, or the like can be used.

  The insulating layer 12 includes an opening 12a exposing at least a part of the conductive pad 11a, an opening 12b exposing at least a part of the conductive pad 11b, and an opening exposing at least a part of the conductive pad 11c. 12c. As the insulating layer 12, for example, an insulating material such as a solder resist is used. For example, a silicon oxide layer or a silicon nitride layer can be used as the insulating layer 12 without being limited thereto. In addition to a silicon oxide layer, a silicon nitride layer, or the like, an organic resin layer may be provided as an insulating layer. The opening 12a to the opening 12c are formed by etching a part of the insulating layer 12, for example.

  Before the step of bonding the substrate 1 and the substrate 2, a step of forming the bumps 31a to 31c on the substrate 1 may be performed. The bump 31a is provided on the conductive pad 11a. The bump 31b is provided on the conductive pad 11b. The bump 31c is provided on the conductive pad 11c. Without being limited thereto, the bumps 31 a to 31 c may be formed on the substrate 2. In this case, the bump 31a is provided on the conductive pad 21a (the lower surface side of the substrate 2 in FIG. 1), the bump 31b is provided on the conductive pad 21b (the lower surface side of the substrate 2 in FIG. 1), and the bump 31c is provided. It is provided on the conductive pad 21c (the lower surface side of the substrate 2 in FIG. 1).

  For example, solder bumps such as solder balls are used as the bumps 31a to 31c. As the solder bumps, for example, tin-silver or tin-silver-copper lead-free solder bumps can be used.

  The substrate 2 has, for example, a rectangular planar shape. For example, a semiconductor chip or the like is used as the substrate 2. Further, a stacked body of a plurality of semiconductor chips or a semiconductor package having the chip stacked body may be used as the substrate 2. The substrate 2 includes a semiconductor substrate such as a silicon substrate.

  At least a part of each of the conductive pads 21 a to 21 c is exposed on the substrate 2. As shown in FIG. 1, the conductive pad 21b is closer to the center of the substrate 2 than the conductive pad 21a. The center of the substrate 2 is, for example, the center of the planar shape of the substrate 2. Further, as shown in FIG. 1, the conductive pad 21c is closer to the center of the substrate 2 than the conductive pad 21a and farther from the center of the substrate 2 than the conductive pad 21b. As the conductive pads 21a to 21c, for example, a single layer or a laminate of aluminum, copper, titanium, titanium nitride, chromium, nickel, gold, palladium, or the like can be used.

  The substrate 2 is bonded to the substrate 1 so that the formation surfaces of the conductive pads 21a to 21c face the formation surfaces of the conductive pads 11a to 11c. The substrate 2 shown in FIG. 1 is warped so that the surface on the opposite side of the surface on the substrate 1 side is convex. Since the semiconductor chip used as the substrate 2 is very thin, it may warp before or after the bonding process. At this time, if the bumps 31a to 31c have the same height, the conductive pads located in the wide area between the substrate 1 and the substrate 2 among the conductive pads 21a to 21c are not connected to the bumps. Connection failure may occur.

  In order to suppress the above-mentioned connection failure, for example, it is conceivable to form bumps having different sizes for each region where the distance between the substrate 1 and the substrate 2 is different. However, it is difficult in the manufacturing process to form a plurality of bumps having different sizes.

  In the method for manufacturing a semiconductor device according to the present embodiment, the exposed area of the conductive pad exposed in the opening of the insulating layer 12 is made different for each region where the distance between the substrate 1 and the substrate 2 is different. As shown in FIG. 1, for example, the exposed area of the conductive pad 11a exposed in the opening 12a has an area S1. The exposed area of the conductive pad 11b exposed in the opening 12b has an area S2 having a value different from the area S1. The exposed area of the conductive pad 11c exposed in the opening 12c has an area S3 that is a value between the area S1 and the area S2. In FIG. 1, as an example, the area S2 is a value smaller than the area S1, and the area S3 is smaller than the area S1 and larger than the area S2. However, the present invention is not limited to this, and the area S2 is larger than the area S1. The area S3 may be larger than the area S1 and smaller than the area S2.

  When the exposed areas of the conductive pads 11a to 11c exposed in the openings 12a to 12c of the insulating layer 12 are different from each other, the contact areas of the conductive pads 11a to 11c and the bumps 31a to 31c are also different. For this reason, the height of the bump changes according to the difference in surface tension. For example, the bump 31a has a height corresponding to the area S1. The bump 31b has a height corresponding to the area S2. The bump 31c has a height corresponding to the area S3. In FIG. 1, the bump 31b is higher than the bump 31a, and the bump 31c is higher than the bump 31a and lower than the bump 31b, but is not limited thereto.

  In this way, by changing the exposed areas of the conductive pads 11a to 11c exposed in the openings 12a to 12c of the insulating layer 12, even if the bumps 31a to 31c have the same volume, the bumps 31a to 31c. Can be different from each other. Further, the exposed areas of the conductive pads 11a to 11c exposed in the openings 12a to 12c can be changed by, for example, etching a part of the insulating layer 12 to change a mask pattern for forming the openings 12a to 12c and the like. Can be different. Therefore, a plurality of bumps having different heights can be easily formed without increasing the number of manufacturing steps. Note that when the substrate 1 is a wiring substrate, for example, it is less likely to warp than the substrate 2 which is a semiconductor chip. Therefore, by forming the bumps 31a to 31c on the substrate 1, the positional deviation of the bumps 31a to 31c can be suppressed.

  FIG. 2 is a schematic cross-sectional view showing a structural example of the semiconductor device after the bonding step. As described above, the heights of the bumps 31a to 31c differ depending on the distance between the substrate 1 and the substrate 2. In the bonding step, the bump 31a is located between the conductive pad 11a and the conductive pad 21a so as to have a height corresponding to the distance L1 between the conductive pad 11a and the conductive pad 21a as shown in FIG. Are electrically connected. Further, the bump 31b electrically connects the conductive pad 11b and the conductive pad 21b so as to have a height corresponding to the distance L2 between the conductive pad 11b and the conductive pad 21b. Further, the bump 31c electrically connects the conductive pad 11c and the conductive pad 21c so as to have a height corresponding to the distance L3 between the conductive pad 11c and the conductive pad 21c. In FIG. 2, the interval L2 is wider than the interval L1, and the interval L3 is wider than the interval L1 and narrower than the interval L2, but it is not limited to this.

  A region between the substrate 1 and the substrate 2 is sealed by forming a sealing resin layer 4 such as an underfill resin between the substrate 1 and the substrate 2 after the bonding step. The semiconductor device is manufactured through the above steps.

  In the example of the semiconductor device manufacturing method of the present embodiment, the substrate 1 and the substrate 2 are bonded using a plurality of bumps having different heights for each region where the distance between the substrate 1 and the substrate 2 is different. Thereby, even if it is a case where the board | substrate 2 warps in the process before or after a joining process, the connection failure between the board | substrate 1 and the board | substrate 2 can be suppressed. Therefore, the reliability of the semiconductor device is improved.

  The structural example of the semiconductor device is not limited to the structural example illustrated in FIG. FIG. 3 is a schematic cross-sectional view showing another structure example of the semiconductor device. In the semiconductor device shown in FIG. 3, the conductive pads 21 a to 21 c exposed on the substrate 2 are different from each other according to the distance between the substrate 1 and the substrate 2 as compared with the semiconductor device shown in FIG. 2. The configuration having the exposed area is different.

  In the semiconductor device shown in FIG. 3, the exposed area of the conductive pad 21a exposed on the substrate 2 has the first area, and the exposed area of the conductive pad 21b exposed on the substrate 2 is different from the first area. The exposed area of the conductive pad 21c exposed on the substrate 2 has a third area which is a value between the first area and the second area. The relationship in size of the exposed areas of the conductive pads 21a to 21c is designed corresponding to the size of the exposed areas of the conductive pads 11a to 11c. In the semiconductor device shown in FIG. 3, the exposed area of the conductive pad 21b is smaller than the exposed area of the conductive pad 21a, and the exposed area of the conductive pad 21c is smaller than the exposed area of the conductive pad 21a. The value is larger than the exposed area of the pad 21b. Without being limited thereto, the exposed area of the conductive pad 21b is larger than the exposed area of the conductive pad 21a, and the exposed area of the conductive pad 21c is larger than the exposed area of the conductive pad 21a. It may be a value smaller than the exposed area.

  As shown in FIG. 3, in addition to the openings 12a to 12c of the insulating layer 12, the exposed areas of the conductive pads 21a to 21c are made different according to the distance between the substrate 1 and the substrate 2 to further increase the bumps. Can be high. Thereby, the connection failure between the board | substrate 1 and the board | substrate 2 can further be suppressed. Therefore, the reliability of the semiconductor device is improved.

  FIG. 4 is a schematic cross-sectional view showing another structural example of the semiconductor device. The semiconductor device shown in FIG. 4 is different from the semiconductor device shown in FIG. 2 in that the substrate 2 is warped so that the surface on the substrate 1 side is convex. In the semiconductor device shown in FIG. 4, the area S2 is larger than the area S1, and the area S3 is larger than the area S1 and smaller than the area S2.

  The bump 31a electrically connects the conductive pad 11a and the conductive pad 21a so as to have a height corresponding to the distance L1 between the conductive pad 11a and the conductive pad 21a. Further, the bump 31b electrically connects the conductive pad 11b and the conductive pad 21b so as to have a height corresponding to the distance L2 between the conductive pad 11b and the conductive pad 21b. Further, the bump 31c electrically connects the conductive pad 11c and the conductive pad 21c so as to have a height corresponding to the distance L3 between the conductive pad 11c and the conductive pad 21c.

  In FIG. 4, the interval L2 is shorter than the interval L1, and the interval L3 is shorter than the interval L1 and longer than the interval L2. It should be noted that the substrate 2 is not limited to FIGS. 2 and 4 and may be curved, for example. Even in this case, a plurality of bumps having different heights are formed by changing the exposed area of the conductive pad exposed in the opening of the insulating layer 12 according to the distance between the substrate 1 and the substrate 2. Thereby, the connection failure between the board | substrate 1 and the board | substrate 2 can be suppressed. Therefore, the reliability of the semiconductor device is improved.

(Second Embodiment)
5 and 6 are diagrams illustrating a structure example of a semiconductor device in which semiconductor chips having through electrodes such as TSV (Through Silicon Via) are stacked. FIG. 5 is a top view, and FIG. 6 is a cross-sectional view taken along line AB in FIG. In FIG. 5, some components are not shown for convenience. In addition, about the part which is common in the component of 1st Embodiment, description of 1st Embodiment can be used suitably.

  A semiconductor device 100 shown in FIGS. 5 and 6 includes a wiring substrate 101 having a first surface and a second surface facing each other, a chip stack 102 mounted on the first surface of the wiring substrate 101, a wiring A sealing resin layer 103 that seals between the substrate 101 and the chip stack 102, a sealing resin layer 104 provided so as to cover the chip stack 102, and a second surface of the wiring substrate 101. And an external connection terminal 105.

  The wiring substrate 101 corresponds to the substrate 1 in the first embodiment. The wiring substrate 101 includes a plurality of connection pads 111 and an insulating layer 112 that exposes at least a part of the connection pads 111. The connection pad 111 corresponds to any one of the conductive pads 11a to 11c in the first embodiment, and the insulating layer 112 corresponds to the insulating layer 12 in the first embodiment. Further, the first surface of the wiring substrate 101 corresponds to the upper surface of the wiring substrate 101 in FIG. 6, and the second surface corresponds to the lower surface of the wiring substrate 101 in FIG.

  The chip stacked body 102 corresponds to the substrate 2 in the first embodiment. The chip stacked body 102 is electrically connected to the wiring substrate 101 via the plurality of connection pads 111 of the wiring substrate 101. The chip stack 102 includes a plurality of semiconductor chips 121 and semiconductor chips 126. An insulating adhesive layer 122 is provided between the plurality of semiconductor chips 121. The insulating adhesive layer 122 seals between the plurality of semiconductor chips 121. Note that the number of stacked semiconductor chips 121 is not limited to the number shown in FIG. Moreover, although the planar shape of the semiconductor chip 121 is a square, it is not limited to this.

  The insulating adhesive layer 122 has a function as a sealing material that seals between the plurality of semiconductor chips 121. As the insulating adhesive layer 122, for example, a thermosetting insulating adhesive material having both an adhesive function and a sealing function such as NCF (Non-Conductive Film: NCF) can be used. The insulating adhesive material includes, for example, an epoxy resin.

  The plurality of semiconductor chips 121 are electrically connected to each other through a plurality of through electrodes 123 that penetrate the semiconductor chip 121 and a plurality of bumps 124 that penetrate the insulating adhesive layer 122. For example, the plurality of semiconductor chips 121 can be electrically connected to each other by electrically connecting the conductive pads provided on the plurality of semiconductor chips 121 with the through electrodes 123 and the bumps 124. Note that when the wiring substrate 101 side is the upper surface of the chip stacked body 102, the through electrode may not be provided in the lowermost semiconductor chip 121.

  As the semiconductor chip 121, for example, a memory chip or the like can be used. As the memory chip, for example, a storage element such as a NAND flash memory can be used. Note that a circuit such as a decoder may be provided in the memory chip.

  The semiconductor chip 126 is electrically connected to the semiconductor chip 121 via the rewiring layer 125 provided on the uppermost semiconductor chip 121 when the wiring substrate 101 side is the upper surface of the chip stack 102. The rewiring layer 125 may function as a planarization layer. The chip stacked body 102 is electrically connected to the wiring substrate 101 via connection pads 127 and bumps 128 provided on the rewiring layer 125. The bump 128 corresponds to any of the bumps 31a to 31c shown in FIG.

  As the semiconductor chip 126, for example, an interface chip or a controller chip can be used. For example, when the semiconductor chip 121 is a memory chip, a controller chip is used as the semiconductor chip 126, and writing to and reading from the memory chip can be controlled by the controller chip. Note that the semiconductor chip 126 is preferably smaller than the semiconductor chip 121.

  The chip stack 102 is formed as follows, for example. First, another semiconductor chip 121 having a bump layer and an insulating adhesive layer 122 formed thereon is stacked on one semiconductor chip 121 by using a mounter or the like, and finally the semiconductor chip 121 having a rewiring layer formed on the surface thereof. to paste together. Further, heat treatment is performed to melt at least a part of the bump layer or the insulating adhesive layer 122, and then the semiconductor chip 121 is penetrated through the insulating adhesive layer 122 while curing the insulating adhesive layer 122 by cooling. Bumps 124 are formed for electrical connection therebetween.

  Thereafter, the semiconductor chip 126 is mounted on the rewiring layer 125, and the connection pad 127 and the plurality of bumps 128 are formed, whereby the chip stacked body 102 is formed.

  The chip stack 102 is mounted on the wiring substrate 101 using a mounter or the like so that the rewiring layer 125 is positioned inside by being inverted, for example. At this time, the stacking order of the chip stacked body 102 is reverse to that at the time of forming the chip stacked body 102. Bonding between the wiring substrate 101 and the chip stack 102 is performed using, for example, a pulse heat method. However, the present invention is not limited to this, and the chip stacked body 102 may be mounted by temporarily bonding the wiring substrate 101 and the chip stacked body 102 and then performing main bonding using the bumps 128 by reflow.

  As the sealing resin layer 103, for example, an underfill resin or the like can be used. Note that the sealing resin layer 103 is not necessarily provided. For example, the sealing resin layer 103 can be formed by filling the underfill resin with a dispenser using a needle or the like.

As the sealing resin layer 104, a resin material containing an inorganic filler such as SiO ₂ , for example, an inorganic filler mixed with an insulating organic resin material or the like can be used. The inorganic filler is contained in 80% to 95% by mass of the whole, and has a function of adjusting the viscosity, hardness, and the like of the sealing resin layer 104. As the organic resin material, for example, an epoxy resin can be used.

  For example, the external connection terminal 105 is applied with a solder ball on the second surface of the wiring board 101, and then a solder ball is mounted, and the solder ball is melted by being put in a reflow furnace, and joined to the connection pad of the wiring board 101. . Thereafter, the flux is removed by washing with a solvent or pure water. For example, the external connection terminals 105 may be formed by forming bumps. The number of external connection terminals 105 is not limited to the number shown in FIG.

  FIG. 7 is a schematic cross-sectional view showing a structural example of a part of a connection portion between the wiring substrate 101 and the chip stack 102. In FIG. 7, the connection pad 111, the insulating layer 112 having an opening exposing at least a part of the connection pad 111, the through electrode 123, the conductive layer 129 provided on the through electrode 123, and the conductive layer 129 Insulating layer 131 having an opening exposing at least a part thereof, rewiring layer 125 electrically connected to conductive layer 129 in the opening of insulating layer 131, and opening exposing at least a part of rewiring layer 125 An insulating layer 132 having a portion, a connection pad 127 electrically connected to the rewiring layer 125 in the opening of the insulating layer 132, and a bump 128 electrically connecting the connection pad 111 and the connection pad 127 The sealing resin layer 103 filled between the wiring substrate 101 and the chip stack 102 is shown.

  As the connection pad 111, for example, a material applicable to the conductive pads 11a to 11c can be used. The connection pad 111 illustrated in FIG. 7 includes a conductive layer 111a containing copper, a conductive layer 111b containing nickel, and a conductive layer 111c containing gold. With the above structure, diffusion of elements contained in the bump 128 can be suppressed. Moreover, manufacturing cost can be reduced by using copper. For the insulating layer 112, for example, a material applicable to the insulating layer 12 can be used.

  As the through electrode 123, for example, a simple substance such as nickel, copper, silver, gold, or an alloy thereof can be used. As the conductive layer 129, a single layer or a stacked layer using, for example, aluminum, copper, titanium, titanium nitride, chromium, nickel, gold, or palladium can be used. The connection pad 127 corresponds to one of the conductive pads 21a to 21c, for example. As the connection pad 127, for example, a material applicable to the conductive pads 21a to 21c can be used.

  As the insulating layer 131 and the insulating layer 132, for example, silicon oxide, silicon nitride, epoxy resin, silicone resin, epoxy / silicone mixed resin, acrylic resin, polyimide resin, polyamide resin, or phenol resin can be used. For example, the insulating layer 131 may have a stacked structure of a silicon nitride layer and a resin material layer. The insulating layer 132 may include a resin material layer.

  In the semiconductor device of this embodiment, the exposed area of the connection pad 111 exposed in the opening of the insulating layer 112 is made different according to the interval between the wiring substrate 101 and the chip stack 102 as in the first embodiment. Thus, the height of the bump 128 is varied. Thereby, even if the semiconductor chip in the chip stack 102 is warped, a connection failure between the wiring substrate 101 and the chip stack 102 can be suppressed. Therefore, the reliability of the semiconductor device is improved.

  Each embodiment is presented as an example and is not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 2 ... Board | substrate, 4 ... Sealing resin layer, 11a, 11b, 11c ... Conductive pad, 12 ... Insulating layer, 12a, 12b, 12c ... Opening part, 21a, 21b, 21c ... Conductive pad, 31a , 31b, 31c ... bump, 100 ... semiconductor device, 101 ... wiring board, 102 ... chip laminated body, 103 ... sealing resin layer, 104 ... sealing resin layer, 105 ... external connection terminal, 111 ... connection pad, 111a, 111b, 111c ... conductive layer, 112 ... insulating layer, 121 ... semiconductor chip, 122 ... insulating adhesive layer, 123 ... through electrode, 124 ... bump, 125 ... redistribution layer, 126 ... semiconductor chip, 127 ... connection pad, 128 ... Bump, 129 ... conductive layer, 131 ... insulating layer, 132 ... insulating layer.

Claims (5)

A first opening in which first to third conductive pads and at least a part of the first conductive pad are exposed, and an exposed area of the exposed first conductive pad has a first area. And a second area in which at least a part of the second conductive pad is exposed and an exposed area of the exposed second conductive pad is different from the first area. At least a part of the opening and the third conductive pad is exposed, and an exposed area of the exposed third conductive pad is a value between the first area and the second area. A first substrate comprising: an insulating layer having a third opening having a third area;
A fourth conductive pad that is provided to face the first substrate and overlaps the first conductive pad; a fifth conductive pad that overlaps the second conductive pad; A second substrate comprising: a sixth conductive pad overlapping the third conductive pad;
A first bump for electrically connecting the first conductive pad and the fourth conductive pad;
A second bump for electrically connecting the second conductive pad and the fifth conductive pad;
A third bump for electrically connecting the third conductive pad and the sixth conductive pad;
The second conductive pad is closer to the geometric center of the first substrate than the first conductive pad;
The third conductive pad is closer to the geometric center of the first substrate than the first conductive pad and farther from the geometric center of the first substrate than the second conductive pad. , Semiconductor devices. The first bump has a first height corresponding to the first area;
The second bump has a second height corresponding to the second area,
The semiconductor device according to claim 1, wherein the third bump has a third height corresponding to the third area. First to third conductive pads, a first opening that exposes at least part of the first conductive pad, and a second opening that exposes at least part of the second conductive pad. And a first substrate comprising: a third opening that exposes at least a portion of the third conductive pad; and a first substrate,
A fourth conductive pad that is provided to face the first substrate and overlaps the first conductive pad so as to have a first interval; and a value that is different from the first interval. A fifth conductive pad overlapping the second conductive pad so as to have a spacing of 2, and a third spacing that is a value between the first spacing and the second spacing. A second substrate comprising: a sixth conductive pad superimposed on the third conductive pad;
A first bump that electrically connects the first conductive pad and the fourth conductive pad to have a first height corresponding to the first distance;
A second bump for electrically connecting the second conductive pad and the fifth conductive pad so as to have a second height corresponding to the second distance;
And a third bump for electrically connecting the third conductive pad and the sixth conductive pad to have a third height corresponding to the third distance. ,
The second conductive pad is closer to the geometric center of the first substrate than the first conductive pad;
The third conductive pad is closer to the geometric center of the first substrate than the first conductive pad and farther from the geometric center of the first substrate than the second conductive pad. , Semiconductor devices. First to third conductive pads, a first opening that exposes at least part of the first conductive pad, and a second opening that exposes at least part of the second conductive pad. And a second substrate comprising fourth to sixth conductive pads, and an insulating layer having a third opening exposing at least a portion of the third conductive pad. The fourth conductive pad overlaps the first conductive pad with the first bump interposed therebetween, and the fifth conductive pad sandwiches the second bump with the second conductive pad. A step of superimposing on a pad, and joining the sixth conductive pad so as to overlap the first conductive pad with a third bump interposed therebetween,
The second conductive pad is closer to the geometric center of the first substrate than the first conductive pad;
The third conductive pad is closer to the geometric center of the first substrate than the first conductive pad and farther from the geometric center of the first substrate than the second conductive pad. ,
The first bump has a first height corresponding to a first distance between the first conductive pad and the fourth conductive pad, and the first bump has a first height. Electrically connecting to the fourth conductive pad;
The second bump has a second height corresponding to a second distance between the second conductive pad and the fifth conductive pad, which is a value different from the first distance. Electrically connecting between the second conductive pad and the fifth conductive pad,
The third bump corresponds to a third distance between the third conductive pad and the sixth conductive pad, which is a value between the first distance and the second distance. A method of manufacturing a semiconductor device, wherein the third conductive pad and the sixth conductive pad are electrically connected so as to have a third height.   Before the bonding step, the first bump is formed on the first conductive pad, the second bump is formed on the second conductive pad, and the third conductive is formed. The method for manufacturing a semiconductor device according to claim 4, further comprising a step of forming the third bump on a pad.

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