JP2017163709A - Three-phase inverter and semiconductor module therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor module having an easy-to-manufacture structure and capable of satisfying an equilibrium condition of an equivalent bridge circuit of a three-phase inverter.SOLUTION: A semiconductor module 200U includes: high-voltage side insulation substrates 30, 40 and low-voltage side insulation substrates 50, 60. The high-voltage side insulation substrates 30, 40 have high-voltage side intermediate conductor layers 35, 45 provided between first high-voltage side insulator layers 34a, 44a and second high-voltage side insulator layers 34b, 44b. The low-voltage side insulation substrates 50, 60 have low-voltage side intermediate conductor layers 55, 65 provided between first low-voltage side insulator layers 54a, 64a and second low-voltage side insulator layers 54b, 64b. The high-voltage side intermediate conductor layers 35, 45 and the low-voltage side intermediate conductor layers 55, 65 are structured to connect a high-voltage side switching element SW1 with a mid-point MID_U of a low-voltage side switching element SW2.SELECTED DRAWING: Figure 11

Description

  The technology disclosed in this specification relates to a three-phase inverter and a semiconductor module for the three-phase inverter.

  For example, an electric vehicle includes a three-phase inverter that converts DC power of a DC power source into AC power for driving a traveling motor. Such a three-phase inverter includes a cooler and a semiconductor module, and is configured to efficiently transfer heat generated by a switching element in the semiconductor module to the cooler. Thereby, a three-phase inverter suppresses that the switching element in a semiconductor module becomes high temperature, and implement | achieves the stable operation | movement of a switching element.

  The semiconductor module for a three-phase inverter has an insulating substrate provided between the switching element and the cooler in order to electrically insulate the switching element and the cooler. The insulating substrate functions as a capacitor against high frequency noise. For this reason, a stray capacitance is formed between the switching element and the cooler.

  The switching element switches at high speed when power conversion is performed. For this reason, a switching element becomes a generation source of high frequency noise. Thereby, the high frequency noise generated when the switching element switches generates a common mode current flowing from the switching element through the insulating substrate to the cooler.

  Patent Document 1 finds that when a three-phase inverter is operated, a circuit constituting the three-phase inverter becomes an equivalent bridge circuit, and by satisfying the equilibrium condition of the equivalent bridge circuit, the common mode current Disclosure of technology

JP 2009-273272 A

  In Patent Document 1, in order to satisfy the equilibrium condition of the equivalent bridge circuit, the stray capacitance existing on the insulating substrate between the high-voltage side switching element and the cooler and the low-voltage side switching element and the cooler in the semiconductor module. Disclosed is a technique for adjusting a capacitance ratio between stray capacitances existing on an insulating substrate. In the technique of Patent Document 1, it is necessary to increase the capacity ratio to 100 times or more. For this purpose, it is necessary to make the thickness and / or the material different between the insulating substrates. However, such a design is not easy for the following reasons. The insulating substrate needs to maintain an insulating performance for withstanding a high voltage. Since the insulating performance of the insulating substrate is proportional to the thickness, it is difficult to maintain the insulating performance of the insulating substrate when the thickness of the insulating substrate is reduced to 1/100. The insulating substrate needs to have a low thermal resistance so as not to hinder the cooling performance of the cooler. Since the thermal resistance of the insulating substrate is proportional to the thickness, if the thickness of the insulating substrate is increased 100 times, the cooling performance of the cooler is hindered. Moreover, the material which can be used for the insulating substrate is limited in consideration of insulating performance, low thermal resistance, mechanical strength, and the like. For this reason, it is practically impossible to use materials having dielectric constants different by 100 times between insulating substrates. The present specification provides a three-phase inverter that has a semiconductor module that can be easily manufactured and that can satisfy the equilibrium condition of an equivalent bridge circuit. The present specification also provides a semiconductor module for such a three-phase inverter.

  One embodiment of the three-phase inverter disclosed in the present specification includes a cooler, a semiconductor module that is used by being cooled by the cooler, and constitutes a U phase, a V phase, and a W phase, a high voltage terminal, and a low voltage terminal. . The semiconductor module includes a high voltage side switching element, a low voltage side switching element, a high voltage side insulating substrate, and a low voltage side insulating substrate in each phase. The high voltage side insulating substrate and the low voltage side insulating substrate may be configured separately or may be integrally formed. The semiconductor module may be a double-sided cooling type or a single-sided cooling type. The high voltage side switching element is connected to the high voltage terminal. The low voltage side switching element is connected to the low voltage terminal. The high voltage side switching element and the low voltage side switching element are connected in series between the high voltage terminal and the low voltage terminal. The high voltage side insulating substrate is provided between the high voltage side switching element and the cooler. The low voltage side insulating substrate is provided between the low voltage side switching element and the cooler. The high voltage side insulating substrate includes a first high voltage side insulator layer disposed on the high voltage side switching element side, a second high voltage side insulator layer disposed on the cooler side, and a first high voltage. A high-voltage-side intermediate conductor layer provided between the side-insulator layer and the second high-voltage-side insulator layer; The low voltage side insulating substrate includes a first low voltage side insulator layer disposed on the low voltage side switching element side, a second low voltage side insulator layer disposed on the cooler side, and a first low voltage. A low high voltage side intermediate conductor layer provided between the side insulator layer and the second low voltage side insulator layer; The high voltage side intermediate conductor layer and the low voltage side intermediate conductor layer are configured to be connected to a midpoint between the high voltage side switching element and the low voltage side switching element.

  The equivalent bridge circuit of the three-phase inverter of the above embodiment is configured so as to satisfy the equilibrium condition itself. For this reason, the semiconductor module used in the three-phase inverter of the above-described embodiment has a configuration that has a high degree of design freedom with respect to the thickness and / or material of the insulating substrate and is easy to manufacture.

  It is desirable that the high voltage side insulating substrate has a common form between the phases. Furthermore, it is desirable that the low-voltage side insulating substrate has a common form between the phases. In this case, the equilibrium condition is satisfactorily satisfied in the equivalent bridge circuit of the three-phase inverter.

The circuit structure of an inverter is shown. The principal part sectional drawing of the double-sided cooling type semiconductor module of a prior art is typically shown. The equivalent circuit of the double-sided cooling type semiconductor module of a prior art is shown. The equivalent circuit of the double-sided cooling type semiconductor module of a prior art is shown. The equivalent circuit of the inverter of a prior art is shown. An equivalent circuit when a prior art inverter operates is shown. An equivalent circuit when a prior art inverter operates is shown. An equivalent circuit when a prior art inverter operates is shown. An equivalent circuit when a prior art inverter operates is shown. The structure of a general bridge circuit is shown. The principal part sectional drawing of the double-sided cooling type semiconductor module disclosed by this specification is typically shown. 2 shows an equivalent circuit of a double-sided cooling type semiconductor module disclosed in the present specification. 2 shows an equivalent circuit of a double-sided cooling type semiconductor module disclosed in the present specification. 6 shows an equivalent circuit when the inverter disclosed in this specification operates. 6 shows an equivalent circuit when the inverter disclosed in this specification operates. 6 shows an equivalent circuit when the inverter disclosed in this specification operates. 6 shows an equivalent circuit when the inverter disclosed in this specification operates. The principal part sectional drawing of the single-sided cooling-type semiconductor module disclosed by this specification is typically shown.

  First, in order to help understanding of the technology disclosed in this specification, it will be described that when a three-phase inverter operates, a circuit constituting the three-phase inverter becomes an equivalent bridge circuit. FIG. 1 exemplifies a circuit configuration of a three-phase inverter 1 used by being mounted on an electric vehicle, for example. The three-phase inverter 1 converts DC power from a DC power supply (not shown) into AC power for driving the traveling motor MG.

  The three-phase inverter 1 includes a high voltage terminal 10P, a low voltage terminal 10N, a smoothing capacitor C10, and three legs 10U, 10V, and 10W. The high voltage terminal 10P is connected to the positive electrode of a DC power supply (not shown), and the low voltage terminal 10N is connected to the negative electrode of a DC power supply (not shown). A transformer for transformation may be connected between the three-phase inverter 1 and a DC power supply (not shown).

  The smoothing capacitor C10 has one end connected to the high voltage terminal 10P and the other end connected to the low voltage terminal 10N. The smoothing capacitor C10 smoothes the AC power input to the high voltage terminal 10P and the low voltage terminal 10N.

  The three legs 10U, 10V, and 10W are connected in parallel between the high voltage terminal 10P and the low voltage terminal 10N, and each has two switching elements. As will be described later, each of the legs 10U, 10V, and 10W is configured as a semiconductor module.

  The U-phase leg 10U includes a first switching element SW1 connected to the high voltage terminal 10P and a second switching element SW2 connected to the low voltage terminal 10N. The first switching element SW1 and the second switching element SW2 are connected in series between the high voltage terminal 10P and the low voltage terminal 10N. U-phase midpoint MID_U between first switching element SW1 and second switching element SW2 is connected to one end of U-phase winding MG_U of motor MG. A first diode D1 is connected in antiparallel to the first switching element SW1, and a second diode D2 is connected in antiparallel to the second switching element SW2.

  The V-phase leg 10V includes a third switching element SW3 connected to the high voltage terminal 10P and a fourth switching element SW4 connected to the low voltage terminal 10N. The third switching element SW3 and the fourth switching element SW4 are connected in series between the high voltage terminal 10P and the low voltage terminal 10N. V-phase midpoint MID_V between third switching element SW3 and fourth switching element SW4 is connected to one end of V-phase winding MG_V of motor MG. A third diode D3 is connected in antiparallel to the third switching element SW3, and a fourth diode D4 is connected in antiparallel to the fourth switching element SW4.

  The W-phase leg 10W includes a fifth switching element SW5 connected to the high voltage terminal 10P and a sixth switching element SW6 connected to the low voltage terminal 10N. The fifth switching element SW5 and the sixth switching element SW6 are connected in series between the high voltage terminal 10P and the low voltage terminal 10N. A W-phase midpoint MID_W between the fifth switching element SW5 and the sixth switching element SW6 is connected to one end of the W-phase winding MG_W of the motor MG. A fifth diode D5 is connected in antiparallel to the fifth switching element SW5, and a sixth diode D6 is connected in antiparallel to the sixth switching element SW6.

  Of the combinations of switching elements and diodes, the combination of switching elements SW1, SW3, SW5 and diodes D1, D3, D5 connected to the high voltage terminal 10P is referred to as an upper arm. Of the combinations of switching elements and diodes, the combination of switching elements SW2, SW4, SW6 and diodes D2, D4, D6 connected to the low voltage terminal 10N is referred to as a lower arm. The upper-arm switching elements SW1, SW3, and SW5 are examples of the high-voltage side switching elements described in the claims, and the lower-arm switching elements SW2, SW4, and SW6 are the low-voltage side switching elements described in the claims. It is an example of an element.

  MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors) are used for the switching elements SW1 to SW6 constituting the three-phase inverter 1. Further, these switching elements SW1 to SW6 may be reverse conducting IGBTs in which corresponding diodes D1 to D6 are integrated. Below, the case where switching element SW1-SW6 is IGBT is illustrated.

  FIG. 2 schematically shows a cross-sectional view of the main part of the U-phase semiconductor module 100U constituting the U-phase leg 10U. A U-phase semiconductor module 100U shown in FIG. 2 is an example of a conventional technique. The other V-phase leg 10V and W-phase leg 10W also have a common type semiconductor module. Therefore, hereinafter, only the U-phase semiconductor module 100U will be described, and the description of the other leg 10V, 10W semiconductor modules will be omitted.

  The U-phase semiconductor module 100U is a double-sided cooling type semiconductor module, and is interposed between the opposing coolers 20. The U-phase semiconductor module 100U includes two insulating substrates 30 and 40 corresponding to the semiconductor chip 2 including the first switching element SW1 and the first diode D1. The U-phase semiconductor module 100U further includes two insulating substrates 50 and 60 corresponding to the semiconductor chip 4 including the second switching element SW2 and the second diode D2.

  The first insulating substrate 30 is provided between the semiconductor chip 2 including the first switching element SW1 and the first diode D1 and the cooler 20, and includes a chip-side conductor layer 32, an insulator layer 34, and a cooler-side conductor layer. 36. The chip-side conductor layer 32, the insulator layer 34, and the cooler-side conductor layer 36 are laminated in this order from the chip 2 toward the cooler 20, and the insulator layer 34 forms the chip-side conductor layer 32 and the cooler-side conductor. Insulate layer 36. The chip-side conductor layer 32 is connected to the emitter of the first switching element SW1 and the anode of the first diode D1, and the cooler-side conductor layer 36 is connected to the cooler 20.

  The second insulating substrate 40 is provided between the semiconductor chip 2 including the first switching element SW1 and the first diode D1 and the cooler 20, and includes a chip-side conductor layer 42, an insulator layer 44, and a cooler-side conductor layer. 46. The chip side conductor layer 42, the insulator layer 44, and the cooler side conductor layer 46 are laminated in this order from the chip 2 toward the cooler 20, and the insulator layer 44 includes the chip side conductor layer 42 and the cooler side conductor. Insulate layer 46. The chip-side conductor layer 42 is connected to the collector of the first switching element SW1 and the cathode of the first diode D1, and the cooler-side conductor layer 46 is connected to the cooler 20.

  The third insulating substrate 50 is provided between the semiconductor chip 4 including the second switching element SW2 and the second diode D2 and the cooler 20, and includes a chip-side conductor layer 52, an insulator layer 54, and a cooler-side conductor layer. 56. The chip-side conductor layer 52, the insulator layer 54, and the cooler-side conductor layer 56 are laminated in this order from the chip 4 toward the cooler 20, and the insulator layer 54 forms the chip-side conductor layer 52 and the cooler-side conductor. Insulate layer 56. The chip-side conductor layer 52 is connected to the collector of the second switching element SW2 and the cathode of the second diode D2, and the cooler-side conductor layer 56 is connected to the cooler 20.

  The fourth insulating substrate 60 is provided between the semiconductor chip 4 including the second switching element SW2 and the second diode D2 and the cooler 20, and includes a chip-side conductor layer 62, an insulator layer 64, and a cooler-side conductor layer. 66. The chip side conductor layer 62, the insulator layer 64, and the cooler side conductor layer 66 are laminated in this order from the chip 4 toward the cooler 20, and the insulator layer 64 forms the chip side conductor layer 62 and the cooler side conductor. Insulate layer 66. The chip-side conductor layer 62 is connected to the collector of the second switching element SW2 and the cathode of the second diode D2, and the cooler-side conductor layer 66 is connected to the cooler 20.

  The chip side conductor layer 42 of the second insulating substrate 40 is connected to the high voltage terminal 10P, and the chip side conductor layer 52 of the third insulating substrate 50 is connected to the low voltage terminal 10N. The chip-side conductor layer 32 of the first insulating substrate 30 and the chip-side conductor layer 62 of the fourth insulating substrate 60 are connected via the connection wiring 72 and constitute the U-phase midpoint MID_U.

  Thus, each of the insulating substrates 30, 40, 50, 60 has a capacitor structure. For this reason, stray capacitance is formed in each of these capacitor structures. FIG. 3 shows an equivalent circuit of the U-phase semiconductor module 100U. FIG. 4 shows an equivalent circuit of the U-phase semiconductor module 100U in which the equivalent circuit of FIG. 3 is arranged. 3 and 4, the stray capacitance existing in each of the insulating substrates 30, 40, 50 and 60 is indicated by a broken line. Thus, the stray capacitance Cp_U exists between the chip-side conductor layer 42 and the cooler-side conductor layer 46 (that is, the cooler 20) of the second insulating substrate 40, and the stray capacitance Cn_U is the chip of the third insulating substrate 50. It exists between the side conductor layer 52 and the cooler side conductor layer 56 (that is, the cooler 20). Further, the stray capacitance Cmid_U is cooled between the chip-side conductor layer 32 and the cooler-side conductor layer 36 (that is, the cooler 20) of the first insulating substrate 30 and between the chip-side conductor layer 62 of the fourth insulating substrate 60 and the cooling. It exists between the container side conductor layers 66 (that is, the cooler 20).

  As described above, each of the semiconductor modules constituting the legs 10U, 10V, and 10W has a common form. Therefore, like the U-phase semiconductor module 100U of the U-phase leg 10U described in FIG. 3 and FIG. 4, stray capacitances also exist in each of the other leg 10V, 10W semiconductor modules. FIG. 5 shows stray capacitances present in all the leg 10U, 10V, 10W semiconductor modules constituting the three-phase inverter 1. Note that the other end of each of the windings MG_U, MG_V, MG_W constituting the motor MG is grounded via a ground floating capacitance Cm.

  FIG. 6 shows an equivalent circuit of the three-phase inverter 1 when the three-phase inverter 1 operates. In FIG. 6, the U-phase leg 10U performs a switching operation, the third switching element SW3 of the V-phase leg 10V and the fifth switching element SW5 of the W-phase leg 10W are in a conductive state (short circuit), and the V-phase leg 10V The case where 4 switching element SW4 and 6th switching element SW6 of W phase leg 10W are a non-conduction state (open | released) is shown. In the U-phase leg 10U that performs the switching operation, the first switching element SW1 and the second switching element SW2 can be regarded as voltage sources having opposite phases of high-frequency noise. Since the smoothing capacitor C10 has a low impedance to high frequency noise, it can be regarded as a short circuit.

  FIG. 7 shows an equivalent circuit of the three-phase inverter 1 in which the equivalent circuit of FIG. 6 is arranged. As shown in FIG. 7, the voltage source of high frequency noise by the first switching element SW1 and the second switching element SW2 is a voltage source of the same amplitude connected in parallel. For this reason, these can be put together into one voltage source. Further, as described above, the semiconductor modules constituting the legs 10U, 10V, and 10W have a common form. That is, the corresponding insulating substrates 30, 40, 50, 60 are common among the semiconductor modules constituting the legs 10 U, 10 V, 10 W. Therefore, the stray capacitances Cn_U, Cn_V, and Cn_W of the legs 10U, 10V, and 10W can be commonly expressed as the stray capacitance Cn, and the stray capacitances Cp_U, Cp_V, and Cp_W can be commonly expressed as the stray capacitance Cp. The stray capacitances Cmid_U, Cmid_V, and Cmid_W can be commonly expressed as stray capacitance Cmid. For this reason, the equivalent circuit shown in FIG. 7 can be organized into the equivalent circuit shown in FIG.

  Here, in the above, the equivalent circuit of the three-phase inverter 1 is created by taking the case where the U-phase leg 10U performs the switching operation as an example. However, in the case where the V-phase leg 10V performs a switching operation and the case where the W-phase leg 10W performs a switching operation, an equivalent circuit similar to FIG. Also, in each leg that does not perform the switching operation, the upper arm and the lower arm are in the conductive state as long as either the upper arm or the lower arm is in the conductive state (short circuit) and the other is in the nonconductive state (open). An equivalent circuit similar to that in FIG. 8 is created by the same procedure regardless of how the (short circuit) and non-conduction states (open) are selected. Therefore, the midpoint of the leg that performs the switching operation is denoted as MID_A, the midpoints of the other legs are denoted as MID_B and MID_C, respectively, and the winding connected to the midpoint of the leg that performs the switching operation is denoted as MG_A. When the windings connected to the midpoints of the other legs are denoted as MG_B and MG_C, respectively, the equivalent circuit of FIG. 8 is rewritten to the equivalent circuit of FIG. FIG. 9 can be regarded as an equivalent circuit of the three-phase inverter 1 when the three-phase inverter 1 operates. Thus, in the three-phase inverter 1, the equivalent circuit when operated can be regarded as a bridge circuit. Here, the cooler 20 is used while being grounded. For this reason, the common mode current Ic flows through the three-phase inverter 1, the motor MG, and the cooler 20.

FIG. 10 shows a common mode current Ic flowing through a general bridge circuit. The smaller the impedance ratio, that is, the difference between the values of Z _A1 / Z _A2 and Z _B1 / Z _B2 , the more the equilibrium condition of the bridge circuit is satisfied, the smaller the potential difference between point A and point B, and the smaller the common mode current. . Comparing FIG. 9 and FIG. 10, the impedance Z _A1 corresponds to the impedance depending on the stray capacitance Cmid, the impedance Z _A2 corresponds to the impedance depending on the stray capacitance (2Cmid + 3Cn + 3Cp), and the impedance Z _B1 depends on the winding MG_A. The impedance Z _B2 corresponds to the impedance depending on the winding MG_B and the winding MG_C. The impedance Z _C corresponds to the impedance that depends on ground stray capacitance Cm of the motor MG. In general, since the motor MG has a three-phase symmetrical structure, the impedance depending on each of the windings MG_A, MG_B, and MG_C is equal. Therefore, since the impedance Z _B2 is half of the impedance Z _B1 , in FIG. 9, Z _B1 / Z _B2 is 2/1. Therefore, in order to satisfy the equilibrium condition of the equivalent bridge circuit of the three-phase inverter 1, it is desirable to adjust Z _A1 / Z _{A2 to} be 2/1.

  In the technique of Japanese Patent Laid-Open No. 2009-273272 described in the background art, the floating capacitance Cp and the floating capacitance Cn are adjusted to be sufficiently smaller than the floating capacitance Cmid in order to satisfy the equilibrium condition of the equivalent bridge circuit ( Cn, Cp << Cmid). For example, in the technique disclosed in Japanese Patent Application Laid-Open No. 2009-273272, the capacity ratio of each of Cmid / Cn and Cmid / Cp is set to 100 times or more. In order to realize such a capacitance ratio, referring to FIG. 2, the thickness of the insulating layers 34 and 64 of the insulating substrates 30 and 60 corresponding to the stray capacitance Cmid is set to the insulating substrate 40 corresponding to the stray capacitances Cp and Cn. , 50 of the insulating layers 44, 54 must be sufficiently thick. Alternatively, the material of the insulating layers 34 and 64 of the insulating substrates 30 and 60 corresponding to the stray capacitance Cmid must be different from the material of the insulating layers 44 and 54 of the insulating substrates 40 and 50 corresponding to the stray capacitances Cp and Cn. Don't be. However, such a design is not easy for the following reasons. The insulating substrate needs to maintain an insulating performance for withstanding a high voltage. Since the insulating performance of the insulating substrate is proportional to the thickness, it is difficult to maintain the insulating performance of the insulating substrate when the thickness of the insulating substrate is reduced to 1/100. The insulating substrate needs to have a low thermal resistance so as not to hinder the cooling performance of the cooler. Since the thermal resistance of the insulating substrate is proportional to the thickness, if the thickness of the insulating substrate is increased 100 times, the cooling performance of the cooler is hindered. Moreover, the material which can be used for the insulating substrate is limited in consideration of insulating performance, low thermal resistance, mechanical strength, and the like. For this reason, it is practically impossible to use materials having dielectric constants different by 100 times between insulating substrates.

  The technology disclosed in this specification will be described below. The present specification discloses a three-phase inverter that has a semiconductor module that can be easily manufactured and that can satisfy the equilibrium condition of an equivalent bridge circuit. The present specification also discloses a semiconductor module for such a three-phase inverter.

  First, the circuit configuration of the three-phase inverter to which the technology disclosed in this specification is applied is the same as that of the three-phase inverter 1 shown in FIG. Therefore, the description is omitted. Next, FIG. 11 schematically shows a cross-sectional view of a main part of a double-sided cooling type U-phase semiconductor module 200U constituting the U-phase leg 10U disclosed in this specification. Constituent elements common to the conventional U-phase semiconductor module 100U shown in FIG. 2 are denoted by common reference numerals, and description thereof is omitted. The other V-phase leg 10V and W-phase leg 10W also have a common type semiconductor module.

  Compared with the conventional U-phase semiconductor module 100U of FIG. 2, the U-phase semiconductor module 200U of FIG. 11 has an intermediate conductor layer on each of the insulator layers 34, 44, 54, 64 of the insulating substrates 30, 40, 50, 60. 35, 45, 55, and 65 are inserted. Here, the suffix “a” written on each of the insulator layers 34, 44, 54, 64 indicates the chip side, and the suffix “b” indicates the cooler side.

  The first insulating substrate 30 is provided between the semiconductor chip 2 including the first switching element SW1 and the first diode D1 and the cooler 20, and includes a chip-side conductor layer 32, a chip-side insulator layer 34a, and an intermediate conductor layer. 35, a cooler side insulator layer 34b and a cooler side conductor layer 36 are provided. The chip side conductor layer 32, the chip side insulator layer 34a, the intermediate conductor layer 35, the cooler side insulator layer 34b, and the cooler side conductor layer 36 are laminated in this order from the chip 2 toward the cooler 20, The chip-side insulator layer 34a insulates the chip-side conductor layer 32 and the intermediate conductor layer 35, and the cooler-side insulator layer 34b insulates the intermediate conductor layer 35 and the cooler-side conductor layer 36.

  The second insulating substrate 40 is provided between the semiconductor chip 2 including the first switching element SW1 and the first diode D1 and the cooler 20, and includes a chip-side conductor layer 42, a chip-side insulator layer 44a, and an intermediate conductor layer. 45, a cooler side insulator layer 44b and a cooler side conductor layer 46. The chip side conductor layer 42, the chip side insulator layer 44a, the intermediate conductor layer 45, the cooler side insulator layer 44b, and the cooler side conductor layer 46 are laminated in this order from the chip 2 toward the cooler 20, The chip-side insulator layer 44 a insulates the chip-side conductor layer 42 and the intermediate conductor layer 45, and the cooler-side insulator layer 44 b insulates the intermediate conductor layer 45 and the cooler-side conductor layer 46.

  The third insulating substrate 50 is provided between the semiconductor chip 4 including the second switching element SW2 and the second diode D2 and the cooler 20, and includes a chip-side conductor layer 52, a chip-side insulator layer 54a, and an intermediate conductor layer. 55, a cooler-side insulator layer 54b and a cooler-side conductor layer 56. The chip side conductor layer 52, the chip side insulator layer 54a, the intermediate conductor layer 55, the cooler side insulator layer 54b, and the cooler side conductor layer 56 are laminated in this order from the chip 4 toward the cooler 20, The chip-side insulator layer 54a insulates the chip-side conductor layer 52 and the intermediate conductor layer 55, and the cooler-side insulator layer 54b insulates the intermediate conductor layer 55 and the cooler-side conductor layer 56.

  The fourth insulating substrate 60 is provided between the semiconductor chip 4 including the second switching element SW2 and the second diode D2 and the cooler 20, and includes a chip-side conductor layer 62, a chip-side insulator layer 64a, and an intermediate conductor layer. 65, a cooler-side insulator layer 64b and a cooler-side conductor layer 66. The chip side conductor layer 62, the chip side insulator layer 64a, the intermediate conductor layer 65, the cooler side insulator layer 64b, and the cooler side conductor layer 66 are laminated in this order from the chip 4 to the cooler 20, The chip-side insulator layer 64a insulates the chip-side conductor layer 62 and the intermediate conductor layer 65, and the cooler-side insulator layer 64b insulates the intermediate conductor layer 65 and the cooler-side conductor layer 66.

  The chip side conductor layer 42 of the second insulating substrate 40 is connected to the high voltage terminal 10P, and the chip side conductor layer 52 of the third insulating substrate 50 is connected to the low voltage terminal 10N. The chip-side conductor layer 32 of the first insulating substrate 30 and the chip-side conductor layer 62 of the fourth insulating substrate 60 are connected via the connection wiring 72 and constitute the U-phase middle point MID_U. Further, the chip-side conductor layer 32 and the intermediate conductor layer 35 of the first insulating substrate 30 are connected via the connection wiring 82, and the intermediate conductor layer 35 of the first insulating substrate 30 and the intermediate conductor layer of the third insulating substrate 50 are connected. 55 is connected via a connection wiring 84, the chip-side conductor layer 62 of the fourth insulating substrate 60 and the intermediate conductor layer 65 are connected via a connection wiring 86, and the intermediate conductor layer of the fourth insulating substrate 60 is connected. 65 and the intermediate conductor layer 45 of the second insulating substrate 40 are connected via a connection wiring 88.

  Here, the chip-side insulator layer 34a of the first insulating substrate 30 and the chip-side insulator layer 44a of the second insulating substrate 40 are examples of the first high-voltage-side insulator layer described in the claims, The cooler-side insulator layer 34b of the first insulating substrate 30 and the cooler-side insulator layer 44b of the second insulating substrate 40 are examples of the second high-voltage-side insulator layer described in the claims. The intermediate conductor layer 35 of the substrate 30 and the intermediate conductor layer 45 of the second insulating substrate 40 are examples of the high voltage side intermediate conductor layer described in the claims. Furthermore, the chip-side insulator layer 54a of the third insulating substrate 50 and the chip-side insulator layer 64a of the fourth insulating substrate 60 are examples of the first low-voltage-side insulator layer described in the claims. The cooler-side insulator layer 54b of the insulating substrate 50 and the cooler-side insulator layer 64b of the fourth insulating substrate 60 are examples of the second low-voltage-side insulator layer recited in the claims, and the third insulating substrate 50 intermediate conductor layers 55 and the intermediate conductor layer 65 of the fourth insulating substrate 60 are examples of the low-voltage-side intermediate conductor layer described in the claims.

  FIG. 12 shows an equivalent circuit of the U-phase semiconductor module 200U. FIG. 13 shows an equivalent circuit of the U-phase semiconductor module 200U in which the equivalent circuit of FIG. 12 is arranged. 12 and 13, the stray capacitance existing in each of the insulating substrates 30, 40, 50 and 60 is indicated by a broken line. In the U-phase semiconductor module 200U, the intermediate conductor layers 35, 45, 55, 65 are inserted into the insulator layers 34, 44, 54, 64 of the insulating substrates 30, 40, 50, 60, respectively. , 40, 50, 60 each have two stray capacitances. Here, the subscript “a” written in the stray capacitance indicates a stray capacitance corresponding to the chip-side insulator layers 34a, 44a, 54a, 64a, and the subscript “b” indicates the cooler-side insulator layer 34b, The stray capacitances corresponding to 44b, 54b, and 64b are indicated.

  As shown in FIG. 12, in the first insulating substrate 30, the intermediate conductor layer 35 is connected to the U-phase middle point MID_U through the connection wiring 82. For this reason, the stray capacitance Cmid_Ua corresponding to the chip-side insulator layer 34a of the first insulating substrate 30 disappears. In the fourth insulating substrate 60, the intermediate conductor layer 65 is connected to the U-phase middle point MID_U via the connection wiring 86. For this reason, the stray capacitance Cmid_Ua corresponding to the chip-side insulator layer 64a of the fourth insulating substrate 60 disappears. In the second insulating substrate 40, the intermediate conductor layer 45 is connected to the U-phase middle point MID_U via the connection wires 72, 86, 88. Therefore, in the second insulating substrate 40, the stray capacitance Cp_Ua corresponding to the chip-side insulator layer 44a exists between the chip-side conductor layer 42 and the U-phase middle point MID_U, and the cooler-side insulator layer 44b. The stray capacitance Cp_Ub corresponding to is present between the U-phase midpoint MID_U and the cooler 20. In the third insulating substrate 50, the intermediate conductor layer 55 is connected to the U-phase middle point MID_U via the connection wires 82 and 84. Therefore, in the third insulating substrate 50, the stray capacitance Cn_Ua corresponding to the chip-side insulator layer 54a exists between the chip-side conductor layer 52 and the U-phase middle point MID_U, and the cooler-side insulator layer 54b. The stray capacitance Cn_Ub corresponding to is present between the U-phase midpoint MID_U and the cooler 20. For this reason, the equivalent circuit of FIG. 12 can be organized into an equivalent circuit of the U-phase semiconductor module 200U of FIG.

  As described above, each of the semiconductor modules constituting the legs 10U, 10V, and 10W has a common form. Therefore, like the U-phase semiconductor module 100U of the U-phase leg 10U described with reference to FIGS. 12 and 13, stray capacitance also exists in each of the other leg 10V, 10W semiconductor modules. FIG. 14 shows stray capacitances present in all the semiconductor modules of the legs 10U, 10V, and 10W constituting the three-phase inverter 1, and an equivalent circuit when the three-phase inverter 1 operates. FIG. 14 illustrates a case where the U-phase leg 10U performs a switching operation. Note that the other end of each of the windings MG_U, MG_V, MG_W constituting the motor MG is grounded via a ground floating capacitance Cm. The ground stray capacitance of the motor is not limited to this example, and may exist in different modes depending on the type of the motor. As will be described later, the technique disclosed in the present specification is not limited to the aspect of the ground floating capacitance of the motor, and can exert an effect. In other words, the technology disclosed in this specification can be applied to various types of motors.

  In FIG. 14, if the stray capacitance that disappears due to a short circuit is deleted, the equivalent circuit of FIG. 15 can be arranged. As described above, each of the semiconductor modules constituting the legs 10U, 10V, and 10W has a common form. That is, the corresponding insulating substrates 30, 40, 50, 60 are common among the semiconductor modules constituting the legs 10 U, 10 V, 10 W. Therefore, the stray capacitances Cn_Ub, Cn_Vb, and Cn_Wb of the legs 10U, 10V, and 10W can be commonly expressed as the stray capacitance Cnb, and the stray capacitances Cp_Ub, Cp_Vb, and Cp_Wb can be commonly expressed as the stray capacitance Cpb. The capacitors Cmid_Ub, Cmid_Vb, and Cmid_Wb can be commonly expressed as stray capacitance Cmidb. For this reason, the equivalent circuit shown in FIG. 15 can be organized into the equivalent circuit shown in FIG.

  FIG. 16 illustrates a case where the U-phase leg 10U performs a switching operation. However, as described above with reference to FIGS. 7 to 9, also in this example, when the V-phase leg 10 </ b> V performs the switching operation and when the W-phase leg 10 </ b> W performs the switching operation, the same procedure is used. An equivalent circuit similar to is created. Also, in each leg that does not perform the switching operation, the upper arm and the lower arm are in the conductive state as long as either the upper arm or the lower arm is in the conductive state (short circuit) and the other is in the nonconductive state (open). An equivalent circuit similar to that in FIG. 16 is created by the same procedure regardless of how the (short-circuit) and non-conduction states (open) are selected. Therefore, the midpoint of the leg that performs the switching operation is denoted as MID_A, the midpoints of the other legs are denoted as MID_B and MID_C, respectively, and the winding connected to the midpoint of the leg that performs the switching operation is denoted as MG_A. When the windings connected to the midpoints of the other legs are denoted as MG_B and MG_C, respectively, the equivalent circuit of FIG. 16 is rewritten to the equivalent circuit of FIG. FIG. 17 can be regarded as an equivalent circuit of the three-phase inverter 1 when the three-phase inverter 1 operates.

When the equivalent circuit of FIG. 17 is compared with the general bridge circuit of FIG. 10, the impedance Z _A1 corresponds to the impedance depending on the stray capacitance (Cmidb + Cnb + Cpb), and the impedance Z _A2 corresponds to the impedance depending on the stray capacitance (2Cmidb + 2Cnb + 2Cpb). The impedance Z _B1 corresponds to the impedance dependent on the winding MG_A, and the impedance Z _B2 corresponds to the impedance dependent on the winding MG_B and the winding MG_C. The impedance Z _C corresponds to the impedance that depends on ground stray capacitance Cm of the motor MG. Here, in FIG. 17, Z _A1 / Z _A2 is 2/1, and Z _B1 / Z _B2 is also 2/1. For this reason, the equivalent bridge circuit of the three-phase inverter 1 is configured to satisfy the equilibrium condition.

As described above, the equivalent bridge circuit of the three-phase inverter 1 disclosed in this specification is allocated with the stray capacitance existing in the semiconductor module so as to satisfy the equilibrium condition itself. As described above, each of the semiconductor modules constituting the legs 10U, 10V, 10W of the three-phase inverter 1 has a common form. Therefore, the impedance ratio of the equivalent bridge circuit of the three-phase inverter 1, that is, the values of Z _A1 / Z _A2 and Z _B1 / Z _B2 agree very well, and the common mode current is extremely reduced. In the three-phase inverter 1, each of the semiconductor modules constituting the legs 10U, 10V, 10W needs to have a common form, but the insulating substrates 30, 40, 50, 60 constituting each leg 10U, 10V, 10W are required. Are not in common form, the intermediate conductor layers 35, 45, 55, 65 are inserted into the insulator layers 34, 44, 54, 64, and the intermediate conductor layers 35, 45, 55, 65 are in the middle. If short-circuited to the points MID_U, MID_V, and MID_W, the common mode current can be reduced by the stray capacitance distribution effect that satisfies the equilibrium condition.

  As described above, in the technique of Japanese Patent Application Laid-Open No. 2009-273272 described in the background art, in order to increase the capacitance ratio between the insulating substrates, the thickness is different between the insulating substrates, or the materials are different between the insulating substrates. You have to let them. For this reason, the freedom degree of design will be restrict | limited. On the other hand, the three-phase inverter 1 disclosed in the present specification has an effect of stray capacitance distribution that satisfies the equilibrium condition, and therefore, it is possible to relax the restriction on the degree of freedom of design. For example, if each of the semiconductor modules has a common form, the equilibrium condition of the equivalent bridge circuit is satisfied, so that the thickness and material of the insulating substrate of the semiconductor module can be freely designed.

  In the above, the technology disclosed in this specification has been described by taking the double-sided cooling U-phase semiconductor module 200U as an example. However, the technology disclosed in this specification can also be applied to a three-phase inverter including a single-sided cooling type semiconductor module. it can. FIG. 18 schematically shows a cross-sectional view of a main part of a single-sided cooling U-phase semiconductor module 300U constituting the U-phase leg 10U disclosed in the present specification. Constituent elements common to the double-sided cooling U-phase semiconductor module 200U shown in FIG. The other V-phase leg 10V and W-phase leg 10W also have a common type semiconductor module.

  The equivalent bridge circuit of the three-phase inverter 1 constituted by such a single-sided cooling type semiconductor module corresponds to a circuit obtained by removing the stray capacitance Cp_Ua and the stray capacitance Cpb from the equivalent bridge circuit of FIG. In this case as well, the equivalent bridge circuit of the three-phase inverter 1 is configured to satisfy the equilibrium condition, and the common mode current is reduced.

  As described above, the technology disclosed in this specification is characterized in that the intermediate conductor layers 35, 45, 55, 65 of the insulating substrates 30, 40, 50, 60 are short-circuited to the midpoints MID_U, MID_V, MID_W. To do. In the above, the state of short-circuiting is described using the connection wirings 82, 84, 86, and 88, but the connection wirings 82, 84, 86, and 88 are described for the purpose of showing the state of short-circuiting. In order to short-circuit, various forms can be adopted. For example, the first insulating substrate 30 and the third insulating substrate 50 include chip-side insulator layers 34a and 54a, intermediate conductor layers 35 and 55, cooler-side insulator layers 34b and 54b, and cooler-side conductor layers 36 and 56. You may be comprised with the integral laminated body. In this case, the connection wiring 84 is unnecessary. Similarly, the second insulating substrate 40 and the fourth insulating substrate 60 include chip-side insulator layers 44a and 64a, intermediate conductor layers 45 and 65, cooler-side insulator layers 44b and 64b, and cooler-side conductor layers 46 and 66. May be composed of an integral laminate. In this case, the connection wiring 88 is unnecessary.

  As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

1: three-phase inverter 2: semiconductor chip 4: semiconductor chip 10N: low voltage terminal 10P: high voltage terminal 10U: U phase leg 10V: V phase leg 10W: W phase leg 20: cooler 30: first insulating substrate 40: Second insulating substrate 50: Third insulating substrate 60: Fourth insulating substrates 32, 42, 52, 62: Chip side conductor layers 34a, 44a, 54a, 64a: Chip side insulating layers 34b, 44b, 54b, 64b: Cooling Appliance side insulator layers 35, 45, 55, 65: Intermediate conductor layers 36, 46, 56, 66: Cooler side conductor layers 72, 82, 84, 86, 88: Connection wiring SW1-6: Switching element D1-6 : Diode MG: Motor

Claims (3)

A three-phase inverter,
A cooler,
A semiconductor module which is used after being cooled by the cooler, and which constitutes a U phase, a V phase and a W phase,
A high voltage terminal;
A low voltage terminal, and
The semiconductor module, in each phase,
A high voltage side switching element connected to the high voltage terminal;
A low voltage side switching element connected to the low voltage terminal;
A high voltage side insulating substrate provided between the high voltage side switching element and the cooler;
A low voltage side insulating substrate provided between the low voltage side switching element and the cooler,
The high voltage side switching element and the low voltage side switching element are connected in series between the high voltage terminal and the low voltage terminal,
The high-voltage side insulating substrate is
A first high voltage side insulator layer disposed on the high voltage side switching element side;
A second high voltage side insulator layer disposed on the cooler side;
A high voltage side intermediate conductor layer provided between the first high voltage side insulator layer and the second high voltage side insulator layer,
The low voltage side insulating substrate is:
A first low voltage side insulator layer disposed on the low voltage side switching element side;
A second low voltage side insulator layer disposed on the cooler side;
A low voltage side intermediate conductor layer provided between the first low voltage side insulator layer and the second low voltage side insulator layer,
The three-phase inverter, wherein the high voltage side intermediate conductor layer and the low voltage side intermediate conductor layer are configured to be connected to a midpoint between the high voltage side switching element and the low voltage side switching element. The high voltage side insulating substrate is in a common form between the phases,
The three-phase inverter according to claim 1, wherein the low-voltage side insulating substrate has a common form between the phases. A semiconductor module for a three-phase inverter that is used after being cooled by a cooler,
A high voltage side switching element connected to a high voltage terminal of the three-phase inverter;
A low voltage side switching element connected to a low voltage terminal of the three-phase inverter;
A high voltage side insulating substrate provided between the high voltage side switching element and the cooler;
A low voltage side insulating substrate provided between the low voltage side switching element and the cooler,
The high voltage side switching element and the low voltage side switching element are configured to be connected in series between the high voltage terminal and the low voltage terminal,
The high-voltage side insulating substrate is
A first high voltage side insulator layer disposed on the high voltage side switching element side;
A second high voltage side insulator layer disposed on the cooler side;
A high voltage side intermediate conductor layer provided between the first high voltage side insulator layer and the second high voltage side insulator layer;
The low voltage side insulating substrate is:
A first low voltage side insulator layer disposed on the low voltage side switching element side;
A second low voltage side insulator layer disposed on the cooler side;
A low voltage side intermediate conductor layer provided between the first low voltage side insulator layer and the second low voltage side insulator layer;
The semiconductor module, wherein the high voltage side intermediate conductor layer and the low voltage side intermediate conductor layer are configured to be connected to a midpoint between the high voltage side switching element and the low voltage side switching element.

Images