JP2017163435A - Method of controlling programmable device and programmable device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the update time of a function of a logic circuit mounted on a programmable device.SOLUTION: A programmable device (FPGA) 3 includes: a plurality of look-up tables (LUTs) for holding logical data indicating the functions of a logic circuit; and an LUT update module 12 for updating logical data held by a part of the LUTs among the plurality of LUTs on the basis of an instruction to update the logical data held by the part of LUTs.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a programmable device control method and a programmable device.

  In recent years, Field Programmable Gate Array (FPGA) that can change the function of a logic circuit has been used. The FPGA is also referred to as a programmable device. The FPGA is equipped with a Look Up Table (LUT). The LUT is a table indicating the function of the logical circuit, and the function of the FPGA logic circuit is updated by updating the data of the LUT.

  As a related technique, a technique that simplifies the LUT setting operation in a programmable logic circuit incorporating a LUT format data conversion process has been proposed (see, for example, Patent Document 1). In addition, a technique relating to an information processing device that can operate based on a re-read program without requiring restart has been proposed (see, for example, Patent Document 2).

JP 2004-045468 A JP 2005-182410 A

  For example, each LUT mounted on an FPGA (programmable device) is updated by configuration processing. The configuration process is performed by storing the LUT data of each LUT in a Read Only Memory (ROM) provided outside the FPGA and setting the LUT data read from the ROM in each LUT. .

  At this time, the LUT data of each LUT is updated from the top area of the ROM to the entire area. As the number of LUTs mounted on the FPGA increases, the time required for the configuration process increases. For this reason, even when some of the LUTs mounted on the FPGA are updated, the update time becomes longer.

  As one aspect, an object of the present invention is to shorten the update time of the function of a logic circuit mounted on a programmable device.

  In one aspect, a control method for a programmable device is a control method for controlling a programmable device in which a plurality of logical data holding units that hold logic data indicating the function of a logic circuit are mounted, and controls the programmable device. The apparatus outputs an instruction to update the logical data held by some of the plurality of logical data holding units to the programmable device, and the logical data updating unit mounted on the programmable device includes: Based on the instruction, the logical data held by the partial logical data holding unit is updated.

  According to one aspect, the update time of the function of the logic circuit mounted on the programmable device can be shortened.

It is a figure which shows an example of an electronic device and a control apparatus. FIG. 2 is a diagram illustrating an example of an FPGA (part 1); FIG. 2 is a diagram (part 2) illustrating an example of an FPGA. It is a functional block diagram which shows an example of a control apparatus. It is an example of a screen which shows an example of update instruction generation. It is an example of a screen which shows the other example of update instruction generation. FIG. 3 is a third diagram illustrating an example of an FPGA. It is a figure which shows an example of the output of the LUT update module which input the update instruction | indication. FIG. 4 is a diagram illustrating an example of an FPGA (part 4); It is a flowchart which shows an example of the flow of a process of a control apparatus. It is a flowchart which shows an example of the flow of processing of FPGA. It is a figure which shows an example of the hardware constitutions of a control apparatus.

  Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 shows an example of an electronic device 1 and a control device 2. The electronic device 1 is, for example, a video device or a communication device, and the FPGA 3, the configuration ROM 4, and the CPU 5 are mounted on the substrate of the electronic device 1. A control device 2 is connected to the electronic device 1. The example of the electronic device 1 is not limited to the example of FIG.

  The FPGA 3 is a programmable device that can update the function of the logic circuit. The configuration ROM 4 stores data for collectively setting the functions of the respective logic circuits mounted on the FPGA 3. A central processing unit (CPU) 5 is connected to the FPGA 3.

  The control device 2 is a computer connected to the configuration ROM 4 and the CPU 5. The control device 2 stores data for collectively setting the functions of the logic circuits in the configuration ROM 4 and controls the FPGA 3 through the CPU 5.

  FIG. 2 is a diagram illustrating an example of the FPGA 3. The FPGA 3 includes a bus interface 10 (indicated as “bus I / F” in FIG. 2), a storage circuit 11, an LUT update module 12, and a plurality of Look Up Tables (LUTs).

  The bus interface 10 is connected to the CPU 5 and inputs / outputs data to / from the CPU 5. The storage circuit 11 stores various information input from the CPU 5. The storage circuit 11 may be, for example, a register or a memory. The information stored in the storage circuit 11 is information used when the FPGA 3 controls the electronic device 1, for example.

  The bus interface 10 is connected to the storage circuit 11. The LUT update module 12 is connected to the bus interface 10. In addition, a plurality of LUTs are mounted on the FPGA 3. The number of LUTs mounted on the FPGA 3 may be an arbitrary number.

  The LUT will be described. The LUT is a table included in the logic cell of the FPGA 3. The LUT of the embodiment inputs four signals and outputs one signal. However, the number of signals input to the LUT is not limited to four, and the number of signals output is not limited to one.

  By updating data held by the LUT (hereinafter referred to as LUT data), the function of the logic circuit realized by the LUT is changed. LUT data is an example of logical data.

  For example, when the LUT data is updated, the logic circuit realized by the LUT is changed to an arbitrary logic circuit such as an AND circuit or an OR circuit. Each LUT is given an address. The address is an example of specific data for specifying the LUT.

  In the example of FIG. 2, “LUT-X: X is an integer greater than or equal to zero”, “X” indicates the address of the LUT. “LUT-0” indicates that the address is “0”, and “LUT-1” indicates that the address is “1”.

  Each LUT is connected to the configuration ROM 4. The control device 2 stores data (collective setting data) for collectively setting the functions of the logic circuits in the configuration ROM 4. The batch setting data includes an LUT address and LUT data to be held in the LUT.

  The batch setting data stored in the configuration ROM 4 is input to the FPGA 3 and the LUT data is input to each LUT, whereby the LUT data held by each LUT is updated collectively. This process is also called a configuration process.

  FIG. 3 shows an example of the configuration process. For example, in the batch setting data, it is assumed that the address “0” is associated with LUT data indicating AND logic. In this case, LUT data (AND logic data) indicating AND logic is input to the LUT-0, and the LUT-0 holds the LUT data.

  Thereby, LUT-0 functions as an AND logic circuit. In the example of FIG. 3, LUT data indicating OR logic (OR logic data) is input to the LUT-1, and the LUT-1 holds the LUT data. Thereby, LUT-1 functions as an OR logic circuit.

  Similarly, LUT data (EOR logical data) indicating Exclusive OR (EOR) logic is input to LUT-2, and LUT-2 holds the LUT data. Thereby, LUT-2 functions as an EOR logic circuit.

  By performing the configuration process, LUT data is also input to the other LUTs mounted on the FPGA 3, and each of the other LUTs holds the LUT data. Accordingly, the other LUTs function as predetermined logic circuits.

  The batch setting data may be, for example, bit file data. An operator who operates the control device 2 (for example, a setter who sets the circuit configuration of the FPGA 3) sets LUT data to be held in each LUT mounted on the FPGA 3 in the control device 2.

  For example, the operator uses the control device 2 to code a program code, and sets LUT data to be held in each LUT mounted on the FPGA 3. The setting of LUT data may be performed by a method other than coding.

  The control device 2 accepts input of LUT data settings for each LUT. The control device 2 generates batch setting data from the set LUT data of each LUT, and stores the generated batch setting data in the configuration ROM 4.

  When the batch setting data is stored in the configuration ROM 4, the control device 2 updates the entire area from the top area of the configuration ROM 4 and stores the batch setting data in the configuration ROM 4.

  Here, it is assumed that the LUT table held by some of the LUTs is updated by configuration processing. In this case, when the configuration process is performed, the entire area is updated from the top area of the configuration ROM 4.

  Further, the LUT data held by all the LUTs mounted on the FPGA 3 is updated. Accordingly, even when not all the LUTs mounted on the FPGA 3 but the LUT data held by some LUTs is updated, the time required for the configuration process becomes long.

  The configuration process is a process for updating the LUT data held by all the LUTs, and the FPGA 3 does not function as a device while the configuration process is being performed.

  For this reason, while the configuration process is being performed on the FPGA 3, the FPGA 3 does not perform any operation other than the configuration process, and thus the electronic device 1 does not operate during this period. For example, when the electronic device 1 is a communication device, the communication device does not function while the configuration process is performed on the FPGA 3.

  Therefore, in the embodiment, the LUT update module is mounted on the FPGA 3 in order to update the LUT data for only some of the LUTs mounted on the FPGA 3 without performing configuration processing.

  The LUT update module 12 is a circuit connected to the bus interface 10 and is an example of a logical data update unit. The control device 5 generates an instruction to update the LUT data (hereinafter referred to as an update instruction) only to a part of the LUTs to be updated among the plurality of LUTs mounted on the FPGA 3.

  An example of the control device 2 will be described with reference to FIG. The control device 2 includes a storage unit 20, a detection unit 21, an update instruction generation unit 22, a data output unit 23, a screen control unit 24, and an input reception unit 25.

  The control device 2 is connected to the display device 31, the input device 32, and the CPU 5. The display device 31 is, for example, a display, and the input device 32 is, for example, a mouse or a keyboard.

  Various data are stored in the storage unit 20. For example, a code (program code) describing LUT data held by all the LUTs mounted on the FPGA 3 is stored in the storage unit 20.

  When the program code is changed, the detection unit 21 detects the changed part of the program code. For example, in the program code, the correspondence between the LUT address and the LUT data is described for each LUT.

  When the LUT data of the LUT corresponding to any one of the addresses of each LUT is changed, the detection unit 21 detects the changed LUT data address and the updated LUT data.

  For example, when the program code is edited, the address of the updated LUT and the updated LUT data may be detected by comparing character strings of the program code before editing and the program code after editing.

  The update instruction generation unit 22 generates an update instruction for updating the LUT data held by the LUT corresponding to the LUT address detected by the detection unit 21. This update instruction includes the LUT address, the updated LUT data, and an enable signal for enabling the update of the LUT data.

  The data output unit 23 outputs the generated update instruction to the CPU 5. The screen control unit 24 performs screen control of the display device 31. For example, the screen control unit 24 performs control to display the program code on the display device 31.

  The input receiving unit 25 receives an operation performed using the input device 32. For example, an operator who operates the control device 2 edits the program code using the input device 32. The input receiving unit 25 receives the edited content.

  FIG. 5 shows an example of generation of an update instruction. In the example of FIG. 5, the display device 31 displays an edit screen for editing the program code (denoted as “code edit screen” in FIG. 5).

  Before updating the LUT data, “LUT0 = AND” is described in the program code (the broken line portion in the example of FIG. 5). This description indicates that AND logic is set in the LUT having the address “0”. In addition, logic for other LUTs is set in the program code.

  For example, it is assumed that the operator of the control device 2 uses the input device 32 to change “LUT0 = AND” to “LUT0 = NAND” as shown in the example of FIG. In this case, the detection unit 21 detects that the character string “LUT0 = AND” has been changed to “LUT0 = NAND”.

  FIG. 5 shows an example in which the LUT data of LUT-0 is changed, but the LUT data of a plurality of LUTs may be changed. For example, the LUT data of two LUTs, LUT-0 and LUT-1, may be changed.

  When the change of the program code is completed (for example, when the edited program code is saved), the update instruction generation unit 22 generates an update instruction based on the change detected by the detection unit 21.

  In the case of the example of FIG. 5, the detection unit 21 detects that the LUT data held by the LUT having the address “0” has been updated from the AND logic to the NAND logic. Accordingly, the update instruction generation unit 22 generates an update instruction including the address “0” of the updated LUT, the machine language indicating the NAND logic as the updated LUT data, and the enable signal.

  FIG. 6 shows another example of generation of an update instruction. In the example of FIG. 6, the LUT update screen is a screen displayed on the display device 31 under the control of predetermined software executed by the control device 2.

  The operator uses the input device 32 to specify a target LUT for updating the LUT data. For example, in the case of the example of FIG. 6, the operator uses the mouse as the input device 32 to place the pointer P on the pull-down menu M of “LUT-0” and press it down.

  When the input receiving unit 25 receives this pressing operation, the screen control unit 24 displays information indicating various logic circuits (for example, OR logic, EOR logic, etc.) on the display device 31. The operator uses the mouse to select a desired logic circuit.

  The input receiving unit 25 receives this selection operation. As a result, the update instruction generation unit 22 generates an update instruction including the address “0” of the updated LUT, the machine language indicating the NAND logic as the updated LUT data, and the enable signal.

  As shown in the example of FIG. 7, when an update instruction is generated, the data output unit 23 of the control device 2 outputs the generated update instruction to the CPU 5. The CPU 5 outputs an update instruction to the bus interface 10.

  This update instruction is input to the LUT update module 12 via the bus interface 10. FIG. 8 shows an example of the output of the LUT update module 12 that has received an update instruction.

  In the example of FIG. 8, the update instruction includes LUT data indicating NAND logic, data indicating an address “0”, and an enable signal that enables updating of the LUT data held by each LUT. This update instruction is input to the LUT update module 12.

  The LUT update module 12 includes an enable signal control unit 41. The enable signal control unit 41 is a circuit that performs control to enable or disable the enable signal for each LUT connected to the LUT update module 12.

  In the example of FIG. 8, the LUT update module 12 outputs LUT data indicating NAND logic included in the input update instruction to each LUT mounted on the FPGA 3. The LUT update module 12 outputs data indicating the address “0” included in the input update instruction to each LUT.

  The enable signal control unit 41 inputs an address “0” included in the update instruction and an enable signal indicating “valid”. The enable signal control unit 41 changes the enable signal for the LUT other than the LUT corresponding to the address included in the update instruction from valid to invalid.

  In the example of FIG. 8, the address included in the update instruction is “0”. Therefore, the enable signal control unit 41 changes the enable signal output to the LUT other than LUT-0 from valid to invalid. In this case, the enable signal output to LUT-1 and LUT-2 is changed to invalid.

  On the other hand, the enable signal control unit 41 does not change the enable signal output to the LUT-0. For this reason, the enable signal output to LUT-0 remains valid.

  As shown in the example of FIG. 9, the LUT-0 inputs LUT data indicating NAND logic and data indicating an address “0”. The LUT-0 inputs an enable signal indicating that it is valid. LUT-0 updates the LUT data because the input address is “0” and the enable signal is valid.

  As a result, the LUT data held by the LUT-0 is changed from the AND logic to the NAND logic. Among the LUTs mounted on the FPGA 3, an enable signal indicating invalidity is input to LUTs other than LUT-0. For this reason, LUTs other than LUT-0 do not update LUT data.

  Accordingly, the LUT update module 12 updates the LUT data for only some of the LUTs (updating LUTs) among the LUTs mounted on the FPGA 3 based on the input update instruction.

  Therefore, the LUT data held by the update target LUT is updated without performing configuration processing for the FPGA 3. As described above, when the configuration process is performed, the entire area is updated from the top area of the configuration ROM 4, so that the time for the configuration process becomes long.

  In the embodiment, the configuration process is not performed when the LUT data held by some of the LUTs mounted on the FPGA 3 is updated. In this case, since the LUT update module updates only the LUT data held by the update target LUT, the update time can be shortened.

  For example, when the number of LUTs mounted on the FPGA 3 is about several hundred thousand, the configuration process may take several hours. When the LUT data held by one LUT (LUT-0) among the LUTs mounted on the FPGA 3 is updated by the configuration process, the update process takes several hours.

  In the embodiment, the LUT update module 12 mounted on the FPGA 3 updates only the LUT data held by the LUT-0 designated by the control device 2. For this reason, even when the number of LUTs mounted on the FPGA 3 is about several hundred thousand, the update process may be completed in about several minutes. Therefore, the update time of LUT data is shortened.

  Further, the LUT update module 12 updates only the LUT specified by the update instruction among the plurality of LUTs mounted on the FPGA 3. While the LUT is being updated, the LUT update module 12 outputs an enable signal for invalidating the update of the LUT data to the LUTs other than the update target among the LUTs mounted on the FPGA 3.

  Accordingly, while the LUT specified by the update instruction is being updated, LUTs other than the update target can operate. When the LUT to be updated is only LUT-0, LUTs other than LUT-0 are operable among the plurality of LUTs mounted on the FPGA 3.

  When the configuration process is performed, the FPGA 3 does not function as a device. On the other hand, in the embodiment, since the LUTs other than the update target operate even when some of the LUTs mounted on the FPGA 3 are updated, the FPGA 3 can function as a device during the LUT update. it can.

<Example of Flowchart of Embodiment>
Next, an example of the processing flow of the control device 2 will be described with reference to the flowchart of FIG. When receiving an update operation of the LUT of the FPGA 3, the control device 2 determines whether the update operation is an operation designating the configuration process (Step S <b> 1).

  This determination may be made based on an input received from the input device 32 by the input receiving unit 25, for example. When the configuration process is designated (YES in step S1), the control device 2 outputs a configuration instruction for causing the FPGA 3 to execute the configuration to the configuration ROM 4 (step S2).

  In this case, the entire area is updated from the top area of the configuration ROM 4 and a configuration process is performed in which the batch setting data is stored. When the configuration process is executed, the FPGA 3 does not function.

  When the configuration process is not specified (NO in step S1), the update instruction generation unit 22 specifies the address of the LUT to be updated based on the input content received by the input reception unit 25 (step S3).

  The update instruction generation unit 22 recognizes LUT data corresponding to the specified LUT (step S4). The recognized LUT data is data indicating the updated logic. For example, when the AND logic associated with LUT-0 is changed to NAND logic, the detection unit 21 detects the change.

  Thereby, the update instruction generation unit 22 recognizes LUT data corresponding to the specified LUT. The update instruction generation unit 22 generates an update instruction for only the specified LUT (step S5).

  This update instruction includes the address of the specified LUT, the updated LUT data, and an enable signal for enabling the update of the LUT data. The data output unit 23 outputs the generated update instruction to the CPU 5 (step S6). The update instruction output to the CPU 5 is input to the FPGA 3.

  Next, an example of processing of the FPGA 3 will be described with reference to the flowchart of FIG. An update instruction is input from the CPU 5 to the bus interface 10 of the FPGA 3. Then, the update instruction is input to the LUT update module 12.

  The LUT update module 12 outputs the LUT data included in the update instruction to each LUT mounted on the FPGA 3 (step S11). The LUT update module 12 outputs data indicating the address included in the update instruction to each LUT mounted on the FPGA 3 (step S12).

  The enable signal control unit 41 of the LUT update module 12 inputs an enable signal and data indicating an address. The enable signal control unit 41 outputs a valid or invalid enable signal for each LUT based on the data indicating the address included in the update instruction (step S13).

  Based on the data indicating the address included in the update instruction, the enable signal control unit 41 outputs the LUT at the address while keeping the enable signal valid.

  On the other hand, the enable signal control unit 41 changes the enable signal from valid to invalid for the LUT at an address other than the address included in the update instruction, and outputs the enable signal changed to invalid.

  The LUT to be updated receives LUT data included in the update instruction, data indicating an address, and an enable signal indicating validity. As a result, the update target LUT updates the held LUT data to the input LUT data (step S14).

  Therefore, LUT data update processing is performed by the update target LUT. While the update process is being performed, the FPGA 3 operates a logic circuit realized by an LUT other than the LUT to be updated (step S15).

  As described above, the LUT data held by the update target LUT is updated without performing the configuration process. For this reason, the time for updating can be shortened.

  Also, while the update target LUT is being updated, the FPGA 3 functions because the LUTs other than the update target LUT function as logic circuits. For example, when the electronic device 1 is a communication device, the communication device can perform communication even when some LUTs of the FPGA 3 are updated.

<Example of hardware configuration of control device>
Next, an example of the hardware configuration of the control device 2 will be described with reference to the example of FIG. As shown in the example of FIG. 12, a processor 111, a random access memory (RAM) 112, and a ROM 113 are connected to the bus 100. The auxiliary storage device 114, the medium connection unit 115, the display device 31, and the input device 32 are connected to the bus 100.

  The processor 111 executes a program expanded in the RAM 112. As a program to be executed, a program for performing processing of the control device in the embodiment may be applied.

  The ROM 113 is a non-volatile storage device that stores programs developed in the RAM 112. This ROM 113 is the ROM 113 of the control device 2 and is different from the configuration ROM 4.

  The auxiliary storage device 114 is a storage device that stores various types of information. For example, a hard disk drive or a semiconductor memory may be applied to the auxiliary storage device 114. The medium connection unit 115 is provided so as to be connectable to the portable recording medium 118.

  As the portable recording medium 118, a portable memory or an optical disc (for example, Compact Disc (CD), Digital Versatile Disc (DVD), semiconductor memory, etc.) may be applied. A program for performing the processing of the embodiment may be recorded on the portable recording medium 118.

  As described above, the display device 31 is a display, for example. As described above, the input device 32 is, for example, a mouse or a keyboard.

  The storage unit 20 may be realized by the RAM 112, the auxiliary storage device 114, or the like. The detection unit 21, the update instruction generation unit 22, the data input / output unit 23, the screen control unit 24, and the input reception unit 25 of the control device 2 may be realized by the processor 111 executing a given program.

  The RAM 112, the ROM 113, the auxiliary storage device 114, and the portable recording medium 118 are all examples of a tangible storage medium that can be read by a computer. These tangible storage media are not temporary media such as signal carriers.

<Others>
The present embodiment is not limited to the above-described embodiment, and various configurations or embodiments can be taken without departing from the gist of the present embodiment.

1 Electronic device 2 Control device 3 FPGA
4 Configuration ROM
DESCRIPTION OF SYMBOLS 10 Bus interface 11 Memory circuit 12 Update module 21 Detection part 22 Update instruction generation part 23 Data input / output part 24 Screen control part 25 Input reception part 31 Display apparatus 32 Input apparatus 111 Processor 112 RAM
113 ROM

Claims (6)

A control method for controlling a programmable device having a plurality of logic data holding units for holding logic data indicating the function of a logic circuit,
The control device for controlling the programmable device outputs an instruction to update the logical data held by some of the plurality of logical data holding units to the programmable device,
The logical data update unit mounted on the programmable device updates the logical data held by the partial logical data holding unit based on the instruction.
A control method of a programmable device characterized by the above. The instruction includes specific data for specifying the part of the logical data holding unit, logical data corresponding to the part of the logical data holding unit, a signal for enabling the updating of the plurality of logical data holding units, Including,
The method of controlling a programmable device according to claim 1. The logical data update unit
Outputting logical data indicating the update content to the plurality of logical data holding units;
Based on the specific data, the signal for the logical data holding units other than the partial logical data holding unit among the plurality of logical data holding units is changed from valid to invalid.
The method of controlling a programmable device according to claim 2. The controller is
Among the plurality of logical data holding units, accepting the designation of the logical data holding unit for updating the logical data and the input of the logical data to be updated,
The designated logical data holding unit is used as the partial logical data holding unit, and the instruction is generated only for the partial logical data holding unit.
The method of controlling a programmable device according to claim 2 or 3, The programmable device is:
While the logical data updating unit is updating the logical data held by the part of the logical data holding unit, the logical data holding unit other than the part of the logical data holding unit among the plurality of logical data holding units Operate the logic circuit realized by
The method for controlling a programmable device according to any one of claims 1 to 4, wherein: A plurality of logical data holding units for holding logical data indicating the function of the logic circuit;
A logical data updating unit that updates logical data held by the some logical data holding units based on an instruction to update logical data held by some logical data holding units among the plurality of logical data holding units; ,
A programmable device comprising:

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