JP2010206513A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a burden of function settings to a variable logic in the configuration where a storage circuit for achieving a variable logic function is handled as a circuit equivalent with a logic circuit. <P>SOLUTION: A semiconductor device includes a function reconfiguration memory device (8) which is controlled by an access control device (2). The function reconfiguration memory device includes: an interface control circuit which receives an access request from the access control device; a plurality of function reconfiguration cells (20) connected to the interface control circuit; and a variable arithmetic cell (101) provided in one-to-one correspondence to each of the function reconfiguration cells for performing arithmetic operation upon receipt of output from the function reconfiguration cells. A control circuit of each function reconfiguration cell performs logic operation by autonomously controlling data, such as truth value data that are initially set to a control field and a data field of a storage circuit during a first operation mode, on the basis of data in the control field during a second operation mode. The variable arithmetic cell is enabled to perform the arithmetic operation on the basis of control data or the like output from the control field of the storage circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device capable of variably realizing a logic function using a memory circuit, and is effective when applied to, for example, a semiconductor data processing device including a variable logic module capable of realizing a peripheral function in a programmable manner. Regarding technology.

  As a variable logic module or a variable logic device (reconfigurable device), a PLD (programmable logic device) or an FPLD (field PLD) has already been used. The present inventor previously focused on dynamically rewriting the logic configuration of the variable logic module and applying the variable logic module to an actual circuit such as a peripheral circuit as described in Patent Document 1. Therefore, a semiconductor device that can treat a memory circuit for realizing a variable logic function as a circuit equivalent to a logic circuit has been developed.

International Publication No. 2008/142767

  The present inventor further examined a variable logic module that treats a memory circuit for realizing a variable logic function as a circuit equivalent to the logic circuit. It has been found that when control data is constantly rewritten, the burden of correction and re-creation of control data increases. Furthermore, it has been found that there is a need for facilitating the correspondence to parallel arithmetic processing in response to a request for high-speed processing.

  An object of the present invention is to provide a semiconductor device capable of partially reducing the burden of function setting for variable logic in a configuration in which a memory circuit for realizing a variable logic function is handled as a circuit equivalent to a logic circuit. is there.

  Another object of the present invention is that, in a configuration in which a memory circuit for realizing a variable logic function is handled as a circuit equivalent to a logic circuit, the function setting burden for the variable logic can be partially reduced, and a parallel operation An object of the present invention is to provide a semiconductor device that can easily cope with processing.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  A semiconductor device according to the present invention includes a function reconfigurable memory device that is controlled by an access control device such as a CPU. The function reconfigurable memory device receives an access request from the access control device by an interface control circuit. The interface control circuit is connected to a plurality of function reconfigurable cells and a variable arithmetic cell that is provided in a one-to-one correspondence with the function reconfigurable cells and performs an operation upon receiving an output from the function reconfigurable cell. The function reconfigurable cell has a memory circuit and a control circuit, and the control circuit has a read address of data such as truth data initially stored in the control field and data field of the memory circuit in the first operation mode, In the second operation mode, a logical operation is performed by autonomously controlling based on the data in the control field. On the other hand, the variable operation cell can be operated based on the control data output from the control field of the storage circuit or the control data initialized by the access control device, for example, the final operation from the function reconfigurable cell. A logical operation such as inversion is additionally performed on the logical operation output.

  As a result, reading of the memory circuit for storing the truth value data can be autonomously controlled by the function reconfigurable cell itself, so that the memory circuit for realizing the variable logic function is treated as a circuit equivalent to the logic circuit. be able to. Therefore, it is possible to obtain flexibility in the feasible logic configuration and logic scale, and it is possible to realize a variable logic function that can cope with a large logic scale with a small chip occupation area. Since it has a variable operation cell that performs an operation based on control data output from the control field without burdening the function reconfigurable cell with all of the arithmetic circuit functions, the burden of function setting for the variable logic is partially Can be reduced.

  An arithmetic circuit that receives the output data of the operation result from the plurality of variable operation cells in parallel and performs an operation is further provided, and the access control device can access a data register in which the operation circuit holds the operation result. Thereby, it is easy to cope with parallel arithmetic processing.

  In addition, for the address mapping for random access to the memory circuit in the first operation mode, the memory mapped I / O register address for acquiring the logic operation result is individually obtained in the function reconfigurable cell in the second operation mode. Turn into. As a result, even if the logic function for the function reconfigurable cell is dynamically reconfigured, the logical address for the function reconfigurable cell is dynamically reconfigured without changing the read address for acquiring the logic operation result. Becomes easier. In particular, when a peripheral function is set in the function reconfigurable cell, when considering the matching between the memory access path by the central processing unit and the architecture separating the access path to the peripheral circuit, the access requesting entity The function setting access path to the function reconfigurable cell for the interface control circuit may be separated from the function set access path to the function reconfigurable cell.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the memory circuit for realizing the variable logic function can be handled as a circuit equivalent to the logic circuit, and the function setting burden for the variable logic can be partially reduced.

FIG. 1 is a block diagram illustrating an example of a variable function unit including a function reconfigurable cell. FIG. 2 is a block diagram illustrating an array configuration of a plurality of variable function units. FIG. 3 is a block diagram illustrating the overall configuration of the function reconfigurable memory. FIG. 4 is a block diagram showing another example of the array configuration of the variable operation cells 101 in the function reconfigurable memory. FIG. 5 is a block diagram illustrating the overall configuration of the function reconfiguration memory of FIG. FIG. 6 is a block diagram showing a second example of the variable function unit. FIG. 7 is a block diagram illustrating an array configuration of a plurality of variable function units 100A. FIG. 8 is a block diagram illustrating an overall configuration of the function reconfiguration memory 8 configured by employing the arithmetic circuit 110 together with an array configuration of a plurality of variable function units 100A. FIG. 9 is a block diagram showing another example of the array configuration of the variable operation cell 101A in the function reconfigurable memory. FIG. 10 is a block diagram illustrating the overall configuration of the function reconfiguration memory of FIG. FIG. 11 is a block diagram showing a third example of the variable function unit. FIG. 12 is an address map illustrating the address mapping between the function reconfigurable cell and the route selection circuit. FIG. 13 is an explanatory diagram showing the basic concept of the logic operation in the function reconfigurable cell. FIG. 14 is a flowchart illustrating the internal sequence of FIG. FIG. 15A is a block diagram illustrating an example in which a reloadable down counter is configured with function reconfigurable cells. FIG. 15B is an explanatory diagram illustrating information held in the memory circuit in the function reconfigurable cell of FIG. 15A. FIG. 15C is a flowchart of the down-count operation by the function reconfigurable cell of FIG. 15A. FIG. 16 is a block diagram showing an example in which a reload type down counter is configured with two function reconfigurable cells. FIG. 17 is a data example showing an example in which a 3-bit counter is configured with the configuration of FIG. 15A. FIG. 18 is a flowchart illustrating an operation sequence of the 3-bit counter operation shown in FIG. FIG. 19 is an operation explanatory diagram showing a specific operation example corresponding to the logical operation basic conceptual diagram of FIG. FIG. 20 is a block diagram showing an example in which a 6-bit counter is configured by connecting function reconfigurable cells constituting the 3-bit counter by a connection selection circuit. FIG. 21 is a block diagram generally showing a data processor according to an example of the present invention. FIG. 22 is an explanatory diagram illustrating an access mode of the function reconfigurable memory by the CPU. FIG. 23A is an explanatory diagram illustrating the data format of operation control data set in the register 102. FIG. 23B is an explanatory diagram illustrating the types of logical operations designated by the logical operation designation field CRF2. FIG. 23C is an explanatory diagram illustrating the significance of the enable signal Cond_LE for the variable operation cell 101. FIG. 24A is an explanatory diagram showing the relationship between the function reconfigurable cell 20 and the variable operation cell 101 in one variable function unit 100. FIG. 24B is an explanatory diagram schematically showing the function of the variable operation cell. FIG. 24C is an operation explanatory diagram illustrating a case where a negative logic operation is performed on input data DAT_D and DAT_C in units of words and operation result data L (DAT_D) and L (DAT_C) are output. FIG. 24D is an operation explanatory diagram illustrating a case where the operation result data L (DAT_D) and L (DAT_C) are output by performing a negative logic operation on the designated bits of the input data DAT_D and DAT_C. FIG. 25 is an explanatory diagram illustrating an operation mode in which the arithmetic circuit 110 performs parallel arithmetic on the outputs of the plurality of variable arithmetic cells 101. FIG. 26 is an explanatory diagram illustrating an operation mode in which the outputs of the plurality of variable calculation cells 101 are cascade-connected to perform sequential calculation. FIG. 27A is a block diagram schematically showing a cascade connection form of the front and rear variable function units 100A. FIG. 27B is an explanatory diagram schematically showing functions of the variable operation cell 101A. FIG. 27C shows an operation result data L obtained by performing a logical OR operation on input data DAT_D (n), DAT_C (n) and L (DAT_D (n-1)), L (DAT_C (n-1)) in units of words. It is operation | movement explanatory drawing which illustrates the case where (DAT_D (n)) and L (DAT_C (n)) are output. FIG. 27D shows the logical product of the input data DAT_D (n), DAT_C (n) and the third bit of L (DAT_D (n-1)), L (DAT_C (n-1)), and the other bits. On the other hand, it is an operation explanatory diagram illustrating the case where the input data DAT_D (n) and DAT_C (n) on the TML2 side are output through. FIG. 28 is a block diagram illustrating an operation mode in which the outputs of the plurality of variable calculation cells 101A are cascade-connected to perform sequential calculation. FIG. 29A is a block diagram schematically showing the variable calculation cell 101B. FIG. 29B is an explanatory diagram illustrating a selection form by the selectors 104 and 105. FIG. 30 is a block diagram illustrating a function reconfigurable memory 8A that can control the arithmetic operation of the variable arithmetic cell 101C based on the control data initially set by the CPU 2 in the arithmetic control register (ACREG).

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor device according to the present invention includes an access control device (2) and a function reconfigurable memory device (8) under the control of the access control device. The function reconfigurable memory device includes an interface control circuit (40, 41, 42) that receives an access request from the access control device, a plurality of function reconfigurable cells (20) connected to the interface control circuit, and the function A variable operation cell (101, 101A, 101B, 101C) that is provided in a one-to-one correspondence with the reconfiguration cell and performs an operation upon receiving an output from the function reconfiguration cell, and another variable operation cell that outputs the variable operation cell Or a transmission circuit (35, IBUS) for enabling supply to another function reconfigurable cell. The function reconfigurable cell has a memory circuit (23) and a control circuit (24). The memory circuit has a data field (27_D) and a control field (27_C) that are accessed based on address information output from the control circuit. The control circuit randomly accesses the storage circuit based on address information given to the interface control circuit in response to an access request from the access control device in the first operation mode, and first in the second operation mode The next read address of the storage circuit is autonomously controlled based on the control field information read from the storage circuit or the external event input. In the transmission circuit, a transmission path is set based on data given from the interface control circuit.

  According to this, since reading of the memory circuit can be autonomously controlled by the function reconfigurable cell itself, the memory circuit for realizing the variable logic function can be handled as a circuit equivalent to the logic circuit. Therefore, it is possible to obtain flexibility in the feasible logic configuration and logic scale, and it is possible to realize a variable logic function that can cope with a large logic scale with a small chip occupation area. Since a variable operation cell that performs an operation without burdening the function reconfigurable cell with all of the arithmetic circuit functions is provided, it is possible to partially reduce the burden of function setting for the variable logic.

  [2] In the semiconductor device of [1], the variable operation cells (101, 101A, 101B) are controlled in operation based on control data output from the control field of the memory circuit. It becomes easy to synchronize the arithmetic operation of the variable arithmetic cell with the logical operation by the function reconfigurable cell.

  [3] In the semiconductor device according to item 1, the variable operation cell (101C) is controlled in operation based on control data initially set in the operation control register (143) by the access control device. The variable operation cell can be logically operated without depending on the setting contents for the control field of the function reconfigurable cell.

  [4] <Next Read Address> In the semiconductor device according to item 1, in the second operation mode, the control circuit sends address information (ADR_EXT) supplied to the interface control circuit in response to the access request, a predetermined external event. Address information determined by the control circuit on condition of input (EXEV), address information previously read from the data field of the memory circuit, or address information obtained by address calculation of the address information previously output to the memory circuit Are output as the next read address.

  [5] <Operation instruction> In the semiconductor device according to item 4, the variable operation cell inputs / outputs operation data in a processing unit of a plurality of bits, and performs a logical operation type based on the control data output from the control field. And the operation target data bits are determined. This makes it possible to select the type of logical operation depending on the control data setting, and also to select the bit to be operated, so that operations can be easily added to the logical operation result of the function reconfigurable cell with a certain degree of flexibility. It becomes possible to do.

  [6] <Switch matrix circuit> In the semiconductor device according to item 5, the transmission circuit connects the switch circuit to a switch circuit (36) in which connection between adjacent function reconfigurable cells and variable logic cells is variable. Signal wiring (IBUS). Since the connection between the function reconfigurable cell and the variable logic cell is variable by the switch circuit, the flexibility for the programmable logic operation and arithmetic operation is further increased.

  [7] In the semiconductor device of [6], the switch circuit determines connection between adjacent function reconfigurable cells and variable logic cells based on data written by the access control device via the interface control circuit.

  [8] <Logical operation for parallel plural inputs> In the semiconductor device according to item 5, the variable operation cell includes a first input terminal (TML1) that receives an output from a corresponding storage circuit as an input terminal of operation target data; A second input terminal (TML2) for receiving the output of another variable logic cell is provided separately. Thereby, the variable operation cell can perform a logical operation on a plurality of parallel inputs.

  [9] The semiconductor device according to [1], further including an arithmetic circuit (110) that receives the output data of the arithmetic results from the plurality of variable arithmetic cells in parallel and performs arithmetic operations. The arithmetic circuit includes a data register (112) for holding an arithmetic result. The access control device can access the data register through the interface control circuit. Thereby, it is easy to cope with parallel arithmetic processing.

  [10] In the semiconductor device of [9], a first memory mapped IO register address arranged in an address space of the access control device is assigned to the data register.

  [11] In the semiconductor device of [10], a memory address arranged in an address space of the access control device is assigned to the storage circuit included in the function reconfigurable memory device in the first operation mode.

  [12] In the semiconductor device of [11], a memory mapped IO register address arranged in an address space of the access control device is assigned to each of the function reconfigurable memory devices in the second operation mode.

  According to this, for the address mapping for random access to the storage circuit in the first operation mode, the memory mapped I / O register for acquiring the logic operation result in the function reconfigurable cell in the second operation mode By individualizing the address, even if the logic function for the function reconfigurable cell is dynamically reconfigured, the logical address for the function reconfigurable cell is dynamically changed without changing the read address for acquiring the logic operation result. It will be easy to reconfigure. In particular, when a peripheral function is set in the function reconfigurable cell, when considering the matching between the memory access path by the central processing unit and the architecture separating the access path to the peripheral circuit, the access requesting entity The function setting access path to the function reconfigurable cell for the interface control circuit may be separated from the function set access path to the function reconfigurable cell.

  [13] Another semiconductor device according to the substantially same aspect of the present invention includes an access control device and a function reconfigurable memory device that is controlled by the access control device. The function reconfigurable memory device is provided in a one-to-one correspondence with an interface control circuit that receives an access request from the access control device, a plurality of function reconfigurable cells connected to the interface control circuit, and the function reconfigurable cell. A variable operation cell that performs an operation by receiving an output from the function reconfigurable cell, a transmission circuit for enabling the output of the variable operation cell to be supplied to another variable operation cell or another function reconfigurable cell, An arithmetic circuit that receives the output data of the operation results from the plurality of variable operation cells and performs the operation in parallel. The function reconfigurable cell has a memory circuit and a control circuit. The storage circuit has a data field and a control field that are accessed based on address information output from the control circuit. The control circuit randomly accesses the storage circuit based on address information given to the interface control circuit in response to an access request from the access control device in the first operation mode, and first in the second operation mode The next read address of the storage circuit is autonomously controlled based on the control field information read from the storage circuit or the external event input. The variable operation cell separately includes a first input terminal that receives an output from a corresponding memory circuit and a second input terminal that receives an output of another variable logic cell as input terminals for operation target data. In the transmission circuit, a transmission path is set based on data given from the interface control circuit.

  [14] In the semiconductor device of item 13, the variable operation cell is controlled in operation based on control data output from the control field of the memory circuit. It becomes easy to synchronize the arithmetic operation of the variable arithmetic cell with the logical operation by the function reconfigurable cell.

  [15] In the semiconductor device of item 13, the variable operation cell is controlled in operation based on control data initially set in the operation control register by the access control device. The variable operation cell can be logically operated without depending on the setting contents for the control field of the function reconfigurable cell.

  [16] In the semiconductor device of item 13, the arithmetic circuit includes a data register for holding an arithmetic result, and the access control device is allowed to access the data register through the interface control circuit.

2. Details of Embodiments Embodiments will be further described in detail.

<Data processor>
FIG. 21 illustrates a data processor 1 according to an example of the present invention. The data processor shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a complementary MOS integrated circuit manufacturing technique.

  The data processor 1 is a central processing unit (CPU) 2 as an access control device that fetches and executes instructions according to a program, a read only memory (ROM) 3 that stores programs executed by the CPU 2, and a work area of the CPU 2 A random access memory (RAM) 4 used for the above, and a direct memory access controller (DMAC) 5 for controlling data transfer according to an initial setting by the CPU 2, which are a system bus (first bus) SBUS Connected to. The system bus SBUS is connected to a peripheral bus (second bus) PBUS via a bus state controller (BSC) 6. The system bus SBUS is positioned as a high-speed bus that transmits data, addresses, bus commands, and the like in synchronization with the operating frequency of the CPU 2. On the other hand, the peripheral bus PBUS is connected to a peripheral circuit having a low operation speed, and data and the like are transmitted at a low speed. When the CPU 2 or the like issues an access request to the peripheral circuit, the BSC 6 performs bus control such as the number of bus cycles and the number of parallel data bits necessary for access via the peripheral bus according to the mapping address of the peripheral circuit related to the access request. .

  A function reconfiguration memory (RCFGM) 8 is connected to both the system bus SBUS and the peripheral bus PBUS. In the function reconfigurable memory 8, logical functions are variably set according to logical function setting information (configuration information) written from the system bus SBUS by the CPU 2 or the like, and data is set via the peripheral bus PBUS for the set logical functions. I / O is enabled.

  As a peripheral circuit connected to the peripheral bus PBUS, a digital / analog converter (DAC) 10 that converts a digital signal into an analog signal and outputs the analog signal, and a watch dog timer (WDT) 11 that monitors an instruction execution state of the CPU 2 and the like A timer (TMR) 12 capable of timer / counter operations such as input capture and compare match, a serial communication interface controller (SCI) 13, a pulse width modulation circuit (PWM) 15, and an interrupt controller (INTC) 16 are exemplified. In the figure, INTa and INTb are representatively shown as interrupt signals. The interrupt controller 16 performs interrupt mask control and priority level control on the interrupt signal, receives the interrupt signal, and issues a vector corresponding to the received interrupt signal. The CPU 2 issues an interrupt request signal IRQ to cause the CPU 2 to execute the interrupt processing program indicated by the vector. In addition, an IO port (not shown) is provided as a peripheral circuit.

  The function reconfiguration memory 8 includes a plurality of variable function units (VFU) 100, an interface control circuit (IFCNT) 21 that controls the function reconfiguration cell 20 in response to an access request from the outside, an arithmetic circuit (LOB) 110, and the like. Prepare. The variable function unit (VFU) 100 includes a function reconfigurable cell (ACMU) 20 connected to the interface control circuit 21 and a variable operation cell (LOC) 101 (101A) that receives an output from the function reconfigurable cell and performs an operation. Become. The output of the variable arithmetic cell is supplied to another variable arithmetic cell or another function reconfigurable cell via a transmission circuit such as a switch matrix circuit, the details of which will be described later.

  In the function reconfigurable cell 20, a logical function is set variably in accordance with configuration information written from the system bus SBUS by the CPU 2 or the like. In FIG. 21, some of the plurality of function reconfigurable cells 20 include a FIFO buffer (FIFO_B), a 16-bit pulse width modulation circuit (PWM_16b), an 8-bit pulse width modulation circuit (PWM_8b), a serial transmission unit (SCI_Tx), a serial The logical functions of the receiving unit (SCI_Rx) and the 24-bit timer (TMR_24b) are set. The remaining function reconfigurable cells 20 are made available as an internal memory (ITNR_RAM) that can be randomly accessed via the system bus SBUS. Writing of data used for the set logical operation, an instruction to start the logical operation, and data reading of the logical operation result are performed via the peripheral bus PBUS. The variable operation cell 101 (101A) is used when further operations are added to the result of the logic operation by the variable logic cell 20, and the operation function is variable but limited to some extent by hardware. Is arranged in order to partially reduce the function setting burden for the variable logic without burdening the configuration information for the function reconfigurable cell 20. In addition, the arithmetic circuit 110 is arranged to facilitate the correspondence to the parallel operation in which the operation results of the plurality of variable operation cells 101 (101A) are received in parallel. When the processing by the function reconfigurable cell 20 and the variable operation cell 101 (101A) is performed in series, the details thereof will be described later, but this can be realized by using the switch matrix circuit or the like.

<< First example of variable function unit >>
FIG. 1 shows an example of a variable function unit (VFU) 100. The function reconfigurable cell 20 has a memory circuit (MRY) 23 and a control circuit (MCNT) 24. The storage circuit 23 includes, for example, a single port static random access memory (SRAM) 25 and an address latch circuit (ADRLAT) 26. The SRAM 25 includes a memory array 27, an address decoder (SDEC) 28, and a timing controller (TMCNT) 29. The memory array 27 has a data field (DFLD) 27_D and a control field (CFLD) 27_C that are accessed by an address signal supplied from the address latch circuit 26. The address decoder (SDEC) 28 decodes the address signal output from the address latch circuit (ADRLAT) 26 and selects an access unit memory cell from each of the data field (DFLD) 27_D and the control field (CFLD) 27_C. The timing controller (TMCNT) 29 controls the read operation or write operation instructed by the read / write signal RW_j (j = 0 to m) with respect to the memory cell of the selected access unit.

  The control circuit 24 includes a selector (ADRSL) 30 that supplies an address signal to the address latch circuit 26, an address incrementer (ICRM) 31 that increments the address signal latched by the address latch circuit 26 by 1, and an access control decoder (ACDEC) 32. Have The selector 30 receives the information DAT_D read from the data field 27_D, the output of the address incrementer 31, and part of the address information ADR_EXT of the access address information supplied from the buses SBUS and PBUS. The access control decoder 32 is supplied with control information DAT_C read from the control field 27_C, an external event signal EXEVT, a random access selection signal RDMAE_j for the function reconfigurable cell 20, a logic enable signal LOGJ_j, and an IO access selection signal IOAE_j. Based on this, the output operation of the selector 30, the operation operation of the variable operation cell 101, and the like are controlled. The memory array 27 further includes an address field (AFLD) (not shown) and a path (DAT_A) that uses the output of the address field as an input to the selector 30 to access the memory array 27 and access the output from the address field. It is also possible to set the next access address of the memory array 27 by the control decoder.

  When the random access selection signal RDMAE_j is activated, the access control decoder 32 causes the selector 30 to select the address information ADR_EXT, and instructs the timing controller 29 to perform an access operation according to the read / write signal RW_j according to the address information ADR_EXT. As a result, the SRAM 25 can randomly access the address specified by the address information ADR_EXT.

  When the IO access selection signal IOAE_j is activated and a read operation is instructed by the read / write signal RW_j, the access control decoder 32 keeps the address latch state of the address latch circuit 26 at that time and performs the timing according to the latch address information. The controller 29 is instructed to perform a read access operation. Thereby, when the IO access selection signal IOAE_j of the function reconfigurable cell 20 is activated, the storage area selected by the SRAM 25 can be accessed at that time, and one memory mapped IO data is accessed for the SRAM 25. An access operation equivalent to reading a register becomes possible. When the IO access selection signal IOAE_j is activated and a write operation is instructed by the read / write signal RW_j, the access control decoder 32 causes the address selector 30 to select the address information ADR_EXT, and the address information ADR_EXT is address latch 26. The read address for the SRAM 25 can be initialized. Thus, when the IO access selection signal IOAE_j is enabled, the address latch circuit 26 to be written can be grasped as a register equivalent to the memory mapped IO register to be written. This equivalent register is referred to as a start address setting equivalent IO register. Further, when the IO access selection signal IOAE_j is enabled, the SRAM memory area to be read can be grasped as an equivalent register to the memory mapped IO register to be read. This equivalent register is referred to as a data read equivalent IO register.

  When the logic enable signal LOGJ_j is activated, the access control decoder 32 starts the memory read cycle of the SRAM 25 repeatedly during the active period using the address held by the address latch 26 as the start address, and for each cycle, The selection operation of the selector 30 is controlled in accordance with the control information DAT_C read from the control field 27_C. When the external event signal EXEVT is enabled, the access control decoder 32 causes the address selector 30 to output a specific address (for example, the start address of the SRAM 25) in the memory read cycle. When the logic enable signal LOG_j is enabled, the address latch 26 that holds the start address can be grasped as a register equivalent to a memory mapped IO register to which an enable bit for instructing the start of the logic operation is to be written. This equivalent register is referred to as a logic enable equivalent IO register.

  The operation mode in which random access is enabled is the first operation mode. The IO access operation mode in which the IO access selection signal IOAE_j is activated and the logic operation mode in which the logic enable signal LOGE_j is activated are the second operation mode with respect to the first operation mode.

  According to this function reconfigurable cell 20, reading of the memory circuit 23 can be autonomously controlled by the function reconfigurable cell 20 itself. For example, the control circuit 24 autonomously controls the next read address of the SRAM 25 based on the information DAT_C of the control field CFLD read from the SRAM 25 and the input of the external event signal EXEVT supplied to the access control decoder 32. Is possible. Thereby, the memory circuit 23 for realizing the variable logic function can be handled as a circuit equivalent to the logic circuit. Therefore, it is possible to obtain flexibility in the feasible logic configuration and logic scale, and it is possible to realize a variable logic function that can cope with a large logic scale with a small chip occupation area.

  Further, the control circuit 24 of the function reconfigurable cell 20 performs write protection on the memory array 27 of the storage circuit 23 based on an instruction for logic enable given to the interface control circuit 21 from the outside. As a result, it is possible to prevent the risk that data once set in the storage unit for realizing the logical function is erroneously erased or rewritten by random access. The instruction for logic enable is an instruction to perform an operation of determining the next read address of the memory array using the information of the control field 27_C previously read from the memory array 27. When an operation for executing the set logical function is instructed, the logical function is not changed undesirably.

  The variable operation cell 101 includes a logical operation field (LGCF) 103 and a control register (REG_L) 102. In the logical operation field 103, logical operation functions such as logical sum, logical product, inversion, exclusive logical sum, and exclusive logical product can be selected, and these logical operation functions refer to hard wired logic or truth table data. Thus, it is realized by a look-up table method for realizing a logical function. The control data is set in the control register 102 by the access control decoder 32 decoding the control data from the control field 27_C. When the logical operation field 103 is enabled by the enable signal Cond_LE, the logical operation function is selected based on the operation control data set in the control register 102. The calculation result is output as L (DAT_D) and L (DAT_C). Although not particularly limited, L (DAT_D) corresponds to the calculation result for DAT_D, and L (DAT_C) corresponds to the calculation result for DAT_C. The enable signal Cond_LE is output by the bus interface circuit 4 in accordance with an instruction from the CPU 2 or the like, for example.

  FIG. 2 illustrates an array configuration of a plurality of variable function units 100. The plurality of variable function units 100 are arranged in a matrix, and a connection path selection circuit (RSW) 35 is disposed between the variable function units 100 adjacent to the left and right. The variable function unit 100 and the connection path selection circuit 35 are connected to the internal bus IBUS_i (i = 0, 1,...) In units of rows. The internal bus IBUS_i is roughly divided into an address bus IABUS_i and a data bus IDBUS_i. The internal address bus IABUS_i supplies the address ADR_EXT to the control circuit 24. The internal data bus IDBUS_i is used to transmit information DAT_C, DAT_D, L (DAT_C), L (DAT_D) and the like to and from the variable function unit 100. The connection path selection circuit 35 passes the transmission paths of the data DAT_C, DAT_D and L (DAT_C), L (DAT_D) of the variable function unit 100 vertically or horizontally adjacent to the variable function unit 100 or the internal data bus IDBUS_i of the corresponding row. And a connection storage circuit 37 for holding switch control information of the switch circuit. The switch circuit 36 outputs the data L (DAT_D) and L (DAT_C) input from the variable function unit 100 as they are, and can supply the data L (DAT_D) and L (DAT_C) in parallel from the plurality of switch circuits 36. It has the operation form to do. The connection storage circuit 37 is randomly accessed via the internal buses IABUS_i and IDBUS_i, whereby necessary switch control information for the switch circuit 36 is set. When random access to the storage circuit 23 is instructed, the switch circuit 36 uses the random access selection signal RDMAE_j to set the storage circuit 23 to be accessed as an internal data bus regardless of the setting contents of the connection storage circuit 37. It is controlled to connect to IDBUS_i.

  Data DAT_C and DAT_D of one function reconfigurable cell 20 are transferred to another function reconfigurable cell 20 or other variable calculation cell 101, and data L (DAT_C) and L (DAT_D) of variable calculation cell 101 are set to other functions. Since it can be transmitted to the reconfigurable cell 20 or another variable arithmetic cell 101, it becomes possible to link the autonomous control among a plurality of function reconfigurable cells 20, and variable at that time. An arithmetic cell 101 can be used. A plurality of function reconfigurable cells 20 can be operated in series or in parallel to realize a unit of logic function. Specific examples will be described later.

  Configuration information for defining a logic function is randomly set in the memory circuit 23 of the function reconfigurable cell 20, and configuration information for defining a connection path in the connection memory circuit 37 of the connection path selection circuit 35. Is set by random access. When the function reconfigurable cell 20 to which the logic function is set is instructed to start the logic operation, the information obtained by the logic operation is transferred to another function reconfigurable cell 20 arranged on the left or right or top and bottom. The information by the logic operation of the function reconfigurable cell 20 can be read to the outside via the corresponding bus IBUS_i by an access operation equivalent to reading to the memory mapped IO register.

  FIG. 3 illustrates the overall configuration of the function reconfiguration memory 8. In response to an access request from the buses SBUS and PBUS, a bus interface circuit (BUSIF) 40 is used as an interface control circuit for controlling the array of the plurality of variable function units 100 and the connection path selection circuit 35 described in FIG. An address decoder (ADEC) 41 and an internal bus selection circuit (IBSL) 42 are included.

  As illustrated in FIG. 12, the addresses of the first address range AA1 are mapped to the memory area of the memory circuit 23 (the memory area of the SRAM 25) of the plurality of function reconfigurable cells 20. The first address range AA1 is a partial address space of the memory space connected to the system bus SBUS. The start address setting equivalent IO register, the data read equivalent IO register, and the logic enable equivalent IO register can be grasped as equivalent memory mapped IO registers for the respective function reconfigurable cells 20. Is mapped with the address of the second address range AA2. In FIG. 12, the address of SRAM in one function reconfigurable cell is 256 words, and the address of the three equivalent memory mapped IO registers in one function reconfigurable cell is 3 words. Address. The second address range AA2 is a partial address space of the memory-mapped IO address space allocated to the peripheral circuit registers and the like connected to the peripheral bus PBUS. The address of the third address range AA3 is mapped to the storage area of the connection storage circuit 37. The third address range AA3 is a part of the memory space connected to the system bus SBUS or the peripheral bus PBUS.

  The bus state controller 6 performs access control as an access to the memory address space in the address space of the data processor when there is an access request to the first or third address range AA1, AA3, and the second address space AA2 When an access request is made, access control is performed as an access to the IO address space in the address space of the data processor. The bus interface circuit 40 of the function reconfigurable memory 8 accepts access regardless of the access to any of the first to third address ranges. The bus interface circuit 40 activates the memory window enable signal CME when there is an access request to the first or third address range AA1, AA3, and the bus interface circuit when there is an access request for the second address range AA2. 40 activates the logic window enable signal CRE. The direction of data related to the access request is determined by a read signal RD and a write signal WT issued from the access request source. The memory window enable signal CME and the logic window enable signal CRE are supplied to the address decoder 41, for example.

  The address decoder 41 decodes the higher-order bits of the address signal related to the access request, and determines which one of the function reconfigurable cell 20 and the connection path selection circuit 35 arranged in the array is designated. When the connection path selection circuit 35 is designated, the connection storage circuit 37 of the circuit is enabled, the corresponding internal bus IBUS_i is selected by the bus selection circuit 42 and connected to the system bus SBUS, and the access request is accompanied. Using the lower address information of the address signal, the connection storage circuit 37 can be randomly accessed. Thereby, the CPU 2 and the like can arbitrarily define the connection between the function reconfigurable cells 20 by writing to the connection storage circuit 37 by random access designating the address in the third address range AA3.

  Further, when the address decoder 41 determines by address decoding that the function reconfigurable cell 20 is designated by the address in the address range AA1, the address decoder 41 activates RDMAE_j assigned to the function reconfigurable cell and responds accordingly. The internal bus IBUS_i is selected by the bus selection circuit 42 and connected to the system bus SBUS, and the low-order address information of the address signal accompanying the access request is used to enable random access to the connection storage circuit 37. Thereby, the CPU 2 and the like can arbitrarily define the logical configuration of the function reconfigurable cell 20 by writing to the SRAM 25 of the storage circuit 23 by random access designating the address in the first address range AA1.

  When the address decoder 41 determines by the address decoding that the equivalent memory mapped IO register of the function reconfigurable cell 20 is specified by the address in the address range AA2, the specified equivalent memory map Depending on the IO register, IOAE_j or LOGJ is activated, and the read / write signal RW_j is generated.

  That is, at that time, when the write operation is instructed by the write signal WT by specifying the start address setting equivalent IO register from the peripheral bus PBUS, the address decoder 41 uses the lower address information of the address signal accompanying the access request. The IOAE_j assigned to the designated function reconfigurable cell 20 is activated. Further, the write operation is designated by the read / write signal RW_j. As a result, write data is set in the ADRLAT 26 via the ADRSEL 30 of the function reconfigurable cell 20.

  At that time, when the logic enable equivalent IO register is specified from the peripheral bus PBUS and a read operation is instructed by the read signal RD, the address decoder 41 is specified by the lower address information of the address signal accompanying the access request. LOG_j assigned to the function reconfigurable cell 20 to be activated is activated. Further, the read operation is designated by the read / write signal RW_j. As a result, the access control decoder 32 of the function reconfigurable cell 20 starts the memory read cycle of the SRAM 25 repeatedly during the active period using the address held by the address latch 26 as the start address, and from the data field 27_D every cycle. The read data information DAT_D is fed back to the selector, and the logic operation is realized by controlling the selection operation of the selector 30 in accordance with the control information DAT_C read from the control field 27_C every cycle.

  At that time, when the read operation is instructed by the read signal RD by designating the data read equivalent IO register from the peripheral bus PBUS, the address decoder 41 designates the lower address information of the address signal accompanying the access request. The IOAE_j assigned to the function reconfigurable cell 20 to be executed is activated. Further, the bus interface circuit 40 designates a read operation by the read / write signal RW_j. As a result, the bus interface circuit 40 receives information read from the storage area of the SRAM 25 selected by the address information held in the ADRLAT 26 of the function reconfigurable cell 20 and outputs it as read data to the peripheral bus PBUS. Thereby, the CPU 2 or the like can arbitrarily obtain the result of the logical operation by the function reconfigurable cell 20 in which the logical function is set by the read access designating the address in the second address range AA2. When the bus interface circuit 40 recognizes a request such as completion of the logic operation as one of the results of the logic operation, the bus interface circuit 40 can supply an interrupt signal to the interrupt controller 16. For example, the CPU 2 to which the interrupt is given shifts to an operation routine for acquiring the result of the logic operation from the function reconfigurable cell 20 which has finished the logic operation by designating the read operation to the data read equivalent IO register. It becomes possible to do.

  As described above, the memory allocated to the function reconfigurable cell in order to obtain the logical operation result by the function reconfigurable cell with the function set for the address mapping (first address range) for random access to the memory circuit. In order to obtain a logic operation result by dynamically reconfiguring a logic function for a function reconfigurable cell by individualizing an address (address in the second address range) such as a mapped I / O address Therefore, it is easy to dynamically reconfigure the logic function for the function reconfigurable cell without changing the read address.

  The basic concept of logic operation in the function reconfigurable cell 20 is shown in FIG. The control circuit 24 uses the address Y, which is the external address ADR_EXT under the condition COND = 1, as the access address of the storage circuit 23. During the condition COND = 0, the address specified by the data information DAT_D according to the internal sequence determined by the control information DAT_C To access the memory circuit 23. As illustrated in FIG. 14, when the process A is performed according to the internal sequence, the process branches to the process B according to the address specified by the data information DAT_D defined by the internal sequence while the condition COND = 0. It is also possible to branch to the process C specified by the external address ADR_EXT when the condition COND = 1. Here, the condition COND may be grasped as a condition determined by the access form to the function reconfiguration memory 8 by the CPU 2 or the like, and further as a condition determined by the control information DAT_C.

  An example in which a reloadable down counter is configured with the function reconfigurable cell 20 is shown in FIG. 15A. Here, TYPE and CFLAG are assumed to be included in the control information DAT_C. FIG. 15B illustrates information held in the memory circuit 23. Data means information of the data field DFLD, and address means address information supplied to the address latch circuit 26. For example, when “0110” is input as the external address ADR_EXT when CFLAG = 1 (COND = 1), CFLAG = 0 and Data = “0101” are read using this as the address, and the read data is the next The same operation is repeated until CFLAG = 1 = 1. The data information DAT_D output during this period is a down count value from “1010” to “0000”. When COND = 1, the count initial value can be reloaded again to repeat down-counting. FIG. 15C illustrates a flowchart in the down-counting operation.

  An example in which a reload type down counter is configured by two function reconfigurable cells 20 is shown in FIG. When all the bits of the output data DAT_D of the lower byte are all “0”, CFLAG is given to the control circuit of the function reconfigurable cell 20 of the upper byte to start the operation of the upper byte. When all the bits of the output data DAT_D of the upper byte are all “0”, the multi-byte down-count is completed, and the multi-byte down-count can be restarted by reloading the lower byte count initial value again. it can.

  FIG. 17 shows an example in which a 3-bit counter is configured with the configuration of FIG. 15A. FIG. 17 illustrates data stored in the SRAM. The Next Address column shown in the figure means the value of the address latch circuit 26. [Reg] shown at the end means that an address can be arbitrarily set from the outside by CFLAG = 1. FIG. 18 illustrates an operation sequence of the 3-bit counter operation according to FIG. In step S11-1, N is set to "000" as the initial address value, and in step S11-2, the value "111" stored in the Next Address field of address "000" is set as the N value. In S11-3, the value “0” stored in the CFLAG field of the address “111” is determined. Thereafter, steps S11-2 and S11-3 are repeated until the value of the CFLAG field becomes “1”. In the process of repetition, the value of the Data field at address N is output as a 1-down counter from “111” to “000”.

  A specific operation example corresponding to the logical operation basic conceptual diagram of FIG. 13 is shown in FIG. As an external trigger, for example, “111” is input to the address latch 26 as an initial address value by designating the start address setting equivalent IO register (S1). Next, the logic operation is started when the address information of the address latch 26 is started to be supplied to the SRAM 25 by the designation of the logic enable equivalent IO register (S2). As a result, “110” is supplied to the selector 30 as the data information DAT_D from the data field DFLD designated by the address (S3), and the information “101” is supplied from the control field CFLD as the control information DAT_C to the access control decoder 32. Is supplied (S4). The access control decoder 32 decodes the information “101”, selects the information “110” fed back in S3 (S5), and this time the SRAM 25 is accessed using this information “110” as an address (S6). Thereafter, the same operation is repeated to perform a required logical operation (3-bit down counter operation). CLK is an operation reference clock signal of the function reconfigurable cell 20 that defines a memory cycle of the SRAM 25 and the like.

  FIG. 20 shows an example in which a function reconfigurable cell 20 constituting a 3-bit counter is connected by a connection selection circuit 35 to constitute a 6-bit counter. In this configuration, each function reconfigurable cell shows an example in which a 3-bit up counter operation is performed, and the set value of the data field DFLD and the initial address value supplied from the outside are different from the example of FIG. The function reconfigurable cell 20_L constitutes the lower 3 bits, 20_U constitutes the upper 3 bits, and the connection path selection circuit 35 obtains the inverted value of the least significant bit of the control field CFLD of the function reconfigurable cell 20_L constituting the lower 3 bits. This is supplied as the logic enable signal LOG_j of the function reconfigurable cell 20_U constituting the upper 3 bits. Before starting the count operation, “000” is set as an initial address value in the address latch circuit 26 of the function reconfigurable cells 20_L and 20_U, and then LOG_i is made active and the function reconfigurable cell 20_L performs a count operation of lower 3 bits. Let it begin. LOG_j is changed to active only for one cycle during which up-counting by the lower 3 bits of the function reconfigurable cell 20_L ends and the control information DAT_C outputs “100”, and the upper 3 bits of the function reconfigurable cell 20_U is counted. To do. When the control information DAT_C of the function reconfigurable cell 20_L outputs “100”, the 20_L address control decoder 32 selects the input from the outside to the selector 30 and sets it in the address latch circuit 26. As a value, “001” may be set.

  An access mode of the function reconfigurable memory 8 by the CPU is illustrated in FIG. Random access to the function reconfiguration memory 8 by the CPU 2 or DMAC 5 is performed using the path PAS_S. This access operation is used for setting configuration information for setting functions for the function reconfigurable cell 20 and the connection path selection circuit 35. This is also the case where the function reconfigurable cell 20 that has not been used for setting the logic function is read / write accessed as an internal RAM (ITNR_RAM). Further, the memory mapped IO register access to the function reconfigurable memory 8 by the CPU 2 and the DMAC 5 is performed using the path PAS_P. This access operation is used, for example, for accessing the start address setting equivalent IO register, data read or IO register, and logic enable equivalent IO register. The address mapping for random access and the address mapping for memory mapped IO register access are separated from each other.

  As described above, by setting required configuration information in the function reconfigurable cell 20 and the connection path selection circuit 35, a required peripheral function can be realized using one or a plurality of function reconfigurable cells 20. By using this function, it is possible to realize a required arithmetic function such as a logical operation, an arithmetic operation, and further an encoding / decoding operation in one or a plurality of function reconfigurable cells 20. At this time, as illustrated in FIG. 1, the function reconfiguration memory 8 includes a variable operation cell 101 having a logic function limited to some extent together with the function reconfiguration cell 20, and a load of operation function setting for the function reconfiguration cell 20. Has been reduced.

  Next, the variable arithmetic cell 101 added to the function reconfigurable cell 20 and the arithmetic circuit 110 for facilitating parallel arithmetic will be further described.

  FIG. 23A illustrates the data format of the operation control data set in the register 102. It has an input selection field CRF1, a logical operation designation field CRF2, and a logical operation bit designation field CRF3. In the example of FIG. 1, the input selection field CRF1 is ignored. The logical operation designation field CRF2 designates the type of logical operation. The logical operation bit specification field CRF3 specifies which bit of the input operation target data is to be the operation target bit. Here, the input unit of the operation target data is referred to as a word. The logical operation designation field CRF2 illustrated in FIG. 23B is 3 bits and designates the type of logical operation, for example, logical sum, exclusive logical sum, logical product, negative logic, and “000” to “011” are word unit operations. And “100” to “111” designate bitwise operations. In the operation designation in bit units, the operation target bit is designated by a 4-bit bit designation field CRF3 illustrated in FIG. 23B. Here, up to 16 bits per word can be supported. In the example of FIG. 1, one operation target data of two inputs of logical sum, exclusive logical sum, or logical product is DAT_D, DAT_C, and the other operation target data is not particularly limited, but is not externally input data. , And a fixed value unique to the LGCF 103. Alternatively, one operation target data is DAT_D, the other operation target data is DAT_C, an operation result is L (DAT_D), and DAT_C is output to L (DAT_C) as it is. FIG. 23C illustrates the significance of the enable signal Cond_LE for the variable operation cell 101. If “0”, the data to be calculated outputs DAT_D and DAT_C through, and if “1”, the calculation is performed according to the specification of the calculation control data.

  24A to 24D show calculation examples by the variable calculation cell 101. FIG. FIG. 24A shows the relationship between the function reconfigurable cell 20 and the variable operation cell 101 in one variable function unit 100. FIG. 24B schematically shows the function of the variable operation cell. FIG. 24C illustrates a case where the operation result data L (DAT_D) and L (DAT_C) are output by performing a negative logic operation on the input data DAT_D and DAT_C in units of words. FIG. 24D illustrates a case where a negative logic operation is performed on the designated bits of the input data DAT_D and DAT_C, and operation result data L (DAT_D) and L (DAT_C) are output.

  FIG. 25 illustrates an operation mode in which the arithmetic circuit 110 performs parallel arithmetic on the outputs of the plurality of variable arithmetic cells 101. The arithmetic type of the arithmetic circuit is logical sum, logical product, exclusive logical sum, exclusive logical product or the like for parallel input data, and the arithmetic type may be fixed or variable depending on the initial setting from the CPU 2. May be. The calculation result is stored in a data register (DOTREG) 112 in the calculation circuit 110. A unique IO address is assigned to the data register 112, and the accumulated calculation result can be read out to the outside via the internal bus IBUS_0 by an IO register read access designating the register 112. The parallel computation path may be determined by setting data written to the connection storage circuit 37 in the connection path selection circuit 35.

  FIG. 26 illustrates an operation mode in which the outputs of a plurality of variable calculation cells 101 are connected in cascade and the calculation is performed sequentially. The cascade-connected first-stage variable arithmetic cell 101 inputs data DAT_D and DAT_C output from the function reconfigurable cell 20 and performs arithmetic operations. The variable calculation cells 101 in the second and subsequent stages perform calculations by inputting the output data L (DAT_D) and L (DAT_C) of the variable calculation cell 101 in the previous stage. A serial operation path is determined by setting data written in the connection storage circuit 37 in the connection path selection circuit 35.

  4 and 5 show another example of the array configuration of the variable operation cells 101 in the function reconfigurable memory 8. 4 corresponds to FIG. 2, and FIG. 5 corresponds to FIG. The difference from FIG. 2 and FIG. 3 is that the arithmetic circuit 110 is not provided and the parallel path of the arithmetic data L (DAT_D) and L (DAT_C) from the variable arithmetic cell 101 to the arithmetic circuit 110 is eliminated. Although the arithmetic operation according to the parallel connection mode of FIG. 25 cannot be performed, the hardware can be reduced accordingly.

<< Second example of variable function unit >>
FIG. 6 shows a second example of the variable function unit. The variable function unit 100A shown in the figure has a variable operation cell 101A different from that shown in FIG. The variable operation cell 101A includes a logical operation field (LGCF) 103A and the control register (REG_L) 102. The logical operation field 103A serves as an input terminal for operation target data and receives a plurality of second outputs from the corresponding storage circuit 23. One input terminal TML1 and a plurality of second input terminals TML2 receiving the output of another variable logic cell are separately provided. FIG. 7 illustrates an array configuration of a plurality of variable function units 100A, and FIG. 8 illustrates a function reconfiguration memory 8 configured using the arithmetic circuit 110 together with an array configuration of a plurality of variable function units 100A. The overall configuration is illustrated. 7 and 8 has a transmission path 12 for data L (DAT_D) and L (DAT_C) added as compared to FIGS. As apparent from FIG. 7, the data L (DAT_D) and L (DAT_C) output from one variable arithmetic cell 101A are connected to the second input terminal TML2 of another variable arithmetic cell 101A via the connection path selection circuit 35. Can be entered.

  The data format of the operation control data in the register 102 is as described with reference to FIGS. 23A to 23C. However, the input selection field CRF1 is not ignored, and when the negative logic is selected in the logic operation field 103, the input is the first input terminal. Designate whether to use TML1 or the second input terminal TML2. The logical operation field 103 is not particularly limited, but as described above, logical operation of logical sum, exclusive logical sum, logical product, or negative logic is enabled, and logical sum, exclusive logical sum, or logical product is When specified, the input data from the first input terminal TML1 and the input data from the second input terminal TML1 are to be calculated. The type of calculation operation is specified in the logical calculation designation field CRF2, and the calculation target bit is specified in the bit designation field CRF3. The calculation target bits other than those specified are not particularly limited, but the corresponding bits on the input side specified in the input selection field CRF1 are output through.

  FIG. 27A to FIG. 27D show calculation examples by the variable calculation cell 101A. FIG. 27A schematically shows a cascade connection form of the front and rear variable function units 100A. In the logical operation field 103A, when logical sum, exclusive logical sum, or logical product is designated, the output DAT_D, DAT_C of the corresponding function reconfigurable cell 20 and the operation result data L output from the preceding logical operation field 103A (DAT_D) and L (DAT_C) are calculated and output to the subsequent variable function unit 100A. FIG. 27B schematically shows the function of the variable operation cell 101A. FIG. 27C shows a logical OR operation on input data DAT_D (n), DAT_C (n) and L (DAT_D (n-1)), L (DAT_C (n-1)), and results data An example of outputting L (DAT_D (n)) and L (DAT_C (n)) will be described. FIG. 27D shows the logical product of the input data DAT_D (n), DAT_C (n) and the third bit of L (DAT_D (n-1)), L (DAT_C (n-1)), and the other bits. On the other hand, a case where the input data DAT_D (n) and DAT_C (n) on the TML2 side is output through is illustrated.

  FIG. 28 illustrates an operation mode in which the outputs of a plurality of variable calculation cells 101A are cascade-connected to perform calculation sequentially. The exceptional variable arithmetic cell 101A connected in cascade performs arithmetic on the data DAT_D, DAT_C (input data from the input terminal TML1) output from the function reconfigurable cell 20 and the input data from the input terminal TML2. A serial operation path is determined by setting data written in the connection storage circuit 37 in the connection path selection circuit 35.

  Since the operation mode in which the arithmetic circuit 110 performs parallel arithmetic on the outputs of the plurality of variable arithmetic cells 101A is the same as described above, detailed description thereof is omitted.

  FIGS. 9 and 10 show another example of the array configuration of the variable operation cell 101A in the function reconfigurable memory 8. FIG. 9 corresponds to FIG. 2, and FIG. 10 corresponds to FIG. The difference from FIG. 2 and FIG. 3 is that the arithmetic circuit 110 is not provided and the parallel path of the arithmetic data L (DAT_D) and L (DAT_C) from the variable arithmetic cell 101A to the arithmetic circuit 110 is abolished. Although it is not possible to perform an arithmetic operation in a parallel connection form, the hardware can be reduced accordingly.

<< Third example of variable function unit >>
FIG. 11 shows a third example of the variable function unit. The variable function unit 100B shown in the figure has a variable operation cell 101B different from that shown in FIG. The variable operation cell 101B includes a feedback path 130 for returning the output of the logic operation field (LGCF) 103A to the input terminal TML2, and data from the feedback path 130 or previous stage data L (DAT_D), 6 is different from FIG. 6 in that selectors (INSLC) 104 and 105 for selecting L (DAT_C) are provided. Since other configurations are the same as those in FIG. 6, a detailed description thereof will be omitted.

  29A and 29B exemplify the selection control form of the selectors 104 and 105 in the variable arithmetic cell 101B. As schematically shown in FIG. 29A, the variable arithmetic cell 101B performs the selection operation according to the value of the input selection field CRF1 of the register 102. The selection form is illustrated in FIG. 29B. With this configuration, the number of calculation forms by the variable calculation cell 101B is further increased.

<< Fourth example of variable function unit >>
In the above description, the variable operation cells 101, 101A, 101B have been described as being controlled in operation based on control data output from the control field 27_C of the storage circuit 23. The present invention is not limited to this, and the arithmetic operation may be controlled based on control data initially set in the arithmetic control register by the CPU, or both may be used in combination.

  FIG. 30 illustrates a function reconfigurable memory 8A that can control the arithmetic operation of the variable arithmetic cell 101C based on the control data initially set by the CPU 2 in the arithmetic control register (ACREG). The variable functional unit 100C is different from the variable functional unit 100A in the configuration of the variable arithmetic cell 101C. An arithmetic control circuit 140 for the variable arithmetic cell 101C includes an input / output buffer (IOBUF) 141, a data register (DATREG) 142, and an arithmetic control register (ACREG) 143. In the arithmetic control register (ACREG) 140, arithmetic control data is initialized by the CPU 2. The data register (DATREG) 141 is a memory mapped IO register in which the operation result is stored, and is accessible by the CPU 2. The variable arithmetic cell 101C is different from the variable arithmetic cells 101A and 101B in that control data to the register 102 is transmitted from the arithmetic control register (ACREG) 143, and the other configurations are the same as those described with reference to FIG. This is the same, and detailed description thereof is omitted.

  In the description of FIG. 30, the configuration in which the variable operation cells 101C are cascade-connected in advance is taken as an example, but it is needless to say that the present invention can be applied to the array configuration using the switch matrix circuit described in FIG.

  The microcomputer 1 described above has the following effects.

  (1) Reading of the memory circuit 23 can be autonomously controlled by the function reconfigurable cell 20 itself. Therefore, the memory circuit 23 for realizing the variable logic function can be handled as a circuit equivalent to the logic circuit, the logic configuration that can be realized is flexible, and it can cope with a large logic scale with a small chip occupation area. A variable logic function can be realized.

  (2) The CPU 2 or the like makes a write access request to the third address range AA3, thereby randomly accessing the connection storage circuit 35 to which the address related to the access request is assigned, and between the function reconfigurable cells 20 The switch control information for defining the connection can be arbitrarily written.

  (3) The CPU 2 or the like makes an access request to the first address range AA1, thereby randomly accessing the SRAM 25 of the function reconfigurable cell 20 to which the address related to the access request is assigned, and reconfiguring the function. Information for realizing a predetermined logic function can be arbitrarily defined in the SRAM 25 of the cell 20.

  (4) The CPU 2 or the like requests the data read equivalent IO register access to the second address range AA2, thereby reading the information output from the SRAM 23 by the control circuit 24 as a result obtained by the logic function. can do. Thereby, the CPU 2 or the like can arbitrarily obtain the result of the logical operation by the function reconfigurable cell 20 in which the logical function is set by the read access designating the address in the second address range AA2.

  (5) The memory mapped IO address assigned to the function reconfigurable cell 20 in order to obtain the logical operation result by the function reconfigurable cell 20 with the function set for the address mapping of AA1 and AA3 for random access By individualizing the address mapping of AA2 as described above, even if the logic function for the function reconfigurable cell 20 and the connection selection circuit 35 is dynamically reconfigured, the read address or the like for obtaining the logic operation result is changed. Therefore, it is easy to dynamically reconfigure the logic function for the function reconfigurable cell 20.

  (6) The system bus SBUS is used as a function setting access path from the CPU 2 to the function reconfigurable cell 20 for the bus interface circuit 40, and an equivalent memory-mapped register access to the function reconfigured cell 20 having the function set is performed. Since the peripheral bus is used as the path and both paths are separated, when the peripheral function is set in the function reconfigurable cell 20, the memory access path by the CPU 2 or the like and the access path to the peripheral circuit are separated. It can be easily matched with the existing architecture.

  (7) Since the variable operation cells 101, 101A, and 101B that perform the operation without burdening the function reconfigurable cell 20 with all of the arithmetic circuit functions are provided, it is possible to partially reduce the function setting burden for the variable logic. .

  (8) Since the arithmetic operation of the variable arithmetic cells 101, 101A, 101B is controlled based on the control data output from the control field 27_C of the storage circuit, the arithmetic operation of the variable arithmetic cells is function reconfigurable cell. It becomes easy to synchronize with the logic operation by 20.

  (9) Since the calculation operation of the variable calculation cell 101C is controlled based on the control data initially set in the calculation control register 143 by the CPU 2, the variable calculation cell 101C is variable without depending on the setting contents for the control field of the capacity reconfigurable cell 20. It becomes possible to perform a logical operation of the operation cell.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  The function reconfigurable memory 8 has been described as being configured with SRAM, but may be configured with, for example, MRAM. The MRAM is a non-volatile memory that enables high-speed read / write operations. It can also be configured by a flash memory, a phase change memory, or the like, which is another known nonvolatile memory. Comparing the MRAM and the flash memory, there is an advantage that the read / write operation is faster in the MRAM and there is no limit on the number of rewrites the flash memory has. Compared with the phase change memory, the read / write operation speed is almost the same, but there is an advantage that the heat resistance is higher than that of the phase change memory. On the other hand, since MRAM is a magnetic storage system, its magnetic resistance is lower than that of phase change memory. What is necessary is just to select the memory which comprises the function reconfiguration | reconstruction memory 8 according to use environment.

  By configuring the function reconfigurable memory 8 with a non-volatile memory, it is possible to obtain the advantage that the once configured logic function is maintained even if the power is cut off, and the program stored in the ROM 3 is functioned. The reconfigurable memory 8 can be stored in a partial space of a random accessible internal memory (ITNR_RAM). By configuring with an MRAM or a phase change memory, it is possible to use another space of an internally accessible memory (ITNR_RAM) instead of the RAM 4 as a work area of the central processing unit.

  Also, the equivalent memory mapped IO register access is an example, and the enable signal for LOGG_j and the type of the equivalent memory mapped IO register can be changed as appropriate. If an architecture that separates the system bus and the peripheral bus is not adopted, the random access path for the function reconfigurable cell and the equivalent memory mapped IO register access path need not be separated. As a connection form between the function reconfigurable cells arranged in matrix and the bus, a connection form in which buses are arranged in the X and Y directions and addressed from the X and Y directions and connected to the bus may be employed. The peripheral functions realized by the function reconfigurable cell are not limited to the above and can be changed as appropriate. Moreover, it is not limited to so-called peripheral functions for the CPU. It is also possible to assign a calculation function or the like that reduces the burden on the CPU, such as an accelerator. The access control device is not limited to a CPU. The circuit mounted on the semiconductor device together with the function reconfigurable memory is not limited to that shown in FIG. 21 and can be changed as appropriate according to the function and application of the semiconductor integrated circuit. The semiconductor device is not limited to a single chip, and can also be applied to a semiconductor device such as a system-in-package in which a multichip is mounted on a module substrate and sealed. The function reconfigurable cell to which clock generation control and clock enable control are added can be widely applied to the realization of various circuit functions other than PWM and counter. The present invention can be widely applied to semiconductor devices such as a semiconductor data processing device provided with a variable logic module.

1 Data processor 2 Central processing unit (CPU)
4 Random access memory (RAM)
5 Direct memory access controller (DMAC)
SBUS system bus (first bus)
6 Bus State Controller (BSC)
PBUS peripheral bus (second bus)
8 Function reconfiguration memory (RCFGM)
16 Interrupt controller (INTC)
20 Function Reconfigurable Cell (ACMU)
21 Interface control circuit (IFCNT)
23 Memory circuit (MRY)
24 Control circuit (MCONT)
25 Static random access memory (SRAM)
26 Address latch circuit (ADRLAT)
27 Memory array 27
28 Address decoder (SDEC)
29 Timing controller (TMCNT)
27_D Data field (DFLD)
27_C Control field (CFLD)
30 Selector (ADRSL)
31 Address Incrementer (ICRM)
32 Access Control Decoder (ACDEC)
DAT_C Control information EXEVT External event signal RDME_j Random access selection signal IOAE_j IO access selection signal RW_j Read / write signal LOG_j Logic enable signal 35 Connection path selection circuit IBUS_i Internal bus IABUS_i Internal address bus IDBUS_i Internal data bus 36 Switch circuit 37 Connection circuit 37 40 Bus interface circuit (BUSIF)
41 Address decoder (ADEC)
42 Internal bus selection circuit (IBSL)
AA1 First address range AA2 Second address range AA3 Third address range 51 Operation control unit 52 Operation logic unit 53 Memory unit 54 Operation control unit 55 Operation lock unit 100, 100A, 100B, 100C Variable function unit 101, 101A , 101B, 101C Variable operation cell 102 Control register 103, 103A Logic operation field 104, 105 Input selection circuit (INSLC)
TML1 first input terminal TML2 second input terminal 110 arithmetic circuit

Claims (16)

An access control device and a function reconfigurable memory device that is controlled by the access control device;
The function reconfigurable memory device is provided in a one-to-one correspondence with an interface control circuit that receives an access request from the access control device, a plurality of function reconfigurable cells connected to the interface control circuit, and the function reconfigurable cell. A variable operation cell that performs an operation upon receiving an output from the function reconfigurable cell; and a transmission circuit that enables the output of the variable operation cell to be supplied to another variable operation cell or another function reconfigurable cell. Have
The function reconfigurable cell has a memory circuit and a control circuit;
The storage circuit has a data field and a control field that are accessed based on address information output from the control circuit,
The control circuit randomly accesses the storage circuit based on address information given to the interface control circuit in response to an access request from the access control device in the first operation mode, and first in the second operation mode Autonomously controlling the next read address of the memory circuit based on the control field information or external event input read from the memory circuit;
A semiconductor device in which a transmission path is set based on data given from the interface control circuit.   The semiconductor device according to claim 1, wherein the variable operation cell is controlled in operation based on control data output from the control field of the storage circuit.   2. The semiconductor device according to claim 1, wherein the operation operation of the variable operation cell is controlled based on control data initially set in an operation control register by the access control device.   In the second operation mode, the control circuit includes address information supplied to the interface control circuit in response to the access request, address information determined by the control circuit on the condition of a predetermined external event input, 2. The semiconductor device according to claim 1, wherein address information read from a data field or address information obtained by address calculation of address information previously output to the storage circuit is output as the next read address.   The variable operation cell inputs / outputs operation data in a processing unit of a plurality of bits, and determines a type of logic operation and an operation target data bit based on control data output from the control field. Semiconductor device.   The semiconductor device according to claim 5, wherein the transmission circuit includes a switch circuit in which connection between adjacent function reconfigurable cells and variable logic cells is variable, and a signal wiring that connects the switch circuits.   7. The semiconductor device according to claim 6, wherein in the switch circuit, connection of adjacent function reconfigurable cells and variable logic cells is determined by data written by the access control device via the interface control circuit.   The variable operation cell separately includes a first input terminal that receives an output from a corresponding memory circuit and a second input terminal that receives an output of another variable logic cell as input terminals for operation target data. 5. The semiconductor device according to 5. An arithmetic circuit that receives the output data of the operation result of the plurality of variable operation cells in parallel and performs an operation;
The arithmetic circuit includes a data register for holding a calculation result,
The semiconductor device according to claim 1, wherein the access control device is allowed to access the data register through the interface control circuit.   10. The semiconductor device according to claim 9, wherein a first memory mapped IO register address arranged in an address space of the access control device is assigned to the data register.   2. The semiconductor device according to claim 1, wherein in the first operation mode, the memory circuit included in the function reconfigurable memory device is arranged in an address space of the access control device and is assigned a memory address.   The semiconductor device according to claim 11, wherein in the second operation mode, each of the function reconfigurable memory devices is assigned a memory mapped IO register address arranged in an address space of the access control device. An access control device and a function reconfigurable memory device that is controlled by the access control device;
The function reconfigurable memory device is provided in a one-to-one correspondence with an interface control circuit that receives an access request from the access control device, a plurality of function reconfigurable cells connected to the interface control circuit, and the function reconfigurable cell. A variable operation cell that performs an operation by receiving an output from the function reconfigurable cell, a transmission circuit for enabling the output of the variable operation cell to be supplied to another variable operation cell or another function reconfigurable cell, An arithmetic circuit that receives the output data of the operation results from a plurality of variable operation cells in parallel and performs an operation;
The function reconfigurable cell has a memory circuit and a control circuit;
The storage circuit has a data field and a control field that are accessed based on address information output from the control circuit,
The control circuit randomly accesses the storage circuit based on address information given to the interface control circuit in response to an access request from the access control device in the first operation mode, and first in the second operation mode Autonomously controlling the next read address of the memory circuit based on the control field information or external event input read from the memory circuit;
The variable operation cell separately includes a first input terminal that receives an output from a corresponding storage circuit and an input terminal that receives an output of another variable logic cell as input terminals for operation target data,
A semiconductor device in which a transmission path is set based on data given from the interface control circuit.   The semiconductor device according to claim 13, wherein a calculation operation of the variable calculation cell is controlled based on control data output from the control field of the storage circuit.   14. The semiconductor device according to claim 13, wherein an operation of the variable operation cell is controlled based on control data that is initially set in an operation control register by the access control device. The arithmetic circuit includes a data register for holding a calculation result,
The semiconductor device according to claim 13, wherein the access control device is allowed to access the data register through the interface control circuit.

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