JP2008226186A - Integrated circuit, test condition setting method therefor, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit, a test condition setting method therefor, and a program for easily testing a computing processing function embedded as a module. <P>SOLUTION: An ASIC 100 is provided with respective modules 25-27 for pattern generation, magnification, and edit, switching parts 21-24 for switching whether to input computing processing target data to each of the modules 25-27 or not, and a plurality of registers 14-20 setting processing conditions of the respective modules 25-27 and the selection parts 21-24. The ASIC 100, which can select whether to execute computing processing or not for each module, is provided with a storage part 283 storing test conditions in operating tests using at least one of the respective modules 25-27 for pattern generation, magnification, and edit, and a register setting part 28 setting register values meeting the test conditions to the respective registers 14-20 according to an instruction from an external device. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an integrated circuit, and more particularly to an integrated circuit having a plurality of arithmetic processing modules, a test condition setting method thereof, and a program.

  2. Description of the Related Art Conventionally, an integrated circuit in which specific arithmetic processing is incorporated in a modular form is called an ASIC and is applied to various electronic devices.

  For example, an integrated circuit in which image processing such as pattern generation, scaling, rotation, and editing is modularized and incorporated is used in the image processing apparatus.

  Such an integrated circuit needs to be tested to confirm that it operates normally.

FIG. 6 shows a configuration of a conventional ASIC 200.
The ASIC 200 includes an input terminal 1, a register I / F 2, a register group 3, switching units 4 to 7, a pattern generation module 8, a scaling module 9, an editing module 10, and an output terminal 0.
The input terminal 1 is a terminal to which image data is input from a device (not shown) connected to the previous stage (CPU or the like). The register I / F 2 is an I / F that receives a control signal from a device (not shown) connected to the preceding stage. The register group 3 stores commands for controlling the switching units 4 to 7 and the modules 8 to 10. The switching units 4 to 7 switch data lines of image data. The pattern generation module 8 performs processing for generating an arbitrary image pattern. The scaling module 9 performs processing for converting the magnification of the image. The editing module 10 performs processing such as image trimming and expansion. The output terminal 0 is a terminal for outputting image data to a device (not shown) connected to the subsequent stage.

  In the normal operation, a control signal is input from the preceding device via the register I / F2, and the values of the registers 31 to 37 are set accordingly. For example, the switching unit 4 is set to D1-D2, the switching unit 5 is set to D3-D4, the switching unit 6 is set to D5-D6, and the switching unit 7 is set to D7-D8. Then, each process of editing is performed and output from the output terminal 0.

  At the time of the test operation, a control signal is input from the preceding device via the register I / F 2, and settings dedicated to the test different from the normal operation are made to the registers 31 to 37. For example, when only the scaling module 9 is tested, the data line is set with the switching unit 4 as D1-T1, the switching unit 5 as T1-D4, the switching unit 6 as D5-T2, and the switching unit 7 as T3-D8. Set processing conditions (enlargement / reduction, vertical magnification, horizontal magnification, etc.) in the scaling module. When image data is input via the input terminal 1 after setting the switching units 4 to 7 and the processing conditions in the scaling module 9 in the registers 32 and 34 to 37, the scaling module 9 operates under the set processing conditions. The image data that has been subjected to the scaling process is output from the output terminal 0.

As described above, by setting test conditions (processing conditions in the data line and each module) to the register group 3 via the register I / F 2, it is possible to test any module.
JP-A-10-105535

  However, since various types of functional modules are incorporated in recent ASICs, a large number of values must be set as test conditions in the register. If there is an error in the value set in the register as a test condition (for example, if the scan start position is set after the scan end position in the image processing ASIC), a correct test result cannot be obtained, and the ASIC There was a problem that the module of could not be evaluated correctly.

  Patent Document 1 discloses a data processing apparatus provided with a circuit that automatically generates an address of a register in a selected functional module. Whether the register is set directly or indirectly. This means that the module cannot be evaluated correctly unless the settings that match the test conditions are set correctly.

  The present invention has been made in view of such problems, and an object of the present invention is to provide an integrated circuit, a test condition setting method, and a program for easily testing an arithmetic processing function incorporated as a module.

  In order to achieve the above object, as a first aspect, the present invention provides a plurality of arithmetic processing modules, switching means for switching whether or not to input arithmetic processing target data to each arithmetic processing module, and each arithmetic processing An integrated circuit comprising a plurality of registers for setting processing conditions of the module and the switching means, and capable of selecting whether or not to execute arithmetic processing for each arithmetic processing module, using at least one of the arithmetic processing modules An integrated circuit comprising test condition storage means for storing test conditions for performing a test, and register setting means for setting register values corresponding to the test conditions in each register in accordance with an instruction from an external device A circuit is provided.

  In the first aspect of the present invention, the arithmetic processing module preferably performs image processing on the data to be arithmetic processed. Moreover, it is preferable that at least one of the arithmetic processing modules has a function of generating data to be arithmetic processed. The register setting means preferably detects bit information of each register and sets a register value in each register based on the bit information based on a test condition. Further, it is preferable that the register setting means obtains an arithmetic processing module used for a test and the number of tests as instructions from an external device.

  In order to achieve the above object, as a second aspect, the present invention provides a plurality of arithmetic processing modules, switching means for switching whether or not to input arithmetic processing target data to each arithmetic processing module, Each arithmetic processing module includes a plurality of registers for setting processing conditions for the arithmetic processing module and the switching means, and test condition storage means for storing test conditions for performing a test using at least one of the arithmetic processing modules. Whether or not to perform the arithmetic processing is provided, and has a register setting means for setting a register value corresponding to the test condition in each register according to an instruction from an external device. A condition setting method, which is a register value corresponding to a test condition stored in a test condition storage unit according to an instruction from an external device. There is provided a test condition setting method for an integrated circuit, characterized in that set in the registers.

  In order to achieve the above object, as a third aspect, the present invention provides a plurality of arithmetic processing modules, switching means for switching whether or not to input arithmetic processing target data to each arithmetic processing module, Each arithmetic processing module includes a plurality of registers for setting processing conditions for the arithmetic processing module and the switching means, and test condition storage means for storing test conditions for performing a test using at least one of the arithmetic processing modules. Whether or not to perform the arithmetic processing is provided, and has a register setting means for setting a register value corresponding to the test condition in each register according to an instruction from an external device. A test condition setting program for causing a computer to set conditions, in which the computer performs a test in response to an instruction from an external device. The register values corresponding to the test conditions stored in the condition storage means is to provide a test condition setting program of the integrated circuit, characterized in that set in the registers.

  ADVANTAGE OF THE INVENTION According to this invention, the integrated circuit which can test easily the arithmetic processing function incorporated as a module, its test condition setting method, and a program can be provided.

  An integrated circuit according to a preferred embodiment of the present invention will be described. FIG. 1 shows the configuration of the ASIC according to this embodiment. The ASIC 100 includes an input terminal 11, a register I / F 12, a UI 13, registers 14 to 20, switching units 21 to 24, a pattern generation module 25, a scaling module 26, an editing module 27, a register setting unit 28, and an output terminal 29. Each unit other than the UI 13 and the register setting unit 28 is the same as the conventional ASIC.

  At the time of normal operation, a control signal is input via the register I / F 12 from the preceding device (CPU or the like) as in the conventional ASIC, and the values of the registers 14 to 20 are set accordingly. The registers 14 to 20 control the switching units 21 to 24 and the modules 25 to 27 according to the set values, and specify the data line and the processing conditions in each module. Image data input from the preceding apparatus via the input terminal 11 is processed in each module on the set data line, and then output from the external terminal 29.

  During the test operation, test conditions such as which test is performed how many times are input to the register setting unit 28 via the UI 13 as a control signal. The input content is stored in the counting unit 281 and the instruction unit 282. It is possible to set not only to repeat the test under the same condition but also to perform the test under a plurality of conditions. For example, a setting such as “one time each for condition A, condition B, and condition C” is also possible.

  The setting contents (register values) relating to the test to be executed are read from the storage unit 283 and output from the register setting unit 28 to the registers 14 to 20.

  An example of register setting values corresponding to each module is shown in FIG. Each register set value is a combination of parameters of predetermined bits. For example, the setting relating to the scaling module 26 is “main scanning scaling mode (shrinking / enlarging)” indicating whether to reduce or enlarge in the main scanning direction, and “sub scanning” indicating whether to reduce or enlarge in the sub scanning direction. This is performed by combining each of the following parameters: “magnification mode (reduction / enlargement)”, “main scanning magnification” indicating the magnification in the main scanning direction, and “sub scanning magnification” indicating the magnification in the sub scanning direction. These values are predetermined values according to the type of test.

FIG. 3 shows the flow of the test operation.
The register setting unit 28 recognizes the test target module and the number of tests based on the control signal input via the UI 13 (step S1). The test target module and the number of tests are stored in the instruction unit 282 and the counting unit 281, respectively.

  Image data is input from the preceding apparatus via an input terminal. The type of image to be input is arbitrary. For example, random data or increment data can be used.

  The register setting unit 28 determines register correspondence (step S3). First, the register setting unit 28 acquires bit information from the modules 25 to 27 recognized as test targets (step S31). Then, the register setting unit 28 acquires setting information corresponding to the acquired bit information using the table stored in the storage unit 283 (step S32). Based on the setting information acquired from the storage unit 283, the register setting unit 28 selects a method for setting a value in the register to be tested (step S33).

  After selecting the register setting method, the register setting unit 28 sets the values of the registers 14 to 16 based on the selected setting information, and determines the processing conditions (step S4).

  The register setting unit sets the values of the registers 17 to 20 and designates the data line (step S5). FIG. 4 shows an example of the data line. The data lines are indicated by bold lines in the figure. Here, the switching unit 21 is D1-D2, the switching unit 22 is D3-T2, the switching unit 23 is T2-D6, and the switching unit 24 is D7-D8, so that the pattern generation module 25 and the editing module 27 are It is set as a module to be tested.

When a data line is designated, a test operation is executed, and the register setting unit 28 counts up each time one test is completed. When the count value reaches the value stored in the counting unit 281, the test is completed (step S 6 / Yes, S 7).
If the value stored in the counting unit 281 has not been reached (No in step S6), the register setting and the data line setting are performed again to execute the test operation, and the count value is changed to the value stored in the counting unit 281. Repeat until it reaches.

  As shown in FIG. 5, when the ASIC 100 includes a module (in this example, the pattern generation module 25) having a function for generating data that can be used for testing, the data generated in the module is used. It is also possible to test the ASIC 100. In the figure, the data lines in this case are indicated by bold lines.

  Thus, the integrated circuit according to the present embodiment does not require the user to manually set the test conditions for the register. Thereby, it is possible to prevent a test condition setting failure caused by a human error.

In addition, the said embodiment is an example of suitable implementation of this invention, and this invention is not limited to this.
For example, in the above embodiment, the register setting unit 28 obtains bit information from the registers 14 to 20 every time a test operation is performed, but the bit information may be stored in the storage unit. If the bit information is stored in the storage unit, the number of processes during test execution can be reduced, so that the processing can be performed at a high speed and the circuit configuration can be simplified. However, if the bit information is acquired from the registers 14 to 20, the capacity of the storage unit 283 can be reduced. Therefore, priority is given to reducing the size of the storage unit 283 or to speeding up the processing and simplifying the circuit. It is preferable to determine which configuration is selected according to the above.
In the above embodiment, the ASIC for image processing has been described as an example. However, it is needless to say that the present invention is applicable not only to image processing but also to any arithmetic processing integrated circuit.
As described above, the present invention can be variously modified.

It is a figure which shows the structure of ASIC which concerns on suitable embodiment of this invention. It is a figure which shows an example of the setting value of the register | resistor corresponding to each module. It is a figure which shows the flow of the test operation | movement in ASIC which concerns on suitable embodiment of this invention. It is a figure which shows an example of a data line. It is a figure which shows the data line in the case of producing | generating the data used for a test in the module in ASIC. It is a figure which shows the structure of the conventional ASIC.

Explanation of symbols

11 Input terminal 12 Register I / F
13 UI
14, 15, 16, 17, 18, 19, 20 Register 21, 22, 23, 24 Switching unit 25 Pattern generating module 26 Scaling module 27 Editing module 28 Register setting unit 29 Output terminal 100 ASIC

Claims (7)

A plurality of arithmetic processing modules, a switching means for switching whether or not each arithmetic processing module inputs data to be processed, and a plurality of registers for setting processing conditions of the arithmetic processing modules and the switching means. An integrated circuit capable of selecting whether or not to execute arithmetic processing for each arithmetic processing module,
A test condition storage means for storing a test condition when performing a test using at least one of the arithmetic processing modules is set, and a register value corresponding to the test condition is set in each register according to an instruction from an external device An integrated circuit comprising register setting means.   The integrated circuit characterized in that the arithmetic processing module performs image processing on the data to be arithmetic processed.   The integrated circuit according to claim 1, wherein at least one of the arithmetic processing modules has a function of generating data to be arithmetically processed.   The register setting means detects bit information of each register, and sets a register value in each register based on the bit information based on the test condition. The integrated circuit according to claim 1.   5. The integrated circuit according to claim 1, wherein the register setting unit acquires an arithmetic processing module used for a test and the number of tests as the instruction from the external device. 6. A plurality of arithmetic processing modules, a switching means for switching whether or not each arithmetic processing module inputs data to be processed, a plurality of registers for setting processing conditions for the arithmetic processing modules and the switching means, A test condition storage unit that stores test conditions when performing a test using at least one of the arithmetic processing modules, and can select whether to perform arithmetic processing for each arithmetic processing module; A test condition setting method for an integrated circuit comprising register setting means for setting a register value corresponding to a test condition in each register according to an instruction from an external device,
A test condition setting method for an integrated circuit, wherein a register value corresponding to a test condition stored in the test condition storage means is set in each register according to an instruction from the external device. A plurality of arithmetic processing modules, a switching means for switching whether or not each arithmetic processing module inputs data to be processed, a plurality of registers for setting processing conditions for the arithmetic processing modules and the switching means, A test condition storage unit that stores test conditions when performing a test using at least one of the arithmetic processing modules, and can select whether to perform arithmetic processing for each arithmetic processing module; A test condition setting program for causing a computer to set a test condition for an integrated circuit, comprising register setting means for setting a register value corresponding to a test condition in each register according to an instruction from an external device,
In accordance with an instruction from the external device, the computer sets a register value corresponding to the test condition stored in the test condition storage means in each register.

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