JP2017151955A - Systems and methods for sending data from non-volatile solid state devices before error correction - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide systems and methods for sending data from non-volatile solid state devices before error correction.SOLUTION: A memory controller is configured to retrieve data packets 202 from memory and send each retrieved data packet to a host, as each data packet is retrieved. The memory controller is configured to retrieve an error correcting code (ECC) packet 204 corresponding to the retrieved data packets and execute an ECC algorithm 206 to identify and correct potential errors 218 in the retrieved plurality of data packets. The memory controller is configured to send any corrected data packets to the host if any of the retrieved data packets had errors, and send a completion packet 208 to the host.SELECTED DRAWING: Figure 2C

Description

  The present disclosure relates to a system and method for transmitting data stored in a non-volatile solid state device, and in particular for transmitting data prior to completion of error correction.

  Non-volatile solid state devices (SSDs) are widely used for primary and secondary storage in computer systems. The bit error rate of some non-volatile memories, such as phase change memory (PCM), resistive RAM (ReRAM), and magnetic RAM (MRAM), may be higher than that of dynamic read access memory (DRAM) However, the bit error rate of the NAND flash memory can be significantly reduced. These intermediate bit error rates therefore require better error correction than the short Hamming codes used in DRAM. For this reason, when executing an error correction algorithm, a long waiting time may occur. For example, when executing error correction codes (ECC) such as all BCH codes (acronyms of code inventor, Raj Bose, DK Ray-Chaudhuri, and Alexis Hocquechem) for 512B blocks, for example. It may take about half the time to read bits from the medium.

  Furthermore, the probability of error in an arbitrary block of, for example, 4 kb may be sufficiently low so that no error occurs in most blocks. Therefore, the waiting time due to the error correction algorithm is wasted in most reading. Also, conventional systems perform a non-pipelined flow, and typically read all bits from the storage medium to reconstruct a single 512B block, then run the ECC algorithm, and the ECC algorithm Once complete, transmission of data to the host can begin. Thus, block transmission is delayed until the ECC algorithm is complete.

US patent application Ser. No. 14 / 466,538 US patent application Ser. No. 14 / 489,881

  The present disclosure relates to a method and system for performing operations according to a communication protocol.

  One embodiment may include a method for performing operations on a communication protocol. The method includes providing a target device in communication with the host and the memory, and receiving by the target device a first command including a request to obtain a plurality of data packets from the memory. Good. The method also includes obtaining a plurality of data packets from the memory by the target device and transmitting each obtained data packet to the host each time each data packet is obtained by the target device. May contain. The method further includes the step of obtaining an error correction code (ECC) packet corresponding to the obtained plurality of data packets by the target device, and executing the ECC algorithm by the target device to obtain the obtained plurality of data packets. Identifying and correcting any potential errors. The method also includes the steps of: sending a corrected data packet to the host by the target device if any of the acquired data packets are in error; and sending a completion packet to the host by the target device. May contain.

  An alternative embodiment may include a method for performing operations on a communication protocol. The method includes providing a target device in communication with the host and the memory, and receiving by the target device a first command including a request to obtain a plurality of data packets from the memory. Good. The method also includes the step of acquiring a plurality of data packets from the memory by the target device and each acquired data excluding the last acquired data packet each time each data packet is acquired by the target device. Sending the packet to the host. The method also includes obtaining an error correction code (ECC) packet corresponding to the obtained plurality of data packets by the target device, and executing an ECC algorithm by the target device to obtain the obtained plurality of data packets. Identifying and correcting any potential errors. The method further includes the step of transmitting the corrected data packet to the host by the target device if any of the acquired data packets are in error, and transmitting the last acquired data packet by the target device. Steps may be included.

  An alternative embodiment may include a memory controller that performs operations with a communication protocol. The memory controller includes an interface controller configured to receive a first command from the host that is in communication with the host and the memory and includes a request to obtain a plurality of data packets from the memory, and a storage controller. Good. The storage controller acquires a plurality of data packets from the memory, and each time each data packet is acquired, the storage controller sends each acquired data packet to the host except for the last acquired data packet. It may be configured to command. The storage controller further acquires an error correction coding (ECC) packet corresponding to the acquired plurality of data packets and executes an ECC algorithm to identify and correct potential errors in the acquired plurality of data packets. It may be configured as desired. The storage controller further directs the interface controller to send the corrected data packet to the host if any of the acquired data packets are in error, and sends the last acquired data packet to the interface controller. May be configured to command.

  An alternative embodiment may include a memory controller that performs operations with a communication protocol. The memory controller includes an interface controller configured to receive a first command from the host that is in communication with the host and the memory and includes a request to obtain a plurality of data packets from the memory, and a storage controller. Good. The storage controller acquires a plurality of data packets from the memory and executes an error detection algorithm for each acquired data packet to determine whether the acquired data packet contains an error. It may be configured. The storage controller further instructs the interface controller to send each acquired data packet to the host, except for the last acquired data packet, for each acquired data packet. An error correction code packet corresponding to the data packet may be obtained and an ECC algorithm may be executed to identify and correct potential errors in the obtained plurality of data packets. The storage controller further directs the interface controller to send the corrected data packet to the host if any of the acquired data packets are in error, and sends the last acquired data packet to the interface controller. May be configured to command.

  Various objects, features and advantages of the present disclosure will be better understood by reviewing the following detailed description with reference to the accompanying drawings, in which like elements are given like reference numerals. The accompanying drawings are for illustrative purposes only and do not in any way limit the invention as defined by the claims.

2 illustrates an exemplary system for executing a communication protocol according to embodiments of the present disclosure. An example of a conventional method for transmitting data from a storage medium will be described. 6 illustrates an example of transmitting data from a storage medium according to aspects of the present disclosure. 6 illustrates an example of transmitting data from a storage medium according to aspects of the present disclosure. An example of a conventional method for transmitting data from a storage medium will be described. 6 illustrates an example of transmitting data from a storage medium according to aspects of the present disclosure. 6 illustrates an example of transmitting data from a storage medium according to aspects of the present disclosure. 6 illustrates an exemplary method for transmitting data from a storage medium according to aspects of the present disclosure. 6 illustrates an exemplary method for transmitting data from a storage medium according to aspects of the present disclosure.

  Systems and methods for transmitting data stored in non-volatile memory are provided. If the data packet is obtained from non-volatile memory before performing error correction, it can be sent to the host. If all the data packets in one block are obtained from the non-volatile memory, error correction can be performed. If any of the acquired data packets are in error, it can be corrected and retransmitted to the host.

  FIG. 1 illustrates an example system 100 that implements a communication protocol in accordance with embodiments of the present disclosure. The system 100 includes a host 102 that is in communication with a target device 104 and a storage 122. The host 102 includes a user application 106, an operating system 108, a driver 110, a host memory 112, a queue 118a, and a communication protocol 114a. Target device 104 includes interface controller 117, communication protocol 114 b, queue 118 b, and storage controller 120 in communication with storage 122.

  Host 102 may execute user level application 106 on operating system 108. The operating system 108 can run a driver 110 that provides an interface with the host memory 112. In some embodiments, the memory 112 may be a DRAM. The host memory 112 can store a command from the host 102 that instructs the target device 104 to perform processing using the queue 118a. Examples of commands added to the store or queue may include read or write operations from the host 102. The communication protocol 114 a allows the host 102 to communicate with the target device 104 using the interface controller 117.

  The target device 104 can communicate with the host 102 using the interface controller 117 and the communication protocol 114b. The communication protocol 114 b can provide a queue 118 for accessing the storage 122 via the storage controller 120. For example, the user level application 106 can generate an access request to the storage 122 for data acquisition. The target device 104 can execute an error correction code that corrects an error when a memory block is obtained from the storage 122.

  As described above, in order to execute an error correction code such as all BCH codes in, for example, a 512B block, about half of the time for reading data from the storage 122 may be consumed. Conventional systems, such as systems that perform non-pipelined flows, typically read all bits from the storage medium to reconstruct a block, then run the ECC algorithm and are corrected after the ECC algorithm is complete You can start sending data to the host. This is indicated generally at 200 in FIG. 2A and illustrates an exemplary method of transmitting packets, eg, four packets 202, from a storage medium to a host. In a particular example, the system first reads packet 202 and ECC packet 204 and then executes error correction algorithm 206 to determine if any packet is in error and if an error is detected. Correct it. The system can then send an end packet 208 to the host notifying that 4 blocks and the transfer is complete. One skilled in the art will appreciate that ECC bits can be multiple packets depending on how the bits are placed on the medium due to the design of the correction scheme.

  According to aspects of the present disclosure, a data packet is transmitted from the storage medium to the host prior to executing the error correction algorithm. This is generally indicated at 210 in FIG. 2B. The disclosed system and method first obtains the packet 202. Each packet is transmitted to the host as it is acquired from the storage medium. For example, when the first packet is acquired, it is transmitted to the host (212). Similarly, when the second packet is acquired, it is transmitted to the host (214). This operation is continued until all the packets 202 are acquired from the storage medium. After all the packets are acquired, the ECC packet 204 is read and the error correction algorithm 206 is executed. If the algorithm does not detect any errors, an end packet 208 is transmitted to notify the host that the transfer is complete. As shown in FIG. 2B, the disclosed method can save a significant amount of latency (216) in the most common case where the data packet obtained from the storage device is error free. For example, latency savings are approximately equal to the time required to send all data packets to the host.

  The disclosed system and method can save latency even if the data obtained from the storage medium contains errors. In general, 220 in FIG. 2C illustrates the latency savings in transmitting a data packet to the host if the acquired data packet is in error. Specifically, in the example shown in the figure, the second data packet 218 includes an error. Since the disclosed method does not wait for the error detection and correction algorithm to complete before the packet is sent to the host, the packet 218 with the error is received at the host. If an error is detected (206), the erroneous data packet 218 is corrected and the correct data packet 220 is retransmitted to the host. When a plurality of packets with errors are acquired from the storage medium, all packets with errors are corrected and transmitted to the host. Next, an end packet 208 is transmitted to notify the host that the transfer has been completed. As also shown in FIG. 2C, the disclosed method significantly increases the latency even if there is an error in the data packet acquired from the storage device, for example, if there is one error in the acquired data (224). Can save.

  FIG. 3A shows an alternative embodiment of the non-pipelined flow of a conventional system. In particular, generally 300 of FIG. 3A illustrates another exemplary way of sending a packet, eg, four packets 302, from a storage medium to a host without sending separate completion packets. In a particular example, the system first obtains packet 302 and ECC packet 304 and then executes error correction algorithm 306 to determine if any packet is in error and an error is detected. If so, correct it. The system can then send 4 blocks to the host. The last packet 308 can also function as a completion packet that can notify the host that the transfer is complete. Exemplary protocols that can remove completion signals in preference to other completion detection procedures are described in, for example, “Ack-less protocol for notifying completion of read requests” filed Aug. 22, 2014 and 2014. It is described in (Patent Document 2) “Acknowledgment-less protocol for solid state drive interface” filed on Sep. 18, the entire contents of which are cited in this specification.

  According to alternative aspects of the present disclosure, the data packet 302 from the storage medium can be transmitted to the host prior to executing the error correction algorithm without transmitting a completion packet. This is generally indicated at 310 in FIG. 3B. The disclosed system and method first obtains the packet 302. As each packet is acquired from the storage medium, it is sent to the host. For example, when the first packet 312 is acquired, it is transmitted to the host. Similarly, when the second packet 314 is acquired, it is transmitted to the host. According to aspects of the disclosure, the last packet 308 is not sent to the host until an error detection and correction algorithm is performed. Specifically, after the ECC packet 304 is acquired from the storage medium, the ECC algorithm is executed (306). If no error is detected, the last packet 308 is sent to the host. When the last packet 308 is received on the host side, the host can be notified that the transfer has been completed. As shown in FIG. 3B, the disclosed method can save a significant amount of latency (316) in the most general case where there is no error in the data packet obtained from the storage device.

  220 of FIG. 3C generally illustrates latency savings in transmitting a data packet to the host when the data packet is in error and there is no completion packet. Specifically, in the example shown in the figure, the second data packet 314 includes an error. Since the disclosed method does not wait for the error detection and correction algorithm to complete before the packet is sent to the host, the second packet 314 in error is received at the host side. According to aspects of this disclosure, the last packet 308 is not transmitted until an error detection and correction algorithm is performed. If an error is detected in the second packet 314, the erroneous data packet 314 is corrected (306) and the correct data packet is retransmitted to the host (316). After the correction packet 316 is sent, the method can send the last data packet 308. When the last packet 308 is received on the host side, the host can be notified that the transfer has been completed. One skilled in the art will appreciate that if the last data packet obtained is in error, the corrected data packet is sent to the host. As shown in FIG. 3C, the disclosed method significantly saves latency even if there is an error in the data packet acquired from the storage device, eg, one error in the acquired data (324). it can.

  According to alternative aspects of the present disclosure, after an error is detected, only a subset of the packets that were acquired in error, eg, only the subset that contains the error, are retransmitted to the host. If a subset is received at the host side, the appropriate part of the packet can be overwritten.

  According to alternative aspects of the disclosure, when a data packet is obtained from a storage medium, an error detection algorithm, such as symptom confirmation (calculation of a polynomial that returns a value indicating the number of bits with errors), is performed, It is determined whether there is an error in the acquired data packet. If there is no error in all the acquired packets, the ECC algorithm is not executed any more.

  FIG. 4 shows a flow diagram 400 of an exemplary method for transmitting a data packet to a host in accordance with aspects of the present disclosure. A memory controller can obtain a plurality of data packets from memory (402). When the memory controller acquires the data packet, it transmits it to the host (404). The memory controller may also obtain an ECC packet corresponding to the obtained data packet (406). Once the ECC packet is acquired, the memory controller can execute an ECC algorithm to identify and correct potential errors in the acquired data packet (408). The method may then check whether the acquired data packet is in error (410). If no error is detected, the memory controller can send a completion packet to the host (412). If there is an error in the acquired data, the memory controller can send a corrected data packet to the host (414) and then send a completion packet (412).

  FIG. 5 shows a flow diagram 500 of an exemplary method for sending a data packet to a host in accordance with alternative aspects of the present disclosure. The memory controller can obtain a plurality of data packets from the memory (502). When the memory controller acquires the data packet, each packet can be transmitted to the host except for the data packet acquired last (504). The memory controller can also obtain an ECC packet corresponding to the obtained data packet (506). Once the ECC packet is acquired, the memory controller can execute an ECC algorithm to identify and correct potential errors in the acquired data packet 508. The method can then check whether the acquired data packet 510 is in error. If no error is detected, the memory controller can send the last acquired packet to the host 512. If there is an error in the acquired data, the memory controller can send a corrected data packet 514 and then the last acquired packet 512 to the host.

  Those skilled in the art will appreciate that the various exemplary items in the specification text and drawings described herein can be implemented by electronic hardware, computer software, or a combination of both. To illustrate that hardware and software are interchangeable, various illustrative blocks, modules, elements, elements, methods, and algorithms have been described generically in terms of their functionality. Whether such functionality is implemented as hardware, software, or a combination thereof depends on the particular application and design constraints imposed on the overall system. Those skilled in the art can implement the described functions in various ways for each particular application. The various elements and blocks can all be configured differently (eg, arranged in a different order or divided differently) without departing from the scope of the subject technology.

  Furthermore, the execution of the communication protocol can be realized centrally in a single computer system or distributedly with different elements arranged across a plurality of computer systems connected to each other. Any type of computer system or other apparatus adapted to perform the methods described herein is suitable for performing the functions described herein.

  A typical combination of hardware and software can be a general purpose computer system with a computer program that, when loaded and executed, controls the computer system to perform the methods described herein. A method for a communication protocol may also be embedded in a computer program product that includes all features that enable the method described herein to be performed and that can execute the method when loaded into a computer system. .

  A computer program or application in this context means that a system having an information processing function directly executes a specific function, or a) conversion into another language, code, or notation, b) in a different media format Means any language, code or notation of a set of instructions intended to be executed after one or both of the reproductions have been executed. Importantly, the communication protocol can be implemented in other specific forms without departing from its spirit or basic attributes, and thus is not intended to illustrate the scope of the present Reference is made to the following claims.

  The communication protocol has been described in detail with specific reference to exemplary embodiments. However, it is obvious that various modifications and changes can be made within the spirit and scope of the present disclosure as described in the above-described specification text, and such modifications and changes are equivalent. It should be considered part of this disclosure.

100 system 102 host 104 target device 106 application 108 operating system 110 driver 112 memory 114a communication protocol 114b communication protocol 117 interface controller 118a queue 118b queue 120 storage controller 122 storage 202 packet 204 ECC packet 206 error correction algorithm 208 end packet 212 host Send to 214 Send to host 216 Latency savings in most common cases 220 Retransmission 224 Latency savings in case of one error 302 packets 304 ECC packets 306 corrections 308 packets 312, 314 packets 316 Most common Time savings in typical cases 324 Waiting in case of one error Saving of time

Claims (20)

A method for performing an operation in a communication protocol,
Providing a target device in communication with the host and memory;
Receiving, from the host, a first command including a request to obtain the plurality of data packets from the memory by the target device;
Obtaining the plurality of data packets from the memory by the target device;
Each time each data packet is acquired by the target device, sending each acquired data packet to the host;
Obtaining, by the target device, an error correction code (ECC) packet corresponding to the obtained plurality of data packets;
Executing, by the target device, an ECC algorithm to identify and correct potential errors in the obtained plurality of data packets;
If any of the acquired data packets are in error, the target device sends a corrected data packet to the host;
Sending by the target device a completion packet to the host.   The method of claim 1, wherein the memory is a non-volatile memory.   The method of claim 2, wherein the non-volatile memory is phase change memory (PCM).   The method of claim 1, wherein the ECC algorithm performs a BCH code. A method for performing an operation in a communication protocol,
Providing a target device in communication with the host and memory;
Receiving from the host a first command including a request to obtain a plurality of data packets from the memory by the target device;
Obtaining the plurality of data packets from the memory by the target device;
Each time each data packet is acquired by the target device, sending each acquired data packet to the host except for the last acquired data packet;
Obtaining, by the target device, an error correction code (ECC) packet corresponding to the obtained plurality of data packets;
Executing, by the target device, an ECC algorithm to identify and correct potential errors in the obtained plurality of data packets;
If any of the acquired data packets are in error, the target device sends a corrected data packet to the host;
Transmitting the last acquired data packet by the target device.   The method of claim 5, wherein the memory is a non-volatile memory.   The method of claim 6, wherein the non-volatile memory is a phase change memory (PCM).   The method of claim 5, wherein the ECC algorithm implements a BCH code. A method for performing an operation in a communication protocol,
Providing a target device in communication with the host and memory;
Receiving, from the host, a first command including a request to obtain the plurality of data packets from the memory by the target device;
Obtaining the plurality of data packets from the memory by the target device;
Performing an error detection algorithm on each acquired data packet to determine whether the acquired data packet contains an error; and
Each time each data packet is acquired by the target device, sending each acquired data packet to the host;
Obtaining, by the target device, an error correction code (ECC) packet corresponding to the obtained plurality of data packets;
If any of the acquired data packets are in error, the target device executes an ECC algorithm to correct potential errors in the acquired plurality of data packets;
If any of the acquired data packets are in error, the target device sends a corrected data packet to the host;
Sending by the target device a completion packet to the host.   The method of claim 9, wherein the memory is a non-volatile memory. An interface controller configured to receive a first command from the host that is in communication with the host and the memory and includes a request to obtain a plurality of data packets from the memory;
A memory controller including a storage controller,
The storage controller is
Obtaining the plurality of data packets from the memory;
Instructing the interface controller to send each acquired data packet to the host each time each data packet is acquired,
Obtaining an error correction coding (ECC) packet corresponding to the obtained plurality of data packets;
Performing an ECC algorithm to identify and correct potential errors in the obtained plurality of data packets;
If any of the acquired data packets are in error, instruct the interface controller to send a corrected data packet to the host;
A memory controller configured to instruct the interface controller to send a completion packet to the host.   The memory controller of claim 11, wherein the memory is a non-volatile memory.   The memory controller of claim 12, wherein the non-volatile memory is a phase change memory (PCM).   The memory controller of claim 11, wherein the ECC algorithm implements a BCH code. A memory controller that is in communication with a host and a memory and includes a storage controller and an interface controller configured to receive from the host a first command including a request to obtain a plurality of data packets from the memory. The storage controller
Obtaining a plurality of data packets from the memory;
Each time each data packet is acquired, the interface controller is instructed to send each acquired data packet to the host except the last acquired data packet,
Obtaining an error correction coding (ECC) packet corresponding to the obtained plurality of data packets;
Performing an ECC algorithm to identify and correct potential errors in the obtained plurality of data packets;
If any of the acquired data packets are in error, instruct the interface controller to send the corrected data packet to the host;
A memory controller configured to instruct the interface controller to transmit the last acquired data packet.   The memory controller of claim 15, wherein the memory is a non-volatile memory.   The memory controller of claim 16, wherein the non-volatile memory is a phase change memory (PCM).   The memory controller of claim 15, wherein the ECC algorithm implements a BCH code. A memory controller that is in communication with a host and a memory and includes a storage controller and an interface controller configured to receive from the host a first command including a request to obtain a plurality of data packets from the memory. And
The storage controller is
Obtaining the plurality of data packets from the memory;
Performing an error detection algorithm on each acquired data packet to determine whether the acquired data packet contains an error;
Instructing the interface controller to send each acquired data packet to the host, except for the last acquired data packet, as each data packet is acquired,
Obtaining an error correction code (ECC) packet corresponding to the obtained plurality of data packets;
Performing an ECC algorithm to identify and correct potential errors in the obtained plurality of data packets;
If any of the acquired data packets are in error, instruct the interface controller to send the corrected data packet to the host;
A memory controller configured to instruct the interface controller to transmit the last acquired data packet.   The memory controller of claim 19, wherein the memory is a non-volatile memory.

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