JP2009187405A - Control system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control system which improves throughput and performs flexible error recovery processing. <P>SOLUTION: A target device 4 outputs an error identification code showing a cause of an error to a master device 3 when the error occurs during data transfer. Contents of error recovery processing to be executed upon the occurrence of an error are previously set on the basis of the error identification code, and the master device 3 executes the previously set error recovery processing when an error occurs. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a control system in which a master device that controls data transfer and a target device that receives an access request from the master device and performs processing are connected via a system bus.

  Generally, in a control system in which a master device and a target device are connected via a system bus, when data is transferred from one target device to another target device, the master device controls the data transfer.

  First, the master device issues a read command to the target device that is the data transfer source. The transfer source target device that has received the read command prepares read data at the designated address and returns it to the master device. The master device writes the data by issuing a write command to the transfer destination target device. Thereby, data transfer between target devices can be performed.

  Here, if the read data cannot be prepared within the specified response time after the external device connected to the transfer source target device receives the read command, the master device waits until the read data is prepared, or It is necessary to wait for the transfer source target device to output a timeout error.

  When the master device detects a time-out error, the master device outputs an interrupt to the host, and the host must check the cause of the error that causes the interrupt and perform recovery processing for the error.

  When an error occurs during data transfer in this way, the host takes time to handle the error, which causes a reduction in throughput of the entire system.

  When an error occurs in the transmission / reception processing of transfer data, the bus interface described in Patent Document 1 retries the processing as a countermeasure against transmission errors.

  When a timeout error occurs, the bus master retries up to the set number of times. When a CRC error occurs in the transfer data, the bus error interrupt BERR is asserted, and the retry is performed up to the set number of times. A method is disclosed in which the bus master itself performs error recovery processing.

JP 2003-196228 A

  However, in the bus interface described in Patent Document 1, the bus master can set the number of times to retry the error, but cannot perform error recovery processing according to the content of the error.

  An object of the present invention is to provide a control system capable of improving throughput and performing flexible error recovery processing.

The present invention provides a master device for controlling data transfer via a system bus;
In a control system connected to a target device that receives an access request from the master device and performs processing,
The target device is
A code output means for outputting an error identification code indicating the cause when an error occurs during data transfer to the master device;
The master device is
Setting means for presetting the contents of error recovery processing to be executed by the master device based on the error identification code when an error occurs;
And a recovery means for executing the error recovery process set by the setting means.

  In the invention, it is preferable that the master device has selection means for selecting whether or not the recovery means performs error recovery processing when an error occurs.

  In the present invention, when the data transfer method is isochronous transfer, the setting means is set so that no retry is performed as the error recovery processing when the cause of the error is a timeout or the data itself has an error. It is characterized by doing.

  According to the present invention, the error identification code output from the target device is assigned a signal line for outputting a code for each cause of the error.

  Further, the present invention is characterized in that the priority of access to the target device in which an error has occurred is lowered.

  According to the present invention, when an error occurs in the target device, the master device executes an error recovery process set in advance for each cause of the error, so that the recovery process is performed without notifying the host of an error interrupt. The throughput of the entire control system can be improved.

  Further, according to the present invention, since it is possible to select whether or not to perform error recovery processing, a flexible system can be constructed according to the application.

  Further, according to the present invention, when adopting an isochronous transfer method that requires real-time performance rather than data reliability, data transfer is performed by not performing a retry when a time-out error or data itself has an error. Can be continued.

  In addition, according to the present invention, since a signal line for outputting a code is assigned for each cause of error occurrence, the master device can be notified even when a plurality of errors occur simultaneously. Accordingly, error recovery processing can be performed without missing.

  Further, according to the present invention, by reducing the priority order of target devices that are not highly reliable, the bandwidth of highly reliable target devices can be improved and the throughput of the entire system can be improved.

  Also, by arbitrarily setting whether or not to notify the host when an error occurs, it is possible to freely select whether to notify the host or to allow the master device to perform automatic recovery processing according to the application.

  Further, the priority of the transfer order of the master device can be lowered by the occurrence of an error, and the system can be optimized.

FIG. 1 is a schematic diagram showing a configuration of a control system 1 according to an embodiment of the present invention.
The control system 1 includes a CPU 2, a master device 3, a target device 4 and a system bus 5, and the target device 4 is connected to an external device 6.

  In general, the control system 1 includes a plurality of target devices 4, and each target device individually connects to an external device 6 to control data transmission / reception with the external device 6.

  In the present embodiment, the target device 4 includes three target devices 4 (first target device 4a, second target device 4b, and third target device 4c), and each of the target devices 4a, 4b, and 4c includes a first external device 6a, Data transmission / reception is controlled by connecting to the second external device 6b and the third external device 6c.

  Here, the external device 6 is an external storage device such as a semiconductor memory or a hard disk drive, a communication device such as a USB interface or a LAN interface, or a display device such as a liquid crystal display. Is done.

  The master device 3 controls data transfer via the system bus 5 and receives data from the host CPU 2 or an external host to transfer data between the target devices 4. In general, this is called DMA (Direct Memory Access) transfer. The target device 4 performs various data transmission / reception processes with the external device 6 in response to an access request from the master device 3.

  An example of data transfer will be described. For example, when transferring data from the first target device 4a to the second target device 4b, the master device 3 first issues a read command to the first target device 4a. The first target device 4a issues a read command at the designated address to the first external device 6a. The first external device 6a places the data at the designated address on the data bus. The first target device 4a outputs the read data to the master device 3 after fetching the read data from the first external device 6a.

  Next, the master device 3 issues a write command to the second target device 4b, and outputs the read data output from the first target device 4a as write data. The second target device 4b outputs write data to the second external device 4b and issues a write command. This series of processing is repeated until a predetermined data size is transferred.

  When the data transfer for the set data size is completed, the master device 3 outputs an interrupt signal to the CPU 2 to notify the end of the data transfer process. In the data transfer, there is no problem if the transfer is normally performed, but there is a case where the response of the target device 4 is delayed for some reason or the data itself contains an error.

  For example, when a time-out error that does not respond within a certain time from the target device 4 occurs, the master device 3 outputs an interrupt to the CPU 2 to notify that an error has occurred, or to issue a read command again. , You need to do any processing.

  Further, when the data transfer method is a method that must guarantee a certain data transfer band like the isochronous transfer method, it indicates that a timeout error of the target device 4 or an error is included in the data itself. Even if a parity error occurs, it is necessary to continue data transfer. For this reason, the master device 3 needs to perform control to ignore the generated error.

  In addition, when there are a plurality of master devices 3 and a competitive operation is performed, the priority of each master device 3 is adjusted by an arbiter circuit (not shown). Normally, each master device 3 is made equal or the priority is changed according to the application. However, by lowering the priority of the target device 4 in which an error has occurred during data transfer, the influence of the system failure due to the error is eliminated. Can be.

FIG. 2 is a block diagram showing the configuration of the target device 4.
The command receiving unit 40 receives and analyzes a command from the master device 3 and transmits the command to the control unit 41. The control unit 41 issues a command according to the protocol of the bus interface with the external device 6. The timeout error detection unit 42, the parity error detection unit 43, and the address error detection unit 44 each detect whether an error has occurred during data transfer.

  In this embodiment, it is possible to detect the occurrence of three errors: a timeout error, a parity error, and an address error. When an error is detected by each error detection unit, it is notified to the error identification code generation unit 45, where it is converted into a preset code and an error identification code indicating the cause of the error is sent to the master device 3. Is done.

FIG. 3 is a block diagram showing the configuration of the master device 3.
The command issuing unit 30 outputs the address of the target device 4 to be accessed and issues a read or write command. The data buffer 31 temporarily stores write data or read data. The error identification code from the target device 4 is analyzed by the error identification code analysis unit 32 and notifies the error processing control unit 33 of the cause of the error.

  In the error processing setting unit 34, the CPU 2 sets in advance what error recovery processing the master device 3 performs when an error occurs. When an error occurs in the master device 3 and an error identification code is received, the error processing control unit 33 controls the control unit based on the error recovery process associated with the error identification code set in the error processing setting unit 34. 35.

FIG. 4 is a timing chart of the control system 1.
As a precondition, the content of the error recovery processing is set by the error processing setting unit 34 to continue data transfer for a parity error and retry for a timeout error.

  In the time chart, a signal starting from m is a signal driven by the master device 3, and a signal starting from s is a signal driven by the target device 4.

  First, in cycle T1, the master device 3 executes an read by outputting an address to madr and a read command to mcmd.

  When the read data is prepared, the target device 4 outputs the read data to sdata and the data identifier to sresp in cycles T4 to T7. Data identifiers include V and E, where V is Valid and indicates definite data, and E is Error and indicates that some error has occurred in the data.

  In the chart shown in FIG. 4, the identifier E is output at cycle T7, indicating that an error has occurred. Furthermore, the cause of the error is output with serrid (Error ID). The error identification code is set in a code correspondence table as shown in FIG. 5, for example. The configuration is such that the number of serrid bits is assigned to each cause of error. Therefore, if there are four types of error occurrence causes, serrid has only to prepare 4 bits.

  If the 0th bit is 1, it indicates that a parity error has occurred. Similarly, if the first bit is 1, a timeout error, if the second bit is 1, a CRC error, and if the third bit is 1, an exception address error has occurred.

  By assigning one bit for each cause of error occurrence in this way, even if multiple errors occur simultaneously, the master device 3 will not miss the cause of error occurrence, so error recovery processing must be performed reliably. Is possible.

Here, the cause of the error will be described.
Parity error is a parity check error that checks for data errors. Parity check divides data into an appropriate length (about 8 bits) and calculates the number of 0s or 1s contained in it. The result is added together with the data as a parity bit. If the result of parity calculation from the data on the receiving side is compared with the parity bit, it can be seen that some bit is garbled and an error has occurred.

  The timeout error is an error that occurs when the response to the read command is not within the specified time, and occurs due to a response speed delay of the external device 6 connected to the target device 4.

  A CRC error is a CRC (Cyclic Redundancy Check) error, and is caused by a data error as well as a parity error. Calculation is performed by a method called a CRC generator polynomial that combines shift and addition.

  Since the parity check is based on the number of 0s or 1s, if two or more pieces of data are garbled at the same time, they may be offset and considered as normal. Can be suppressed.

  An exception address error is an error that occurs when an address outside the address area assigned to the target device is accessed, and indicates that the read data is invalid.

  For example, if a parity error has occurred, the recovery process for the parity error is set to continue data transfer in advance, so that in cycles T8 to T12, the master device 3 directly receives the received data as another target device 4. Issue a write command to and transfer.

  Further, the second data transfer is performed from the cycle T14. However, since the response cannot be made even at the cycle T30, the target device 4 outputs E2 (timeout error) to the serrid as an error identification code. When a time-out error occurs, the master device 3 is retrying the read command in cycle T34 because it is set to retry as the recovery process.

FIG. 6 is a flowchart showing the data transfer process of the control system 1.
First, in step S1, device initialization is performed. The initial parameters of the master device 3 and the target device 4 that the CPU 2 wants to operate are set.

  Next, in step S2, the master device 3 is activated. The CPU 2 starts data transfer by setting the master device 3 in an operating state.

  In step S3, the master device 3 determines whether an error has occurred during data transfer. If an error has occurred, the cause of the error is identified in step S4, and a preset error recovery process is performed. Execute. If no error has occurred, in step S5, the master device 3 determines whether the data transfer for the set size has been completed. If the data transfer has been completed, the process ends. If not, the process returns to step S3.

  In another embodiment of the present invention, it is possible to optimize the system by lowering the priority of access to the target device in which an error has occurred.

  Unlike the control system 1 shown in FIG. 1, the configuration of the control system of the present embodiment includes three master devices (hereinafter referred to as master devices 3a, 3b, and 3c) and three target devices. An example in which one of the target devices has a timeout error will be described.

  In the data transfer, the master device 3a accesses the target device 4a, and similarly, the master device 3b accesses the target device 4b and the master device 3c accesses the target device 4c. In addition, the priority of access is set such that the target 4a has the highest priority, such as target device 4a> target device 4b> target device 4c.

FIG. 7 is a timing chart when the access priority is not adjusted.
In the timing chart, operation states on the master devices 3a, 3b, 3c and the system bus are shown. For example, “TgtA RD” indicates a read command to the target device 4a.

  At time t1, the three master devices 3a, 3b, and 3c simultaneously issue read commands to the target devices 4a, 4b, and 4c, respectively, and read commands to the target device 4a by the master device 3a based on a predetermined priority order. Is issued on the system bus at time t2.

  If a problem occurs in the target device 4a and the target device 4a returns a timeout error at time t5, the read command of the master device 3b is issued on the system bus at time t6, and the target device 4b from the target device 4b at time t9. At the same time as the read data is returned, the master device 3a issues a read command again.

  At this time, the master device 3a and the master device 3c issue a read command, but the read command for the master device 3a is issued on the system bus based on the priority order. If the failure of the target device 4a has not been resolved, the target device 4a returns a timeout error again at time t13. Thereafter, at time t14, the read command of the master device 3c is issued on the system bus, and at time t17, the read command from the target device 4c is returned.

  When priority adjustment is not performed in this way, access to the target device 4a in which a time-out error has occurred occupies the system bus, consuming useless bandwidth and delaying processing of the entire system.

  On the other hand, in the present embodiment, optimization of processing as the entire system is performed by adjusting priority.

FIG. 8 is a timing chart in the case of adjusting the access priority.
When priority adjustment is performed, the operation up to time t9 is as described above regardless of whether or not priority adjustment is performed. However, when a time-out error occurs at time t5, the priority order is the target device 4b> target device 4c. > The target device 4a is changed, and the priority order of the target device 4a is the lowest.

  Therefore, at time t10, based on the changed priority, the read command for the master device 3b, not the master device 3a, is issued on the system bus.

  Similarly, at time t14, a read command for the master device 3c is issued on the system bus.

  Then, the read command of the master device 3a to the target device 4a having the lowest priority is issued at time t18 when the read commands of the other master devices 3b and 3c are not issued.

  In this way, by lowering the priority of access to the target device in which an error such as a timeout error has occurred, the commands of other target devices are processed preferentially, and the system bus bandwidth is effectively used as a whole system. Processing optimization can be performed.

  The priority order of the target devices may be stored in advance in a storage area of the CPU 2 or other storage device, and the priority order may be updated when a target device error occurs.

It is the schematic which shows the structure of the control system 1 which is one Embodiment of this invention. 3 is a block diagram showing a configuration of a target device 4. FIG. 2 is a block diagram showing a configuration of a master device 3. FIG. 3 is a timing chart of the control system 1. It is a figure which shows the example of the code corresponding | compatible table which shows a response | compatibility with an error identification code and an occurrence cause. 3 is a flowchart showing a data transfer process of the control system 1. It is a timing chart when not adjusting the priority of access. It is a timing chart in the case of adjusting the priority of access.

Explanation of symbols

1 Control system 2 CPU
3 Master device 4 Target device 5 System bus 6 External device

Claims (5)

A master device for controlling data transfer via the system bus;
In a control system connected to a target device that receives an access request from the master device and performs processing,
The target device is
A code output means for outputting an error identification code indicating the cause when an error occurs during data transfer to the master device;
The master device is
Setting means for presetting the contents of error recovery processing to be executed by the master device based on the error identification code when an error occurs;
And a recovery means for executing the error recovery process set by the setting means.   The control system according to claim 1, wherein the master device has a selection unit that selects whether or not the recovery unit performs an error recovery process when an error occurs.   When the data transfer method is isochronous transfer, the setting means sets so that no retry is performed as the error recovery process when the cause of the error is a timeout or the data itself has an error. The control system according to claim 1.   2. The control system according to claim 1, wherein the error identification code output from the target device is assigned a signal line for outputting a code for each cause of the error.   The control system according to claim 1, wherein the priority of access to a target device in which an error has occurred is lowered.

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