JP4439295B2 - Data transfer control device - Google Patents

Description

  The present invention relates to a data transfer control device capable of notifying a local module of a remote transfer state in a system in which a host or an input / output device and a memory are connected, and particularly in a system including a PCI bus. Thus, the present invention relates to a data transfer control device designed to improve the efficiency of the data transfer status notification method.

In a Disk control system including a plurality of printed boards, a centralized module (hereinafter referred to as CM) on the remote side and an adapter (hereinafter referred to as ADP) on the local side are respectively routers (Router: (Hereinafter referred to as RT), message transfer and data transfer are performed between the centralized module (CM) and the adapter (ADP) using direct memory access (DMA). The centralized module (CM) and adapter (ADP) each have a built-in CPU.
Between the centralized module (CM) ← → adapter (ADP), the PCI-bus is used for transfer processing.
FIG. 6 is a diagram for explaining a conventional data transfer process in the system.
In FIG. 1, the adapter 1 includes a data transfer controller 11, a data buffer 12, a memory controller 13, a main storage device 14, and a CPU 15.
A remote-side centralized module (CM) 2 composed of a processor, a cache memory, and the like is connected to the adapter 1 via a router (RT) 3.

In FIG. 6, data transfer is performed as follows.
The CPU 15 sets a descriptor in the data transfer controller 11 by the program in the adapter 1 ((1), (i) in FIG. 6). In the descriptor, the PCI address in the centralized module 2, the number of transfer bytes, the address of the data buffer 12 that is the transfer source, and the like are set.
Thereafter, the data transfer engine 11a in the data transfer controller 11 is activated by the program in the adapter 1 (FIGS. 6 (2) and (ii)), and the descriptor in the data transfer controller 11 is set in the data transfer engine 11a. ((Iii) in FIG. 6).
Then, according to the descriptor setting, the data stored in the data buffer 12 is transferred to the centralized module 2 ((3), (iv) in FIG. 6).

At this time, the adapter 1 cannot know whether the data sent from the adapter 1 has normally reached the centralized module 2 due to the specification of the PCI bus.
This is a problem in a disk array system that requires reliability, and there is a known method in which PCI transfer normal completion confirmation (AA) is separately performed after data transfer. (Patent Document 1).
This is because information on errors detected by the router 3 until the data received from the adapter 1 is transferred to the centralized module 2 is displayed as follows. A. The data is stored in a predetermined format called a code, and when the data transfer controller 11 of the adapter 1 finishes transferring a certain unit of data, the A. A. This is a method of knowing the presence or absence of an error during transfer by reading a code. A. A. Reading of the code is performed by A. A. This is done by executing a descriptor for reading the code.
A. above. A. The code includes detailed information such as whether an error was detected at the interface with the centralized module 2, whether it was detected inside the router 3, and at which address it was detected during access. Yes.

FIG. 7 is a diagram showing a normal end confirmation process of the data transfer.
As shown in FIG. A. The router 3 acquires the code set from the centralized module 2 ((i) in FIG. 7).
The data transfer controller 11 includes A.I. A. By executing the descriptor for reading the code, A. A. The code is read and held in its own register ((ii) in FIG. 7).
Thereafter, an interrupt is given to the memory controller 13 in order to notify the CPU of the end of data transfer and the end of storing error information (FIG. 7 (iii)).
When this interrupt is transmitted to the memory controller 13, the bit corresponding to the data transfer control of the interrupt factor register in the memory controller 13 is set.
Further, when the memory controller 13 raises an interrupt to the CPU 15 ((iv) in FIG. 7), an interrupt processing routine is started by the CPU 15, the cause of the interrupt is specified, and the data transfer ends abnormally. A. The code is read ((v) (vi) in FIG. 7).
The interrupt factor is identified by the following procedure (a)-(c).
(a) The CPU 15 reads the interrupt factor register in the memory controller 13 and knows that the data transfer controller 11 is the factor depending on which bit is set.
(b) The CPU 15 reads the interrupt factor register of the data transfer controller 11 and knows that the data transfer has ended normally or ended abnormally.
(c) If the data transfer is abnormally terminated, the A.C. A. Read the code to see the detailed error cause.
JP 2001-243206 A

The disk control system has a host or a disk as an upper interface. However, since the multiplicity of processing increases as the transfer speed with the upper interface increases, the CPU 15 assigns a descriptor in the data transfer controller 11 for each data transfer. Setting itself was a burden.
In the conventional method, when the adapter 1 performs transfer processing with the centralized module 2, descriptor setting to the data transfer controller 11, activation of the data transfer engine, A. A. When the data transfer controller 11 is started up, each time a register access occurs, an overhead occurs, causing performance degradation.
In addition, as described above, in order to check the normality of the transfer, it is necessary to read the register in the memory controller 13 once and the register in the data transfer controller 11 twice, which increases the load on the CPU 15. It was.
The present invention has been made to solve the above-mentioned problems of the prior art, and aims to improve the efficiency of data transfer and the method of notifying the data transfer status in the data transfer control device. The object is to reduce the burden on the processing apparatus provided.

In the present invention, the above-described problems are solved as follows.
The local side module, comprising a processing unit, a data transfer control means, connected between the processing device and the data transfer control unit, the register to generate an interrupt to the processor when data is set memory It comprises a control means and a main storage device connected to the memory control means.
The processing device stores data transfer information and information indicating whether or not to acquire data transfer normal end confirmation information in the main storage device, and the data transfer control means is stored in the main storage means. The above information is read and data is transferred to the remote module, and after the data transfer, data transfer normal completion confirmation information is acquired from the remote module, and the acquired data transfer normal completion confirmation information is stored in the memory control. Set in the register of the means. The processing device acquires data transfer normal end confirmation information from the register based on the interrupt from the register.

In the present invention, the following effects can be obtained.
(1) Using the function of a register that generates an interrupt when data provided in the memory control means is set, an interrupt is issued to the processing device, and the processing device checks whether there is error information and details when an error occurs. Therefore, it is possible to reduce the load on the processing apparatus at the time of normal termination confirmation (Access Assurance).
(2) By providing the data transfer control means with a function of reading information (descriptor) prepared in the high-speed main storage device and indicating whether or not to acquire the data transfer information and the data transfer normal completion confirmation information, The load on the processing device can be further reduced, and the processing device resources used for data transfer can be given to other processing.

FIG. 1 is a diagram showing a configuration example of a data transfer control device according to an embodiment of the present invention.
In FIG. 1, the local adapter 1 includes the data transfer controller 11, the data buffer 12, the memory controller 13, the main storage device 14, and the CPU 15 as described above. The data transfer controller 11 and the memory controller 13 are connected via an interface module 16 to a host or disk device that is an upper level interface.
The centralized module 2 on the remote side is connected to the adapter 1 via the router 3.
The data transfer controller 11 has three PCI buses. Here, the data transfer controller 11 and the interface module 16 are locally-PCI (LPCI), the data transfer controller 11 and the memory controller 13 are communication-PCI (CPCI), The area between the data transfer controller 11 and the centralized module 2 will be referred to as System-PCI (SPCI).
LPCI performs message transfer and data transfer with the host and the disk, CPCI performs message transfer with the CPU 15, and SPCI performs message transfer and data transfer with the centralized module 2 as described above.

FIG. 2 shows the overall configuration of a RAID device (RAID: Redundant Array of Inexpensive Disks) which is an application example of the present invention.
In FIG. 2, the RAID device 20 includes disk devices 21-1 to 21-4 configured by a plurality of disk groups, and each disk device 21 is connected to the adapters 1-1 to 1-4, and each adapter is connected to each adapter. 1-1 to 1-4 are connected to the centralized modules 2-1 and 2-2 via routers 3-1 and 3-2. As described above, the adapters 1-1 to 1-4 transfer the data transferred from the disk devices 21-1 to 21-4 via the routers 3-1 and 3-2 and the centralized module 2-. 1 and 2-2.
The RAID device 20 is connected to the host computers 22-1 and 22-2. The adapters 1-5 to 1-8 are connected to the host computers 22-1 and 22-2, and each adapter 1-5 to 1-8 is centralized via routers 3-3 and 3-4. -Connected to modules 2-1 and 2-2. As described above, the adapters 1-5 to 1-8 transfer the data transferred from the host to the centralized modules 2-1 and 2-2 via the routers 3-1 and 3-2. .

3 and 4 are diagrams for explaining the operation of the data transfer control device according to the present embodiment. Hereinafter, the operation of the data transfer control device according to the present embodiment will be described with reference to FIG.
FIG. 3 is a diagram for explaining data transfer processing in the present embodiment. In this embodiment, data transfer is performed as follows.
The transfer data is sent to the data transfer controller 11 via the interface module 16 and stored in the data buffer 12. Further, the CPU 15 is notified from the interface module 16 via the memory controller 13 that data has been stored in the data buffer 12.
Upon receiving the above notification, the CPU 15 creates a descriptor and sets the descriptor in the main storage device 14 by the program in the adapter 1 ((1), (i) in FIG. 3).
As shown in FIG. 5A, a PCI address in the centralized module 2, the number of transfer bytes, the address of the data buffer 12 that is the transfer source, and the like are set in the descriptor. A. A. At the break of data transfer that needs to be read. A. If this flag is set, after the data transfer as described above, the router 3 sends the A.I. A. The code is read. A. A. For example, as shown in FIG. 5B, the code stores an area for storing a flag indicating whether or not the data transfer has been normally performed, and an error code indicating the error contents when the data transfer ends abnormally. It has the area to be.

Next, the CPU 15 notifies the data transfer controller 11b of the data transfer controller 11 of the address of the main storage device 14 in which the descriptor is set, and starts the data transfer engine 11a of the data transfer controller 11 ((2 in FIG. 3). ), (ii)).
Thereby, the data transfer control unit 11b of the data transfer controller 11 reads the descriptor from the notified address of the main storage device 14, and sets it in the data transfer engine 11a ((iii) in FIG. 3).
Then, according to the descriptor setting, the data stored in the data buffer 12 is transferred to the centralized module 2 through the transfer engine 11a ((3) and (iv) in FIG. 3).
During the execution of the data transfer, the CPU 15 sets a descriptor for the next data transfer in the main storage device 14 ((v) in FIG. 3). This setting is repeated for burst transfer.

In the prior art, the CPU 15 prepares a descriptor in a register in the data transfer controller 11, but in this embodiment, as described above, a descriptor is prepared in the high-speed main storage device 14, and the CPU 15 stores transfer information therein. Then, the address of the set descriptor is given to the data transfer controller 11, and the data transfer controller 11 reads the descriptor from the main storage device 14 and performs data transfer. For this reason, the load on the CPU 15 is reduced, and the CPU resources conventionally used for data transfer can be given to other processes.
In particular, the main storage device 14 has a larger capacity than the register in the data transfer controller 11 and can write descriptors one after another while the data transfer controller 11 is performing data transfer processing. Therefore, it is not necessary to wait until the data transfer is completed and write the descriptor to the data transfer controller 11.
In addition, as described above, the disk control system has a plurality of PCI buses, and as the transfer rate with the host interface increases, the multiplicity of processing increases, and a descriptor is set for each data transfer as in the conventional example. However, according to the present embodiment, the burden on the CPU 15 can be reduced as compared with the conventional example.

FIG. 4 is a diagram for explaining normal completion confirmation processing of data transfer in this embodiment.
As shown in FIG. A. The router 3 acquires the code set from the centralized module 2 ((i) in FIG. 4).
The data transfer controller 11 has the above-described A.I. A. By executing the descriptor for reading the code, the router 3 executes the above A.D. A. The code is read ((ii) in FIG. 4), and is not held by itself but is set in the mailbox register 13a of the memory controller 13 ((iii) in FIG. 4).
The mailbox register 13a has a function of generating an interrupt when data is written. A. At the same time as the code is transferred to the memory controller 13, an interrupt is raised to the CPU 15 ((iv) in FIG. 4).

The CPU 15 performs an interrupt process from the memory controller 13 ((v) in FIG. 4). A. By reading the code and judging it, it is possible to know the presence or absence of error information and its detailed error cause ((vi) in FIG. 4).
That is, the cause of the interruption after the data transfer using the function of the mailbox register 13a is specified as follows.
(a) The CPU 15 reads the interrupt factor register of the memory controller 13, and the cause is A.B. A. Know that.
(b) The CPU 15 reads the mailbox register 13a in the memory controller 13 and confirms the presence / absence of error information and the detailed cause of the error.
By taking the above procedure, in the prior art, the CPU 15 needs to read the register in the memory controller 13 once and the register in the data transfer controller 11 twice in order to check error information during data transfer. On the other hand, in this embodiment, it is only necessary to read the register in the memory controller 13 twice, and the load on the CPU 15 can be reduced.

  In the present embodiment, as described above, with respect to Access Assurance (AA), which is a normal end confirmation in data transfer between the data transfer controller 11 and the centralized module 2, the mailbox register 13a of the memory controller 13 is used. In the mailbox register 13a. A. When the code is set, the CPU 15 is automatically interrupted, so the load on the CPU can be reduced and the performance of the disk control system can be improved.

It is a figure which shows the structural example of the data transfer control apparatus of the Example of this invention. It is a figure which shows the whole structure of the RAID apparatus which is an example of application of this invention. It is a figure explaining the data transfer process in the Example of this invention. It is a figure explaining the normal completion confirmation process of the data transfer in the Example of this invention. Descriptor and A. A. It is a figure which shows the example of a code | cord. It is a figure explaining the conventional data transfer process. It is a figure explaining the normal completion confirmation process of the conventional data transfer.

Explanation of symbols

1 Adapter (ADP)
2 Centralized module (CM)
3 Router (RT)
11 Data Transfer Controller 11a Data Transfer Engine 11b Data Transfer Control Unit 12 Data Buffer 13 Memory Controller 13a Mailbox Register 14 Main Memory 15 CPU
16 Interface module 20 RAID device 21 Disk device

Claims (1)

A data transfer control device for transferring data from a local module to a remote module,
The local module includes a processing device, data transfer control means, memory control means connected between the processing device and data transfer control means, and a main storage device connected to the memory control means. The memory control means includes a register that generates an interrupt to the processing device when data is set,
The processing device stores data transfer information and information indicating whether to acquire the data transfer normal end confirmation information in the main storage device,
The data transfer control means reads the information stored in the main storage means, transfers the data to the remote module, and acquires data transfer normal end confirmation information from the remote module after the data transfer. The acquired data transfer normal end confirmation information is set in the register of the memory control means,
The data processing control device, wherein the processing device acquires data transfer normal end confirmation information from the register based on an interrupt from the register.

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