JP2017143138A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thyristor having an isolated structure which improves reverse breakdown voltage.SOLUTION: A semiconductor device comprises: a first conductivity type isolation region 17 which is formed on a circumferential part of a semiconductor substrate 10 and joined to a semiconductor region 12; and a second conductivity type channel stopper region 16 which is formed on a principal surface 10b of the semiconductor substrate 10 so as to surround a semiconductor region 13 and contains an impurity at a higher concentration than the semiconductor region 12. The isolation region 17 has: a diffusion region 18 which extends from a principal surface 10a to the inside of the semiconductor substrate 10 to be connected to a first conductivity type semiconductor region 11; and a diffusion region 19 which extends from the principal surface 10b to the inside of the semiconductor substrate 10 to be connected to the diffusion region 18. The shortest distance D1 between the channel stopper region 16 and the diffusion region 18 is shorter than the shortest distance D2 between the channel stopper region 16 and the diffusion region 19.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

Conventionally, a thyristor having an isolation structure in which a P-type isolation region is provided on a peripheral portion of a semiconductor substrate is known (see Patent Document 1). By adopting an isolation structure, there is an advantage that reverse withstand voltage such as repetitive peak reverse voltage _VRRM (Repetitive Peak Reverse Voltage) can be secured at low cost.

JP-A-57-78171

  By the way, in the thyristor having an isolated structure, there is a problem that it is difficult to ensure a sufficient reverse breakdown voltage due to non-uniform electric field strength in a bias application state. This will be described in detail with reference to FIG. FIG. 7 shows only the right half of the semiconductor substrate 110 of the thyristor.

  As shown in FIG. 7, the thyristor includes a P-type semiconductor region 111, an N-type semiconductor region 112, a P-type semiconductor region 113, and an N-type semiconductor region 114 formed on the lower surface of the semiconductor substrate 110. Have a structure in which these are joined in order. Although an anode electrode, a cathode electrode, and a gate electrode are not shown in FIG. 7, actually, an anode electrode is provided on the semiconductor region 111, a cathode electrode is provided on the semiconductor region 114, and Is provided with a gate electrode.

  The thyristor further includes a P-type guard ring 115, an N-type channel stopper region 116, and a P-type isolation region 117. The guard ring 115 is formed on the upper surface of the semiconductor substrate 110 so as to surround the semiconductor region 113. The channel stopper region 116 is formed on the upper surface of the semiconductor substrate 110 so as to surround the guard ring 115, and contains a higher concentration (N +) impurity than the semiconductor region 112.

  The isolation region 117 is formed at the peripheral edge of the semiconductor substrate 110 and is joined to the semiconductor region 112. The isolation region 117 includes a diffusion region formed by thermally diffusing impurities introduced into the peripheral portion of the semiconductor substrate 110. That is, the isolation region 117 is a region in which the diffusion region 119 on the front side of the semiconductor substrate 110 and the diffusion region 118 on the back side of the semiconductor substrate 110 are connected inside the semiconductor substrate 110.

  In the thyristor, the region A near the junction boundary between the diffusion region 119 and the semiconductor region 112, the region B near the junction boundary between the diffusion region 118 and the semiconductor region 112, and the semiconductor region 111 and the semiconductor region 112. Between regions C in the vicinity of the junction boundary between them, the non-uniformity of the electric field strength in the reverse bias applied state is large. Specifically, the electric field strength in the region A is the highest, the electric field strength in the region C is the next highest, and the electric field strength in the region B is the smallest (see “design dimension 85 μm” in FIG. 3). The reason why the electric field strength in the region B is smaller than the electric field strengths in the regions A and C is that the depletion layer width in the region B in the reverse bias applied state is wider than the depletion layer width in the regions A and C.

  As described above, in the thyristor having the conventional isolated structure, the electric field strength is highest in the region A when the reverse bias is applied. As a result, breakdown (breakdown) is most likely to occur in the region A, and it has been difficult to ensure a sufficient reverse breakdown voltage.

  The present invention has been made based on the above technical recognition, and an object thereof is to improve the reverse breakdown voltage of a thyristor having an isolated structure.

A semiconductor device according to the present invention includes:
A first conductive type first semiconductor region formed on the one main surface, and a second conductive type second semiconductor region, between one main surface and the other main surface of the semiconductor substrate facing each other; A semiconductor device in which a third semiconductor region of a first conductivity type and a fourth semiconductor region of a second conductivity type are joined in order,
An isolation region of a first conductivity type formed on a peripheral portion of the semiconductor substrate and bonded to the second semiconductor region;
A channel stopper region of a second conductivity type formed on the other main surface of the semiconductor substrate so as to surround the third semiconductor region and containing a higher concentration of impurities than the second semiconductor region;
The isolation region extends from the one main surface to the inside of the semiconductor substrate, a first diffusion region connected to the first semiconductor region, and extends from the other main surface to the inside of the semiconductor substrate. And a second diffusion region connected to the first diffusion region,
The shortest distance between the channel stopper region and the first diffusion region is shorter than the shortest distance between the channel stopper region and the second diffusion region.

In the semiconductor device,
The diffusion coefficient of the first conductivity type impurity contained in the first diffusion region may be larger than the diffusion coefficient of the first conductivity type impurity contained in the second diffusion region.

In the semiconductor device,
The width of the first main surface of the first diffusion region may be larger than the width of the other main surface of the second diffusion region.

In the semiconductor device,
In a cross section perpendicular to the main surface of the semiconductor substrate and passing through the third semiconductor region and the isolation region, the curvature of the junction boundary between the first diffusion region and the second semiconductor region is the second diffusion region. And the curvature of the junction boundary between the second semiconductor region and the second semiconductor region.

A method for manufacturing a semiconductor device according to the present invention includes:
A first conductive type first semiconductor region formed on the one main surface, and a second conductive type second semiconductor region, between one main surface and the other main surface of the semiconductor substrate facing each other; A method of manufacturing a semiconductor device in which a third semiconductor region of a first conductivity type and a fourth semiconductor region of a second conductivity type are sequentially joined,
Forming a first conductivity type isolation region having a first diffusion region and a second diffusion region on a peripheral edge of the semiconductor substrate;
Forming a second conductivity type channel stopper region containing an impurity at a higher concentration than the second semiconductor region so as to surround the third semiconductor region on the other main surface of the semiconductor substrate. ,
In the step of forming the isolation region, the second diffusion region is formed by introducing and diffusing impurities of the first conductivity type from the other main surface of the semiconductor substrate, and from one main surface of the semiconductor substrate. Introducing and diffusing impurities of the first conductivity type to form the first diffusion region connected to the second diffusion region and larger than the second diffusion region;
In the step of forming the channel stopper region, the shortest distance between the channel stopper region and the first diffusion region is shorter than the shortest distance between the channel stopper region and the second diffusion region. A channel stopper region is formed.

In the method for manufacturing the semiconductor device,
In the step of forming the isolation region, the second diffusion region is formed using an impurity having a first diffusion coefficient, and the first diffusion is performed using an impurity having a second diffusion coefficient larger than the first diffusion coefficient. A region may be formed.

  In the present invention, the isolation region extends from one main surface of the semiconductor substrate to the inside of the semiconductor substrate, and is connected to the first semiconductor region, and from the other main surface of the semiconductor substrate to the semiconductor substrate. A second diffusion region extending inward and connected to the first diffusion region, the shortest distance between the channel stopper region and the first diffusion region being the shortest distance between the channel stopper region and the second diffusion region Shorter than distance. As a result, the depletion layer width in the region near the junction boundary between the first diffusion region and the second semiconductor region becomes shorter than that in the conventional case when the reverse bias is applied, and the electric field strength in the region increases accordingly. The electric field strength in the vicinity of the junction boundary between the second diffusion region and the second semiconductor region is reduced. As a result, the electric field strength is made uniform between the regions.

  Therefore, according to the present invention, the reverse breakdown voltage of a thyristor having an isolated structure can be improved.

1 is a cross-sectional view of a semiconductor device 1 according to an embodiment of the present invention. 1 is a cross-sectional view of a semiconductor substrate 10 of a semiconductor device 1 according to an embodiment of the present invention. It is a graph which shows the simulation result of the electric field strength of field A, field B, and field C at the time of reverse bias application. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device 1 which concerns on embodiment. FIG. 5 is a process cross-sectional view for explaining the manufacturing method of the semiconductor device 1 according to the embodiment, which is subsequent to FIG. 4; FIG. 6 is a process cross-sectional view for explaining the manufacturing method of the semiconductor device 1 according to the embodiment, which is subsequent to FIG. 5; It is a fragmentary sectional view of the thyristor which has the conventional isolation structure.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings.

<Semiconductor device 1>
With reference to FIG. 1 and FIG. 2, the structure of the semiconductor device 1 which concerns on embodiment of this invention is demonstrated. In FIG. 1, the region A is a region near the junction boundary between the diffusion region 19 and the semiconductor region 12, and the region B is a region near the junction boundary between the diffusion region 18 and the semiconductor region 12, Region C is a region near the junction boundary between the semiconductor region 11 and the semiconductor region 12.

  The semiconductor device 1 is a thyristor having an isolated structure. As shown in FIG. 2, the first conductivity type formed on the main surface 10 a between the main surface 10 a (one main surface) and the main surface 10 b (the other main surface) facing each other of the semiconductor substrate 10. Semiconductor region 11 (first semiconductor region), second conductivity type semiconductor region 12 (second semiconductor region), first conductivity type semiconductor region 13 (third semiconductor region), and second conductivity type semiconductor region 14 (fourth semiconductor region) are sequentially joined.

  The semiconductor substrate 10 is a silicon substrate containing a second conductivity type impurity. The semiconductor substrate 10 may be a substrate made of another semiconductor, for example, a compound semiconductor (GaAs, GaN, SiC, etc.).

  In the present embodiment, the first conductivity type is P-type, and the second conductivity type is N-type. However, the present invention is not limited to this, and the first conductivity type may be N-type and the second conductivity type may be P-type.

  In addition to the semiconductor regions 11 to 14 described above, the semiconductor device 1 includes a guard ring 15, a channel stopper region 16, an isolation region 17, an anode electrode 21, a cathode electrode 22, as shown in FIG. And a gate electrode 23. The anode electrode 21 is formed on the semiconductor region 11, the cathode electrode 22 is formed on the semiconductor region 14, and the gate electrode 23 is formed on the semiconductor region 13. The upper surface (main surface 10b) of the semiconductor substrate 10 is covered with an insulating film 25.

  The guard ring 15 is provided in order to suppress the occurrence of electric field concentration near the end of the semiconductor region 13 when forward bias is applied and to increase the breakdown voltage of the thyristor. The guard ring 15 is formed in an annular shape so as to surround the semiconductor region 13 on the main surface 10 b of the semiconductor substrate 10. The guard ring may be omitted depending on the performance required for the thyristor, or may be provided in multiple (double, triple, etc.).

  The channel stopper region 16 prevents a depletion layer extending from the regions A and B from reaching the semiconductor region 13 when a reverse bias is applied, and suppresses leakage current (channel current). The channel stopper region 16 is a second conductivity type semiconductor region containing a higher concentration (N +) impurity than the semiconductor region 12, and is formed on the main surface 10 b of the semiconductor substrate 10 so as to surround the semiconductor region 13. Yes. In the present embodiment, as shown in FIG. 1, an electrode 24 is provided for making the channel stopper region 16 equipotential and suppressing the generation of channel current.

  As shown in FIGS. 1 and 2, the isolation region 17 is formed on the peripheral portion of the semiconductor substrate 10 and is a first conductivity type semiconductor region joined to the semiconductor region 12. Here, the “peripheral portion” is a peripheral portion of the semiconductor substrate 10 including the side surface 10 c of the semiconductor substrate 10.

  The isolation region 17 has a diffusion region 18 (first diffusion region) and a diffusion region 19 (second diffusion region). The diffusion region 19 is connected to the diffusion region 18 and is smaller than the diffusion region 18.

  The diffusion region 18 is a region formed by diffusing impurities introduced from the main surface 10 a of the semiconductor substrate 10. Similarly, the diffusion region 19 is a region formed by diffusing impurities introduced from the main surface 10 b of the semiconductor substrate 10. As shown in FIG. 2, the diffusion region 18 is formed larger than the diffusion region 19.

  Diffusion region 18 extends from main surface 10 a to the inside of semiconductor substrate 10. The diffusion region 19 extends from the main surface 10 b to the inside of the semiconductor substrate 10. The diffusion region 19 is connected to the diffusion region 18, and the diffusion region 18 is connected to the semiconductor region 11. As the diffusion region 18 advances from the main surface 10a to the inside of the semiconductor substrate 10, the width from the side surface 10c becomes narrower. Similarly, the width of the diffusion region 19 from the side surface 10 c becomes narrower as it goes from the main surface 10 b to the inside of the semiconductor substrate 10.

  The diffusion coefficient of the first conductivity type impurity contained in the diffusion region 18 may be larger than the diffusion coefficient of the first conductivity type impurity contained in the diffusion region 19. For example, the impurity contained in the diffusion region 18 is aluminum, and the impurity contained in the diffusion region 19 is boron. Further, as shown in FIG. 2, the width W <b> 1 of the main surface 10 a of the diffusion region 18 may be larger than the width W <b> 2 of the main surface 10 b of the diffusion region 19.

  In the present embodiment, as shown in FIG. 2, the shortest distance D1 between the channel stopper region 16 and the diffusion region 18 is shorter than the shortest distance D2 between the channel stopper region 16 and the diffusion region 19. As a result, when a reverse bias is applied to the thyristor, the depletion layer width in the region B near the junction boundary between the diffusion region 18 and the semiconductor region 12 becomes shorter than the conventional one, so that the electric field strength in the region B increases. . Along with this, the electric field strength in the region A decreases. This will be described in more detail with reference to FIG.

  FIG. 3 shows a simulation result of the electric field strengths in the regions A, B, and C when the reverse bias is applied. The “design dimension” in FIG. 3 indicates the size of the impurity introduction region when the diffusion region 18 is formed. In the case of the “design dimension 85 μm”, the sizes of the impurity introduction regions on the front and back sides of the semiconductor substrate 10 are equal, and the diffusion region 18 and the diffusion region 19 have substantially the same size. In the case of “design dimension 140 μm”, “design dimension 250 μm”, and “design dimension 350 μm”, the width of the impurity introduction region for forming the diffusion region 19 (corresponding to the exposure width X2 in FIG. 4 (1) described later) Is 85 μm, and the width of the impurity introduction region for forming the diffusion region 18 (corresponding to an exposure width X1 in FIG. 4 (1) described later) is set as a value of each design dimension. The thickness of the semiconductor substrate 10 (silicon substrate) was 350 μm.

  As a result of simulation, the shortest distance D2 between the channel stopper region 16 and the diffusion region 19 was 217 μm. On the other hand, the shortest distance D1 between the channel stopper region 16 and the diffusion region 18 was 304 μm, 231 μm, and 184 μm for the design dimensions of 140 μm, 250 μm, and 350 μm, respectively. That is, in this simulation, the shortest distance D1 is shorter than the shortest distance D2 when the design dimension is 350 μm. As shown in FIG. 3, when the design dimension is 350 μm, the electric field strength in the region A, the region B, and the region C is increased by the increase in the electric field strength in the region B and the accompanying decrease in the electric field strength in the region A. It became almost the same (flat). That is, the electric field strength was made uniform between the regions A, B, and C.

  As described above, in the present embodiment, the shortest distance D1 between the channel stopper region 16 and the diffusion region 18 is shorter than the shortest distance D2 between the channel stopper region 16 and the diffusion region 19, so that the region B The width of the depletion layer can be reduced to increase the electric field strength, thereby reducing the difference in electric field strength between regions A, B, and C. Therefore, according to the present embodiment, breakdown in the region A where the electric field strength is highest can be suppressed in the conventional thyristor, and the reverse breakdown voltage of the semiconductor device 1 (thyristor) can be improved.

Furthermore, by improving the reverse breakdown voltage, it becomes easy to secure the repeated peak reverse voltage V _RRM , and the reliability of the thyristor can be improved. In addition, if the reverse breakdown voltage of the same level as before is sufficient, the thyristor can be reduced in size.

  In order to increase the electric field strength in the region B, the diffusion region 18 may have a pointed shape toward the inside of the semiconductor substrate 10 rather than the diffusion region 19. That is, as shown in FIG. 2, in the cross section perpendicular to the main surfaces 10a and 10b of the semiconductor substrate 10 and passing through the semiconductor region 13 and the isolation region 17 (that is, the longitudinal cross section of the semiconductor substrate 10), The curvature of the junction boundary J1 with the semiconductor region 12 may be larger than the curvature of the junction boundary J2 between the diffusion region 19 and the semiconductor region 12. Here, the curvature of the joint boundaries J1 and J2 is the reciprocal of the radius of the circle inscribed in the joint boundaries J1 and J2.

  Strictly speaking, the curvature of the junction boundary J1 changes according to the depth from the main surface 10a of the semiconductor substrate 10. That is, the curvature of the junction boundary J1 increases as the position from the main surface 10a of the semiconductor substrate 10 becomes deeper, reaches a maximum at a position slightly shallower than the portion where the diffusion region 18 and the diffusion region 19 are connected, and then decreases. The same applies to the curvature of the joint boundary J2. It is preferable that at least the maximum value of the curvature of the joint boundary J1 is larger than the maximum value of the curvature of the joint boundary J2.

<Method for Manufacturing Semiconductor Device 1>
Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS.

  First, the second conductivity type (N-type in this embodiment) semiconductor substrate 10 is prepared. Then, as shown in FIG. 4A, an oxide film 31 is formed on the main surface 10a of the semiconductor substrate 10, and an oxide film 32 is formed on the opposite main surface 10b. The oxide films 31 and 32 are, for example, thermal oxide films, and are formed by heating the semiconductor substrate 10.

  Next, as shown in FIG. 4A, a resist film 33 and a resist film 34 are formed on the oxide film 31 and the oxide film 32, respectively. The resist film 33 does not cover the peripheral portion of the oxide film 31, and an annular region having an exposed width X 1 is exposed at the peripheral portion of the oxide film 31. Similarly, the resist film 34 does not cover the peripheral portion of the oxide film 32, and an annular region having a width X 2 is exposed at the peripheral portion of the oxide film 32. The resist films 33 and 34 are formed so that X1> X2.

  Next, as shown in FIG. 4B, the oxide films 31 and 32 not covered with the resist films 33 and 34 are removed using the resist films 33 and 34 as etching masks. Thereafter, the resist films 33 and 34 are removed. Thus, the peripheral portions of the main surfaces 10a and 10b of the semiconductor substrate 10 are not covered with the oxide films 31 and 32 and are exposed.

  Next, a first conductivity type isolation region 17 is formed on the peripheral edge of the semiconductor substrate 10 by a deposition method. More specifically, as shown in FIG. 4 (3), by introducing and diffusing impurities of the first conductivity type into the semiconductor substrate 10 from the region of the main surface 10 b not covered with the oxide film 32, the diffusion region 19. Form. Similarly, by introducing and diffusing impurities of the first conductivity type into the semiconductor substrate 10 from the region of the main surface 10 a not covered with the oxide film 31, the diffusion region 18 connected to the diffusion region 19 and larger than the diffusion region 19. Form. The impurity to be introduced is, for example, aluminum or boron.

  As described above, since the resist films 33 and 34 are formed so that X1> X2, the amount of impurities introduced from the main surface 10a is larger than the amount of impurities introduced from the main surface 10b. Therefore, as shown in FIG. 4 (3), the diffusion region 18 is formed larger than the diffusion region 19, and is connected to the diffusion region 19 on the main surface 10 b side from the center in the thickness direction of the semiconductor substrate 10. Become. As shown in FIG. 4 (3), the exposed regions at the peripheral portions of the main surfaces 10a and 10b are covered with an oxide film formed by heating in the deposition process.

  Next, a resist film 37 is formed on the oxide film 32 as shown in FIG. The resist film 37 is provided with an opening 37a and an annular opening 37b. The opening 37 a is provided in correspondence with the formation region of the semiconductor region 13, and the opening 37 b is provided in correspondence with the formation region of the guard ring 15.

  Next, as shown in FIG. 5B, the oxide film 32 not covered with the resist film 37 is removed using the resist film 37 as an etching mask. Thereafter, the resist film 37 is removed. Further, the oxide film 31 on the back surface of the semiconductor substrate 10 is also removed.

  Next, as shown in FIG. 5 (3), the first conductivity type impurity is introduced into the semiconductor substrate 10 from the main surface 10a and the region of the main surface 10b not covered with the oxide film 32 by the deposition method. To do. Impurities to be introduced are, for example, aluminum and boron. Thereby, the semiconductor region 11, the semiconductor region 13, and the guard ring 15 are formed. Note that the oxide film 38 in FIG. 5C is a thermal oxide film formed by heating in the deposition process.

  Next, as shown in FIG. 6A, a resist film 40 is formed on the oxide film 32. The resist film 40 is provided with an opening 40a and an annular opening 40b. The opening 40 a is provided corresponding to the region where the semiconductor region 14 is to be formed, and the opening 40 b is provided corresponding to the region where the channel stopper region 16 is to be formed.

  Next, as shown in FIG. 6B, the oxide film 32 not covered with the resist film 40 is removed using the resist film 40 as an etching mask. Thereafter, the resist film 40 is removed.

  Next, a second conductivity type channel stopper region 16 is formed on the main surface 10 b of the semiconductor substrate 10 so as to surround the semiconductor region 13. More specifically, as shown in FIG. 6 (3), the second conductivity type impurity is introduced into the semiconductor substrate 10 from the region of the main surface 10 b not covered with the oxide film 32 by the deposition method. Impurities to be introduced are, for example, phosphorus and arsenic. Thereby, the channel stopper region 16 is formed. In addition to the channel stopper region 16, the semiconductor region 14 is formed in the semiconductor region 13 in this step.

  In the step of forming the channel stopper region 16, as shown in FIG. 6 (3), the shortest distance D 1 between the channel stopper region 16 and the diffusion region 18 is the shortest distance between the channel stopper region 16 and the diffusion region 19. A channel stopper region 16 is formed at a position shorter than D2. That is, even if the diffusion region 18 is formed larger than the diffusion region 19, if the channel stopper region 16 is formed close to the diffusion region 19, the shortest distance D1 is longer than the shortest distance D2. Therefore, the channel stopper region 16 is formed at a position away from the diffusion region 19 so that the shortest distance D1 is shorter than the shortest distance D2.

  Next, after removing the oxide films 32 and 38, the insulating film 25 having openings at predetermined positions (positions where various electrodes are formed) is formed on the main surface 10 b of the semiconductor substrate 10. Thereafter, metal deposition such as aluminum is performed to form the anode electrode 21, the cathode electrode 22, the gate electrode 23 and the electrode 24. Through the above steps, the semiconductor device 1 shown in FIG. 1 is manufactured.

  In the step of forming the isolation region 17, the diffusion region 18 may be formed using an impurity having a diffusion coefficient larger than that of the diffusion region 19. That is, the diffusion region 19 may be formed using an impurity having a first diffusion coefficient, and the diffusion region 18 may be formed using an impurity having a second diffusion coefficient larger than the first diffusion coefficient. For example, the diffusion region 18 is formed using aluminum having a large diffusion coefficient, while the diffusion region 19 is formed using boron having a diffusion coefficient smaller than that of aluminum. As a result, the diffusion region 18 can be formed larger, and the shortest distance D1 between the channel stopper region 16 and the diffusion region 18 can be made larger than the shortest distance D2 between the channel stopper region 16 and the diffusion region 19. It becomes easy to shorten.

  Further, when the diffusion region 18 and the diffusion region 19 are formed using impurities having different diffusion coefficients as described above, it is not essential that the exposure widths X1 and X2 are set to X1> X2, for example, X1 = X2 Also good.

  In the description of the above embodiment, the semiconductor device 1 is a thyristor. However, the present invention is not limited to this, and may be applied to other semiconductor devices such as diodes and various transistors (MOSFETs, bipolar transistors, etc.). Is possible.

  Based on the above description, those skilled in the art may be able to conceive additional effects and various modifications of the present invention, but the aspects of the present invention are not limited to the above-described embodiments. Various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the present invention derived from the contents defined in the claims and equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10,110 Semiconductor substrate 10a, 10b Main surface 10c Side surface 11, 12, 13, 14, 111, 112, 113, 114 Semiconductor region 15, 115 Guard ring region 16, 116 Channel stopper region 17, 117 Isolation region 18, 19, 118, 119 Diffusion region 21 Anode electrode 22 Cathode electrode 23 Gate electrode 24 (channel stopper) electrode 25 Insulating films 31, 32, 38 Oxide films 33, 34, 37, 40 Resist films 37a, 37b, 40a, 40b Opening A, B, C Area D1, D2 Shortest distance J1, J2 Junction boundary W1, W2 (Diffusion area) width X1, X2 Exposure width

Claims (6)

A first conductive type first semiconductor region formed on the one main surface, and a second conductive type second semiconductor region, between one main surface and the other main surface of the semiconductor substrate facing each other; A semiconductor device in which a third semiconductor region of a first conductivity type and a fourth semiconductor region of a second conductivity type are joined in order,
An isolation region of a first conductivity type formed on a peripheral portion of the semiconductor substrate and bonded to the second semiconductor region;
A channel stopper region of a second conductivity type formed on the other main surface of the semiconductor substrate so as to surround the third semiconductor region and containing a higher concentration of impurities than the second semiconductor region;
The isolation region extends from the one main surface to the inside of the semiconductor substrate, a first diffusion region connected to the first semiconductor region, and extends from the other main surface to the inside of the semiconductor substrate. And a second diffusion region connected to the first diffusion region,
2. The semiconductor device according to claim 1, wherein a shortest distance between the channel stopper region and the first diffusion region is shorter than a shortest distance between the channel stopper region and the second diffusion region.   The diffusion coefficient of the first conductivity type impurity contained in the first diffusion region is larger than the diffusion coefficient of the first conductivity type impurity contained in the second diffusion region. The semiconductor device described.   3. The semiconductor device according to claim 1, wherein a width of the first main surface of the first diffusion region is larger than a width of the second main surface of the second diffusion region.   In a cross section perpendicular to the main surface of the semiconductor substrate and passing through the third semiconductor region and the isolation region, the curvature of the junction boundary between the first diffusion region and the second semiconductor region is the second diffusion region. The semiconductor device according to claim 1, wherein a curvature of a junction boundary between the first semiconductor region and the second semiconductor region is larger. A first conductive type first semiconductor region formed on the one main surface, and a second conductive type second semiconductor region, between one main surface and the other main surface of the semiconductor substrate facing each other; A method of manufacturing a semiconductor device in which a third semiconductor region of a first conductivity type and a fourth semiconductor region of a second conductivity type are sequentially joined,
Forming a first conductivity type isolation region having a first diffusion region and a second diffusion region on a peripheral edge of the semiconductor substrate;
Forming a second conductivity type channel stopper region containing an impurity at a higher concentration than the second semiconductor region so as to surround the third semiconductor region on the other main surface of the semiconductor substrate. ,
In the step of forming the isolation region, the second diffusion region is formed by introducing and diffusing impurities of the first conductivity type from the other main surface of the semiconductor substrate, and from one main surface of the semiconductor substrate. Introducing and diffusing impurities of the first conductivity type to form the first diffusion region connected to the second diffusion region and larger than the second diffusion region;
In the step of forming the channel stopper region, the shortest distance between the channel stopper region and the first diffusion region is shorter than the shortest distance between the channel stopper region and the second diffusion region. A method of manufacturing a semiconductor device, comprising forming a channel stopper region.   The second diffusion region is formed using an impurity having a first diffusion coefficient, and the first diffusion region is formed using an impurity having a second diffusion coefficient larger than the first diffusion coefficient. Item 6. A method for manufacturing a semiconductor device according to Item 5.

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