JP2017130743A - Programmable gain amplifier circuit - Google Patents

Programmable gain amplifier circuit Download PDF

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JP2017130743A
JP2017130743A JP2016007845A JP2016007845A JP2017130743A JP 2017130743 A JP2017130743 A JP 2017130743A JP 2016007845 A JP2016007845 A JP 2016007845A JP 2016007845 A JP2016007845 A JP 2016007845A JP 2017130743 A JP2017130743 A JP 2017130743A
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JP6630575B2 (en
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努 涌井
Tsutomu Wakui
努 涌井
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New Japan Radio Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To cancel the offset component included in two input voltages, without increasing the resolution of a DA converter outputting the offset component for cancellation, or spreading the dynamic range of the output voltage.SOLUTION: A programmable gain amplifier circuit includes first and second instrumentation amplifiers 21, 22 for amplifying two input signals Vinp, Vinn with the same gain, and a fully differential amplifier 23 outputting a two-phase output signal by amplifying the difference of the output signals from the first and second instrumentation amplifiers 21, 22. A bias voltage VCM is applied to the inverted input terminal of the fully differential amplifier 23 via a first variable resistor 25, and an adjustment voltage for cancelling the offset component, included in the difference of the two input signals, is applied to the non-inverted input terminal via a second variable resistor 26 having the same resistance value as that of the first variable resistor. The resistance values of the first and second variable resistors 25, 26 can be varied by the correction data D1 of external input.SELECTED DRAWING: Figure 1

Description

本発明は、入力信号に含まれるオフセット成分をキャンセルしたプログラマブルゲインアンプ回路（以下、ＰＧＡ回路と称する。）に関する。   The present invention relates to a programmable gain amplifier circuit (hereinafter referred to as a PGA circuit) in which an offset component included in an input signal is canceled.

図５はブリッジ型のセンサ回路１０の差動出力電圧Ｖinn，Ｖinp を入力して増幅し出力電圧Ｖoutp_2，Ｖoutn_2 として出力する従来の完全差動のＰＧＡ回路２０Ａを示すものである。このＰＧＡ回路２０Ａは、計装アンプ２１，２２、と完全差動アンプ２３で構成されている（非特許文献１参照）。Ｒ１、Ｒ２，Ｒ３，Ｒ４，Ｒ５，Ｒ６，Ｒ７は抵抗である。   FIG. 5 shows a conventional fully differential PGA circuit 20A that receives and amplifies differential output voltages Vinn and Vinp of a bridge type sensor circuit 10 and outputs them as output voltages Voutp_2 and Voutn_2. The PGA circuit 20A includes instrumentation amplifiers 21 and 22 and a fully differential amplifier 23 (see Non-Patent Document 1). R1, R2, R3, R4, R5, R6, and R7 are resistors.

電圧Ｖinn を増幅する計装アンプ２１の出力電圧をＶon，電圧Ｖinp を増幅する計装アンプ２２の出力電圧をＶop とし、完全差動アンプ２３のＤＣゲインＡが非常に大きいと仮定すると、ＰＧＡ回路２０Ａの出力電圧（Ｖoutp_2−Ｖoutn_2 ）は次の式（１）となる。ただし、各抵抗の抵抗値は、Ｒ１＝Ｒａ，Ｒ２＝Ｒ３＝Ｒｂ，Ｒ４＝Ｒ５＝Ｒｃ，Ｒ６＝Ｒ７＝Ｒｄである。

Figure 2017130743
Assuming that the output voltage of the instrumentation amplifier 21 that amplifies the voltage Vinn is Von, the output voltage of the instrumentation amplifier 22 that amplifies the voltage Vinp is Vop, and the DC gain A of the fully differential amplifier 23 is very large, the PGA circuit The output voltage (Voutp_2−Voutn_2) of 20A is expressed by the following equation (1). However, the resistance values of the resistors are R1 = Ra, R2 = R3 = Rb, R4 = R5 = Rc, and R6 = R7 = Rd.
Figure 2017130743

このＰＧＡ回路１０Ａのゲインは、抵抗Ｒ２，Ｒ３の抵抗値Ｒｂと、抵抗Ｒ４，Ｒ５の抵抗値Ｒｄを固定値とし、抵抗Ｒ１の抵抗値Ｒａや抵抗Ｒ４，Ｒ５の抵抗値Ｒｃをプログラムによって可変することで、設定することができる。例えば、Ｒａ＝２Ｒｂ，Ｒｃ＝Ｒｄに設定すれば、ゲインは２倍となる。また、Ｒａ＝（２／３）Ｒｂ，Ｒｃ＝Ｒｄに設定すれば、ゲインは４倍となる。   The gain of the PGA circuit 10A is such that the resistance value Rb of the resistors R2 and R3 and the resistance value Rd of the resistors R4 and R5 are fixed values, and the resistance value Ra of the resistor R1 and the resistance value Rc of the resistors R4 and R5 are variable by a program. This can be set. For example, if Ra = 2Rb and Rc = Rd are set, the gain is doubled. If Ra = (2/3) Rb and Rc = Rd are set, the gain becomes four times.

式（１）では、入力源のセンサ回路１０にオフセットが発生すると、このとき同一電圧値であるべき電圧ＶinpとＶinn に差分が生じる。このため、ＰＧＡ回路２０Ａのゲインが高い場合に、出力電圧（Ｖoutp_2−Ｖoutn_2 ）が電源電圧の一方に張り付き、あるいはセンサ回路１０のオフセット成分が出力電圧（Ｖoutp_2−Ｖoutn_2 ）のダイナミックレンジの大半を占めてしまい、「入力電圧＋オフセット成分」の信号を正確に処理できないという問題点がある。   In the equation (1), when an offset occurs in the sensor circuit 10 of the input source, a difference occurs between the voltages Vinp and Vinn that should be the same voltage value at this time. Therefore, when the gain of the PGA circuit 20A is high, the output voltage (Voutp_2−Voutn_2) sticks to one of the power supply voltages, or the offset component of the sensor circuit 10 occupies most of the dynamic range of the output voltage (Voutp_2−Voutn_2). Therefore, there is a problem that the signal of “input voltage + offset component” cannot be processed accurately.

そこで図６に示すように、センサ回路１０に発生したオフセット成分をキャンセルする構成を含めたＰＧＡ回路２０Ｂが提案されている（特許文献１、２参照）。このＰＧＡ回路２０Ｂでは、完全差動アンプ２３の反転入力端子に抵抗Ｒ８を介してバイアス電圧ＶＣＭを印加し、完全差動アンプ２３の非反転入力端子に抵抗Ｒ９を介して電圧ＶＤＡＣをＤＡ変換器２４から印加する構成を採用している。   Therefore, as shown in FIG. 6, a PGA circuit 20B including a configuration for canceling an offset component generated in the sensor circuit 10 has been proposed (see Patent Documents 1 and 2). In the PGA circuit 20B, the bias voltage VCM is applied to the inverting input terminal of the fully differential amplifier 23 via the resistor R8, and the voltage VDAC is applied to the non-inverting input terminal of the fully differential amplifier 23 via the resistor R9. 24 is applied.

このＰＧＡ回路１０Ｂにおいて得られる出力電圧（Ｖoutp_3−Ｖoutn_3 ）は、次の式（２）となる。抵抗値はＲ８＝Ｒ９＝Ｒｅである。図７にこの内容を図示した。図７のＶoffset ＝Ｖinp−Ｖinn である。

Figure 2017130743
The output voltage (Voutp_3−Voutn_3) obtained in the PGA circuit 10B is expressed by the following equation (2). The resistance value is R8 = R9 = Re. This is illustrated in FIG. In FIG. 7, Voffset = Vinp−Vinn.
Figure 2017130743

式（１）と比較して式（２）では、ＤＡ変換器２４の出力電圧ＶＤＡＣを調整して右項の第１項と第２項を逆極性で一致させることで、センサ回路１０のオフセット成分をキャンセルし、出力電圧（Ｖoutp_3−Ｖoutn_3 ）のダイナミックレンジを確保できる。しかし、抵抗Ｒ６，Ｒ７の抵抗値Ｒｄと、抵抗Ｒ８，Ｒ９の抵抗値Ｒｅのマッチングによってその割合が決まるという問題点がある。つまり、Ｒｄ＝Ｒｅにマッチングしなければならない。Ｒｄ＞Ｒｅのときは、Ｒｄ／Ｒｅの値が１を超えるため、精度よくオフセット成分をキャンセルするために、電圧ＶＤＡＣの分解能を高くしなければならない。また、Ｒｄ＜Ｒｅのときは、Ｒｄ／Ｒｅの値が１を下回るため、電圧ＶＤＡＣの可変範囲を広くする必要がある。   Compared with Equation (1), in Equation (2), the output voltage VDAC of the DA converter 24 is adjusted so that the first term and the second term of the right term are matched with opposite polarity, thereby offsetting the sensor circuit 10. By canceling the components, the dynamic range of the output voltage (Voutp_3−Voutn_3) can be secured. However, there is a problem that the ratio is determined by matching the resistance value Rd of the resistors R6 and R7 and the resistance value Re of the resistors R8 and R9. That is, it must match Rd = Re. When Rd> Re, since the value of Rd / Re exceeds 1, the resolution of the voltage VDAC must be increased in order to cancel the offset component with high accuracy. When Rd <Re, the value of Rd / Re is less than 1, so the variable range of the voltage VDAC needs to be widened.

“Fully-Differential Amplifiers,Application Report JAJA122”,TEXAS INSTRUMENTS，Dec.13.2007“Fully-Differential Amplifiers, Application Report JAJA122”, TEXAS INSTRUMENTS, Dec.13.2007 特開２００８−２９４７７２号公報JP 2008-294772 A 特開２００７−０４９２８５号公報JP 2007-049285 A

以上のように、図５の従来回路では、センサ回路１０のオフセット成分をキャンセルすることができず、ＰＧＡ回路２０Ａのゲインが高い場合に、出力電圧が電源電圧の一方に張り付いたり、そのオフセット成分が出力電圧のダイナミックレンジの大半を占めるという問題点があった。   As described above, in the conventional circuit of FIG. 5, when the offset component of the sensor circuit 10 cannot be canceled and the gain of the PGA circuit 20A is high, the output voltage sticks to one of the power supply voltages or the offset thereof. There is a problem that the component occupies most of the dynamic range of the output voltage.

また、図６の従来回路では、センサ回路１０のオフセット成分をキャンセルすることはできるが、抵抗Ｒ６，Ｒ７の抵抗値Ｒｄと、抵抗Ｒ８，Ｒ９の抵抗値Ｒｅとのマッチング如何により、キャンセルの割合が決まるという問題点があった。精度良くオフセット成分をキャンセルするためには、ＤＡ変換器２４の分解能を高くするか、あるいは出力電圧のダイナミックレンジを広げる必要がある。   Further, in the conventional circuit of FIG. 6, the offset component of the sensor circuit 10 can be canceled, but the cancellation ratio depends on the matching between the resistance value Rd of the resistors R6 and R7 and the resistance value Re of the resistors R8 and R9. There was a problem that was decided. In order to cancel the offset component with high accuracy, it is necessary to increase the resolution of the DA converter 24 or widen the dynamic range of the output voltage.

本発明の目的は、キャンセル用のオフセット成分を出力するＤＡ変換器の分解能を高くしたり、出力電圧のダイナミックレンジを広げることなく、入力電圧に含まれるオフセット成分を効果的にキャンセルすることができるようにしたＰＧＡ回路を提供することである。   An object of the present invention is to effectively cancel an offset component included in an input voltage without increasing the resolution of a DA converter that outputs an offset component for cancellation or expanding the dynamic range of the output voltage. An object of the present invention is to provide a PGA circuit.

上記目的を達成するため、請求項１の発明は、２個の入力信号を同一ゲインでそれぞれ増幅する第１及び第２の計装アンプと、該第１及び第２の計装アンプの出力信号の差分を増幅して２相の出力信号を出力する完全差動アンプとを備え、前記完全差動アンプの２個の入力端子の一方の入力端子に固定のバイアス電圧を第１の可変抵抗を介して印加し、他方の入力端子に前記２個の入力信号の差分に含まれるオフセット成分をキャンセルするためにＤＡ変換器から出力する調整電圧を前記第１の可変抵抗と同一抵抗値の第２の可変抵抗を介して印加するプログラマブルゲインアンプ回路であって、前記第１及び第２の可変抵抗の抵抗値は、外部入力の補正データによって可変されることを特徴とする。   In order to achieve the above object, the invention of claim 1 is directed to first and second instrumentation amplifiers respectively amplifying two input signals with the same gain, and output signals of the first and second instrumentation amplifiers. And a fully differential amplifier that outputs a two-phase output signal by amplifying the difference between the two differential input terminals, a fixed bias voltage is applied to one input terminal of the two fully differential amplifiers, and a first variable resistor is provided. And an adjustment voltage output from the DA converter to cancel the offset component included in the difference between the two input signals at the other input terminal is applied to the second variable terminal having the same resistance value as that of the first variable resistor. This is a programmable gain amplifier circuit applied through a variable resistor, wherein the resistance values of the first and second variable resistors are varied by correction data of an external input.

請求項２にかかる発明は、請求項１に記載のプログラマブルゲインアンプ回路において、前記第１及び第２の可変抵抗は、抵抗値Ｒｅの２0 倍、２1 倍、２2 倍、・・・、２N-1 倍の抵抗値を有するＮ（Ｎは１以上の整数）個の抵抗の内から前記補正データに応じて選ばれた１又は２以上を並列接続することで構成され、前記補正データがＮビットのＤ１のとき、前記第１及び第２の可変抵抗の抵抗値Ｒｅ_var は

Figure 2017130743
に設定されることを特徴とする。 Such invention in claim 2, in a programmable gain amplifier circuit according to claim 1, wherein the first and second variable resistors, 2 0 times the resistance Re, 2 1-fold, 2 doubles, ... 1 or 2 or more selected according to the correction data from N (N is an integer of 1 or more) resistors having a resistance value of 2 N-1 times, and the correction When the data is N-bit D1, the resistance value Re_var of the first and second variable resistors is
Figure 2017130743
It is characterized by being set to.

本発明によれば、補正データで抵抗値を調整できる可変抵抗を追加するのみで、抵抗比のマッチングを行うことができるので、ＤＡ変換器の分解能を高くしたり、出力電圧のダイナミックレンジを広げることなく、入力電圧に含まれるオフセット成分をキャンセルすることができる。このため、回路規模や消費電流の増加を少なくできるという利点がある。   According to the present invention, resistance ratio matching can be performed only by adding a variable resistor whose resistance value can be adjusted by correction data. Therefore, the resolution of the DA converter can be increased and the dynamic range of the output voltage can be expanded. Without offsetting, the offset component included in the input voltage can be canceled. For this reason, there is an advantage that an increase in circuit scale and current consumption can be reduced.

本発明のＰＧＡ回路の実施例の回路図である。It is a circuit diagram of the Example of the PGA circuit of this invention. 図１のＰＧＡ回路の可変抵抗の回路図である。It is a circuit diagram of the variable resistance of the PGA circuit of FIG. 図１のＰＧＡ回路の動作説明図である。It is operation | movement explanatory drawing of the PGA circuit of FIG. Ｄ１が３ビットのときの図１のＰＧＡ回路の可変抵抗の調整の説明図である。It is explanatory drawing of adjustment of the variable resistance of the PGA circuit of FIG. 1 when D1 is 3 bits. 従来のＰＧＡ回路の回路図である。It is a circuit diagram of a conventional PGA circuit. 従来の別のＰＧＡ回路の回路図である。It is a circuit diagram of another conventional PGA circuit. 図６のＰＧＡ回路の動作説明図である。It is operation | movement explanatory drawing of the PGA circuit of FIG.

以下、本発明の１つの実施例のＰＧＡ回路２０について詳細に説明する。ＰＧＡ回路２０はセンサ回路１０の差動出力電圧Ｖinp，Ｖinn を入力して、差動の出力電圧Ｖoutp_1、Ｖoutn_1 を出力する。   Hereinafter, the PGA circuit 20 according to one embodiment of the present invention will be described in detail. The PGA circuit 20 receives the differential output voltages Vinp and Vinn of the sensor circuit 10 and outputs differential output voltages Voutp_1 and Voutn_1.

ＰＧＡ回路２０は、入力電圧Ｖinn を増幅する計装アンプ２１、入力電圧Ｖinp を増幅する計装アンプ２２、計装アンプ２１の出力電圧Ｖon と計装アンプ２２の出力電圧Ｖop を差動増幅する完全差動アンプ２３、外部入力するデータ（図示せず）によってオフセット調整電圧ＶＤＡＣを生成するＤＡ変換器２４を備える。計装アンプ２１，２２の反転入力端子間には抵抗Ｒ１が接続されている。また、計装アンプ２１の出力端子と反転入力端子との間には抵抗Ｒ２が接続され、計装アンプ２２の出力端子と反転入力端子の間には抵抗Ｒ３が接続されている。そして、計装アンプ２１の出力端子と完全差動アンプ２３の反転入力端子の間には抵抗Ｒ４が接続され、計装アンプ２２の出力端子と完全差動アンプ２３の非反転入力端子との間には抵抗Ｒ５が接続されている。また、完全差動アンプの非反転出力端子と反転入力端子の間には抵抗Ｒ６が接続され、反転出力端子と非反転入力端子の間には抵抗Ｒ７が接続されている。さらに、完全差動アンプ２３の反転入力端子には可変抵抗２４を介してバイアス電圧ＶＣＭが印加し、非反転入力端子には可変抵抗２６を介してＤＡ変換器２４の出力電圧ＶＤＡＣが印加している。ここで、各抵抗Ｒ１〜Ｒ７の抵抗値は、Ｒ１＝Ｒａ，Ｒ２＝Ｒ３＝Ｒｂ，Ｒ４＝Ｒ５＝Ｒｃ，Ｒ６＝Ｒ７＝Ｒｄである。可変抵抗２５，２６の抵抗値は、外部入力する補正データＤ１で設定されるＲｅ_varで共通ある。   The PGA circuit 20 includes an instrumentation amplifier 21 that amplifies the input voltage Vinn, an instrumentation amplifier 22 that amplifies the input voltage Vinp, and a complete amplification that differentially amplifies the output voltage Von of the instrumentation amplifier 21 and the output voltage Vop of the instrumentation amplifier 22. The differential amplifier 23 includes a DA converter 24 that generates an offset adjustment voltage VDAC by data (not shown) input from the outside. A resistor R1 is connected between the inverting input terminals of the instrumentation amplifiers 21 and 22. A resistor R2 is connected between the output terminal of the instrumentation amplifier 21 and the inverting input terminal, and a resistor R3 is connected between the output terminal of the instrumentation amplifier 22 and the inverting input terminal. A resistor R4 is connected between the output terminal of the instrumentation amplifier 21 and the inverting input terminal of the fully differential amplifier 23, and between the output terminal of the instrumentation amplifier 22 and the non-inverting input terminal of the fully differential amplifier 23. Is connected to a resistor R5. A resistor R6 is connected between the non-inverting output terminal and the inverting input terminal of the fully differential amplifier, and a resistor R7 is connected between the inverting output terminal and the non-inverting input terminal. Further, the bias voltage VCM is applied to the inverting input terminal of the fully differential amplifier 23 via the variable resistor 24, and the output voltage VDAC of the DA converter 24 is applied to the non-inverting input terminal via the variable resistor 26. Yes. Here, the resistance values of the resistors R1 to R7 are R1 = Ra, R2 = R3 = Rb, R4 = R5 = Rc, and R6 = R7 = Rd. The resistance values of the variable resistors 25 and 26 are common to Re_var set by correction data D1 input from the outside.

図２に、可変抵抗２５の構成を示す。ここでは、Ｎ個（Ｎは１以上の整数）の抵抗Ｒｅ(0)，Ｒｅ(1)，Ｒｅ(2)，・・・，Ｒｅ（N-1) が、個々にＮ個のスイッチＳＷ(0)，ＳＷ(1)，ＳＷ(2)，・・・，ＳＷ(N-1)と直列接続され、そのＮ個の直列回路が並列接続されることで、可変抵抗２５が構成されている。可変抵抗２６も同様である。抵抗Ｒｅ(0)〜Ｒｅ(N-1) の抵抗値は、抵抗Ｒｅ(0) ＝２０×Ｒｅ、抵抗Ｒｅ(1) ＝２１×Ｒｅ、抵抗Ｒｅ(2) ＝２2×Ｒｅ、・・・、抵抗Ｒｅ(N-1) ＝２Ｎ-1×Ｒｅである。スイッチＳＷ(0) 〜ＳＷ(N-1) は、デジタルの補正データＤ１をデコーダ２７によりデコードした値に応じて、全部がオフ又は１以上がオンされる。これにより、抵抗Ｒｅ(0) 〜Ｒｅ(N-1) の内の１又は２以上が選択されて、抵抗Ｒe_ver が決まる。 FIG. 2 shows the configuration of the variable resistor 25. Here, N resistors (N is an integer of 1 or more) resistors Re (0), Re (1), Re (2),..., Re (N−1) are individually connected to N switches SW ( 0), SW (1), SW (2),..., SW (N-1) are connected in series, and the N series circuits are connected in parallel to form the variable resistor 25. . The same applies to the variable resistor 26. The resistance values of the resistors Re (0) to Re (N-1) are as follows: resistor Re (0) = 2 0 × Re, resistor Re (1) = 2 1 × Re, resistor Re (2) = 2 2 × Re, ... Resistance Re (N-1) = 2N-1 * Re. The switches SW (0) to SW (N-1) are all turned off or turned on by one or more depending on the value obtained by decoding the digital correction data D1 by the decoder 27. Thereby, one or more of the resistors Re (0) to Re (N-1) are selected, and the resistor Re_ver is determined.

そして、補正データＤ１がＮビットの場合、可変抵抗２５，２６の抵抗値Ｒｅ_var は、

Figure 2017130743
で表すことができる。Ｒｅは固定の抵抗値である。 When the correction data D1 is N bits, the resistance value Re_var of the variable resistors 25 and 26 is
Figure 2017130743
Can be expressed as Re is a fixed resistance value.

ＰＧＡ回路２０において、出力電圧（Ｖoutp_1−Ｖoutn_1 ）は、式（２）において、Ｒｅ＝Ｒｅ_var に置き換えた次の式（４）のように表すことができる。

Figure 2017130743
In the PGA circuit 20, the output voltage (Voutp_1−Voutn_1) can be expressed as the following equation (4) in which the equation (2) is replaced with Re = Re_var.
Figure 2017130743

この式（４）に式（３）を代入すると、ＰＧＡ回路２０の出力電圧（Ｖoutp_1−Ｖoutn_1 )は、式（５）のように表すことができる。図３にこの内容を図示した。図３のＶoffset ＝Ｖinp−Ｖinn である。

Figure 2017130743
By substituting Equation (3) into Equation (4), the output voltage (Voutp_1−Voutn_1) of the PGA circuit 20 can be expressed as Equation (5). This is illustrated in FIG. In FIG. 3, Voffset = Vinp−Vinn.
Figure 2017130743

式（２）と式（５）を比較すると、式（２）の抵抗値Ｒｅについて、係数分「（１／２N-1）×Ｄ１」だけ、補正データＤ１の分解能で精度高く調整することができることが分かる。このため、ＤＡ変換器２４の分解能を高くしたり、出力電圧（Ｖoutp_1−Ｖoutn_1 ）のダイナミックレンジを広げることなく、入力電圧（Ｖinn−Ｖinp ）に含まれるオフセット成分をキャンセルすることができ、回路規模や消費電流の増加を少なくできるという利点がある。 Comparing Expression (2) and Expression (5), the resistance value Re of Expression (2) is adjusted with high accuracy by the resolution of the correction data D1 by the coefficient “(1/2 N−1 ) × D1”. You can see that For this reason, the offset component included in the input voltage (Vinn−Vinp) can be canceled without increasing the resolution of the DA converter 24 or expanding the dynamic range of the output voltage (Voutp_1−Voutn_1), and the circuit scale There is an advantage that increase in current consumption can be reduced.

図４に補正データＤ１が３ビット（Ｎ＝３）の場合の抵抗値を示した。Ｄ１のデコード値は０〜７である。この場合、３個のスイッチＳＷ（０）〜ＳＷ（２）のうちのオンするスイッチの組み合わせによって、可変抵抗２５，２６の抵抗値Ｒｅ_var を８通り実現することができる。   FIG. 4 shows the resistance value when the correction data D1 is 3 bits (N = 3). The decode value of D1 is 0-7. In this case, eight resistance values Re_var of the variable resistors 25 and 26 can be realized by a combination of the switches that are turned on among the three switches SW (0) to SW (2).

このときのビットの重み付けとして、ここでは、最上位ビット（ＭＳＢ）をＳＷ(0) に、最下位ビット（ＬＳＢ）をＳＷ(N-1) に割り当てている。これにより、可変抵抗２５，２６の式（３）における抵抗値Ｒｅ_var の逆数１／Ｒｅ_var を可変でき、その値を（１／４）×（１／Ｒｅ）の分解能で調整することができる。   In this case, as the bit weighting, the most significant bit (MSB) is assigned to SW (0) and the least significant bit (LSB) is assigned to SW (N-1). Thereby, the reciprocal 1 / Re_var of the resistance value Re_var in the equation (3) of the variable resistors 25 and 26 can be varied, and the value can be adjusted with a resolution of (1/4) × (1 / Re).

１０：ブリッジ型のセンサ回路
２０，２０Ａ，２０Ｂ：ＰＧＡ回路、２１，２２：計装アンプ、２３：完全差動アンプ、２４：ＤＡ変換器、２５，２６：可変抵抗、２７：デコーダ
Ｖinp，Ｖinn：入力電圧
Ｖop，Ｖon：計装アンプの出力電圧
Ｖoutp_1，Ｖoutn_1，Ｖoutp_2，Ｖoutn_2，Ｖoutp_3，Ｖoutn_3：ＰＧＡ回路の出力電圧
ＶＤＡＣ：ＤＡ変換器の出力電圧
ＶＣＭ：バイアス電圧
10: Bridge type sensor circuit 20, 20A, 20B: PGA circuit, 21, 22: Instrumentation amplifier, 23: Fully differential amplifier, 24: DA converter, 25, 26: Variable resistor, 27: Decoder Vinp, Vinn : Input voltage Vop, Von: Output voltage of instrumentation amplifier Voutp_1, Voutn_1, Voutp_2, Voutn_2, Voutp_3, Voutn_3: Output voltage of PGA circuit VDAC: Output voltage of DA converter VCM: Bias voltage

Claims (2)

２個の入力信号を同一ゲインでそれぞれ増幅する第１及び第２の計装アンプと、該第１及び第２の計装アンプの出力信号の差分を増幅して２相の出力信号を出力する完全差動アンプとを備え、前記完全差動アンプの２個の入力端子の一方の入力端子に固定のバイアス電圧を第１の可変抵抗を介して印加し、他方の入力端子に前記２個の入力信号の差分に含まれるオフセット成分をキャンセルするためにＤＡ変換器から出力する調整電圧を前記第１の可変抵抗と同一抵抗値の第２の可変抵抗を介して印加するプログラマブルゲインアンプ回路であって、
前記第１及び第２の可変抵抗の抵抗値は、外部入力の補正データによって可変されることを特徴とするプログラマブルゲインアンプ回路。 First and second instrumentation amplifiers that amplify two input signals with the same gain, respectively, and amplify the difference between the output signals of the first and second instrumentation amplifiers to output a two-phase output signal A fully differential amplifier, a fixed bias voltage is applied to one input terminal of the two input terminals of the fully differential amplifier via a first variable resistor, and the two input terminals are applied to the other input terminal. A programmable gain amplifier circuit that applies an adjustment voltage output from a DA converter to cancel an offset component included in a difference between input signals via a second variable resistor having the same resistance value as that of the first variable resistor. And
The programmable gain amplifier circuit characterized in that the resistance values of the first and second variable resistors are varied by correction data of an external input. 請求項１に記載のプログラマブルゲインアンプ回路において、
前記第１及び第２の可変抵抗は、抵抗値Ｒｅの２0 倍、２1 倍、２2 倍、・・・、２N-1 倍の抵抗値を有するＮ（Ｎは１以上の整数）個の抵抗の内から前記補正データに応じて選ばれた１又は２以上を並列接続することで構成され、前記補正データがＮビットのＤ１のとき、前記第１及び第２の可変抵抗の抵抗値Ｒｅ_var は
Figure 2017130743
に設定されることを特徴とするプログラマブルゲインアンプ回路。 The programmable gain amplifier circuit according to claim 1,
Said first and second variable resistors, 2 0 times the resistance Re, 2 1-fold, 2 doubles, · · ·, N with 2 N-1 times the resistance (N is an integer of 1 or more) One or two or more selected from the resistors in accordance with the correction data are connected in parallel, and when the correction data is N bits D1, the resistances of the first and second variable resistors The value Re_var is
Figure 2017130743
Programmable gain amplifier circuit characterized by being set to.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007049285A (en) * 2005-08-08 2007-02-22 Seiko Instruments Inc Chopper amplifier circuit and semiconductor device
US20120044006A1 (en) * 2010-08-19 2012-02-23 Industrial Technology Research Institute Dc offset calibration apparatus, dc offset calibration system, and method thereof
JP2014120840A (en) * 2012-12-14 2014-06-30 Renesas Electronics Corp Semiconductor device, and method for correcting offset voltage

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007049285A (en) * 2005-08-08 2007-02-22 Seiko Instruments Inc Chopper amplifier circuit and semiconductor device
US20120044006A1 (en) * 2010-08-19 2012-02-23 Industrial Technology Research Institute Dc offset calibration apparatus, dc offset calibration system, and method thereof
JP2014120840A (en) * 2012-12-14 2014-06-30 Renesas Electronics Corp Semiconductor device, and method for correcting offset voltage

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