JP2017130502A - Component mounting method and component mounting line - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a component mounting method and a component mounting line that are capable of mounting a component on a multi-chambered substrate with high productivity in a component mounting line having plural transport lanes.SOLUTION: In a component mounting line having plural transport lanes each having plural mounting work positions, the numbers of defective circuit patterns on multi-chamfered substrates are obtained (ST31), and the multi-chamfered substrates are divided into plural groups, the numbers of the defective circuit patterns on the multi-chamfered substrates of each group being close to one another (ST32). Then, it is determined whether or not a first group can be transported into a first lane (ST33), and if it is possible, the first group is transported into the first lane (ST34). If it is impossible, it is determined whether the first group can be transported in a second lane (ST35). If it is possible, the first group is transported into the second lane (ST36). Then, it is determined whether or not a second group can be transported into the second lane (ST35). If it is possible, the second group is transported into the second lane (ST36). If it is impossible, it is determined whether the second group can be transported into the first lane (ST33). If possible, the second group is transported into the first lane (ST34).SELECTED DRAWING: Figure 9

Description

  The present invention relates to a component mounting method and a component mounting line for mounting components on a multi-sided board in a component mounting line having a plurality of conveyance lanes.

  Conventionally, when a mounting board is produced by mounting components on a so-called multi-sided board in which a plurality of circuit patterns are formed on one board, for defective circuit patterns with defective parts such as short circuits and disconnections Without mounting the components, the components are mounted only on a normal circuit pattern that is a good product and has no defective parts (see Patent Document 1). This prevents an increase in wasted time for mounting the component on the defective circuit pattern and loss of the component that is discarded after being mounted on the defective circuit pattern.

  Also, in a component mounting line that connects multiple so-called dual lane component mounting devices with multiple transport lanes, the same type of board is distributed in order to multiple transport lanes to produce mounting boards in parallel. A component mounting method for improving the production efficiency is known (see Patent Document 2). In this method, a mounting board is produced while transporting the board in order in synchronization with the component mounting apparatus on the downstream side at a tact time interval at which mounting of the components is completed at all of the mounting work positions provided in the transfer lane. ing.

Japanese Patent Laid-Open No. 11-40999 JP 2008-181453 A

  However, in the prior art including Patent Documents 1 and 2, there are the following problems when components are mounted on a multi-sided board by a component mounting line in which a plurality of dual lane type component mounting apparatuses are connected. That is, although the number of defective circuit patterns on the multi-sided board varies, the multi-sided board is allocated in order to the empty transfer lane without considering the number of defective circuit patterns, and there are many defective circuit patterns. A multi-sided board and a few multi-sided boards are produced together in the same transport lane.

  In general, a multi-planar board with few defective circuit patterns (many normal circuit patterns) requires a longer component mounting time than a multi-plane board with many defective circuit patterns. Therefore, the tact time of each conveyance lane is governed by the component mounting time of the multi-sided board with few defective circuit patterns, and the time for waiting for the multi-sided board with many defective circuit patterns without mounting components increases. As a result, there is a problem that productivity in the entire transport lane is lowered.

  Therefore, an object of the present invention is to provide a component mounting method and a component mounting line that can mount components on a multi-sided board with high productivity in a component mounting line including a plurality of conveyance lanes.

  The component mounting method of the present invention is a component mounting line including a plurality of transfer lanes each having a plurality of mounting work positions for mounting components on a board, and mounting the components on a multi-sided board on which a plurality of circuit patterns are formed. In the component mounting method to be performed, the number of defective circuit patterns in the multi-sided board is obtained, and the multi-sided board is divided into a plurality of groups in which the number of defective circuit patterns is close, It is determined whether the first group can be loaded into the first conveyance lane among the plurality of conveyance lanes. If the first group can be loaded, the first group is loaded into the first conveyance lane. It is determined whether it is possible to carry in the second transportation lane among the lanes, and when it is possible to carry into the second transportation lane, the transportation is carried into the second transportation lane. Determining whether it is possible to carry the group into the second transport lane, and if it is possible to carry in the group, determine whether the group can be carried into the first transport lane. If it can be loaded into the first transfer lane, it is loaded into the first transfer lane.

  The component mounting line of the present invention includes a plurality of transfer lanes each having a plurality of mounting work positions for mounting components on a board, a number of defective pattern acquisition unit for acquiring the number of defective circuit patterns on the multi-sided board, A distribution unit that distributes the multi-sided substrate to any of the plurality of transfer lanes based on the number of defective circuit patterns, and the distribution unit includes a plurality of the multiple circuit board that has a plurality of defective circuit patterns that are close to each other. And determine whether it is possible to carry the first group out of the plurality of groups into the first transportation lane of the plurality of transportation lanes, and if it can be carried in, carry it into the first transportation lane. If it is impossible to carry in, it is determined whether it is possible to carry in the second transportation lane among the plurality of transportation lanes. When loading into the transport lane and determining whether the second group of the plurality of groups can be transported into the second transport lane, and when the transport is possible, the transport is transported into the second transport lane and cannot be transported Is determined whether it can be loaded into the first transfer lane, and if it can be loaded into the first transfer lane, it is loaded into the first transfer lane.

  According to the present invention, in a component mounting line including a plurality of transfer lanes, components can be mounted on a multi-sided board with high productivity.

Configuration explanatory diagram of a component mounting line according to an embodiment of the present invention (A) The figure which shows the state before component mounting of an example of the multi-cavity board | substrate with which components are mounted in the component mounting line of one embodiment of this invention (b) The figure which shows the state after component mounting The block diagram which shows the structure of the control system of the component mounting line of one embodiment of this invention The flowchart of the 1st Example of the lane determination process in the component mounting line of one embodiment of this invention (A) (b) Explanatory drawing of the 1st Example of the lane determination process in the component mounting line of one embodiment of this invention The figure which shows the example by which the board | substrate was allocated to the conveyance lane by 1st Example of the lane determination process in the component mounting line of one embodiment of this invention The flowchart of 2nd Example of the lane determination process in the component mounting line of one embodiment of this invention (A) (b) (c) (d) Explanatory drawing of 2nd Example of the lane determination process in the component mounting line of one embodiment of this invention The flowchart of 3rd Example of the lane determination process in the component mounting line of one embodiment of this invention (A) (b) (c) (d) Explanatory drawing of the 3rd Example of the lane determination process in the component mounting line of one embodiment of this invention

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The configuration, shape, and the like described below are illustrative examples, and can be appropriately changed according to the specifications of the component mounting line. Below, the same code | symbol is attached | subjected to the element which respond | corresponds in all the drawings, and the overlapping description is abbreviate | omitted. In FIG. 1 and a part to be described later, as a biaxial direction orthogonal to each other in a horizontal plane, an X direction (horizontal direction in FIG. 1) in the substrate transport direction and a Y direction (front-back direction in FIG. 1) orthogonal to the substrate transport direction. Is shown. In FIG. 1, the left side of the drawing is referred to as the upstream side, the right side of the drawing is referred to as the downstream side, the lower side of the drawing is referred to as the front side, and the upper side of the drawing is referred to as the rear side.

  First, the configuration of the component mounting line 1 will be described with reference to FIG. The component mounting line 1 has a configuration in which the solder printing device M1, the board distribution device M2, and the component mounting devices M3 to M5 arranged in the X direction are connected by the communication network 2 and are controlled by the management computer 3 as a whole. Yes. The component mounting line 1 has a function of mounting the component P on a multi-sided substrate (hereinafter simply referred to as “substrate 4”) composed of a plurality of individual substrates 4a carried in from the upstream side.

  Here, the substrate 4 will be described with reference to FIGS. 2 (a) and 2 (b). 2A shows the substrate 4 before the component P is mounted, and FIG. 2B shows the substrate 4 after the component P is mounted. In FIG. 2A, the substrate 4 is formed with a plurality of individual substrates 4a (here, twelve) on which a circuit pattern C (not shown) including electrodes 4b bonded to the terminals of the component P is formed. Yes. That is, a plurality of circuit patterns C are formed on the substrate 4 (multiple substrate). As shown in FIG. 2B, the component P is mounted on the circuit pattern C so that the electrode 4b and the terminal of the component P are joined. The substrate 4 is separated into individual substrates 4a after all the components P are mounted.

  Some individual substrates 4a (here, four) have a bad mark B attached to the upper right corner of each individual substrate 4a. The bad mark B is a mark for identifying the individual substrate 4a in which the circuit pattern C has a defect such as a short circuit (short circuit) or a disconnection (open). In the component mounting line 1, the component P is not mounted on the defective individual substrate 4a (circuit pattern C) to which the bad mark B is attached.

  In FIG. 1, the solder printing apparatus M1 has a function of printing a solder paste for component bonding on the electrode 4b of the substrate 4. The solder printing apparatus M1 includes a pair of transport conveyors 12, a printing mechanism 13, and an inspection camera 14 that extend in the X direction on a base 11. The conveyer 12 conveys the substrate 4 and positions it at a predetermined printing work position, and carries the substrate 4 on which the solder paste is printed to the substrate sorting device M2 disposed on the downstream side. The printing mechanism 13 prints the solder paste on the substrate 4 positioned at the printing work position. In this way, the transport conveyor 12 and the printing mechanism 13 serve as a printing work unit 15 that carries in a series of solder printing operations for carrying the board 4 in, printing the solder paste, and carrying out the board 4 on which the solder paste has been printed.

  The inspection camera 14 moves relative to the upper side of the substrate 4 in the horizontal direction (XY direction) by a camera movement mechanism (not shown) or a combination of the camera movement mechanism and the transfer conveyor 12, and the electrode 4 b of the substrate 4. The solder paste printed on the substrate 4 and the bad mark B attached to the substrate 4 are imaged.

  The board distribution device M2 has a function of receiving the board 4 from the solder printing apparatus M1 and distributing it to any one of the first lane L1 and the second lane L2 provided in the component mounting apparatuses M3 to M5 described later. Have. The substrate sorting apparatus M2 includes a pair of conveyors 22 that extend in the X direction on the base 21. The conveyor 22 is movable in the Y direction by a conveyor moving mechanism (not shown) (arrow a). The conveyor 22 receives and holds the substrate 4 carried out from the solder printing apparatus M1.

  The conveyor moving mechanism moves the conveyor 22 to a position where the substrate 4 held by the conveyor 22 can be carried out to either the first lane L1 or the second lane L2. Thereafter, the transfer conveyor 22 carries the held substrate 4 to either the first lane L1 or the second lane L2. As described above, the conveyor 22 and the conveyor moving mechanism receive the board 4 from the solder printing apparatus M1, and distribute the board 4 to either the first lane L1 or the second lane L2 provided in the component mounting apparatuses M3 to M5. The distribution work unit 23 performs a series of substrate distribution operations (see FIG. 3).

  The component mounting apparatuses M3 to M5 have the same configuration, and the component mounting apparatus M3 will be described below. In addition, when it is necessary to distinguish the component mounting apparatuses M3 to M5, the first component mounting apparatus M3, the second component mounting apparatus M4, and the third component mounting apparatus M5 are referred to from the upstream side. The component mounting apparatus M3 has a function of mounting the component P on the board 4 that is sorted and carried by the board sorting apparatus M2. In the central portion of the base 31, a pair of first transport conveyors 32A extending in the X direction are provided on the rear side, and a pair of second transport conveyors 32B are provided on the front side in parallel with each other in the Y direction. For convenience, the first conveyor 32A and the second conveyor 32B are simply referred to as “conveyors 32A and 32B” unless it is necessary to distinguish between the first conveyor 32A and the second conveyor 32B.

  The transfer conveyors 32A and 32B transfer the substrate 4 carried out from the substrate distribution device M2 and position it at a predetermined mounting work position (the position of the substrate 4 shown by a solid line in FIG. 1), and the substrate 4 on which the component P is mounted. Has a function of carrying out the operation to a downstream apparatus. Component supply units 33A and 33B are disposed on both sides of the conveyors 32A and 32B, respectively. A plurality of tape feeders 34 arranged in the X direction are set in the component supply units 33A and 33B. The tape feeder 34 pitches the parts P held on the carrier tape and supplies them to the pick-up positions by the mounting heads 35A and 35B.

  The mounting heads 35A and 35B are moved in the horizontal direction (XY direction) by a head moving mechanism (not shown), pick up the components P supplied from the component supply units 33A and 33B, respectively, and are positioned at the mounting work positions. 4 is implemented. At this time, the mounting head 35A may target only the substrate 4 transported by the first transport conveyor 32A, or may target both the substrates 4 transported by the two transport conveyors 32A and 32B. Similarly, the mounting head 35B may target only the substrate 4 transported by the second transport conveyor 32B or may target both the substrates 4 transported by the two transport conveyors 32A and 32B.

  As described above, the conveyors 32A and 32B, the component supply units 33A and 33B, the mounting heads 35A and 35B, and the head moving mechanism mount the component P on the substrate 4 distributed from the substrate distribution device M2 at the mounting operation position. It becomes the mounting work part 36 (refer FIG. 3) carried out to the apparatus of a downstream side.

  In FIG. 1, the first transfer conveyors 32A of the first component mounting apparatus M3, the second component mounting apparatus M4, and the third component mounting apparatus M5 are connected to each other to form a first transfer lane (hereinafter, “first lane L1”). Is configured.). Similarly, the second conveyor 32B of the first component mounting apparatus M3, the second component mounting apparatus M4, and the third component mounting apparatus M5 are connected to each other to form a second conveyance lane (hereinafter referred to as “second lane L2”). Construct.).

  The substrate 4 distributed from the substrate distribution device M2 is transferred to the first lane L1 and the second lane L2, respectively, and each of the first component mounting device M3, the second component mounting device M4, and the third component mounting device M5 is mounted. The component P is mounted at the work position. That is, the component mounting line 1 is configured by connecting a plurality of component mounting apparatuses M3 to M5 each having a plurality of transport lanes (first transport conveyor 32A and second transport conveyor 32B) each having a mounting work position. The component mounting line 1 includes a plurality of transfer lanes (first lane L1 and second lane L2) each having a plurality of mounting work positions for mounting the component P on the substrate 4.

  Next, the configuration of the control system of the component mounting line 1 will be described with reference to FIG. The solder printing apparatus M1 includes a print control unit 16, a print storage unit 17, a print work unit 15, an inspection camera 14, and a communication unit 18. The print storage unit 17 stores data such as defect pattern information 17a as well as work parameters necessary for the control of each unit by the print control unit 16. The print control unit 16 controls the printing operation unit 15 to execute a solder printing operation for printing the solder paste on the substrate 4. Further, the print control unit 16 inspects the solder paste printed on the substrate 4 imaged by the inspection camera 14, and the position of the individual substrate 4 a (circuit pattern C) having a printing defect such as chipping or crushing, in the substrate 4. Information such as the number of defects is stored in the print storage unit 17 as defect pattern information 17a.

  Further, the print control unit 16 detects the bad mark B attached to the substrate 4 imaged by the inspection camera 14, the position of the individual substrate 4 a (circuit pattern C) to which the bad mark B is attached, and the bad in the substrate 4. Information such as the number of marks B is stored in the print storage unit 17 as defective pattern information 17a. That is, the inspection camera 14 and the print control unit 16 serve as a defect detection unit that detects the number of defective circuit patterns C (hereinafter referred to as “number of defects N”) on the substrate 4 (multiple substrate). The communication unit 18 is a communication interface, and exchanges signals and data with the management computer 3 and the board distribution device M2 via the communication network 2. The defect pattern information 17a is transmitted to the management computer 3 via the communication unit 18.

  The substrate distribution device M2 includes a distribution control unit 24, a distribution storage unit 25, a distribution work unit 23, and a communication unit 26. The distribution storage unit 25 stores data such as a distribution destination of the board 4 transmitted from a lane determination processing unit 41b of the management computer 3 to be described later, in addition to work parameters necessary for the control of the distribution work unit 23 by the distribution control unit 24. To do. The distribution control unit 24 controls the distribution operation unit 23 to execute a substrate distribution operation for distributing the substrate 4 to either the first lane L1 or the second lane L2. The communication unit 26 is a communication interface, and exchanges signals and data with the management computer 3, the solder printing apparatus M1, and the component mounting apparatuses M3 to M5 via the communication network 2.

  The control systems of the component mounting apparatuses M3 to M5 have the same configuration. Hereinafter, the component mounting apparatus M3 (first component mounting apparatus M3) will be described. The component mounting apparatus M3 includes a mounting control unit 37, a mounting storage unit 38, a mounting work unit 36, and a communication unit 39. The mounting storage unit 38 stores data such as defect pattern information 38 a transmitted from the management computer 3 in addition to work parameters necessary for controlling the mounting work unit 36 by the mounting control unit 37. In the defect pattern information 38a, the position of the defective circuit pattern C on the substrate 4 (multiple substrate) to be mounted is stored. The mounting control unit 37 controls the mounting operation unit 36 to position the substrate 4 at the mounting operation position, refers to the defect pattern information 38a, and mounts the component P on the individual substrate 4a (circuit pattern C) that is not defective. Let the work be performed.

  The communication unit 39 is a communication interface, and exchanges signals and data with the management computer 3, the board sorting apparatus M2, and the other component mounting apparatuses M4 to M5 via the communication network 2. Further, the mounting control unit 37 of the component mounting apparatuses M3 to M5 synchronizes the board 4 in the first lane L1 or the second lane L2 according to a signal from the management computer 3 or a board transport signal between the component mounting apparatuses M3 to M5. Then, it is transported to a downstream device (mounting work position). In addition, the status of component mounting work in the component mounting apparatuses M <b> 3 to M <b> 5 is transmitted to the management computer 3 via the communication unit 39.

  The management computer 3 includes a management control unit 41, a management storage unit 42, an operation / input unit 43, a display unit 44, and a communication unit 45. The management control unit 41 is an arithmetic device such as a CPU, and has internal processing units such as a defective pattern number acquisition unit 41a and a lane determination processing unit 41b. The management storage unit 42 is a storage device and stores component pattern data for controlling the component mounting line 1 as well as defective pattern information 42a.

  The operation / input unit 43 is an input device such as a keyboard, a touch panel, or a mouse, and is used when an operation command or data is input. The display unit 44 is a display device such as a liquid crystal panel, and displays various data such as the defect pattern information 42a in addition to the operation screen. The communication unit 45 is a communication interface, and exchanges signals and data with the solder printing apparatus M1, the board distribution apparatus M2, and the component mounting apparatuses M3 to M5 via the communication network 2.

  The defect pattern information 42a is obtained by transmitting and storing the defect pattern information 17a acquired in the solder printing apparatus M1, and the position of the defective individual substrate 4a (circuit pattern C) on the substrate 4 (multiple substrate). Information such as the number N of defects is stored. The defective pattern information 42a is transmitted to the component mounting apparatuses M3 to M5 and stored in the mounting storage unit 38 as defective pattern information 38a.

  The defective pattern information 42a is not limited to information acquired by the solder printing apparatus M1. For example, the substrate 4 on which the component P is mounted on the component mounting line 1 (multi-planar substrate) such as information (inspection result) attached to the substrate 4 delivered from the substrate manufacturer or information acquired by an inspection device (not shown) Information on the position of the defective individual substrate 4a (circuit pattern C) in FIG.

  The number of defective pattern acquisition unit 41a is based on the defect pattern information 42a, and the number of defective individual substrates 4a (circuit patterns C) in the substrate 4 (multiple substrate) on which the component P is mounted in the component mounting apparatuses M3 to M5 ( The number of defects N) is obtained. The lane determination processing unit 41b includes the number N of defects acquired by the defect pattern number acquisition unit 41a, the state of component mounting work of the board 4 in the first lane L1 and the second lane L2 (the presence or absence of the board 4 at each mounting work position, etc. ) Is executed to determine which of the first lane L1 and the second lane L2 the board 4 held by the board sorter M2 is to be sorted.

  The distribution destination of the substrate 4 determined by the lane determination processing unit 41b is transmitted to the substrate distribution device M2, and the distribution lane (first lane L1, second lane 2) in which the substrate 4 held by the substrate distribution device M2 is determined by the distribution operation unit 23. Sorted to lane L2) and carried out. That is, the lane determination processing unit 41b and the distribution work unit 23 are arranged on any of the plurality of transport lanes (first lane L1, second lane L2) based on the number N of defects (number of defective circuit patterns C). It becomes a distribution unit for distributing (multi-sided substrate).

  Next, in accordance with the flow of FIG. 4, with reference to FIGS. 5 and 6, the lane determination executed in the component mounting method for mounting the component P on the substrate 4 (multiple substrate) in the component mounting line 1 A first embodiment of processing will be described. The lane determination process is executed when the board 4 on which the solder paste is printed is carried into a plurality of conveyance lanes (first lane L1, second lane L2) included in the component mounting line 1. Here, the flow from the state in which the substrate 4 is held by the substrate distribution device M2 to the distribution to either the first lane L1 or the second lane L2 will be described. The component supply units 33A and 33B of the component mounting apparatuses M3 to M5 have components P distributed in advance so that the component mounting time per individual substrate 4a at each mounting work position is substantially the same. And

  In FIG. 4, when the substrate 4 (1) is held by the substrate distribution device M2, the defect pattern number acquisition unit 41a of the management computer 3 displays the number N of defects of the substrate 4 (1) (the number of defective circuit patterns C). (ST11: first defect pattern number acquiring step). The defective pattern number acquisition unit 41a acquires the latest defective pattern information 17a from the solder printing apparatus M1 when there is no information on the target substrate 4 (1) in the defective pattern information 42a stored in the management storage unit 42. To do. Thus, in the first defective pattern number acquisition step (ST11), the number of defective circuit patterns C (number of defects N) in the multi-sided substrate (substrate 4) is acquired.

  Next, the lane determination processing unit 41b determines whether or not the number N of defects of the substrate 4 (1) is larger than a predetermined number R (first number) that is smaller than the total number of individual substrates 4a of the substrate 4 (multiple substrate). Determine (ST12: first determination step). The number R takes into consideration the distribution of the number of defects N on the board 4 based on the experimental results, production results, operator experience, etc. so that the total waiting time in the component mounting apparatuses M3 to M5 is reduced. It is decided.

  In FIG. 4, when the number N of defects of the substrate 4 (1) is greater than the number R (Yes in ST12), the substrate 4 (1) is carried into the first lane L1 (first transport lane) as the first group G1. (ST13). Specifically, the lane determination processing unit 41b transmits a signal to the substrate distribution device M2 so as to carry the substrate 4 (1) into the first lane L1, and the substrate distribution device M2 holds the substrate 4 (1). Are transferred to the first lane L1. That is, the lane determination processing unit 41b sets the multi-sided board (board 4) having the number of defective circuit patterns C (number of defects N) larger than the first number (number R) as the first group G1, and sets the board sorting apparatus M2. Carries the first group G1 into the first transport lane (first lane L1) among the plurality of transport lanes.

  FIG. 5A schematically shows the operation of the component mounting line 1 in (ST13). In (ST13), the substrate sorting apparatus M2 moves (sorts) the transfer conveyor 22 along the first lane L1, and carries the substrate 4 (1) to the first lane L1 (arrow b1). In (ST13), when there is a board 4 that is undergoing component mounting work at the mounting work position of the first lane L1 of the first component mounting apparatus M3, the board sorting apparatus M2 is connected to the first lane L1 of the first component mounting apparatus M3. After waiting until the board 4 is unloaded from the mounting work position, the board 4 (1) is unloaded to the first lane L1.

  In FIG. 4, when the defect number N of the substrate 4 (1) is equal to or less than the number R (No in ST12), the substrate 4 (1) is carried into the second lane L2 (second conveyance lane) as the second group G2. (ST14). Specifically, the lane determination processing unit 41b transmits a signal to the substrate distribution device M2 so as to carry the substrate 4 (1) into the second lane L2, and the substrate distribution device M2 holds the substrate 4 (1). Is carried out to the second lane L2. That is, the lane determination processing unit 41b sets the multi-sided substrate (substrate 4) having the number of defective circuit patterns C (number of defects N) equal to or less than the first number (number R) as the second group G2, and sets the substrate sorting apparatus M2 Carries the second group G2 into the second transportation lane (second lane L2) among the plurality of transportation lanes.

  FIG. 5B schematically shows the operation of the component mounting line 1 in (ST14). In (ST14), the substrate sorting apparatus M2 moves (sorts) the transfer conveyor 22 along the second lane L2, and carries the substrate 4 (1) to the second lane L2 (arrow b2). In (ST14), when there is a board 4 that is in the process of component mounting at the mounting work position of the second lane L2 of the first component mounting apparatus M3, the board distributing apparatus M2 is connected to the second lane L2 of the first component mounting apparatus M3. After waiting until the board 4 is unloaded from the mounting work position, the board 4 (1) is unloaded to the second lane L2.

  Next, the effect of the lane determination process will be described with reference to FIG. FIG. 6 shows an example in which the number R is set to “5” and the substrates 4 are allocated to the first lane L1 and the second lane L2. # 1A, # 2A, and # 3A indicate mounting work positions of the component mounting apparatuses M3 to M5 in the first lane L1, respectively. # 1B, # 2B, and # 3B indicate mounting work positions of the component mounting apparatuses M3 to M5 in the second lane L2, respectively. Among the items in the table, “number of defects N” indicates the number of defective circuit patterns C, “number of non-defective products” indicates the number of normal circuit patterns C, and “working time” indicates the time required for component mounting work. “Standby time” indicates the time to wait after the component mounting operation is completed before being carried out to the downstream apparatus.

  In this example, the work time at each mounting work position is set uniformly, and is 10 seconds per individual substrate 4a (circuit pattern C). In the first lane L1, the substrates 4 of the first group G1 having a defect number N greater than “5” are allocated, # 1A has a defect number N of “6”, and # 2A has a defect number. There is a substrate 4 in which N is “11” and # 3A has a defect number N of “8”. The tact time of the first lane L1 is determined by the working time of the substrate 4 having the smallest number of defects N, that is, the largest number of non-defective products, and in this example is 60 seconds of working time in # 1A.

  In the second lane L2, the substrates 4 of the second group G2 having the number of defects N of “5” or less are distributed, the number of defects N is “2” for # 1B, and the number of defects is # 2B. There is a substrate 4 in which N is “0” and # 3B has a defect number N of “5”. The tact time of the second lane L2 is determined by the working time of the substrate 4 having the smallest number of defects N, that is, the largest number of non-defective products. In this example, the working time is 120 seconds in # 2B. The tact time changes at any time according to the number N of defects of the substrates 4 in each transport lane.

  The maximum waiting time that can occur when the boards 4 are randomly assigned to the transfer lanes is that the board 4 with all the faults N is “0” if the board 4 with all faults is not put into the component mounting line 1. The difference in work time between the substrate 4 (the number of non-defective products is 12) and the substrate 4 (the number of non-defective products is 1) of 110 is 110 seconds. On the other hand, in the first embodiment of the lane determination process, based on the number of defects N (the number of defective circuit patterns C), the substrates 4 (multi-planar substrates) are divided into a plurality of groups with the number of defects N close to each other. The substrate 4 (multiple substrate) is distributed to any one of the plurality of transfer lanes (first lane L1, second lane L2).

  As a result, the maximum waiting time that can occur in the first lane L1 is the first “11” substrates 4 having the largest number of defects N among the substrates 4 of the first group G1 when the tact time is 60 seconds. It is 50 seconds when it is in lane L1 (corresponding to # 2A). In addition, the maximum standby time that can occur in the second lane L2 is that when the tact time is 120 seconds, among the substrates 4 of the second group G2, “5” substrates 4 with the largest number of defects N are in the second lane L2. Is 50 seconds (corresponding to # 3B). That is, the waiting time is shortened by 60 seconds at the maximum compared to the case where the substrates 4 are randomly distributed, and the productivity of the mounting substrate can be improved.

  As described above, the distribution unit (lane determination processing unit 41b and distribution work unit 23) of the first embodiment of the lane determination process uses the multi-sided substrate (substrate 4) as the number of defective circuit patterns C (number of defects N). ) Is divided into multiple groups. Then, the distribution unit sets the multi-sided substrate (substrate 4) having a number of defective circuit patterns (number of defects N) larger than the first number (number R) as the first group G1, and the first of the plurality of groups is the first group G1. The group G1 is carried into the first transport lane (first lane L1) among the plurality of transport lanes.

  Then, the distribution unit sets the second group G2 as a multi-sided substrate (substrate 4) having a number of defective circuit patterns (number N of defects) equal to or less than the first number (number R), and sets the second group G2 as the second group G2. The group G2 is carried into the second transportation lane (second lane L2) among the plurality of transportation lanes. As a result, in the component mounting line 1 having a plurality of transport lanes, the waiting time in the transport lanes (first lane L1, second lane L2) is reduced, and the component P is formed on the multi-sided board (board 4) with high productivity. Can be implemented.

  Next, according to the flow of FIG. 7, a second embodiment of the lane determination process will be described with reference to FIG. The second embodiment is different from the first embodiment in that the substrate 4 is divided into three groups. When the substrate 4 (2) is held by the substrate sorting apparatus M2, the defective pattern number acquisition unit 41a acquires the number of defects N of the substrate 4 (2) (ST21: second defective pattern number acquisition step). Next, the lane determination processing unit 41b determines whether or not the defect number N of the substrate 4 (2) is larger than a predetermined number S (first number) that is smaller than the total number of the individual substrates 4a of the substrate 4 (ST22: No. 1). 2 determination step).

  In FIG. 7, when the number N of defects of the substrate 4 (2) is larger than the number S (Yes in ST22), the substrate 4 (2) is carried into the first lane L1 (first transport lane) as the first group G1. (ST23). That is, the lane determination processing unit 41b sets the multi-planar board (board 4) having the number of defective circuit patterns C (number of defects N) larger than the first number (number S) as the first group G1, and sets the board sorting apparatus M2. Carries the first group G1 into the first transport lane (first lane L1) among the plurality of transport lanes.

  FIG. 8A schematically shows the operation of the component mounting line 1 in (ST23). In (ST23), the substrate sorting apparatus M2 carries the substrate 4 (2) to the first lane L1 (arrow c1). In (ST23), when there is a board 4 that is undergoing component mounting work at the mounting work position of the first lane L1 of the first component mounting apparatus M3, the board sorting apparatus M2 is connected to the first lane L1 of the first component mounting apparatus M3. After waiting until the board 4 is unloaded from the mounting work position, the board 4 (2) is unloaded to the first lane L1.

  In FIG. 7, when the number of defects N of the substrate 4 (2) is equal to or less than the number S (No in ST22), the lane determination processing unit 41b has a predetermined number T in which the number of defects N of the substrate 4 (2) is smaller than the number S. It is determined whether it is less than (second number) (ST24: third determination step). The number S and the number T are based on experimental results, production results, operator experience, etc. so that the total of the waiting time in the component mounting apparatuses M3 to M5 and the waiting time in the board distribution apparatus M2 is reduced. The distribution is determined in consideration of the distribution of the number N of defects of the substrate 4.

  When the number of defects N of the substrate 4 (2) is smaller than the number T (Yes in ST24), the substrate 4 (2) is carried into the second lane L2 (second transport lane) as the second group G2 (ST25). ). That is, the lane determination processing unit 41b sets the multi-planar substrate (substrate 4) having the number of defective circuit patterns C (number of defects N) smaller than the first number (number S) and smaller than the second number (number T). In the second group G2, the substrate sorting apparatus M2 carries the second group G2 into the second transport lane (second lane L2) among the plurality of transport lanes.

  FIG. 8B schematically shows the operation of the component mounting line 1 in (ST25). In (ST25), the substrate sorting apparatus M2 carries the substrate 4 (2) out to the second lane L2 (arrow c2). In (ST25), when there is a board 4 that is in the process of component mounting at the mounting work position of the second lane L2 of the first component mounting apparatus M3, the board sorting apparatus M2 is connected to the second lane L2 of the first component mounting apparatus M3. After waiting until the substrate 4 is unloaded from the mounting work position, the substrate 4 (2) is unloaded to the second lane L2.

  In FIG. 7, when the defect number N of the substrate 4 (2) is equal to or greater than the number T (No in ST24), the lane determination processing unit 41b sets the substrate 4 (2) as the third group G3, and enters the second lane L2. It is determined whether or not loading is possible (ST26: fourth determination step). When it is possible to carry in the second lane L2 (Yes in ST26), the substrate 4 (2) is carried into the second lane L2 (ST25).

  When the second lane L2 cannot be loaded (No in ST26), the lane determination processing unit 41b determines whether or not the board 4 (2) can be loaded into the first lane L1 (ST27: fifth determination step). When it is possible to carry in the first lane L1 (Yes in ST27), the substrate 4 (2) is carried into the first lane L1 as the third group G3 (ST23). When it cannot carry in to the 1st lane L1 (in ST27 No), it returns to the 4th determination process (ST26), and the possibility of carrying in to the 2nd lane L2 is determined.

  That is, the lane determination processing unit 41b has a number of defective circuit patterns (number of defects N) equal to or less than the first number (number S) and equal to or more than the second number (number T) (substrate 4). Is the third group G3, and the substrate sorting apparatus M2 transports the third group G3 in either the first lane L1 (first transport lane) or the second lane L2 (second transport lane). Carrying into the lane. As a result, the waiting time in the transfer lanes (the first lane L1 and the second lane L2) is shortened, and when there is a transfer lane that can be loaded, the substrate sorting apparatus M2 waits while holding the substrate 4 (2). Time can be reduced and productivity of the mounting board can be improved.

  FIG. 8C schematically shows the operation of the component mounting line 1 in (ST26) and (ST27). In (ST26) and (ST27), when there is a substrate 4 in the component mounting operation at the mounting positions of the first lane L1 and the second lane L2 of the first component mounting device M3, the substrate distribution device M2 is connected to the substrate 4 ( 2) Wait without sorting. As shown in FIG. 8 (d), in (ST26) and (ST27), the board 4 (2) is carried into one of the mounting work positions of the first lane L1 and the second lane L2 of the first component mounting apparatus M3. If possible, the substrate sorting apparatus M2 carries the substrate 4 (2) out to a transferable lane (here, the second lane L2) (arrow c3).

  In (ST26) and (ST27), when the substrate 4 (2) can be carried into any of the conveyance lanes, the substrate 4 (2) is preferentially carried out to the second lane L2, which is a conveyance lane having a long tact time. As a result, it is possible to prevent the third group G3 having a longer work time than the first group G1 from being loaded into the first lane L1 having a shorter tact time and increasing the tact time of the first lane L1.

  As described above, the distribution unit (lane determination processing unit 41b and distribution work unit 23) of the second embodiment of the lane determination process has the number of defective circuit patterns (number of defects N) as the first number (number S). ) The more multi-planar substrate (substrate 4) is the first group G1, and the number of defective circuit patterns (number N of defects) is less than the second number (number T) less than the first number (number S). The multi-sided substrate (substrate 4) is a second group G2.

  Then, the distribution unit transfers the multi-sided substrate (substrate 4) having a number of defective circuit patterns (number of defects N) equal to or smaller than the first number (number S) and equal to or larger than the second number (number T) to a plurality of groups. The third group G3 is included, and the third group G3 is loaded into one of the first transfer lane (first lane L1) and the second transfer lane (second lane L2). Yes. Thereby, in the component mounting line 1 having a plurality of transfer lanes, the waiting time in the distribution unit (substrate distribution device M2) or the transfer lanes (first lane L1, second lane L2) is reduced, and the multi-sided substrate ( The component P can be mounted on the substrate 4) with high productivity.

  Next, according to the flow of FIG. 9, a third embodiment of the lane determination process will be described with reference to FIG. When the substrate 4 cannot be loaded into the predetermined transfer lane, the first embodiment waits until the predetermined transfer lane becomes empty. In the third embodiment, if there is a transfer lane that can be loaded, the transfer lane is loaded. Different. When the substrate 4 (3) is held in the substrate sorting apparatus M2, the defective pattern number acquisition unit 41a acquires the number of defects N of the substrate 4 (3) (ST31: third defective pattern number acquisition step).

  Next, the lane determination processing unit 41b determines whether or not the number of defects N of the substrate 4 (3) is greater than a predetermined number U (first number) that is smaller than the total number of individual substrates 4a of the substrate 4 (multiple substrate). (ST32: sixth determination step). The number U is determined based on the experimental results, production results, operator experience, and the like so that the total waiting time in the component mounting apparatuses M3 to M5 and the waiting time in the board distribution apparatus M2 is reduced. The distribution is determined in consideration of the distribution of the number N of defects.

  In FIG. 9, when the number N of defects of the board 4 (3) is larger than the number U (Yes in ST32), the lane determination processing unit 41b sets the board 4 (3) as the first group G1 and the first lane L1. It is determined whether or not loading is possible (ST33: seventh determination step). When it is possible to carry in the first lane L1 (Yes in ST33), the substrate 4 (3) is carried into the first lane L1 (ST34) (arrow d1 in FIG. 10A). When it is not possible to carry in the first lane L1 (No in ST33), the lane determination processing unit 41b determines whether or not the substrate 4 (3) can be loaded into the second lane L2 (ST35: eighth determination step). When it is possible to carry in the second lane L2 (Yes in ST35), the substrate 4 (3) is carried into the second lane L2 (ST36) (arrow d2 in FIG. 10B).

  In FIG. 9, when the number N of defects of the substrate 4 (3) is equal to or less than the number U (No in ST32), the lane determination processing unit 41b sets the substrate 4 (3) as the second group G2 and sets the eighth determination step ( Proceeding to ST35), it is determined whether or not the substrate 4 (3) can be carried into the second lane L2. When the second lane L2 can be loaded (Yes in ST35), the substrate 4 (3) is loaded into the second lane L2 (ST36) (arrow d3 in FIG. 10C). When the second lane L2 cannot be loaded (No in ST35), the lane determination processing unit 41b proceeds to the seventh determination step (ST33) and determines whether the substrate 4 (3) can be loaded into the first lane L1. . When it is possible to carry in the first lane L1 (Yes in ST33), the substrate 4 (3) is carried into the first lane L1 (ST34) (arrow d4 in FIG. 10D).

  As described above, the distribution unit (lane determination processing unit 41b and distribution work unit 23) of the third embodiment of the lane determination process uses the number of defective circuit patterns C (number of defects N) as the multi-sided substrate (substrate 4). ) Is divided into multiple groups. In the distribution unit, a multi-sided substrate (substrate 4) in which the number of defective circuit patterns (number N of defects) is larger than the first number (number U) is set as the first group G1. Then, the sorting unit determines whether the first group G1 among the plurality of groups can be carried into the first conveyance lane (first lane L1) among the plurality of conveyance lanes. If it is impossible to carry in, it is determined whether it can be carried into the second conveyance lane (second lane L2) among the plurality of conveyance lanes. If it can be carried into the second lane L2, the second lane L2 is entered. Carrying in.

  Further, the distribution unit sets the second group G2 as multi-sided substrates (substrates 4) in which the number of defective circuit patterns (number of defects N) is equal to or less than the first number (number U). Then, the sorting unit determines whether the second group G2 of the plurality of groups can be carried into the second conveyance lane (second lane L2) of the plurality of conveyance lanes. If it is impossible to carry in, it is determined whether it can be carried into the first conveyance lane (first lane L1) of the plurality of conveyance lanes. If it can be carried into the first lane L1, the first lane L1 is entered. Carrying in.

  As a result, in the component mounting line 1 including a plurality of transfer lanes, the waiting time in the board distribution device M2 or the transfer lanes (first lane L1, second lane L2) is reduced, so that a multi-sided board (board 4) is obtained. The component P can be mounted with high productivity. For example, even when the boards 4 carried into the component mounting line 1 are continuously in the first group G1, the first group G1 is also distributed to the second lane L2 to reduce the waiting time in the distribution unit. Can improve productivity.

  In addition, although the component mounting line 1 of this Embodiment demonstrated above is comprised by connecting three component mounting apparatuses M3-M5, the component mounting line 1 is not limited to this structure. For example, the component mounting apparatuses M3 to M5 may be configured by connecting two units or by connecting four or more units. In addition, component mounting apparatuses M3 to M5 each having two or more mounting work positions are used for each transport lane (first lane L1 and second lane L2) of one component mounting apparatus M3 to M5. The component mounting line 1 may be configured with one device M3 to M5. Further, the bad mark B attached to the substrate 4 may be detected by a solder printing inspection device for inspecting the state of the solder paste printed on the substrate 4 (not shown) other than the solder printing device M1.

  The component mounting method and the component mounting line according to the present invention have an effect that a component can be mounted on a multi-sided board with high productivity in a component mounting line including a plurality of conveyance lanes. Useful in the packaging field.

1 Component mounting line 4 Substrate (multi-sided substrate)
L1 first lane (first transport lane)
L2 Second lane (second transport lane)
M3 to M5 component mounting equipment P component

Claims (6)

In a component mounting line having a plurality of transfer lanes each having a plurality of mounting work positions for mounting components on a board, a component mounting method for mounting components on a multi-sided board on which a plurality of circuit patterns are formed,
Obtaining the number of defective circuit patterns in the multi-sided substrate;
Dividing the multi-sided substrate into a plurality of groups in which the number of defective circuit patterns is close,
It is determined whether the first group of the plurality of groups can be loaded into the first conveyance lane of the plurality of conveyance lanes. If the first group can be loaded, the first group is loaded into the first conveyance lane and cannot be loaded. In the case, it is determined whether it is possible to carry in the second transportation lane among the plurality of transportation lanes. If the transportation can be carried into the second transportation lane, the transportation lane is carried into the second transportation lane,
It is determined whether the second group of the plurality of groups can be carried into the second transportation lane. If the second group can be carried in, the second group is carried into the second transportation lane. If the loading is impossible, the first transportation is performed. A component mounting method in which it is determined whether loading into a lane is possible, and when loading into the first conveyance lane is possible, loading into the first conveyance lane is performed. The multi-sided substrate having the number of defective circuit patterns larger than the first number is the first group,
2. The component mounting method according to claim 1, wherein the plurality of chamfered boards having the number of defective circuit patterns equal to or less than the first number is set as the second group.   The component mounting method according to claim 1, wherein the component mounting line is configured by connecting a plurality of component mounting apparatuses each having a plurality of transfer lanes each having the mounting work position. A plurality of transfer lanes each having a plurality of mounting work positions for mounting components on the board;
A defective pattern number acquisition unit for acquiring the number of defective circuit patterns in the multi-sided substrate;
A distribution unit that distributes the multi-sided substrate to any of the plurality of transport lanes based on the number of defective circuit patterns;
The sorting unit is
Dividing the multi-sided substrate into a plurality of groups in which the number of defective circuit patterns is close,
It is determined whether the first group of the plurality of groups can be loaded into the first conveyance lane of the plurality of conveyance lanes. If the first group can be loaded, the first group is loaded into the first conveyance lane and cannot be loaded. In the case, it is determined whether it is possible to carry in the second transportation lane among the plurality of transportation lanes. If the transportation can be carried into the second transportation lane, the transportation lane is carried into the second transportation lane,
It is determined whether the second group of the plurality of groups can be carried into the second transportation lane. If the second group can be carried in, the second group is carried into the second transportation lane. If the loading is impossible, the first transportation is performed. A component mounting line that determines whether it can be loaded into a lane and loads the first transfer lane when it can be loaded into the first transfer lane. The sorting unit is
The multi-sided substrate having the number of defective circuit patterns larger than the first number is the first group,
5. The component mounting line according to claim 4, wherein the multi-sided substrate having the number of defective circuit patterns equal to or less than the first number is the second group.   The component mounting line according to claim 4, wherein the component mounting line is configured by connecting a plurality of component mounting apparatuses each having a plurality of conveyance lanes each having the mounting work position.

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