JP2017126798A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of an SGT having a structure for functioning an upper part of a columnar semiconductor layer as an n type semiconductor layer or a p type semiconductor layer by self align depending on a difference in work functions of metal and semiconductor; and provide a contact structure and the SGT structure which are obtained in the result of the manufacturing method.SOLUTION: A semiconductor device manufacturing method comprises: a first step of forming an insulation film around a fin-like semiconductor layer; a second step of forming a first columnar semiconductor layer, a first dummy gate by first polysilicon, a second columnar semiconductor layer and a second dummy gate by the first polysilicon; a third step of forming a third dummy gate and a fourth dummy gate on sidewalls of the first dummy gate, the first columnar semiconductor layer, the second dummy gate and the second columnar semiconductor layer; a fourth step of forming a third diffusion layer on an upper part of the fin-like semiconductor layer, a lower part of the first columnar semiconductor layer and a lower part of the second columnar semiconductor layer; and subsequent fifth and sixth steps of obtaining the above-described structure.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.

  Semiconductor integrated circuits, in particular integrated circuits using MOS transistors, are becoming increasingly highly integrated. Along with this high integration, the MOS transistors used therein have been miniaturized to the nano region. When the miniaturization of such a MOS transistor progresses, it is difficult to suppress the leakage current, and there is a problem that the occupied area of the circuit cannot be easily reduced due to a request for securing a necessary amount of current. In order to solve such a problem, a Surrounding Gate Transistor (hereinafter referred to as “SGT”) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and a gate electrode surrounds a columnar semiconductor layer is proposed. (For example, see Patent Document 1, Patent Document 2, and Patent Document 3).

In a conventional SGT manufacturing method, a silicon pillar in which a nitride film hard mask is formed in a columnar shape is formed using a mask for drawing a silicon pillar, and a silicon pillar is drawn using a mask for drawing a planar silicon layer. A planar silicon layer is formed at the bottom, and a gate wiring is formed using a mask for drawing the gate wiring (see, for example, Patent Document 4).
That is, a silicon pillar, a planar silicon layer, and a gate wiring are formed using three masks.

  Further, in the conventional SGT manufacturing method, deep contact holes are formed in order to connect the upper part of the planar silicon layer and the metal wiring (see, for example, Patent Document 4). As the device becomes finer, the aspect ratio (depth / opening) of the contact hole increases. Etching rate decreases with increasing aspect ratio. In addition, as the pattern becomes finer, the resist film thickness becomes thinner. When the thickness of the resist is reduced, the resist is also etched during the etching, so that it becomes difficult to form a deep contact hole.

  Further, in a conventional MOS transistor, in order to achieve both a metal gate process and a high temperature process, a metal gate last process for creating a metal gate after a high temperature process is used in an actual product (Non-Patent Document 1). After forming a gate with polysilicon, an interlayer insulating film is deposited, then the polysilicon gate is exposed by chemical mechanical polishing, and after etching the polysilicon gate, a metal is deposited. Therefore, also in SGT, in order to make a metal gate process and a high temperature process compatible, it is necessary to use the metal gate last process which produces a metal gate after a high temperature process.

  In the metal gate last process, after a polysilicon gate is formed, a diffusion layer is formed by ion implantation. In SGT, since the upper part of the columnar silicon layer is covered with the polysilicon gate, a device is required.

When the silicon pillar is thinned, the density of silicon is 5 × 10 ²² pieces / cm ³ , so that it becomes difficult for impurities to exist in the silicon pillar.

In the conventional SGT, it has been proposed to determine the threshold voltage by changing the work function of the gate material by setting the channel concentration to a low impurity concentration of 10 ¹⁷ cm ⁻³ or less (see, for example, Patent Document 5). ).

  In the planar MOS transistor, the sidewall of the LDD region is formed of polycrystalline silicon having the same conductivity type as that of the low concentration layer, and the surface carrier of the LDD region is induced by the work function difference, so that the oxide film sidewall LDD type MOS It has been shown that the impedance of the LDD region can be reduced as compared with a transistor (see, for example, Patent Document 6). The polycrystalline silicon sidewall is shown to be electrically insulated from the gate electrode. In the figure, it is shown that the polysilicon side wall and the source / drain are insulated by an interlayer insulating film.

  In order to reduce the parasitic capacitance between the gate wiring and the substrate, the conventional MOS transistor uses the first insulating film. For example, in FINFET (Non-patent Document 2), a first insulating film is formed around one fin-like semiconductor layer, the first insulating film is etched back, the fin-like semiconductor layer is exposed, and the gate wiring and the substrate The parasitic capacitance between them is reduced. Therefore, also in SGT, it is necessary to use the first insulating film in order to reduce the parasitic capacitance between the gate wiring and the substrate. In SGT, since there is a columnar semiconductor layer in addition to the fin-shaped semiconductor layer, a device for forming the columnar semiconductor layer is required.

JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2009-182317 A JP 2004-356314 A JP 11-297984 A

IEDM2007 K. Mistry et.al, pp 247-250 IEDM2010 CC.Wu, et.al, 27.1.1-27.1.4.

  Therefore, in the gate last process, the gate electrode and the gate wiring are formed around the first columnar semiconductor layer, and at the same time, the contact electrode and the contact wiring connected to the upper portion of the fin-shaped semiconductor layer are formed around the second columnar semiconductor layer. A method of manufacturing an SGT having a structure in which the upper part of the columnar semiconductor layer functions as an n-type semiconductor layer or a p-type semiconductor layer by a work function difference between the metal and the semiconductor, and a contact structure and an SGT obtained as a result. The purpose is to provide a structure.

  The method for manufacturing a semiconductor device of the present invention includes a first step of forming a fin-like semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-like semiconductor layer, and after the first step, A second step of forming a first columnar semiconductor layer, a first dummy gate made of the first polysilicon, a second columnar semiconductor layer, and a second dummy gate made of the first polysilicon; After the step, a third dummy gate and a fourth dummy gate are formed on the side walls of the first dummy gate, the first columnar semiconductor layer, the second dummy gate, and the second columnar semiconductor layer. And a fourth step of forming a third diffusion layer in the upper portion of the fin-like semiconductor layer, the lower portion of the first columnar semiconductor layer, and the lower portion of the second columnar semiconductor layer after the third step. After the fourth step, an interlayer insulating film is deposited and The upper portions of the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate are exposed, and the first dummy gate, the second dummy gate, and the third dummy gate are exposed. And the fourth dummy gate are removed, and a first gate insulating film is formed around the first columnar semiconductor layer and the second columnar semiconductor layer, and the second columnar gate is formed. The first gate insulating film around the bottom of the semiconductor layer is removed, a first metal is deposited, the first columnar semiconductor layer upper portion and the second columnar semiconductor layer upper portion are exposed, and the first columnar semiconductor layer is exposed. A fifth step of forming a gate electrode and a gate wiring around the semiconductor layer and forming a contact electrode and a contact wiring around the second columnar semiconductor layer; and after the fifth step, the first columnar shape Around the semiconductor layer, the gate electrode, and the A second gate insulating film is deposited on the gate wiring, around the second columnar semiconductor layer, on the contact electrode and on the contact wiring, and on a part of the gate wiring and on the contact electrode and the contact wiring. At least a portion of the second gate insulating film is removed, a second metal is deposited, an upper portion of the first columnar semiconductor layer and an upper portion of the second columnar semiconductor layer are exposed, and the first columnar semiconductor layer is exposed. The second gate insulating film on the columnar semiconductor layer is removed, a third metal is deposited, and the third metal and a part of the second metal are etched, so that the second metal is A first contact surrounding the upper sidewall of the first columnar semiconductor layer; a second contact connecting the upper portion of the first contact and the upper portion of the first columnar semiconductor layer; and formed on the gate wiring The second metal and the third gold A third contact made of a genus; a fourth contact in which a second metal surrounds the second sidewall of the second columnar semiconductor layer and is connected to the contact electrode; an upper portion of the fourth contact; and the second columnar And a sixth step of forming a fifth contact connecting the upper portion of the semiconductor layer.

  In the second step, a second insulating film is formed around the fin-like semiconductor layer, and first polysilicon is deposited and planarized on the second insulating film. A second resist for forming the gate wiring and the first columnar semiconductor layer, and a third resist for forming the first contact wiring and the second columnar semiconductor layer are formed on the fin-shaped semiconductor layer. The first columnar semiconductor layer and the first polysilicon are formed by etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer. A first dummy gate, a second columnar semiconductor layer, and a second dummy gate made of the first polysilicon are formed.

  The method may further include forming a third insulating film on the first polysilicon after depositing and planarizing the first polysilicon on the second insulating film.

  Further, after the second step, a fourth insulating film is formed around the first columnar semiconductor layer, the second columnar semiconductor layer, the first dummy gate, and the second dummy gate, A second polysilicon is deposited around the fourth insulating film and etched, whereby the first dummy gate, the first columnar semiconductor layer, the second dummy gate, and the second columnar are formed. A third step of forming a third dummy gate and a fourth dummy gate is left on the side wall of the semiconductor layer.

  Further, a third diffusion layer is formed in the upper part of the fin-like semiconductor layer, the lower part of the first columnar semiconductor layer, and the lower part of the second columnar semiconductor layer, and the third dummy gate, the fourth dummy gate, A fifth insulating film is formed around the substrate, etched, and left in a sidewall shape to form a sidewall made of the fifth insulating film, and a metal and a semiconductor are formed on the third diffusion layer. It has the 4th process of forming a compound, It is characterized by the above-mentioned.

  After the fourth step, an interlayer insulating film is deposited, chemically mechanically polished, and the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate are formed. An upper portion is exposed, and the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate are removed, and the second insulating film and the fourth insulating film are removed. And a first gate insulating film is formed around the first columnar semiconductor layer, around the second columnar semiconductor layer, and inside the fifth insulating film, and the second columnar semiconductor layer is formed. Forming a fourth resist for removing the gate insulating film around the bottom of the second pillar-shaped semiconductor layer, removing the first gate insulating film around the bottom of the second columnar semiconductor layer, depositing a first metal, Exposing the upper portion of the first columnar semiconductor layer and the upper portion of the second columnar semiconductor layer; And a fifth step of forming a gate electrode and a gate wiring around the first columnar semiconductor layer, and forming a contact electrode and a contact wiring around the second columnar semiconductor layer. Features.

  The semiconductor device of the present invention is formed on the fin-like semiconductor layer, the fin-like semiconductor layer formed on the semiconductor substrate, the first insulating film formed around the fin-like semiconductor layer, and the fin-like semiconductor layer. A second columnar semiconductor layer; a contact electrode made of metal formed around the second columnar semiconductor layer; and a metal extending in a direction orthogonal to the fin-shaped semiconductor layer connected to the contact electrode A contact wiring, a third diffusion layer formed in an upper part of the fin-like semiconductor layer and a lower part of the second columnar semiconductor layer, the contact electrode being connected to the third diffusion layer, and the second A fourth contact surrounding the upper sidewall of the columnar semiconductor layer and connected to the contact electrode; and a fifth contact connecting the upper portion of the fourth contact and the upper portion of the second columnar semiconductor layer. And wherein the Rukoto.

  The semiconductor device further includes a first gate insulating film formed between the second columnar semiconductor layer and the contact electrode.

  In addition, the semiconductor device further includes a second gate insulating film formed between the upper sidewall of the second columnar semiconductor layer and the fourth contact.

  The width of the second columnar semiconductor layer in the direction orthogonal to the fin-shaped semiconductor layer is the same as the width of the fin-shaped semiconductor layer in the direction orthogonal to the fin-shaped semiconductor layer.

  Further, the first gate insulating film is formed around the contact electrode and the contact wiring.

  Further, the width of the contact electrode in the direction perpendicular to the contact wiring is the same as the width of the contact wiring in the direction orthogonal to the contact wiring.

  The width of the fourth contact in the direction orthogonal to the contact wiring is equal to the width of the contact electrode in the direction orthogonal to the contact wiring.

  Further, the width of the fifth contact in the direction perpendicular to the contact wiring is equal to the width of the fourth contact in the direction orthogonal to the contact wiring.

  A fin-shaped semiconductor layer formed on the semiconductor substrate; a first insulating film formed around the fin-shaped semiconductor layer; and a first columnar semiconductor layer formed on the fin-shaped semiconductor layer; The first gate insulating film formed around the first columnar semiconductor layer, the gate electrode made of metal formed around the first gate insulating film, and connected to the gate electrode A gate wiring made of metal extending in a direction orthogonal to the fin-like semiconductor layer, the gate electrode, the first gate insulating film formed on the periphery and bottom of the gate wiring, and the gate of the gate electrode The width in the direction perpendicular to the wiring is the same as the width of the gate wiring in the direction perpendicular to the gate wiring, and the third width formed in the upper part of the fin-like semiconductor layer and the lower part of the first columnar semiconductor layer. With a diffusion layer The second gate insulating film formed around the upper sidewall of the first columnar semiconductor layer, and the first contact made of a second metal formed around the second gate insulating film; A second contact made of a third metal connecting the upper portion of the first contact and the upper portion of the first columnar semiconductor layer; the second metal formed on the gate wiring; and the third contact It further has a third contact made of metal.

  The work function of the second metal of the first contact is between 4.0 eV and 4.2 eV.

  The work function of the second metal of the first contact is between 5.0 eV and 5.2 eV.

  According to the present invention, the gate electrode and the gate wiring are formed around the first columnar semiconductor layer, and at the same time, the contact electrode and the contact wiring connected to the upper portion of the fin-shaped semiconductor layer are formed around the second columnar semiconductor layer. A method of manufacturing an SGT having a structure that is a gate-last process and further functions as an n-type semiconductor layer or a p-type semiconductor layer in a self-aligned manner so that the upper part of the columnar semiconductor layer functions as a work function difference between a metal and a semiconductor. Contact structures and SGT structures can be provided.

  After a gate insulating film is formed around the first columnar semiconductor layer, around the second columnar semiconductor layer, and inside the fifth insulating film, a first around the bottom of the second columnar semiconductor layer is formed. Forming a fourth resist for removing the gate insulating film, and removing the first gate insulating film around the bottom of the second columnar semiconductor layer, thereby forming a gate around the first columnar semiconductor layer. An electrode and a gate wiring can be formed, and at the same time, a contact electrode and a contact wiring connected to the upper portion of the fin-shaped semiconductor layer can be formed around the second columnar semiconductor layer. Therefore, it is sufficient to perform etching for the thickness of the first gate insulating film, and a step of forming a deep contact hole is not necessary.

  After the fifth step, a hole having the same shape as the gate electrode and the gate wiring remains above the gate electrode and the gate wiring. In addition, a hole having the same shape as the contact electrode and the contact wiring remains above the contact electrode and the contact wiring. Therefore, the exposed first gate insulating film is removed, and the periphery of the first columnar semiconductor layer, the gate electrode, the gate wiring, the periphery of the second columnar semiconductor layer, the contact electrode, and the contact wiring are removed. A second gate insulating film is deposited on the gate wiring, a part of the gate wiring and at least a part of the second gate insulating film on the contact electrode and the contact wiring are removed, and a second metal is deposited. When etch back is performed, a metal is embedded in a hole having the same shape as the gate electrode and the gate wiring, and a hole having the same shape as the contact electrode and the contact wiring, and the second metal is self-aligned and the second metal is the upper sidewall of the columnar semiconductor layer. And a fourth contact in which the second metal surrounds the upper sidewall of the second columnar semiconductor layer and is connected to the contact electrode.

  In addition, since a part of the second gate insulating film on the gate wiring is removed, a third contact for the gate wiring can be formed at the same time, and the contact for the gate wiring can be easily made. Can be formed.

  Therefore, in order to form a contact, it is only necessary to perform etching for the thickness of the first gate insulating film and the thickness of the second gate insulating film, and a step of forming a deep contact hole is unnecessary.

  The second columnar silicon layer 110, the contact electrode 140c formed around the second columnar silicon layer 110, the contact wiring 140d, and the upper side wall of the second columnar silicon layer 110 are surrounded and connected to the contact electrode 140c. The structure formed by the fourth contact 146 and the fifth contact 148 connecting the upper part of the fourth contact 146 and the upper part of the second columnar silicon layer 110 is such that the contact electrode is the third diffusion. Since the structure is the same as the transistor structure except that it is connected to a layer and the fourth contact 146 is connected to the contact electrode, the number of steps can be reduced.

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  Below, the manufacturing process for forming the structure of SGT which concerns on embodiment of this invention is demonstrated with reference to FIGS.

  First, a first step of forming a fin-like semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-like semiconductor layer is shown. In this embodiment, a silicon substrate is used, but any semiconductor may be used.

  As shown in FIG. 2, a first resist 102 for forming a fin-like silicon layer is formed on the silicon substrate 101.

  As shown in FIG. 3, the silicon substrate 101 is etched to form a fin-like silicon layer 103. Although the fin-like silicon layer is formed using a resist as a mask this time, a hard mask such as an oxide film or a nitride film may be used.

  As shown in FIG. 4, the first resist 102 is removed.

  As shown in FIG. 5, a first insulating film 104 is deposited around the fin-like silicon layer 103. An oxide film formed by high-density plasma or an oxide film formed by low-pressure CVD (Chemical Vapor Deposition) may be used as the first insulating film.

  As shown in FIG. 6, the 1st insulating film 104 is etched back and the upper part of the fin-like silicon layer 103 is exposed. The process up to here is the same as the manufacturing method of the fin-like silicon layer of Non-Patent Document 2.

  Thus, the first step of forming the fin-like semiconductor layer on the semiconductor substrate and forming the first insulating film around the fin-like semiconductor layer is shown.

    Next, a second insulating film is formed around the fin-like semiconductor layer, and a first polysilicon is deposited and planarized on the second insulating film to form a first gate wiring and a first columnar shape. A second resist for forming the semiconductor layer and a third resist for forming the first contact wiring and the second columnar semiconductor layer are arranged in a direction perpendicular to the direction of the fin-shaped semiconductor layer. Forming and etching the first polysilicon, the second insulating film, and the fin-like semiconductor layer to form a first columnar semiconductor layer, a first dummy gate made of the first polysilicon, and a second A second step of forming a columnar semiconductor layer and a second dummy gate made of the first polysilicon is shown.

  As shown in FIG. 7, a second insulating film 105 is formed around the fin-like silicon layer 103. The second insulating film 105 is preferably an oxide film.

  As shown in FIG. 8, a first polysilicon 106 is deposited on the second insulating film 105 and planarized.

  As shown in FIG. 9, a third insulating film 107 is formed on the first polysilicon 106. The third insulating film 107 is preferably a nitride film.

  As shown in FIG. 10, the second resist 108 for forming the gate wiring and the first columnar silicon layer, and the third resist 109 for forming the first contact wiring and the second columnar silicon layer. Are formed in a direction perpendicular to the direction of the fin-like silicon layer 103.

  As shown in FIG. 11, the first columnar silicon layer 111 is etched by etching the third insulating film 107, the first polysilicon 106, the second insulating film 105, and the fin-like silicon layer 103. A first dummy gate 115 made of the first polysilicon, a second columnar silicon layer 110, and a second dummy gate 114 made of the first polysilicon are formed. At this time, the third insulating film is separated and becomes third insulating films 113 and 112. Further, the second insulating film is separated to become second insulating films 117 and 116. At this time, when the second resist 108 and the third resist 109 are removed during etching, the third insulating films 113 and 112 function as a hard mask. When the second resist is not removed during etching, the third insulating film may not be used.

  As shown in FIG. 12, the second resist 108 and the third resist 109 are removed.

  As described above, the second insulating film is formed around the fin-like semiconductor layer, the first polysilicon is deposited and planarized on the second insulating film, and the first gate wiring and the first columnar shape are formed. A second resist for forming the semiconductor layer and a third resist for forming the first contact wiring and the second columnar semiconductor layer are arranged in a direction perpendicular to the direction of the fin-shaped semiconductor layer. Forming and etching the first polysilicon, the second insulating film, and the fin-like semiconductor layer to form a first columnar semiconductor layer, a first dummy gate made of the first polysilicon, and a second The second step of forming the columnar semiconductor layer and the second dummy gate made of the first polysilicon is shown.

  Next, after the second step, a fourth insulating film is formed around the first columnar semiconductor layer, the second columnar semiconductor layer, the first dummy gate, and the second dummy gate. Then, a second polysilicon is deposited around the fourth insulating film and etched, whereby the first dummy gate, the first columnar semiconductor layer, the second dummy gate, and the second dummy gate are etched. A third step of forming the third dummy gate and the fourth dummy gate by remaining on the side wall of the columnar semiconductor layer is shown.

  As shown in FIG. 13, a fourth insulating film 118 is formed around the first columnar silicon layer 111, the second columnar silicon layer 110, the first dummy gate 115, and the second dummy gate 114. Form. The fourth insulating film 118 is preferably an oxide film.

  As shown in FIG. 14, a second polysilicon 122 is deposited around the fourth insulating film 118.

  As shown in FIG. 15, by etching the second polysilicon 122, the first dummy gate 115, the first columnar silicon layer 111, the second dummy gate 114, and the second columnar shape A third dummy gate 124 and a fourth dummy gate 123 are formed by remaining on the sidewall of the silicon layer 110. At this time, the fourth insulating film may be separated and become fourth insulating films 126 and 125.

  As described above, after the second step, a fourth insulating film is formed around the first columnar semiconductor layer, the second columnar semiconductor layer, the first dummy gate, and the second dummy gate. Then, a second polysilicon is deposited around the fourth insulating film and etched, whereby the first dummy gate, the first columnar semiconductor layer, the second dummy gate, and the second dummy gate are etched. The third step of forming the third dummy gate and the fourth dummy gate by remaining on the side wall of the columnar semiconductor layer is shown.

  Next, a third diffusion layer is formed in the upper part of the fin-like semiconductor layer, the lower part of the first columnar semiconductor layer, and the lower part of the second columnar semiconductor layer, and the third dummy gate and the fourth dummy gate are formed. A fifth insulating film is formed around the substrate, etched, and left in a sidewall shape to form a sidewall made of the fifth insulating film, and a metal and a semiconductor are formed on the third diffusion layer. The 4th process of forming the compound of is shown.

  As shown in FIG. 16, an impurity is introduced to form a third diffusion layer 127 below the first columnar silicon layer 111 and below the second columnar silicon layer 110. In the case of an n-type diffusion layer, it is preferable to introduce arsenic or phosphorus. In the case of a p-type diffusion layer, it is preferable to introduce boron. The diffusion layer may be formed after forming a sidewall made of a fifth insulating film described later.

  As shown in FIG. 17, a fifth insulating film 128 is formed around the third dummy gate 124 and the fourth dummy gate 123. The fifth insulating film 128 is preferably a nitride film.

  As shown in FIG. 18, the fifth insulating film 128 is etched and left in the shape of a side wall to form side walls 130 and 129 made of the fifth insulating film.

  As shown in FIG. 19, a metal-semiconductor compound 131 is formed on the third diffusion layer 127. At this time, metal and semiconductor compounds 133 and 132 are also formed on the third dummy gate 124 and the fourth dummy gate 125.

  As described above, a third diffusion layer is formed in the upper portion of the fin-like semiconductor layer, the lower portion of the first columnar semiconductor layer, and the lower portion of the second columnar semiconductor layer, and the third dummy gate and the fourth dummy gate are formed. A fifth insulating film is formed around the substrate, etched, and left in a sidewall shape to form a sidewall made of the fifth insulating film, and a metal and a semiconductor are formed on the third diffusion layer. A fourth step of forming the compound was shown.

  Next, after the fourth step, an interlayer insulating film is deposited, chemically mechanically polished, the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate. The first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate are removed, and the second insulating film and the fourth insulation are exposed. The film is removed, and a first gate insulating film is formed around the first columnar semiconductor layer, around the second columnar semiconductor layer, and inside the fifth insulating film, and the second columnar semiconductor is formed. Forming a fourth resist for removing the gate insulating film around the bottom of the layer; removing the first gate insulating film around the bottom of the second columnar semiconductor layer; depositing a first metal; Exposing the top of the first columnar semiconductor layer and the top of the second columnar semiconductor layer; Performed Tchibakku, the forming a gate electrode and a gate wire around the first columnar semiconductor layer, a fifth step of forming the contact electrode and the contact wires around the second columnar semiconductor layer.

  As shown in FIG. 20, an interlayer insulating film 134 is deposited. A contact stopper film may be used.

  As shown in FIG. 21, chemical mechanical polishing is performed to expose the upper portions of the first dummy gate 115, the second dummy gate 114, the third dummy gate 124, and the fourth dummy gate 123. At this time, the metal and semiconductor compounds 133 and 132 on the third dummy gate 124 and the fourth dummy gate 125 are removed.

  As shown in FIG. 22, the first dummy gate 115, the second dummy gate 114, the third dummy gate 124, and the fourth dummy gate 123 are removed.

  As shown in FIG. 23, the second insulating films 117 and 116 and the fourth insulating films 126 and 125 are removed.

  As shown in FIG. 24, the first gate insulating film 135 is formed around the first columnar silicon layer 111, around the second columnar silicon layer 110, and inside the fifth insulating films 130 and 129. To do.

  As shown in FIG. 25, a fourth resist 136 for removing the first gate insulating film 135 around the bottom of the second columnar silicon layer 110 is formed.

  As shown in FIG. 26, the first gate insulating film 135 around the bottom of the second columnar silicon layer 110 is removed. The first gate insulating film is separated to form first gate insulating films 137, 139, and 138. Further, the first gate insulating films 137 and 139 may be removed by isotropic etching.

  As shown in FIG. 27, the 4th resist 136 is removed.

  As shown in FIG. 28, a first metal 140 is deposited.

  As shown in FIG. 29, the first metal 140 is etched back to form a gate electrode 140 a and a gate wiring 140 b around the first columnar silicon layer 111, and around the second columnar silicon layer 110. Then, a contact electrode 140c and a contact wiring 140d are formed. The contact wiring length may be short.

  After a gate insulating film is formed around the first columnar semiconductor layer, around the second columnar semiconductor layer, and inside the fifth insulating film, a first around the bottom of the second columnar semiconductor layer is formed. Forming a fourth resist for removing the gate insulating film, and removing the first gate insulating film around the bottom of the second columnar semiconductor layer, thereby forming a gate around the first columnar semiconductor layer. An electrode and a gate wiring can be formed, and at the same time, a contact electrode and a contact wiring connected to the upper portion of the fin-shaped semiconductor layer can be formed around the second columnar semiconductor layer. Therefore, it is sufficient to perform etching for the thickness of the first gate insulating film, and a step of forming a deep contact hole is not necessary.

  The structure formed by the second columnar semiconductor layer, the contact electrode formed around the second columnar semiconductor layer, and the contact wiring is a transistor structure except that the contact electrode is connected to the third diffusion layer. Therefore, the number of steps can be reduced.

  As described above, after the fourth step, an interlayer insulating film is deposited, chemically mechanically polished, the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate. The first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate are removed, and the second insulating film and the fourth insulation are exposed. The film is removed, and a first gate insulating film is formed around the first columnar semiconductor layer, around the second columnar semiconductor layer, and inside the fifth insulating film, and the second columnar semiconductor is formed. Forming a fourth resist for removing the gate insulating film around the bottom of the layer; removing the first gate insulating film around the bottom of the second columnar semiconductor layer; depositing a first metal; The upper part of the first columnar semiconductor layer and the upper part of the second columnar semiconductor layer are exposed. Then, etch back is performed, a gate electrode and a gate wiring are formed around the first columnar semiconductor layer, and a contact electrode and a contact wiring are formed around the second columnar semiconductor layer. It was.

  Next, after the fifth step, second around the first columnar semiconductor layer, the gate electrode, and the gate wiring, and around the second columnar semiconductor layer, the contact electrode, and the contact wiring. Depositing a second metal, removing a part of the gate insulating film, a part of the gate wiring, and a part of the contact electrode and the second gate insulating film of the contact wiring. An upper portion of the first columnar semiconductor layer and an upper portion of the second columnar semiconductor layer are exposed; the second gate insulating film on the first columnar semiconductor layer is removed; a third metal is deposited; 3 and part of the second metal are etched, so that the second metal surrounds the first sidewall of the first columnar semiconductor layer, the upper portion of the first contact, and the first metal Connect the top of the columnar semiconductor layer 2 contacts, a third contact made of the second metal and the third metal formed on the gate wiring, and the second metal surrounds the upper sidewall of the second columnar semiconductor layer and the contact A sixth step of forming a fourth contact connected to the electrode, and a fifth contact connecting the upper portion of the fourth contact and the upper portion of the second columnar semiconductor layer is shown.

  After the fifth step, a hole having the same shape as the gate electrode and the gate wiring remains above the gate electrode and the gate wiring. In addition, a hole having the same shape as the contact electrode and the contact wiring remains above the contact electrode and the contact wiring. Therefore, the exposed first gate insulating film is removed, and the periphery of the first columnar semiconductor layer, the gate electrode, the gate wiring, the periphery of the second columnar semiconductor layer, the contact electrode, and the contact wiring are removed. A second gate insulating film is deposited on the gate wiring, and a part of the gate wiring, the previous contact electrode and at least a part of the second gate insulating film on the contact wiring are removed, and a second metal is deposited. When etch back is performed, a metal is embedded in a hole having the same shape as the gate electrode and the gate wiring, and a hole having the same shape as the contact electrode and the contact wiring. And a fourth contact in which the second metal surrounds the upper sidewall of the second columnar semiconductor layer and is connected to the contact electrode.

  As shown in FIG. 30, the exposed first gate insulating films 139, 137, and 138 are removed.

  As shown in FIG. 31, the second gate insulating film is formed around the first columnar silicon layer 111, on the gate electrode 140a and the gate wiring 140b, and around the second columnar silicon layer 110, on the contact electrode 140c and the contact wiring 140d. 141 is deposited.

  As shown in FIG. 32, a fifth resist 142 for removing a part of the gate wiring 140b, the contact electrode 140c, and at least a part of the second gate insulating film 141 on the contact wiring 140d is formed.

  As shown in FIG. 33, a part on the gate wiring 140b, the contact electrode 140c, and at least a part of the second gate insulating film 141 on the contact wiring 140d are removed. The second gate insulating film 141 is separated to form second gate insulating films 143, 144, and 145. Further, the second gate insulating films 143 and 144 may be removed by isotropic etching.

  Since part of the second gate insulating film on the gate wiring is removed, a third contact for the gate wiring can be formed at the same time, and a contact for the gate wiring can be easily formed. .

  Therefore, in order to form a contact, it is only necessary to perform etching for the thickness of the first gate insulating film and the thickness of the second gate insulating film, and a step of forming a deep contact hole is unnecessary.

  As shown in FIG. 34, the 5th resist 142 is removed.

  As shown in FIG. 35, the second metals 146 and 147 are deposited and etched back to expose the upper portion of the first columnar silicon layer 111 and the upper portion of the second columnar silicon layer 110. The work function of the metal of the second metal 146, 147 is preferably between 4.0 eV and 4.2 eV when the transistor is n-type. The work functions of the second metals 146 and 147 are preferably between 5.0 eV and 5.2 eV when the transistor is p-type.

  As shown in FIG. 36, the second gate insulating film 145 on the exposed first columnar silicon layer 111 is removed.

  As shown in FIG. 37, third metals 148 and 149 are deposited. The third metal may be the same metal as the second metal.

  As shown in FIG. 38, the 4th metal 150 for metal wiring is deposited.

  As shown in FIG. 39, metal wiring is formed, and sixth resists 151, 152, and 153 for etching portions of the third metals 148 and 149 and the second metals 146 and 147 are formed.

  As shown in FIG. 40, the 4th metal 150 is etched and the metal wiring 154, 155, 156 is formed. Further, by etching a part of the third metals 148 and 149 and the second metals 146 and 147, the second metal 147 surrounds the upper sidewall of the first columnar silicon layer 111, and the first contact 147a The second contact 149a connecting the upper part of the first contact 147a and the upper part of the first columnar silicon layer 111, the second metal 147b formed on the gate wiring 140b, and the third A third contact 157 made of a metal 149b; a fourth contact 146 in which the second metal surrounds the second sidewall of the second columnar semiconductor layer and is connected to the contact electrode; an upper portion of the fourth contact 146; A fifth contact 148 connecting the upper part of the second columnar silicon layer 110 is formed. Before the metal wiring is formed, part of the third metals 148 and 149 and the second metals 146 and 147 may be etched.

  As shown in FIG. 41, the sixth resists 151, 152, and 153 are removed.

  As described above, after the fifth step, the second columnar semiconductor layer, the gate electrode, and the gate wiring, the second columnar semiconductor layer, the contact electrode, and the contact wiring are second. Depositing a second metal, removing a part of the gate insulating film, a part of the gate wiring, and a part of the contact electrode and the second gate insulating film of the contact wiring. An upper portion of the first columnar semiconductor layer and an upper portion of the second columnar semiconductor layer are exposed; the second gate insulating film on the first columnar semiconductor layer is removed; a third metal is deposited; 3 and part of the second metal are etched, so that the second metal surrounds the first sidewall of the first columnar semiconductor layer, the upper portion of the first contact, and the first metal 1 columnar semiconductor layer upper part A second contact formed on the gate wiring, a third contact made of the second metal and the third metal, and a second metal surrounding the upper sidewall of the second columnar semiconductor layer. A sixth step of forming a fourth contact connected to the contact electrode and a fifth contact connecting the upper portion of the fourth contact and the upper portion of the second columnar semiconductor layer is shown.

  As described above, the gate last process for forming the gate electrode and the gate wiring around the first columnar semiconductor layer and simultaneously forming the contact electrode and the contact wiring connected to the upper part of the fin-shaped semiconductor layer around the second columnar semiconductor layer. In addition, a method for manufacturing an SGT having a structure in which the upper part of the columnar semiconductor layer functions as an n-type semiconductor layer or a p-type semiconductor layer by a work function difference between a metal and a semiconductor by self-alignment is shown.

A structure of a semiconductor device obtained by the manufacturing method is shown in FIG.
A fin-like silicon layer 103 formed on the silicon substrate 101, a first insulating film 104 formed around the fin-like silicon layer 103, and a second columnar shape formed on the fin-like silicon layer 103 A silicon layer 110, a contact electrode 140c made of metal formed around the second columnar silicon layer 110, and a metal extending in a direction perpendicular to the fin-like silicon layer 103 connected to the contact electrode 140c 140 d of contact wiring, a third diffusion layer 127 formed above the fin-like silicon layer 103 and below the second columnar silicon layer 110, and the contact electrode 140 c is the third diffusion layer 127. The contact electrode 140c surrounding the upper side wall of the second pillar-shaped silicon layer 110 It has a fourth contact 146 to be connected, the fifth contact 148 for connecting the upper and the second pillar-shaped silicon layer 110 above the fourth contact 146, a.

  Further, the first gate insulating film 137 is formed between the second columnar silicon layer 110 and the contact electrode 140c.

  In addition, the second gate insulating film 143 is formed between the upper sidewall of the second columnar silicon layer 110 and the fourth contact 146.

  The width of the second columnar silicon layer 110 in the direction perpendicular to the fin-like silicon layer 103 is the same as the width of the fin-like silicon layer 103 in the direction perpendicular to the fin-like silicon layer 103. And

  Further, the first gate insulating film 139 is formed around the contact electrode 140c and the contact wiring 140d.

  Further, the width of the contact electrode 140c in the direction perpendicular to the contact wiring 140d and the width of the contact wiring 140d in the direction perpendicular to the contact wiring 140d are the same.

  The width of the fourth contact 146 in the direction orthogonal to the contact wiring 140d is equal to the width of the contact electrode 140c in the direction orthogonal to the contact wiring 140d.

  Further, the width of the fifth contact 148 in the direction orthogonal to the contact wiring 140d is equal to the width of the fourth contact 146 in the direction orthogonal to the contact wiring 140d.

  Further, the fin-like silicon layer 103 formed on the silicon substrate 101, the first insulating film 104 formed around the fin-like silicon layer 103, and the first formed on the fin-like silicon layer 103. The columnar silicon layer 111, the first gate insulating film 138 formed around the first columnar silicon layer 111, and a gate electrode made of metal formed around the first gate insulating film 138 140a, a gate wiring 140b made of metal extending in a direction orthogonal to the fin-like silicon layer 103 connected to the gate electrode 140a, and the periphery and bottom of the gate electrode 140a and the gate wiring 140b. The first gate insulating film 138, the width of the gate electrode 140a in the direction perpendicular to the gate wiring 140b, and the gate arrangement 140b having the same width in the direction perpendicular to the gate wiring 140b, the third diffusion layer 127 formed above the fin-like silicon layer 103 and below the first columnar silicon layer 111; The second gate insulating film 145 formed around the upper sidewall of the first columnar silicon layer 111 and the first metal made of the second metal formed around the second gate insulating film 145. The contact 147a, the second contact 149a made of a third metal that connects the upper portion of the first contact 147a and the upper portion of the first columnar silicon layer 111, and the first contact formed on the gate wiring 140b. And a third contact 157 made of the second metal 147b and the third metal 149b.

  The work function of the second metal of the first contact 147a is preferably between 4.0 eV and 4.2 eV when the transistor is n-type. The work functions of the second metals 146 and 147 are preferably between 5.0 eV and 5.2 eV when the transistor is p-type.

  Second columnar silicon layer 110, contact electrode 140c and contact wiring 140d formed around second columnar silicon layer 110, and a fourth column surrounding the upper side wall of second columnar silicon layer 110 and connected to contact electrode 140c. The contact 146 and the fifth contact 148 connecting the upper part of the fourth contact 146 and the upper part of the second columnar silicon layer 110 have a structure in which a contact electrode is connected to the third diffusion layer. Since the structure is the same as the transistor structure except that the connection and the fourth contact 146 are connected to the contact electrode, the number of steps can be reduced.

  It should be noted that the present invention can be variously modified and modified without departing from the broad spirit and scope of the present invention. The above-described embodiment is for explaining an example of the present invention, and does not limit the technical scope of the present invention.

For example, in the above embodiment, a method of manufacturing a semiconductor device in which p-type (including p ⁺ -type) and n-type (including n ⁺ -type) are opposite in conductivity type, and a semiconductor obtained thereby An apparatus is naturally included in the technical scope of the present invention.

101. Silicon substrate 102. First resist 103. Fin-like silicon layer 104. First insulating film 105. Second insulating film 106. First polysilicon 107. Third insulating film 108. Second resist 109. Third resist 110. Second columnar silicon layer 111. First columnar silicon layer 112. Third insulating film 113. Third insulating film 114. Second dummy gate 115. First dummy gate 116. Second insulating film 117. Second insulating film 118. Fourth insulating film 122. Second polysilicon 123. Fourth dummy gate 124. Third dummy gate 125. Fourth insulating film 126. Fourth insulating film 127. Third diffusion layer 128. Fifth insulating film 129. Sidewall 130. Sidewall 131. Compound of metal and semiconductor 132. Compound of metal and semiconductor 133. Compound of metal and semiconductor 134. Interlayer insulating film 135. First gate insulating film 136. Fourth resist 137. First gate insulating film 138. First gate insulating film 139. First gate insulating film 140. First metal 140a. Gate electrode 140b. Gate wiring 140c. Contact electrode 140d. Contact wiring 141. Second gate insulating film 142. Fifth resist 143. Second gate insulating film 144. Second gate insulating film 145. Second gate insulating film 146. Second metal, fourth contact 147. Second metal 147a. First contact 147b. Second metal 148. Third metal, fifth contact 149. Third metal 149a. Second contact 149b. Third metal 150. Fourth metal 151. Sixth resist 152. Sixth resist 153. Sixth resist 154. Metal wiring 155. Metal wiring 156. Metal wiring 157. Third contact

Claims (9)

A fin-like semiconductor layer formed on a semiconductor substrate; a first insulating film formed around the fin-like semiconductor layer;
A second columnar semiconductor layer formed on the fin-like semiconductor layer;
A contact electrode made of metal formed around the second columnar semiconductor layer;
A contact wiring made of a metal extending in a direction orthogonal to the fin-like semiconductor layer connected to the contact electrode in a horizontal direction with respect to the substrate;
A third diffusion layer formed above the fin-like semiconductor layer and below the second columnar semiconductor layer;
The contact electrode is connected to the third diffusion layer;
A fourth contact surrounding the upper sidewall of the second columnar semiconductor layer and in direct contact with the contact electrode; a fifth contact connecting the upper portion of the fourth contact and the upper portion of the second columnar semiconductor layer;
A semiconductor device comprising: 2. The width of the second columnar semiconductor layer in the direction perpendicular to the fin-shaped semiconductor layer is the same as the width of the fin-shaped semiconductor layer in the direction perpendicular to the fin-shaped semiconductor layer. The semiconductor device described. The semiconductor device according to claim 1, further comprising an insulating film formed around the contact electrode and the contact wiring. 2. The semiconductor device according to claim 1, wherein the width of the contact electrode in the direction orthogonal to the contact wiring is the same as the width of the contact wiring in the direction orthogonal to the contact wiring. 2. The semiconductor device according to claim 1, wherein a width of the fourth contact in a direction orthogonal to the contact wiring is equal to a width of the contact electrode in a direction orthogonal to the contact wiring. 2. The semiconductor device according to claim 1, wherein a width of the fifth contact in a direction orthogonal to the contact wiring is equal to a width of the fourth contact in a direction orthogonal to the contact wiring. A fin-like semiconductor layer formed on a semiconductor substrate;
A first insulating film formed around the fin-like semiconductor layer;
A first columnar semiconductor layer formed on the fin-shaped semiconductor layer;
The first gate insulating film further formed around the first columnar semiconductor layer;
A gate electrode made of metal formed around the first gate insulating film;
A gate wiring made of a metal extending in a direction orthogonal to the fin-like semiconductor layer connected to the gate electrode;
The first gate insulating film formed on the periphery and bottom of the gate electrode and the gate wiring, the width of the gate electrode in the direction orthogonal to the gate wiring, and the direction of the gate wiring in the direction orthogonal to the gate wiring The width is the same,
The third diffusion layer formed above the fin-like semiconductor layer, the lower part of the first columnar semiconductor layer, and the second gate formed around the upper sidewall of the first columnar semiconductor layer An insulating film;
A first contact made of a second metal formed around the second gate insulating film;
A second contact made of a third metal that connects the upper part of the first contact and the upper part of the first columnar semiconductor layer;
The semiconductor device according to claim 1, further comprising a third contact made of the second metal and the third metal formed on the gate wiring. The semiconductor device according to claim 7, wherein a work function of the second metal of the first contact is between 4.0 eV and 4.2 eV. The semiconductor device according to claim 7, wherein a work function of the second metal of the first contact is between 5.0 eV and 5.2 eV.

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