JP2017108161A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor using an oxide semiconductor which solves a problem of difficulty in causing oxygen atoms or the like to sufficiently and uniformly diffuse in the oxide semiconductor.SOLUTION: A semiconductor device comprises: a gate electrode; a gate insulation film arranged so as to cover one surface of the gate electrode; an oxide semiconductor arranged on the gate insulation film in an overlapping manner; a source electrode and a drain electrode arranged on the oxide semiconductor in an overlapping manner; and an oxygen atom containing film arranged between the source electrode and drain electrode, and the gate insulation film layer so as to contact the oxide semiconductor.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In recent years, a thin film transistor (TFT) using an oxide semiconductor layer is known (see Patent Document 1 below). Specifically, the thin film transistor disclosed in Patent Document 1 includes a gate electrode layer, a gate insulating layer disposed over the gate electrode, an oxide semiconductor layer disposed over the gate insulating layer, and the oxide semiconductor. A source and drain electrode layer is provided on the layer. In order to improve the mobility of the thin film transistor and suppress increase in off-state current, the thin film transistor includes a plurality of conductive oxide clusters over the gate insulating layer.

JP 2010-171406 A

  Here, in general, in a thin film transistor using an oxide semiconductor as described above, water vapor annealing is performed after the formation of the thin film transistor. Thus, oxygen atoms or the like (for example, O or OH) diffuse into the oxide semiconductor, and characteristics such as mobility of the thin film transistor can be improved.

  However, in the above thin film transistor, it is difficult to diffuse oxygen atoms and the like sufficiently and uniformly in the oxide semiconductor. Further, in order to sufficiently diffuse oxygen atoms or the like in the oxide semiconductor, it is necessary to perform the water vapor annealing at a high temperature for a long time.

  In view of the above problems, the present invention provides a semiconductor device having a thin film transistor using an oxide semiconductor in a semiconductor layer, in which oxygen atoms and the like are diffused more sufficiently and uniformly in the oxide semiconductor, and the characteristics of the thin film transistor are further improved. An object of the present invention is to realize a semiconductor device that can be manufactured or a method for manufacturing the semiconductor device.

  (1) A semiconductor device of the present invention includes a gate electrode, a gate insulating film disposed so as to cover one surface of the gate electrode, an oxide semiconductor disposed over the gate insulating film, and the oxidation A source electrode and a drain electrode arranged to overlap with a physical semiconductor; and an oxygen atom-containing film arranged so as to be in contact with the oxide semiconductor between the source electrode and the drain electrode and the gate insulating film layer; Have

  (2) In the semiconductor device according to (1), the oxide semiconductor includes a first oxide semiconductor layer and a second oxide semiconductor layer, and the oxygen atom-containing film includes the first oxide semiconductor layer. The oxide semiconductor layer is disposed between the oxide semiconductor layer and the second oxide semiconductor layer.

  (3) In the semiconductor device according to (1) or (2), the oxygen atom-containing film is a moisture-containing film containing moisture.

  (4) In the semiconductor device according to (3), a moisture concentration of the moisture-containing film is higher than a moisture concentration contained in the oxide semiconductor.

  (5) In the semiconductor device according to (3) or (4), the moisture concentration of the moisture-containing film is 1 atm% to 30 atm%.

  (6) In the semiconductor device according to any one of (1) to (5), the oxygen atom-containing film is provided between 20% and 80% of the thickness of the oxide semiconductor. To do.

  (7) In the semiconductor device according to any one of (1) to (6), the oxygen atom-containing film is a discontinuous film.

  (8) In the semiconductor device according to any one of (1) to (7), the oxide semiconductor has a thickness of 5 nm to 200 nm.

  (9) In the semiconductor device according to any one of (1) to (8), a material of the first oxide semiconductor layer is different from a material of the second oxide semiconductor layer. .

  (10) In the method for manufacturing a semiconductor device of the present invention, at least a first electrode layer is formed on a substrate, and an oxide semiconductor layer and an oxygen atom-containing film are formed on the substrate on which the at least first electrode layer is formed. A channel layer is formed, and at least a second electrode layer is formed on the substrate on which the channel layer is formed, and oxygen atoms contained in the oxygen atom-containing film are diffused into the oxide semiconductor layer. And

  (11) In the semiconductor device according to (10), the oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer, and the substrate on which the first electrode layer is formed. Forming at least the first oxide semiconductor layer, forming the oxygen atom-containing film on the first oxide semiconductor layer, and forming the second oxide semiconductor on the oxygen atom-containing film. The channel layer is formed by forming a layer.

It is the schematic which shows the display apparatus in the 1st Embodiment of this invention. It is a conceptual diagram of the pixel circuit formed on the TFT substrate shown in FIG. FIG. 3 is a diagram for explaining a configuration of a TFT shown in FIG. 2. FIG. 3 is a diagram for explaining a configuration of a cross section of the TFT shown in FIG. 2. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 1st Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 1st Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 1st Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 1st Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 1st Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 1st Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 1st Embodiment. It is a figure for demonstrating the flow of the manufacturing method in 1st Embodiment. It is a figure for demonstrating the structure of the cross section of TFT in the 2nd Embodiment of this invention. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 2nd Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 2nd Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 2nd Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 2nd Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 2nd Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 2nd Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 2nd Embodiment. It is a figure for demonstrating the flow of the manufacturing method in 2nd Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, about drawing, the same code | symbol is attached | subjected to the same or equivalent element, and the overlapping description is abbreviate | omitted.

  FIG. 1 is a schematic view showing a display device according to an embodiment of the present invention. As shown in FIG. 1, for example, the display device 100 includes a TFT substrate 102 on which a TFT or the like (not shown) is formed, and a filter provided with a color filter (not shown) facing the TFT substrate 102. A substrate 101 is included. Further, the display device 100 includes a liquid crystal material (not shown) sealed in a region sandwiched between the TFT substrate 102 and the filter substrate 101, and a backlight positioned in contact with the opposite side of the TFT substrate 102 to the filter substrate 101 side. 103.

  FIG. 2 is a conceptual diagram of a pixel circuit formed on the TFT substrate shown in FIG. As shown in FIG. 2, the TFT substrate 102 includes a plurality of gate signal lines 105 arranged at substantially equal intervals in the horizontal direction of FIG. 2 and a plurality of video signal lines 107 arranged at substantially equal intervals in the vertical direction of FIG. Have The gate signal line 105 is connected to the shift register circuit 104, and the video signal line 107 is connected to the driver 106.

  The shift register circuit 104 includes a plurality of basic circuits (not shown) corresponding to the plurality of gate signal lines 105, respectively. Note that each basic circuit includes a plurality of TFTs, capacitors, and the like, and in accordance with a control signal 115 from the driver 106, the basic circuit is high during a corresponding gate scanning period (signal high period) in one frame period. A gate signal that becomes a voltage and becomes a low voltage during the other period (signal low period) is output to the corresponding gate signal line 105.

  Each pixel region 130 partitioned in a matrix by the gate signal line 105 and the video signal line 107 includes a TFT 109, a pixel electrode 110, and a common electrode 111, respectively. Here, the gate of the TFT 109 is connected to the gate signal line 105, one of the source and the drain is connected to the video signal line 107, and the other is connected to the pixel electrode 110. The common electrode 111 is connected to the common signal line 108. Note that the pixel electrode 110 and the common electrode 111 face each other.

  Next, the operation of the pixel circuit configured as described above will be described. The driver 106 applies a reference voltage to the common electrode 111 via the common signal line 108. The shift register circuit 104 controlled by the driver 106 outputs a gate signal to the gate electrode of the TFT 109 via the gate signal line 105. Further, the driver 106 supplies the voltage of the video signal to the TFT 109 to which the gate signal is output via the video signal line 107, and the voltage of the video signal is further applied to the pixel electrode 110 via the TFT 109. To do. At this time, a potential difference is generated between the pixel electrode 110 and the common electrode 111.

  The driver 106 controls the potential difference generated between the pixel electrode 110 and the common electrode 111, thereby controlling the light distribution of the liquid crystal molecules of the liquid crystal material inserted between the pixel electrode 110 and the common electrode 111. Here, since the light from the backlight 103 is guided to the liquid crystal material, the amount of light from the backlight 103 can be adjusted by controlling the light distribution of the liquid crystal molecules as described above. As a result, an image can be displayed.

  FIG. 3 is a diagram for explaining the configuration of the TFT shown in FIG. Specifically, FIG. 3 shows a part of the upper surface around the TFT 109 of the TFT substrate 102 shown in FIG. Note that the structure shown in the TFT shown in FIG. 3 is an example, and the present invention is not limited to this. For example, FIG. 3 shows an example of the structure of a so-called bottom gate type TFT, but it may have a structure of a so-called top gate type TFT as will be described later.

  As shown in FIG. 3, when viewed from above, the TFT substrate 102 is provided with a gate electrode 402 extending from the gate signal line 105. In addition, a source electrode 405 and a drain electrode 406 are provided so as to extend from the video signal line 107 and overlap with part of the gate electrode 402. Further, a drain electrode 406 and a source electrode 405 are provided so as to overlap a part of the pixel electrode 110 provided adjacent to the gate signal line 105 and the video signal line 107 and a part of the gate electrode 402. Needless to say, each TFT 109 includes the gate electrode 402, the source electrode 405, and the drain electrode 406.

  FIG. 4 is a diagram for explaining a cross-sectional configuration of the TFT in this embodiment. As shown in FIG. 4, the TFT 109 includes a glass substrate 401, a gate electrode 402, a gate insulating film 403, a stacked channel 404, a source electrode 405, and a drain electrode 406 in order from the bottom in the figure.

  The stacked channel 404 includes oxide semiconductors 407 and 409 and a moisture-containing film 408. Here, the oxide semiconductors 407 and 409 include, for example, a lower oxide semiconductor 407 and an upper oxide semiconductor 409 as illustrated in FIG. 4, and the oxide semiconductors 407 and 409 are provided between the lower oxide semiconductor 407 and the upper oxide semiconductor 409. The moisture-containing film 408 is disposed so as to be in contact with the oxide semiconductors 407 and 409. Note that the case where the moisture-containing film 408 is disposed between the lower oxide semiconductor 407 and the upper oxide semiconductor 409 has been described above; however, the moisture-containing film 408 is disposed so as to be in contact with the single-layer oxide semiconductor. Also good. Specifically, for example, the moisture-containing film 408 is formed between the single-layer oxide semiconductor and the gate insulating film 403 or between the source electrode 405 and the drain electrode 406 and the single-layer oxide semiconductor. You may arrange | position between.

  The moisture-containing film 408 is preferably disposed between 20% and 80% of the thickness of the oxide semiconductor (the sum of the lower oxide semiconductor 407 and the upper oxide semiconductor 409). Further, at least the moisture-containing film 408 before annealing described later may be a film containing moisture, or may be an O atom-containing film or an OH atom-containing film containing O atoms or OH atoms. Note that as the material of the moisture-containing film 408, for example, a silicon oxide (SiO) film, a silicon nitride (SiN) film, a silicon nitride oxide (SiON) film, or the like is used. In addition, as the moisture-containing film 408, for example, an insulating film, a semimetal film, a metal film, or the like may be used.

  In addition, the concentration of moisture, O atoms, and the like in the moisture-containing film 408 is higher than the concentrations of moisture and O atoms in the oxide semiconductors 407 and 409. Specifically, for example, the concentration of the moisture-containing film 408 may be 1 atm% to 30 atm%. Furthermore, as will be described later, the film thickness of the moisture-containing film 408 is preferably 2 nm or less, for example. Further, the moisture-containing film 408 does not need to be provided as a continuous continuous film as illustrated in FIG. 4 and may be provided discontinuously on the lower oxide semiconductor 407 or the like.

  The thickness of the oxide semiconductor (the sum of the lower oxide semiconductor 407 and the upper oxide semiconductor 409) is preferably 5 nm to 200 nm, for example. Note that in the case where the oxide semiconductor is formed as a single layer as described above, the thickness of the oxide semiconductor may be, for example, 5 nm to 200 nm. Note that the upper oxide semiconductor 409 and the lower oxide semiconductor 407 may be formed using the same material or different materials. As a material of the oxide semiconductors 407 and 409, for example, an amorphous or crystalline oxide semiconductor containing In—Ga—Zn—O or at least one element of In, Ga, Zn, and Sn as described later is used. Is used.

  Further, as the gate electrode 402, for example, a single layer of a low resistance metal such as Mo, W, Al, Cu, Cu—Al alloy, Al—Si alloy, Mo—W alloy, or a laminated structure thereof, a gate insulating film As 403, for example, a single layer of an insulating film such as a silicon oxide film (SiO), a silicon nitride film (SiN), a silicon oxynitride film (SiON), or a laminated structure thereof is used. Examples of the source / drain electrodes 405 and 406 (including wiring portions connected to the source or drain electrodes 405 and 406) include Mo, W, Al, Cu, Cu—Al alloy, Al—Si alloy, and Mo. A single layer of a low-resistance metal such as a W alloy or a laminated structure thereof).

  Next, a manufacturing method of the TFT in this embodiment will be described with reference to FIGS. Here, FIG. 5A thru | or G are figures which show the cross-section of TFT in each step of the flow of the said manufacturing method. FIG. 6 is a diagram for explaining the flow of the manufacturing method in the present embodiment.

  As shown in FIG. 5A, first, a gate electrode layer for forming a gate electrode 402, for example, Al, about 300 nm, and Mo, about 50 nm are formed on a glass substrate 401 by using a sputtering apparatus. Further, the gate electrode layer is processed into an island shape by well-known photolithography and wet etching or dry etching to form the gate electrode 402 (S101). In addition to the above, the gate electrode layer may be a single layer of a low resistance metal such as Mo, W, Al, Cu, Cu—Al alloy, Al—Si alloy, Mo—W alloy, or a stacked layer thereof. It is good also as a structure.

  Next, as shown in FIG. 5B, for example, a silicon oxide film (SiO) to be the gate insulating film 403 is formed with a plasma chemical vapor deposition (PECVD) apparatus at a film formation temperature of 350 ° C. and a film formation gas of SiH 4. And N2O are used to form a film of about 200 nm (S102). Note that the gate insulating film 403 may be a single layer of an insulating film such as a silicon oxide film (SiO), a silicon nitride film (SiN), or a silicon oxynitride film (SiON), or a stacked structure thereof.

  Next, as illustrated in FIGS. 5C and 5D, a stacked channel 404 including a lower oxide semiconductor 407, a moisture-containing film 408, and an upper oxide semiconductor 409 is formed. For the lower and upper oxide semiconductors 407 and 409, for example, an oxide of In—Ga—Zn—O is used.

  Specifically, first, as shown in FIG. 5C, for example, with a sputtering apparatus, In 2 Ga 2 ZnO 7 is used as a target material, oxygen is added to Ar gas, and an oxide of In—Ga—Zn—O is formed to a thickness of 25 nm. By forming a film, the lower oxide semiconductor 407 is formed (S103). Then, using a PECVD apparatus, a moisture-containing film 408 is formed to a thickness of about 1 nm using TEOS and O2 as the deposition gas at a temperature of 400 ° C. (S104). Next, as shown in FIG. 5D, an In—Ga—Zn—O (IGZO) oxide film having a thickness of 25 nm is formed using a DC sputtering apparatus using In 2 Ga 2 ZnO 7 as a target material and adding oxygen to Ar gas. Thus, the upper oxide semiconductor 409 is formed (S105).

  Note that the material of the oxide semiconductors 407 and 409 is an amorphous or crystalline oxide semiconductor containing at least one element of In, Ga, Zn, and Sn in addition to the In—Ga—Zn—O. Also good. Specifically, for example, an In—Ga—Zn oxide, an In—Ga oxide, an In—Zn oxide, an In—Sn oxide, a Zn—Ga oxide, a Zn oxide, or the like may be used. The lower layer and upper layer oxide semiconductors 407 and 409 may use the same material, or may use different materials such as IGZO as the lower layer oxide semiconductor 407 and ITO as the upper layer oxide semiconductor 409.

  Here, the TEOS film of the moisture-containing film 408 is originally an insulating film, but if the film thickness is about 2 nm or less, the current flowing through the moisture-containing film flows as a tunnel current and does not affect the on-current. . On the other hand, if it is about 2 nm or more, it functions as an insulating film, and the on-current is drastically reduced. For this reason, the TEOS film of the moisture-containing film 408 is formed to be about 2 nm or less.

  When a TEOS film of about 2 nm or less is formed, it may be difficult to form a uniform film. Therefore, the TEOS film may be formed in an island shape, and the other portions may not be formed. . In this case, SiO, Si, O 2, OH, etc., which are residues of the film forming gas, remain in the portions where the film is not formed. O2 and OH of the residue are diffused into the IGZO film by an annealing process to be described later, and the IGZO film is terminated with oxygen, which can contribute to improvement of on-current. Therefore, the moisture-containing film 408 may be formed in an island shape.

  Next, as shown in FIG. 5E, the laminated channel 404 is formed by processing into an island shape by well-known photolithography, wet etching, or dry etching (S106).

  Next, as shown in FIG. 5F, a laminated structure (source / drain electrode layer) of Ti 50 nm / Al 400 nm / Ti 50 nm for forming the source / drain electrodes 405 and 406 (including wiring) is formed by a sputtering apparatus (S107). The source / drain electrode layer may be a single layer of a low resistance metal such as Mo, W, Al, Cu, Cu—Al alloy, Al—Si alloy, Mo—W alloy, or a laminated structure thereof.

  Next, as shown in FIG. 5G, the source / drain electrode layer is processed into a predetermined shape to form a source electrode 405, a drain electrode 406, and wiring portions thereof (S108). Note that the shape shown in FIG. 5G is an example, and the present invention is not limited to this.

  Next, for example, a silicon oxide film, which becomes a passivation film (not shown), is formed by a PECVD apparatus at a film forming temperature of about 250 ° C. and a film forming gas of SiH 4 and N 2 O with a thickness of about 400 nm. Note that the passivation film may be an insulating film such as a silicon nitride (SiN) film, a silicon nitride oxide (SiON) film, and other metal oxide films. Further, as the film forming method, other sputtering, vapor deposition, or the like may be used.

  Finally, annealing is performed for about 1 hour in a nitrogen atmosphere at about 300 ° C. (S110). Accordingly, moisture in the moisture-containing film 408 can be diffused into the IGZO film, and the In—Ga—Zn—O oxide can be terminated with oxygen. As a result, the on-current of the TFT 109 can be improved. Note that although the case where the annealing process is performed last is described above, the annealing may be performed at a different stage as long as it is performed after the formation of the upper oxide semiconductor 409 (S105).

  According to this embodiment, since the moisture-containing film 408 functions as a storage layer for oxygen, moisture, and the like, oxygen is contained in the oxide semiconductors 407 and 409 by the annealing treatment during the formation of the moisture-containing film 408 or after the TFT 109 is formed. In addition, moisture and the like can be diffused more uniformly and sufficiently. As a result, the mobility of the oxide semiconductors 407 and 409 can be increased, and the on-state current of the TFT 109 can be increased. Furthermore, the rise of the drain current with respect to the gate voltage can be made steep, and the switch characteristics can be made better (decrease in the S value). In addition, the time required for the annealing process can be further shortened. As a result, the frame area in the display device 100 can be narrowed and the definition can be increased.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. For example, it can be replaced with a configuration that is substantially the same as the configuration described in the above embodiment, a configuration that exhibits the same operational effects, or a configuration that can achieve the same purpose.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. While the first embodiment has a so-called bottom gate thin film transistor structure, the present embodiment is mainly different in that it has a so-called top gate thin film transistor structure. In the following, description of the same points as in the first embodiment will be omitted.

  FIG. 7 is a diagram for explaining a cross-sectional configuration of the TFT 109 in this embodiment. As shown in FIG. 7, the TFT 109 includes a glass substrate 701, a contamination barrier film 702, source / drain electrodes 703 and 704, a stacked channel 705, a gate insulating film 706, and a gate electrode 707 in order from the bottom in the figure. Here, as the contamination barrier film 702, for example, a single layer of an insulating film such as a silicon oxide film (SiO), a silicon nitride film (SiN), a silicon oxynitride film (SiON), or a laminated structure thereof is used. Note that the stacked channel 705 is formed by stacking a lower oxide semiconductor 708, a moisture-containing film 709, and an upper oxide semiconductor 710, as in the first embodiment.

  Next, a manufacturing method of the TFT 109 in this embodiment will be described with reference to FIGS. 8A to 8G and FIG. 8A to 8G are diagrams showing a cross-sectional structure at each stage of the flow of the manufacturing method. FIG. 9 is a diagram for explaining the flow of the manufacturing method according to the present embodiment.

  First, as shown in FIG. 8A, a silicon nitride film that is a contamination barrier film 702 (insulating film) is formed on a glass substrate 701 using, for example, a PECVD apparatus (S201).

  As shown in FIG. 8B, source / drain electrodes 703 and 704 and wiring portions thereof are formed, for example, a laminated structure (source / drain electrode layer) of Ti 50 nm / Al 400 nm / Ti 50 nm is formed using a sputtering apparatus. (S202). The source / drain electrode layer may be a single layer of a low resistance metal such as Mo, W, Al, Cu, Cu—Al alloy, Al—Si alloy, Mo—W alloy, or a laminated structure thereof. There may be.

  As shown in FIG. 8C, the source / drain electrode layer is processed to form source / drain electrodes 703, 704, etc. (S203). The shape shown in FIG. 8C is an example, and the shape of the source / drain electrodes 703, 704, etc. is not limited to this.

  Next, as illustrated in FIG. 8D, a stacked channel layer that forms the stacked channel 705 including the lower oxide semiconductor 708, the moisture-containing film 709, and the upper oxide semiconductor 710 is formed. Note that the oxide semiconductors 708 and 710 may be formed using an oxide of In—Ga—Zn—O, for example.

  Specifically, for example, first, using a sputtering apparatus, In 2 Ga 2 ZnO 7 is used as a target material, oxygen is added to Ar gas, and the oxide of In—Ga—Zn—O is formed to a thickness of about 25 nm. Thus, a lower oxide semiconductor layer for forming the lower oxide semiconductor 708 is formed (S204).

  Next, a moisture-containing film 709 is formed with a PECVD apparatus at a temperature of 400 ° C. using TEOS and O 2 as a film forming gas (S205).

  Next, an oxide of In—Ga—Zn—O (IGZO) is formed with a DC sputtering apparatus using In 2 Ga 2 ZnO 7 as a target material and oxygen is added to Ar gas to form a film with a thickness of about 25 nm. Thus, an upper oxide semiconductor layer for forming the upper oxide semiconductor 710 is formed (S206).

  Note that as in the first embodiment, the oxide semiconductors 708 and 710 are made of an amorphous material containing at least one element of In, Ga, Zn, and Sn in addition to the In—Ga—Zn—O. Alternatively, a crystalline oxide semiconductor may be used. Specifically, for example, an In—Ga—Zn oxide, an In—Ga oxide, an In—Zn oxide, an In—Sn oxide, a Zn—Ga oxide, a Zn oxide, or the like may be used. The lower layer and upper layer oxide semiconductors 708 and 710 may use the same material, or may use different materials such as IGZO as the lower layer oxide semiconductor 708 and ITO as the upper layer oxide semiconductor 710.

  Here, as in the first embodiment, the TEOS film of the moisture-containing film 709 is originally an insulating film. If the film thickness is about 2 nm or less, the current flowing through the moisture-containing film 709 is a tunnel current. And does not affect the on-current. On the other hand, if it is about 2 nm or more, it functions as an insulating film, and the on-current is drastically reduced. For this reason, the TEOS film of the moisture-containing film 709 is formed to be 2 nm or less.

  Similarly to the first embodiment, when a TEOS film having a thickness of about 2 nm or less is formed, it may be difficult to form a uniform film. Therefore, a TEOS film is formed in an island shape. Other portions may not be formed. In this case, SiO, Si, O 2, OH, etc., which are residues of the film forming gas, remain in the portions where the film is not formed. O2 and OH of the residue are diffused into the IGZO film by an annealing process to be described later, and the IGZO film is terminated with oxygen, which can contribute to improvement of on-current. Therefore, the moisture-containing film 709 may be formed in an island shape. Note that the material of the moisture-containing film 709 may be a silicon oxide (SiO) film, a silicon nitride (SiN) film, a silicon nitride oxide (SiON) film, an insulating film such as AlO or TiO.

  Next, as shown in FIG. 8E, the laminated channel layer is processed into an island shape by photolithography, wet etching, or dry etching to form a laminated channel 705 (S207).

  Next, as shown in FIG. 8F, for example, a silicon oxide film to be the gate insulating film 706 is formed using a plasma enhanced chemical vapor deposition (PECVD) apparatus at a film formation temperature of 350 ° C. and a film formation gas of SiH 4 and N 2 O. About 200 nm is formed (S208). Note that the gate insulating film 706 may be a single layer of an insulating film such as a silicon oxide film (SiO), a silicon nitride film (SiN), a silicon oxynitride film (SiON), or a stacked structure thereof. Then, a stacked layer (gate electrode layer) of Mo 50 nm, Al 300 nm, and Mo 50 nm for forming the gate electrode 707 is formed by a sputtering apparatus (S209). Note that a material for forming the gate electrode 707 is, for example, a single layer of a low-resistance metal such as Mo, W, Al, Cu, a Cu—Al alloy, an Al—Si alloy, or a Mo—W alloy, or a stacked layer thereof. It may be a structure.

  Next, as shown in FIG. 8G, the gate electrode layer is processed into an island shape by photolithography, wet etching, or dry etching to form a gate electrode 707 (S210).

  Next, for example, a silicon oxide film to be a passivation film (not shown) is formed with a PECVD apparatus at a film forming temperature of 250 ° C., using SiH 4 and N 2 O as film forming gas (S211) (S211). Note that the passivation film may be an insulating film such as a silicon nitride (SiN) film, a silicon nitride oxide (SiON) film, and other metal oxide films. Further, as a film forming method, other sputtering, vapor deposition, or the like may be used.

  Finally, annealing is performed for about 1 hour in a nitrogen atmosphere at 300 ° C. (S212). Accordingly, similarly to the first embodiment, moisture or the like of the moisture-containing film 709 can be diffused into the IGZO film, and the In—Ga—Zn—O oxide can be terminated with oxygen. As a result, the on-current of the TFT 109 can be improved. In the above description, the annealing process is performed last. However, the annealing process may be performed at different stages as long as it is performed after the formation of the upper oxide semiconductor 710 (S206).

  Similar to the first embodiment, according to the present embodiment, since the moisture-containing film 709 functions as a storage layer for oxygen, moisture, etc., annealing treatment during the formation of the moisture-containing film 709 or after the formation of the TFT 109 is performed. Accordingly, oxygen, moisture, and the like can be more uniformly and sufficiently thermally diffused in the oxide semiconductors 708 and 710. As a result, the mobility of the oxide semiconductors 708 and 710 can be further increased, and the on-state current of the TFT 109 can be further increased. Furthermore, the rise of the drain current with respect to the gate voltage can be made steep, and the switch characteristics can be made better (decrease in the S value). In addition, the time required for the annealing process can be further shortened.

  The present invention is not limited to the first or second embodiment, and various modifications can be made. For example, it can be replaced with a configuration that is substantially the same as the configuration described in the first or second embodiment, a configuration that exhibits the same operational effects, or a configuration that can achieve the same purpose.

  For example, in the above description, the liquid crystal display device has been mainly described. However, the present invention is not limited to this. You may apply. In the above description, the TFT 109 in the pixel region 130 has been described. However, the present invention is not limited to this, and the TFT 109 may be applied to a TFT constituting the shift register circuit 104, the driver 106, or the like.

  In addition, the image display device according to the present embodiment described above can be employed as a display device for displaying various information such as a personal computer display, a TV broadcast reception display, and a notification display. Further, it can be used as a display unit of various electronic devices such as a digital still camera, a video camera, a car navigation system, a car audio, a game device, and a portable information terminal. Note that the first electrode layer in the claims includes, for example, an electrode layer that forms the gate electrode 402, or an electrode layer that forms the source electrode 703 and the drain electrode 704, and the second electrode layer includes , An electrode layer for forming the source electrode 405 and the drain electrode 406, or an electrode layer for forming the gate electrode 707.

100 display device, 101 filter substrate, 102 TFT substrate, 103 backlight, 104 shift register circuit, 105 gate signal line, 106 driver, 109 TFT, 110 pixel electrode, 111 common electrode, 130 pixel region, 401, 701 glass substrate, 402, 707 Gate electrode, 403, 706 Gate insulating film, 404, 705 Stacked channel, 405, 703 Source electrode, 406, 704 Drain electrode, 407 Lower oxide semiconductor, 408 Water-containing film, 409 Upper oxide semiconductor, 702 Contamination Barrier film.

Claims (18)

A first substrate;
A source electrode and a drain electrode formed on the upper side of the first substrate;
An oxide semiconductor formed on the source electrode and the drain electrode;
A gate insulating film formed on the oxide semiconductor;
A gate electrode formed on the gate insulating film;
A display device comprising: an oxygen atom-containing film disposed between the source and drain electrodes and the gate insulating film so as to be in contact with the oxide semiconductor.   The display device according to claim 1, wherein the oxygen atom-containing film is one of a metalloid film, a metal film, and an insulating film having a thickness of 2 nm or less.   The display device according to claim 2, wherein the oxygen atom-containing film is provided between 20% and 80% of the thickness of the oxide semiconductor.   The display device according to claim 1, wherein the oxygen atom-containing film is a discontinuous film.   The display device according to claim 1, wherein a thickness of the oxygen atom-containing film is smaller than a thickness of the gate insulating film.   The display device according to claim 1, wherein the oxide semiconductor includes a first oxide semiconductor layer and a second oxide semiconductor layer.   The display device according to claim 1, wherein the oxide of the oxide semiconductor is terminated with oxygen.   The display device according to claim 1, wherein the gate insulating film is an oxide film.   The display device according to claim 1, further comprising a passivation film formed on the gate electrode.   The display device according to claim 9, wherein the passivation film is a nitride film. Forming at least a first electrode layer on an upper side of the first substrate;
Forming a channel layer including an oxide semiconductor layer and an oxygen atom-containing film on the first substrate on which the at least first electrode layer is formed;
Forming at least a second electrode layer on the substrate on which the channel layer is formed;
A method for manufacturing a display device, characterized in that oxygen atoms contained in the oxygen atom-containing film are diffused into the oxide semiconductor layer by annealing in a nitrogen atmosphere.   12. The method for manufacturing a display device according to claim 11, wherein the oxygen atom-containing film is formed of any one of a metalloid film, a metal film, and an insulating film having a thickness of 2 nm or less.   The method for manufacturing a display device according to claim 11, wherein the oxygen atom-containing film is thinner than the gate insulating film.   The method for manufacturing a display device according to claim 11, wherein the oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer.   15. The method for manufacturing a display device according to claim 11, wherein the oxide of the oxide semiconductor is terminated with oxygen.   The method for manufacturing a display device according to claim 11, wherein the gate insulating film is an oxide film.   The method for manufacturing a display device according to claim 11, wherein a passivation film is formed on the second electrode layer. The method of manufacturing a display device according to claim 11, wherein the annealing is performed after the second electrode layer is formed.

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