JP2017107441A - Information processing device, and control device and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To guarantee completion of data write to a shared memory in an information processing device having a plurality of master devices connecting to each of a plurality of buses and a shared memory used by the plurality of master devices.SOLUTION: A monitoring unit 25a monitors a read access, via a bus bridge 18 by a CPU 12 connected to a system bus 17, to status information indicating the occurrence of data write of an IO controller 11 connected to an IO bus 16 that corresponds to the occurrence of data write to a shared memory 14a via a bus bridge 13 by the IO controller 11. When the monitoring unit 25a detects a read access to the status information, a mask unit 25c controls supply of the status information acquired by the read access from the bus bridge 18 to the CPU 12 on the basis of the state of data staying stagnant in the bus bridge 13 due to data write of the IO controller 11.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an information processing apparatus having a plurality of master devices connected to each of a plurality of buses and a shared memory used by the plurality of master devices.

  A plurality of master devices (hereinafter referred to as masters) connected to each of a plurality of buses may use the main storage unit as a shared memory. In this case, the first master connected to the first bus frequently writes data to the shared memory, and the second master connected to the second bus frequently reads the data from the shared memory. When data written by the first master to the shared memory is read from the shared memory by the second master, the data writing to the shared memory by the first master is completed before the reading operation of the second master is started. Need to be guaranteed. An example of a technique for this is proposed in Patent Document 1.

  According to Patent Document 1, a monitor circuit that monitors completion of data transfer for the number of transfers staying in a data buffer inside a bus bridge connected between a first bus and a second bus is arranged. Then, an interrupt signal (first master interrupt signal) for notifying the end of transfer is input from the first master to the monitor circuit. The monitor circuit receiving the interrupt signal counts completion of data transfer for the number of transfers staying in the data buffer inside the bus bridge, and outputs the interrupt signal to the second master when the count reaches zero. After the second master receives the interrupt signal from the monitor circuit (in other words, the delayed first master interrupt signal), the second master reads the data from the shared memory to the shared memory. It is possible to read data for which data writing completion is guaranteed.

JP 2012-113615 A

  The technique of Patent Document 1 is the case where the first master performs multi-channel data transfer, and the interrupt signal of the first master that notifies the end of transfer is a single interrupt signal that summarizes multiple factors. Problems can occur. For example, the second master to which the interrupt signal is input from the monitor circuit acquires the value of the status register indicating the transfer state of the first master, and determines the channel in which data writing to the shared memory has been completed. . If channel ch2 data transfer occurs after the completion of channel ch1 data transfer and immediately before the status register value is acquired, the status register value acquired by the second master is the data for both channels ch1 and ch2. It will indicate the completion of transfer.

  The bus bridge determines whether or not to output the data in the internal data buffer according to the congestion status of the system bus. When the system bus is congested, data is temporarily stored in the data buffer in the bus bridge. Therefore, even if the value of the status register indicates the completion of data transfer for both channels ch1 and ch2, for example, data for channel ch2 may remain in the data buffer of the bus bridge (in other words, data transfer Incomplete). When the data transfer of channel ch2 has not been completed, the master 12 reads data that is not guaranteed to be completely written to the shared memory.

  An object of the present invention is to guarantee completion of data writing to a shared memory in an information processing apparatus having a plurality of master devices connected to each of a plurality of buses and a shared memory used by the plurality of master devices. .

  The present invention has the following configuration as one means for achieving the above object.

  A control device according to the present invention is a control device in an information processing device having a plurality of master devices connected to each of a plurality of buses and a shared memory used by the plurality of master devices, and connected to the first bus Via the second bus bridge by the second master device connected to the second bus in response to the occurrence of data writing to the shared memory via the first bus bridge by the first master device Monitoring means for monitoring read access of status information indicating the occurrence of data writing of the first master device; and when the read access of the status information is detected by the monitoring means, data of the first master device Based on the state of data staying in the first bus bridge by writing, the acquired by the read access From said second bus bridge status information and a control means for controlling the supply to the second master device.

  According to the present invention, in an information processing apparatus having a plurality of master devices connected to each of a plurality of buses and a shared memory used by the plurality of master devices, completion of data writing to the shared memory can be guaranteed. .

2 shows a configuration example of an information processing device and a status register status of an IO controller. 1 is a block diagram illustrating a configuration example of an information processing apparatus according to a first embodiment. The flowchart explaining the process of a control circuit. FIG. 3 is a block diagram illustrating a configuration example of an information processing apparatus according to a second embodiment. The flowchart explaining the process of a control circuit.

  Hereinafter, an information processing apparatus according to an embodiment of the present invention, and a control apparatus and control method thereof will be described in detail with reference to the drawings. In addition, an Example does not limit this invention concerning a claim, and all the combinations of the structure demonstrated in an Example are not necessarily essential for the solution means of this invention.

  In the following description, an IO controller connected to the peripheral device IO bus and a CPU connected to the system bus will be described as examples of the master device. That is, an example will be described in which the IO controller performs data write processing on the shared memory managed by the memory controller connected to the system bus, and the CPU performs read processing of the data from the shared memory. However, the embodiments do not limit the types of master devices, and various types of master devices are the subject of the present invention. In the embodiment, for example, an AHB bus in an on-chip bus architecture is assumed as an IO bus, and an AXI bus is assumed as a system bus. However, the present invention is not limited to the type of bus, and can be applied to an information processing apparatus using various buses connected via a bus bridge.

Device configuration An example of the configuration of the information processing device is shown in the block diagram of FIG. The IO controller 11 performs a DMA (direct memory access) write process for writing data to the (shared) memory 14a managed by the memory controller 14 via the IO bus 16, the bus bridge 13, and the system bus 17. The IO controller 11 can perform a plurality of channels of DMA write processing to the memory 14a in parallel. In the following, an example in which the IO controller 11 performs 2-channel DMA write processing will be described, but the number of channels may be “2” or more. The IO controller 11 outputs a single interrupt signal 22 to the monitor circuit 15 when the DMA write processing is completed. FIG. 1B shows the state of the status register 11a of the IO controller 11 after the DMA write processing of channel ch1 by the IO controller 11 is completed.

  The monitor circuit 15 to which the interrupt signal 22 is input sets the number of data staying in the data buffer 13a in the bus bridge 13 as a count value in the counter 15b. The counter value is decremented each time the transfer of each data staying in the data buffer 13a is completed, and when the count value becomes zero, the counter 15b outputs a transfer completion signal indicating the completion of the data transfer to the interrupt delay circuit 15a. The interrupt delay circuit 15a to which the transfer completion signal is input outputs the interrupt signal 24 to the CPU 12.

  The CPU 12 to which the interrupt signal 24 has been input sends the value of the status register 11a (hereinafter, status information) indicating the DMA write processing status (data write status) of the IO controller 11 via the bus bridge 18 and the IO bus 16. ) To get. The status register 11a is mapped in advance to an address on the memory map of the IO controller 11 (hereinafter referred to as SR address). The CPU 12 acquires status information by accessing the SR address.

  The CPU 12 determines a channel for which data transfer has been completed based on the status information. In the example of FIG. 1B, it is determined that the data transfer of the channel ch1 is completed. Based on the status information, the CPU 12 performs a read process of reading data from the memory 14a that is guaranteed to be written to the memory 14a via the system bus 17 and the memory controller 14.

  In this manner, data transfer processing from the IO controller 11 to the CPU 12 in the information processing apparatus having a plurality of master devices connected to each of the plurality of buses and a shared memory used by the plurality of master devices is realized. However, after the channel ch1 DMA write processing is completed, the channel ch2 DMA write processing may occur before the CPU 12 acquires the status information. In this case, status information indicating completion of DMA write processing for both channels ch1 and ch2 is acquired.

  FIG. 1 (c) shows the state of the status register 11a indicating the completion of DMA write processing for both channels ch1 and ch2. Even if the CPU 12 to which the interrupt signal 24 is input acquires the status information shown in Fig. 1 (c), the writing to the memory 14a is not actually completed, and the data of the channel ch2 stays in the data buffer 13a. There is a possibility. In that case, the CPU 12 performs a reading process of reading data of the channel ch2 for which the completion of writing to the memory 14a is not guaranteed.

Apparatus Configuration A configuration example of the information processing apparatus according to the first embodiment is shown in the block diagram of FIG. The same components as those in FIG. 1 (a) are denoted by the same reference numerals, and detailed description thereof is omitted. In the configuration shown in FIG. 2, the interrupt signal 22 is directly input to the CPU 12, and the CPU 12 to which the interrupt signal 22 is input performs read access to the status register 11a (hereinafter, status information access). The configuration shown in FIG. 2 includes a control circuit 25 that replaces the monitor circuit 15 shown in FIG.

  In the control circuit 25, the monitor 25a monitors status information access by the CPU 12, and detects the occurrence of status information access. As a detection method of status information access, the SR address is stored in the monitor 25a, the address signal and command of the IO bus 16 are monitored, and the issue of the read command (read access occurrence) to the SR address may be detected.

  The mask unit 25c has a mask function for two control signals. The first control signal is a read data receivable notification signal (hereinafter referred to as RREADY signal) 31 connected from the system bus 17 to the bus bridge 18, and an M_RREADY signal 32 obtained by masking the RREADY signal 31 is connected to the bus bridge 18. To do. The second control signal is a read data valid notification signal (hereinafter, RVALID signal) 33 connected from the bus bridge 18 to the system bus 17, and connects the M_RVALID signal 34 obtained by masking the RVALID signal 33 to the system bus 17. .

  The RREADY signal 31 is a signal that notifies the CPU 12 that the bus bridge 18 is ready for data reception. The RVALID signal 33 is a signal indicating that the transmission data is valid for the CPU 12 to the bus bridge 18. Transmission and reception of data from the bus bridge 18 to the CPU 12 is established by the exchange of these two control signals. Although not shown, the mask unit 25c is, for example, a signal that becomes H level when a control signal is connected to one input of a simple AND circuit with two inputs and one output, and the condition for canceling the mask is satisfied at the other input. This can be realized by inputting (a mask release signal described later). Here, the configuration of the mask portion 25c is not limited.

  When the monitor 25a detects the status information access, the control circuit 25 masks the RREADY signal 31 and the RVALID signal 33 to the disabled state by the mask unit 25c. The control circuit 25 further sets the number of data staying in the data buffer 13a in the bus bridge 13 (hereinafter sometimes referred to as “staying data”) in the counter 25b as a count value. The count value is decremented each time the transfer of each data staying in the data buffer 13a is completed, and when the count value becomes zero, a mask release signal is output from the counter 25b. The mask unit 25c to which the mask release signal is input releases the mask of the RREADY signal 31 and the RVALID signal 33.

  The bus bridge 18 temporarily holds the status information read by the status information access. When the masking of the RREADY signal 31 and the RVALID signal 33 is cancelled, data transmission / reception from the bus bridge 18 to the CPU 12 is established, and the CPU 12 acquires status information held in the bus bridge 18.

The following situation is assumed as the relationship between the status information acquired by the status information access corresponding to the input of the interrupt signal 22 and the staying data.
Situation A: Status information '10', channel ch1 DMA write processing complete, write to shared memory complete (no stagnant data),
Situation B: Status information '10', channel ch1 DMA write processing complete, write to shared memory has not been completed (there is no stagnant data),
Situation C: Status information '11', channel ch1 and ch2 DMA write processing complete, channel ch1 and ch2 write to shared memory complete (no stagnant data,
Situation D: Status information '11', channel ch1 and ch2 DMA write processing complete, channel ch1 write to shared memory is complete, but channel ch2 write to the shared memory is incomplete (with retained data).

  In situations A and C, there is no dwell data and data writing completion is guaranteed. Further, in the situation B, although there is staying data, the data writing completion can be guaranteed even with the configuration shown in FIG. However, the situation D cannot guarantee the completion of data writing in the configuration shown in FIG.

  When the situation B or the situation D occurs, the RREADY signal 31 and the RVALID signal 33 are masked, and the masking is released when there is no remaining data. By releasing the mask, the CPU 12 can receive the status information and access data for which data writing to the memory 14a is guaranteed to be completed.

  As shown in Fig. 1 (a), even if the interrupt signal 22 is delayed until the transfer of the stagnant data is completed, the completion of the data writing of the channel whose completion is indicated by the status information is indicated. May not be guaranteed (Situation D). On the other hand, according to the configuration shown in FIG. 2, the masking of the READY signal 31 and the RVALID signal 33 is canceled after the transfer of the staying data is completed, and the CPU 12 receives the status information. In other words, the configuration shown in FIG. 1 (a) delays the interrupt signal 22, whereas the configuration shown in FIG. 2 transfers the status information acquired from the CPU 12 status information access from the bus buffer 18 to the CPU 12. Is controlled based on the state of the staying data. As a result, according to the configuration shown in FIG. 2, even in the situation D, the CPU 12 can access data in which data writing to the memory 14a is guaranteed, triggered by reception of status information.

Processing of control circuit The processing of the control circuit 25 will be described with reference to the flowchart of FIG. The monitor 25a detects the status information access by the CPU 12 (S11), and repeats step S11 when the status information access is not detected. If status information access is detected, the process proceeds to step S12.

  When the monitor 25a detects the status information access, the control circuit 25 masks the RREADY signal 31 and the RVALID signal 33 to the disabled state by the mask unit 25c (S12). As a result, the status information read from the status register 11a and supplied to the CPU 12 is held in the bus bridge 18. Subsequently, the control circuit 25 sets the number of data staying in the data buffer 13a of the bus bridge 13 in the counter 25b as a count value (S13), monitors the bus bridge 13, and completes the transfer of each data The count value is decremented every time (S14).

  Next, it is determined whether or not the count value has become zero (S15). If the count value is not zero, the process returns to step S14. When the count value becomes zero, the process proceeds to step S16. That is, when the count value becomes zero and the mask release signal is output from the counter 25b, the masking of the RREADY signal 31 and the RVALID signal 33 by the mask unit 25c is released (S16). As a result, the status information held in the bus bridge 18 is supplied to the CPU 12. Then, the control circuit 25 returns the process to step S11 and repeats the detection of status information access.

  In this way, the RREADY signal 31 and the RVALID signal 33 are temporarily masked in the disabled state until the transfer of the data staying in the data buffer 13a of the bus bridge 13 is completed. This delays the supply of status information read from the status register 11a of the IO controller 11 and supplied to the CPU 12, and guarantees the completion of data writing to the shared memory when the CPU 12 receives the status information. . In other words, even if the interrupt signal 22 indicating the completion of data transfer of the IO controller 11 is a single interrupt signal in which multiple factors are combined, the CPU 12 does not depend on the read timing of the status register 11a by the CPU 12 in all situations Data writing completion is guaranteed. The status information supply delay method described above is merely an example, and status information supply may be delayed by another method.

  Hereinafter, an information processing apparatus and a control method thereof according to a second embodiment of the present invention will be described. Note that the same reference numerals in the second embodiment denote the same parts as in the first embodiment, and a detailed description thereof may be omitted.

Device Configuration A block diagram of FIG. 4 shows a configuration example of the information processing device of the second embodiment. In the second embodiment, the interrupt signal 22 indicating the completion of the DMA writing process is supplied not only to the CPU 12 but also to the control circuit 25. The control circuit 25 is activated using the interrupt signal 22 as a trigger. Activation of the control circuit 25 means activation of functional blocks such as the monitor 25a, the counter 25b, and the mask unit 25c in the control circuit 25. As a starting method, for example, a clock is supplied to the functional block of the control circuit 25 by the input of the interrupt signal 22, or the reset of the functional block of the control circuit 25 is released. do not do.

  After startup, the control circuit 25 maintains the startup state when the interrupt signal 22 is input at the end of execution of the series of processes, and executes a series of processes using the interrupt signal 22 as a trigger. To do. If the interrupt signal 22 is not input at the end of the series of processes, the process shifts to a non-activated state and enters a standby state for input of the interrupt signal 22. Except for the activation of the control circuit 25 triggered by the interrupt signal 22, other configurations and their operations are the same as those in the first embodiment, and thus detailed description thereof is omitted.

Processing of control circuit The processing of the control circuit 25 of the second embodiment will be described with reference to the flowchart of FIG. The control circuit 25 is in a non-activated state waiting for input of the interrupt signal 22 (S21). When the interrupt signal 22 is input, the control circuit 25 shifts to an activated state (S22), and executes the processes of steps S11 to S16 shown in FIG. After unmasking the RREADY signal 31 and the RVALID signal 33 (S16), the control circuit 25 determines whether or not the interrupt signal 22 is input (S23), and the interrupt signal 22 is input. If so, the process returns to step S11. If the interrupt signal 22 is not input, the control circuit 25 shifts to a non-activated state (S24), and the process returns to step S21.

[Other Examples]
The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read and execute the program It can also be realized by processing. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

  11… IO controller, 12… CPU, 13, 18… Bus bridge, 14a… Shared memory, 16… IO bus, 17… System bus, 25a… Monitor, 25c… Mask

Claims (12)

A control device in an information processing apparatus having a plurality of master devices connected to each of a plurality of buses, and a shared memory used by the plurality of master devices,
A second master device connected to the second bus in response to the data write to the shared memory via the first bus bridge by the first master device connected to the first bus; Monitoring means for monitoring read access of status information indicating the occurrence of data writing of the first master device via the bus bridge;
When a read access of the status information is detected by the monitoring means, the data acquired by the read access is based on a state of data staying in the first bus bridge by data writing of the first master device. And a control unit that controls supply of status information from the second bus bridge to the second master device.   2. The control device according to claim 1, wherein the first master device can perform data writing of a plurality of channels in parallel to the shared memory connected to the second bus.   3. The second master device according to claim 1, wherein the second master device reads data written in the shared memory connected to the second bus by the data writing according to the status information. Control device.   4. The control unit according to claim 1, further comprising a mask unit that masks a control signal between the second master device and the second bus bridge in response to detection of read access of the status information. The control device described in any one of the items.   The mask means is connected to the second bus from the second bus bridge to the second bus, and as a control signal, the read data receivable notification signal connected from the second bus to the second bus bridge. 5. The control device according to claim 4, wherein the read data valid notification signal is masked.   The read data receivable notification signal is a signal for notifying that the second master device is ready to receive data to the second bus bridge, and the read data valid notification signal is the second bus bridge. 6. The control device according to claim 5, wherein the bridge is a signal indicating that transmission data is valid for the second master device. The control means sets the number of staying data as a count value in a counter in response to detection of read access of the status information, and decrements the count value each time the staying data is transferred,
The control according to any one of claims 4 to 6, wherein when the count value becomes zero, the counter outputs a mask release signal, and the mask means releases the mask by the output of the mask release signal. apparatus.   The first master device outputs an interrupt signal indicating the end of the data writing to the second master device, and the second master device performs read access of the status information by the interrupt signal. 8. The control device according to any one of claims 1 to 7.   9. The control device according to claim 8, wherein the control device is activated by outputting the interrupt signal.   10. The control device according to claim 8, wherein the control device shifts to a non-activated state when the interrupt signal is not output. Multiple master devices connected to each of multiple buses;
A shared memory used by the plurality of master devices;
An information processing apparatus comprising the control device according to any one of claims 1 to 10. A control method in an information processing apparatus having a plurality of master devices connected to each of a plurality of buses, and a shared memory used by the plurality of master devices,
A second master device connected to the second bus in response to the data write to the shared memory via the first bus bridge by the first master device connected to the first bus; Monitoring read access of status information indicating the occurrence of data writing of the first master device via the bus bridge of
When the read access of the status information is detected, the status information acquired by the read access is based on the state of the data staying in the first bus bridge by the data writing of the first master device. A control method for controlling supply from the second bus bridge to the second master device.

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