JP2017104579A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of appropriately performing a power-off saving processing even when power goes off in the middle of communication between a sub substrate and a device (peripheral substrate).SOLUTION: A game machine comprises: a power-off preprocessing part that includes a processing execution state monitoring part for monitoring an execution state of a communication processing, and a time lag setting part for setting a predetermined time lag for the communication processing, and allows a power-off processing section to start backup at least after execution of the communication processing is completed; and a power-off processing initiating part that allows the power-off preprocessing part to start processing based on a predetermined signal from a power supply part. The power-off preprocessing part is kept on standby after initiation by the power-off processing initiating part until a lapse of the time lag, and allows the power-off processing part to start the backup after the lapse of the time lag.SELECTED DRAWING: Figure 71

Description

  The present invention relates to a gaming machine such as a slot machine.

  2. Description of the Related Art A gaming machine (a spinning machine, slot machine) having a plurality of spinning cylinders with symbols arranged on the outer peripheral surface is known. This type of gaming machine gives a certain game value to a game medium (medal) and performs a game for acquiring such a game medium. In addition, this type of gaming machine has an internal lottery triggered by the player's rotation start operation and starts rotation of a plurality of spinning cylinders, and a mode according to the result of the internal lottery as a player's stop operation trigger. In order to stop multiple cylinders. The game result is determined by the symbol combination displayed on the winning determination line in a state where the plurality of spinning cylinders are stopped, and medals are paid out according to the game result.

JP 2006-223544 A JP 2006-223546 A JP 2006-304898 A JP 2006-304900 A JP 2006-304901 A When the timer interrupt process and the power interruption interrupt process are simultaneous, the power interruption interrupt process has priority, and when there is a power interruption interrupt process during the execution of the timer interrupt process, After the timer interrupt process is completed, the power interruption interrupt process is executed. JP 2009-189708 A JP, 2009-189709, A While backup is given the highest priority on the main side, on the sub side, a power interruption interrupt process A for backup storage of data specifying the effect operation in progress at the time of power interruption, and a control command are the main control. By giving priority to the process B out of the reception interrupt process B that is activated when the data is transmitted from the unit, the main command is prevented from disappearing. JP 2008-295875 A JP, 2008-295876, A Game information is transmitted outside in the predetermined priority order (the highest priority is the current game situation) at the time of power failure.

  The main board and the sub board are provided with a CPU that is a processing unit that executes a process related to a game and a process related to an effect according to a predetermined program. When the power is turned off, the CPU executes a power-off saving process in response to an input of a predetermined power-off notice signal. This process includes a process for obtaining a checksum of data stored in a memory that does not lose data even when the power is turned off. The data stored in this way is backup data. Then, in the initialization process when the power is turned on, the backup data stored in the memory in which data is not lost even when the power is turned off is read and developed on the work memory that is normally used. The two operations of the power-off saving process and the initialization process realize a backup of the state before the power is turned off and a return after the power is turned on based on the backup. That is, when the gaming machine is turned on, it can return to the power-off state.

  Even if the power switch of the gaming machine is turned from on to off, the power supply voltage does not drop immediately, and after a while, the power supply voltage becomes zero. Therefore, the CPU can perform the power-off saving process after receiving the power-off signal and before stopping the operation due to the voltage drop.

To be precise, the processing performed by the CPU from “after receiving the power-off signal to when the operation is stopped due to the voltage drop” is as follows.
(Processing 1) The processing currently being executed is stopped or the end of the processing is awaited.
(Process 2) A power-off saving process is executed instead of the normal process.

  The total time of (Process 1) and (Process 2) must be shorter than “the time from when the power-off signal is received until the operation is stopped due to the voltage drop”.

  By the way, recent CPUs have come to perform multi-process processing, and there are cases where there are a plurality of processes targeted for (Process 1). In multi-process processing, in order to increase processing efficiency, a plurality of processes can be executed in parallel.

  If the data to be backed up is being processed when the power is cut off, the start of the power-off save process is sent until the end of the process. However, higher priority processing may interrupt. For this reason, the time of (Process 1) increases, and it may become impossible to complete the power-off saving process in the “time from when the power-off signal is received until the operation is stopped due to the voltage drop”. (“Stable” means that all the data to be backed up in advance has been successfully backed up).

  The present invention has been made to solve the above-described problem, and has a delay time until execution of the power-off / saving process under the multi-process process as small as possible, and can perform the power-off / saving process stably. The purpose is to provide.

The present invention includes a main board that performs processing related to a game, a sub board that receives a predetermined command from the main board and performs an effect process related to a game, and a power source that supplies power to the main board and the sub board In a gaming machine comprising a
A CPU for performing a multi-process process that simultaneously executes a plurality of processes related to the game and / or the effect process based on a predetermined priority;
A memory for storing data relating to the game and / or data relating to the effect;
In the event of a power interruption, a power interruption processing unit that backs up at least part of the data in the memory;
A priority changing unit that changes the priority of the plurality of processes, and a process execution state monitoring unit that monitors an execution state of the plurality of processes, and a predetermined process of the plurality of processes An electrical disconnection pre-processing unit that causes the electrical disconnection processing unit to start backup after execution is completed,
An electrical disconnection process starting unit that starts the electrical disconnection preprocessing unit based on a predetermined signal from the power supply unit, and
The processing execution state monitoring unit of the power interruption preprocessing unit is
Examining the execution state of the plurality of processes based on the signal from the power interruption process starting unit,
The plurality of processes are classified into a process accessing the data to be backed up (hereinafter “first process”) and a process not accessing the data (hereinafter “second process”). And
By the priority changing unit, the priority of the second process is made lower than the priority of the first process,
Monitoring the first process to see if its execution has ended,
When the processing is completed, the power interruption processing unit performs backup.

When the first process includes a plurality of processes,
The processing execution state monitoring unit of the power interruption preprocessing unit is
Monitoring the first process to see if its execution has ended,
When a part of the first process is finished, the priority of the part of the process is made lower than the priority of the remaining first process by the priority changing unit,
When the entire execution of the first process is completed, the power interruption processing unit may perform backup.

The priority changing unit includes a priority table that holds the priority for each of the plurality of processes related to the multi-process process,
When the priority of the second process is set lower than the priority of the first process, the priority of the second process is set to the lowest one of the predetermined priorities in the priority table. You may do it.

  According to the present invention, under a multi-process process in which a plurality of processes are simultaneously processed in parallel, the plurality of processes are processed by accessing the data to be backed up (first process) and the data. Since the priority of the second process is lower than the priority of the first process, it is distinguished from the process that has not been accessed (second process), so the power is cut off immediately without interrupting the second process. Processing can be executed. Even under multi-process processing, the delay time until execution of the power interruption process can be minimized, and the power interruption process can be performed stably.

It is a front view of the slot machine which shows the state which closed the front door. It is a front view of the slot machine which shows the state which opened the front door 180 degree | times. It is a block diagram of a slot machine. It is a flowchart of the gaming process of the slot machine. 5A is a perspective view of the jog dial, FIG. 5B is a block diagram of the jog dial, and FIG. 5C is a block diagram of the command transmission unit of the main board. It is explanatory drawing of the communication system of a sub board | substrate and a peripheral board | substrate. It is a block diagram of a data transmission part. It is explanatory drawing of the process regarding a peripheral board | substrate. It is a functional block diagram of VDP (video display processor). It is explanatory drawing (timing chart) of each process of drawing data preservation | save in VDP, drawing execution, and a display. It is a block diagram of a sound controller. It is explanatory drawing of audio | voice data. It is the schematic of a movable body (an example). 4A is a top view, FIG. 2B is a front view, FIG. 4C is a cross-sectional view taken along the line BB, and FIG. 4D is a cross-sectional view taken along the line A-A. It is explanatory drawing of the open state (the figure (a)) and closed state (the figure (b)) of a movable element (shutter). It is a block diagram of a movable body control part. It is a flowchart of a movable body effect process. It is explanatory drawing of the relationship between the main process and the interruption process in control of a periphery board | substrate. 1 is a block diagram of a gaming machine according to the present embodiment (a configuration for synchronizing operations among a plurality of peripheral boards). It is explanatory drawing of the movement of the control data in the input / output of a control data and a buffer (memory element) of the gaming machine according to the present embodiment (one control data). It is explanatory drawing of the movement of the control data in the input / output of a control data and a buffer (memory element) of the gaming machine according to the present embodiment (two control data). It is explanatory drawing of the input / output of the control data of the gaming machine according to the present embodiment and the movement of the control data in the buffer (storage element) (one control data, error occurs). FIG. 4 is a reference diagram of input / output of control data of a gaming machine and movement of control data in a buffer (storage element) (two control data, error occurrence, error overwriting). It is explanatory drawing of the input / output of the control data of the gaming machine according to the present embodiment and the movement of the control data in the buffer (storage element) (two control data, error occurs). It is a process flowchart at the time of the error signal reception of the gaming machine according to the present embodiment. It is explanatory drawing of the movement of the control data in the input / output of a control data and a buffer (memory element) of the gaming machine according to another embodiment (two control data, error occurs). It is another explanatory view of the input / output of control data and the movement of the control data in the buffer (storage element) of the gaming machine according to the other embodiment (two control data, error occurs). It is a process flowchart at the time of the error signal reception of the gaming machine according to another embodiment. It is explanatory drawing of the movement of the control data in the input / output of a control data and a buffer (memory element) of the gaming machine according to another embodiment (three control data, error occurs). It is a process flowchart at the time of the error signal reception of the gaming machine according to another embodiment. It is a flowchart of the chattering removal process which concerns on this Embodiment. It is a truth table concerning this embodiment. It is a truth table concerning this embodiment. It is a truth table concerning this embodiment. It is a truth table concerning this embodiment. It is a block diagram of the chattering removal apparatus which concerns on this Embodiment. It is a timing chart for demonstrating the chattering removal process which concerns on this Embodiment. It is a truth table which shows the process result by the chattering removal process which concerns on this Embodiment. It is a flowchart of the chattering removal process which concerns on a comparative example. It is explanatory drawing of a process at the time of applying parallel processing. (A) shows the case where parallel processing is applied to the chattering removal processing according to the present embodiment) shows the case where parallel processing is applied to the comparative example. It is explanatory drawing of the output signal of two sensors of a jog dial. It is explanatory drawing of a signal change when rotating the rotation direction of a jog dial. It is a block diagram of the apparatus which calculates | requires the rotation amount (a rotation direction is included) of the jog dial which concerns on this Embodiment. 43 is an explanatory diagram of the contents stored in the buffer of the apparatus in FIG. 42. FIG. It is explanatory drawing (timing chart) of determination of a forward rotation / reverse rotation of a jog dial. It is a rotation detection process flowchart which concerns on this Embodiment. It is explanatory drawing (timing chart) of the rotation detection process which concerns on this Embodiment. It is a comparative example (partial flowchart) concerning the determination process of the jog dial. It is another rotation detection process flowchart which concerns on this Embodiment. It is another rotation detection processing flowchart which concerns on this Embodiment (continuation). It is explanatory drawing of writing of a sound command. It is explanatory drawing of the delay system (automatic delay and designated delay) for taking effect synchronization. It is operation | movement explanatory drawing (description figure of a command memory | storage part) of an automatic delay system. It is operation | movement explanatory drawing (command buffer explanatory drawing) of an automatic delay system. It is operation | movement explanatory drawing (state transition diagram of a command buffer) of an automatic delay system. It is explanatory drawing of the read table (command buffer) of a designated delay system. It is a state transition diagram of a read table (command buffer) of a designated delay method. It is a block diagram of a designated delay type transmission control unit according to the present embodiment. It is explanatory drawing of the relationship (power-off notice signal) of a power supply part and a sub board | substrate. It is explanatory drawing of the power interruption process in a multi-process system. It is explanatory drawing of the power interruption process in a multi-process system (continuation). It is explanatory drawing of the power interruption process in a multi-process system (continuation). It is a block diagram of the part of the power interruption process of the gaming machine according to the present embodiment. It is a flowchart of the power interruption processing apparatus of the gaming machine according to the present embodiment. It is explanatory drawing of the priority table of the electrical disconnection process which concerns on this Embodiment. It is a block diagram of the part of the electric power interruption process (instantaneous interruption countermeasure) of the gaming machine according to the present embodiment. It is a flowchart of the electric power interruption process (instantaneous interruption countermeasure) apparatus which concerns on this Embodiment. It is explanatory drawing (timing chart) of the electric power interruption process (instantaneous interruption countermeasure) which concerns on this Embodiment. It is another explanatory drawing (timing chart) of the electric power interruption process (instantaneous interruption countermeasure) which concerns on this Embodiment. It is another block diagram (comparative example) of an electric disconnection process. FIG. 70 is an explanatory diagram (timing chart) of the power interruption process of FIG. 69. It is a block diagram of the part of the power interruption process (communication process countermeasure) of the gaming machine according to the present embodiment. It is a flowchart of the electric power interruption process (communication process countermeasure) apparatus which concerns on this Embodiment. It is explanatory drawing (timing chart) of the electric power interruption process (communication processing countermeasure) which concerns on this Embodiment. It is another explanatory drawing (timing chart) of the electric power interruption process (communication processing countermeasure) which concerns on this Embodiment. It is another explanatory drawing (timing chart) of the electric power interruption process (communication processing countermeasure) which concerns on this Embodiment. It is structure explanatory drawing of the message (command) which concerns on this Embodiment. It is explanatory drawing of the message transmission / reception in the multi-process process which concerns on this Embodiment. It is explanatory drawing of the message stored in the message buffer which concerns on this Embodiment. It is operation | movement explanatory drawing (timing chart) of the timer interruption which concerns on this Embodiment, a transmission task, and a reception task (at the time of normal operation). It is operation | movement explanatory drawing of the pointer which concerns on this Embodiment (at the time of normal operation | movement). It is a block diagram of the message transmission / reception part which concerns on this Embodiment. It is a flowchart of the power interruption process which concerns on this Embodiment (only the process part which concerns on the backup of a pointer is shown). It is a flowchart of the return process which concerns on this Embodiment (only the return process part of a pointer is shown). It is operation | movement explanatory drawing (timing chart) of the timer interruption | blocking which concerns on this Embodiment, a transmission task, and a reception task (at the time of a power interruption-recovery). It is operation | movement explanatory drawing of the pointer which concerns on this Embodiment (at the time of a power failure-recovery).

<Structure of gaming machine>
FIG. 1 is a front view of the slot machine with the front door closed, and FIG. 2 is a front view of the slot machine with the front door opened 180 degrees.

  1 and 2, reference numeral 100 denotes a slot machine. As shown in FIG. 1, the slot machine 100 can be opened and closed by a hinge or the like on the slot machine main body 120 and one side of the front surface of the slot machine main body 120. And a front door 130 attached thereto. As shown in FIG. 1, a game display unit 131 is provided substantially in the center of the front door 130, and a medal insertion slot 132 for a player to insert medals is provided at the lower right corner of the game display unit 131. Provided below the medal insertion slot 132 is a reject button 133 for forcibly discharging a clogged medal inserted from the medal insertion slot 132 to the outside of the slot machine 100.

  In addition, a start switch 134 for starting a game is provided at the lower left of the game display unit 131, and three stop switches 140 are provided corresponding to the three reels. A medal payout port 135 is provided at the center of the lower end of the front door. A liquid crystal display device LCD is provided above the game display unit 131.

  A movable body 50 is provided at the position of the liquid crystal display device LCD. The movable body 50 includes two shutters (movable body elements) 51L and 51R. The two shutters 51L and 51R move to the left and right according to the effect, and hide the liquid crystal display device LCD. In the figure, the two shutters 51L and 51R are fully opened to the left and right, and the liquid crystal display device LCD is exposed (the player can see the screen).

  A jog dial PAN as an operation unit is provided between the stop switch 140 and the medal slot 132, specifically, on the upper right side of the rightmost stop switch 140 and on the left side of the medal slot 132.

  As shown in FIG. 5 (a), the jog dial PAN includes two parts, a dial JD that is a ring-shaped part that is provided to rotate left and right, and a push button switch PHSW that is provided at the center of rotation of the ring. Prepare. The player can turn the dial JD of the jog dial PAN left and right, and can press the push button switch PHSW at the center top. Although not shown, a light emitting element is provided inside the push button switch SWSW, and lights up when pressed, for example. The dial JD is rotated in a plurality of steps (for example, the number of steps = 30, the angle = 12 degrees). A predetermined effect is performed according to the rotation direction and / or the rotation amount (angle) of the dial JD and the on / off state of the push button switch.

  As shown in FIG. 5B, the jog dial PAN is provided with two sensors [1] JS1 and [2] JS2 for detecting the rotation of the dial JD together with the push button switch PHSW. The sensors [1] JS1 and [2] JS2 output two digital signals of H / L according to the rotation. This will be further explained later.

  As shown in FIG. 2, the slot machine main body 120 is fixed to the inner bottom surface, stores a plurality of medals therein, and stores the stored medals at a payout port 135 provided on the front surface of the front door 130. A hopper device 121 for paying out the sheets one by one is installed. An upper portion of the hopper device 121 is provided with a hopper tank 122 that opens upward and stores a plurality of medals therein. Inside the slot machine main body 120, a reel unit 203 including three reels is installed at a position where the game display unit 131 comes when the front door 130 is closed. The reel unit 203 includes three reels (first reel to third reel) in which a plurality of types of symbols are arranged on the outer peripheral surface. The game display unit 131 is provided with an opening through which a player can see the symbols of each rotating reel of the reel unit 203. A power supply unit 205 is provided between the upper hopper unit 121 and the reel unit 203.

  As shown in FIG. 2, the medal (coin) selector 1 is attached to the back side of the front door 130 on the back side of the medal slot 132 provided on the front surface of the front door 130. This medal selector 1 rolls the medal toward the hopper device 121 while detecting the passage of the medal inserted from the medal insertion slot 132, and has a different diameter medal or iron or iron whose outer diameter is different from the predetermined dimension. This is an apparatus for selecting and removing illegal medals made of an alloy and selecting and eliminating a predetermined number or more of medals that can be inserted per game.

  Further, as shown in FIG. 2, a lead-out path 136 that covers the lower side and communicates with the payout port 135 of the front door 130 is provided below the medal selector 1. The medals distributed by the medal selector 1 are returned to the player from the payout port 135 via the derivation path 136.

  FIG. 3 shows a functional block diagram of a slot machine 100 as an example of a gaming machine to which this embodiment can be applied.

  In this figure, the display about the power supply system is omitted. Although not shown, the slot machine includes a power supply unit (power supply unit 205 in FIG. 2) for generating a DC power supply (+5 V or the like) from a commercial power supply (AC100V).

  The slot machine 100 includes a main substrate (processing unit) 10 and a sub substrate 20 that operates in response to a command from the main substrate (processing unit) 10 as main processing devices. At least the main substrate 10 is accommodated inside the case so that it cannot be contacted from the outside, and is sealed so that traces remain when these substrates are removed. That is, the main board 10 and the sub board 20 are integrally attached by caulking, and are covered by an integral case that covers the entire main board 10 and the sub board 20.

  The main board 10 is used for performing an internal lottery in response to the player's operation, and for performing processing (game processing) such as rotation / stop of the spinning cylinder and payout of medals. The main board 10 includes a CPU that performs a control operation according to a preset program, a ROM that is a storage unit that stores the program, and a RAM that temporarily stores processing results and the like.

  The sub board 20 is for receiving a command signal from the main board 10 and notifying the result of the internal lottery and performing various effects. The sub-board 20 includes a CPU that performs a control operation in accordance with a preset program corresponding to the command signal, a ROM that is a storage unit that stores the program, and a RAM that temporarily stores processing results and the like. Only one command flows from the main board 10 to the sub board 20, and conversely, no command is issued from the sub board 20 to the main board 10.

<Main board>
The main board 10 has a bet switch BET, a start switch 134, a stop button 140, a reel (rotating cylinder) unit 203, a hopper driving unit 80, a hopper 81, and a medal detection for counting the number of medals paid out from the hopper 81. The part 82 (these constitute the hopper device 121 described above) is connected. A peripheral substrate (local substrate) such as a liquid crystal control substrate 200 for controlling the liquid crystal display device, a speaker substrate 201, and an LED substrate 202 is connected to the sub substrate 20.

  Further, medal sensors S1 and S2 of the medal selector 1 are connected to the main board 10.

  The medal selector 1 is provided with medal sensors S1 and S2 for counting medals. The medal sensors S1 and S2 are provided on the downstream side (near the exit) of a medal passage (not shown) provided in the medal selector 1 (the upstream side of the medal passage communicates with the medal slot 132). The two medal sensors S1 and S2 are arranged side by side at a predetermined interval along the medal traveling direction. The medal sensors S1 and S2 are, for example, photointerrupters that have a light emitting portion and a light receiving portion that face each other, are formed in a U-shaped cross section, and are positioned so that the detection optical axis faces the medal passage from above. . Each photo interrupter detects the passage of a medal sent without being blocked on the way. The reason why two photo interrupters are adjacent is not only to detect the number of medals but also to monitor whether or not the passage of medals is normal. That is, by providing two photo interrupters adjacent to each other, it is possible to detect the passing speed and passing direction of medals, thereby detecting not only the number of medals but also an illegal act moving in the reverse direction.

  The reel unit 203 includes three spinning cylinders 40a to 40c, stepping motors 155a to 155c that respectively rotate these, and spinning cylinder position detectors (index sensors) 159a to 159c that detect their positions, respectively (note that The stepping motors 155a to 155c may be simply referred to as a motor 155 or a motor).

  Based on the reference position signal detected by the index sensor 159 every time each of the rotating cylinders 40a to 40c makes one rotation, the rotating cylinder control means 1300 starts from the reference position (a frame specified by an index (not shown)) of the rotating cylinder 40. Is obtained (by counting the number of rotation steps of the rotation shaft of the step motor), the current rotation state of the drum 40 can be monitored. That is, the main substrate 10 can obtain the position of the rotating drum 40 when the stop button 140 is operated by obtaining the rotation angle from the reference position of the rotating drum 40.

  In the following description, reference numeral 40 is used to indicate any one or a plurality of spinning cylinders, and reference numerals 40a to 40c are used to separately indicate three spinning cylinders.

  The hopper driving unit 80 rotates an unillustrated rotating disk of the hopper 81 and performs an operation of paying out medals of the payout number instructed by the main board 10. The gaming machine includes a medal detection unit 82 that operates every time a medal is paid out, and the main board 10 receives a medal actually paid out from the hopper 81 based on an input signal from the medal detection unit 82. You can manage the number.

  The insertion accepting unit (insertion accepting means) 1050 receives the outputs of the medal sensors S1 and S2 of the medal selector 1, accepts the insertion of medals for each game, and based on the insertion of medals corresponding to the prescribed number of insertions. Then, a process of permitting the start operation of the first to third cylinders for the start switch 134 is performed. Note that the pressing operation of the start switch 134 is an opportunity to start the rotation of the first cylinder to the third cylinder, and is an opportunity to execute the internal lottery. Also, a prescribed number of throws is set according to the gaming state, the prescribed number of throws is set to 3 in the normal state and the bonus established state, and the prescribed number of throws is set to 1 in the bonus state.

  When medals are inserted, the inserted medals are set to the inserted state up to a specified number of insertions according to the gaming state. Alternatively, when the bet switch BET is pressed in a state where medals have been credited to the gaming machine, the credited medals are set to the inserted state by limiting the prescribed number of insertions according to the gaming state. The main board 10 controls whether or not to accept a medal. From the time when the start switch 134 is pressed and the rotation of each cylinder starts (game start time), when the three stop buttons 140 are pressed and the rotation of each cylinder stops (when the medal payout is completed when winning) (game) When the medal is not accepted (when it is not permitted), the medal sensor S1, S2 does not count the medal and is returned as it is. . Similarly, the main board 10 controls the validity / invalidity of the bet switch BET according to whether or not the medal insertion is accepted. In addition, the bet switch BET is valid from the end of the game to the start of the game, but during other periods (when pressing of the BET switch is not permitted), the bet switch BET is pressed. Even it is ignored.

  The main board 10 incorporates random number generating means 1100. The random number generation means 1100 is a means for generating a random number for lottery. The random value can be generated based on, for example, a count value of an increment counter (a counter that counts numerical values so as to circulate a predetermined count range). In this embodiment, the “random number value” is not only a value that is randomly generated in a mathematical sense, but even if the generation itself is regular, the acquisition timing and the like are irregular. Includes a value that can function as a random number.

  The internal lottery means 1200 performs an internal lottery in which the player determines whether or not the winning combination is based on a start signal from the start switch 134. That is, a lottery table selection process for selecting a lottery table (not shown) stored in a memory (not shown) of the main board 10, a random number determination process for determining the winning of a random number obtained from the random number generating means 1100, The lottery flag setting process for setting a flag to that effect when a big win or the like is won by the determination result is performed.

  In the lottery table selection process, a lottery table (not shown) stored in a storage unit (ROM) (not shown) is used to determine which lottery table is used for internal lottery. In the lottery table, for each of a plurality of random values (for example, 65536 random values from 0 to 65535), replay, small role (bell, cherry), regular bonus (RB: bonus), and big bonus (BB :), etc., are associated with each other. In addition, a normal state, a bonus establishment state, and a bonus state can be set as the gaming state, and a replay lottery state, a replay low probability state, and a replay high probability state can be set as replay lottery states.

  The lottery table selection process allows the contents of the lottery to be set within a predetermined range (the probability of winning can be increased or decreased), and the setting work is performed by the store in the hall where the gaming machine is installed. .

  A normal gaming machine includes a plurality of (for example, six) lottery tables having different lottery probabilities such as BB, RB, and small roles in advance. In the lottery of gaming machines, one of the plurality of lottery tables is set, and the winning / losing determination by lottery is made based on the set lottery table. Changing a setting relating to which of a plurality of lottery tables is used is referred to as a setting change (hereinafter referred to as “setting change”).

  Conventionally, for example, in a gaming machine such as a slot machine, when changing a setting value (usually 1 to 6), the door of the gaming machine is opened, and a setting change key is inserted into a setting change key switch provided in the power supply unit. Setting value displayed on a 7-segment display etc. each time the setting change button (push button) is pressed once by turning on the power of the gaming machine with the key switch turned on. Is incremented and the values from 1 to 6 are cyclically changed, and the desired setting value is determined by operating the start switch when the desired setting value is displayed on the display.

  In the random number determination process, on the basis of the start signal from the start switch 134, a random number value (lottery random number) is acquired for each game from random number generation means (not shown), and the lottery table is referred to for the acquired random number value. To determine whether or not they have won the role.

  In the lottery flag setting process, the lottery flag of the winning combination determined to be won based on the result of the random number determination process is changed from the non-winning state (first flag state, off state) to the winning state (second flag state, on Status). When two or more types of winning combinations are won, a lottery flag corresponding to each of the two or more types of winning winning combinations is set to the winning state. The lottery flag setting information is stored in storage means (RAM).

  A lottery flag (possible carryover flag) that can carry over the winning state for the next game until winning, and a lottery flag that is reset to the non-winning state without bringing the winning state to the next game regardless of winning Carry-over impossible flag) may be provided. In this case, there are a regular bonus (RB) and a big bonus (BB) as a combination to which the former carry-over possible flag is associated, and other combinations (for example, small role, replay) correspond to the latter carry-over impossible flag. It is attached. In other words, in the lottery flag setting process, if a regular bonus is won by internal lottery, the winning state of the regular bonus lottery flag is carried over until the regular bonus is won, and if the big bonus is won by internal lottery, the big bonus lottery A process of carrying over the winning state of the flag until the big bonus is won is performed. At this time, the main board 10 determines whether or not a role other than the regular bonus and the big bonus (small role and replay) is used even in a game in which the winning state of the regular bonus or big bonus lottery flag is carried over by the internal lottery function. An internal lottery is performed. In other words, in the lottery flag setting process, in a game in which the winning state of the regular bonus lottery flag is carried over, if a small role or replay is won in the internal lottery, the regular bonus lottery flag and the internal lottery already won In a game in which the lottery flags corresponding to two or more types of winning combinations or replay lottery flags won in the win state are set to the winning state and the winning state of the big bonus lottery flag is carried over, it is small in the internal lottery When a winning combination or replay is won, a lottery flag corresponding to two or more kinds of winning combinations including a big bonus lottery flag that has already been won and a small bonus or replay lottery flag that has been won in an internal lottery is set to a winning state. Set.

  The spinning cylinder control means 1300 rotates the first to third cylinders by a stepping motor based on a start signal generated by the player pressing the start switch 134 (rotation start operation), and the first cylinder -Depressing (stopping) the three stop buttons 140 corresponding to the rotating cylinders in a state where the rotation speed of the third cylinder reaches a predetermined speed (about 80 rpm: a rotational speed of about 80 rotations per minute). In addition to performing control to permit the operation), control is performed to stop the first to third cylinders driven to rotate by the stepping motor in accordance with the lottery flag setting state (internal lottery result).

  In addition, when the player presses the three stop buttons 140 in a state where the pressing operation (stop operation) with respect to the three stop buttons 140 is permitted (validated), Based on the signal, the supply of the drive pulse (motor drive signal) to the stepping motor of the reel unit 203 is stopped, thereby controlling each of the first to third drums.

  That is, each time the three stop buttons 140 are pressed, the spinning cylinder control means 1300 determines the stopping position of the spinning cylinder corresponding to the pressed button among the first to third cylinders. Thus, control is performed to stop the spinning cylinder at the determined stop position. Specifically, referring to a stop control table (not shown) stored in the storage means (ROM), the first time corresponding to the pressing timing, pressing order, etc. of the three stop buttons (mode of stop operation) A stop position of the cylinder to the third cylinder is determined, and control is performed to stop the first cylinder to the third cylinder at the determined stop position.

  Here, in the stop control table, the positions of the first cylinder to the third cylinder (pressing detection position) at the time when the stop button 140 is operated, and the actual stop positions (or pressing detection of the first cylinder to the third cylinder). Correspondence with the number of sliding frames from the position) is set. The number of sliding symbols is a symbol that passes through the reference position between the operation of the stop button 140 and the rotation stop of the corresponding rotating cylinder when a specific symbol that can be visually recognized from the game display unit at the time of stopping the rotating drum is used as the reference position. The number of Since the turning cylinder control means 1300 stops each turning cylinder within 190 ms from the operation of each stop button 140, the number of sliding frames is in the range of 0 to 4 (however, 80 revolutions / minute, (In the condition of the number of symbols = 21). Depending on the setting state of the lottery flag, a stop control table for determining the stop positions of the first cylinder to the third cylinder may be prepared.

  As described above, the spinning cylinder control unit 1300 is based on the reference position signal (the frame detected by the reel index) of the spinning cylinder based on the reference position signal detected by the index sensor 159 every time the rotating cylinder makes one rotation. By obtaining the rotation angle (the number of rotation steps of the rotation shaft of the step motor), the current rotation state of the rotating drum can be monitored. That is, the main board 10 can obtain the position of the rotating cylinder when the stop button 140 is operated by obtaining the rotation angle from the reference position of the rotating cylinder.

  The spinning cylinder control unit 1300 performs so-called pull-in processing and kicking processing as control for stopping the spinning cylinder. The pull-in process is a control for stopping the spinning cylinder so that the symbol corresponding to the combination whose lottery flag is set to the winning state is stopped on a valid winning determination line (so that the winning combination can be won). It is processing. On the other hand, the kicking process means that the symbol corresponding to the combination for which the lottery flag is set to the non-winning state does not stop on a valid winning determination line (so that a non-winning combination cannot be won) Is a control process for stopping the process. That is, in the gaming machine of the present embodiment, the lottery flag setting state, the stop button 140 pressing timing, the pressing order, and the stop position of the spinning cylinder that has already stopped (in the display pattern) in order to realize the pull-in processing and kicking processing. The stop control table is set so that the stop position of each cylinder changes according to the type). In this way, the main board 10 can stop the symbol of the combination for which the lottery flag is set to the winning state in a winning form, while the symbol of the combination for which the lottery flag is set to the non-winning state is in the winning form. Control is performed to stop the first to third cylinders so as not to stop.

  In the gaming machine of the present embodiment, the first to third drums are controlled to stop the rotating drum corresponding to the pressed stop button within 190 ms from the time when the stop button 140 is pressed. Is set to That is, in the stop control table for determining the stop position of each rotating cylinder, the number of frames required from when the stop button 140 is pressed until each cylinder stops is in the range of 0 to 4 frames (predetermined pull-in range). Is set in

  The winning determination means 1400 performs a process of determining whether or not a winning combination has been won based on the stopping modes of the first to third cylinders. Specifically, referring to the winning determination table stored in the storage means (ROM), the symbol combination displayed on the winning determination line when all of the first to third cylinders are stopped. It is determined whether or not this is a predetermined winning combination form.

  The winning determination means 1400 executes a winning process based on the determination result. As a process at the time of winning a prize, for example, when a small role wins, the hopper 81 is driven to perform a medal payout control process, or a credit is increased (a predetermined maximum number is increased to 50, for example, When the replay is won, a replay process is performed. When a big bonus or a regular bonus is won, a game state transition control process for shifting the game state is performed.

  The payout control means 1500 performs payout control processing relating to the payout of medals according to the game result. Specifically, when a small combination wins, the number of medals to be paid out in the game is determined based on a payout predetermined for each combination, and the medals corresponding to the determined number of payouts are determined by the hopper driving unit 80. Then, the hopper 81 is driven to pay out. At this time, a current flows through a motor (not shown) built in the hopper 81.

  When medal credits (internal storage) are permitted, instead of actually paying out medals by the hopper 81, the number of credits stored in a credit storage area (not shown) of the storage means (RAM) (not shown) A credit addition process for adding the number of payouts to the number of credited medals is performed to virtually pay out medals.

  When the replay is won, the replay processing means 1600 performs a replay process (regame process) for setting the same preparatory state as the previous game without requiring insertion of medals owned by the player for the next game. When a replay wins, an automatic insertion process is performed in which the same number of medals as the previous game is automatically set to the insertion state without using the player's own medals (including credit medals). The game machine is set in a state of waiting for a rotation start operation (pressing operation of the start switch 134 by the player) in the next game in a state where the same winning determination line as the previous game is validated.

  The replay processing unit 1600 may perform control to change the winning probability of replay in the internal lottery under a predetermined condition. For example, when a predetermined turn is displayed when the spinning cylinder is stopped by operating the stop button 140, the winning probability of replay varies. The replay lottery states include a replay no lottery state in which replay is excluded from the internal lottery, a replay low probability state in which the replay winning probability is set to about 1 / 7.3, and a replay winning probability of about 1 / A plurality of lottery states such as a high replay probability state set to 6 can be set.

  The error processing unit 1700 determines an error of the gaming machine based on the outputs of a door opening / closing detection sensor (not shown), the medal sensors S1 and S2, and the medal detection unit 82, and notifies that when it determines that there is an error. To a predetermined state (for example, a state in which no operation is accepted).

  A door open / close detection sensor (not shown) is a sensor that detects that the door 130 is closed, and is, for example, an electrical switch such as a micro switch or a contact. When the door 130 is closed, the switch is turned on (or off) when the switch action part contacts the back side of the door 130, and when the door 130 is opened, the action part is separated and turned off (or on). ). The door opening / closing detection sensor may be an optical sensor such as a photo interrupter. The medal sensors S1 and S2 and the medal detection unit 82 have been described above.

Specifically, the error processing unit 1700 performs the following operation.
When an opening of the door 130 is detected based on an output from a door opening / closing detection sensor (not shown), error processing is performed.
-Based on the outputs of the medal sensors S1 and S2, the reverse flow of the medals (the detection order of the sensors S1 and S2 is reversed), the medal retention (the detection times of the sensors S1 and S2 are longer than a predetermined threshold) When error is detected, error processing is performed.
Based on the output of the medal detection unit 82, the medal clogging (the detection time of the medal detection unit 82 is longer than a predetermined threshold), hopper empty (the medal detection unit despite operating the hopper driving unit 80) When 82 detects no medal), error processing is performed.

  When the error processing unit 1700 determines that an error has occurred as described above, the error processing unit 1700 notifies the fact and sets the gaming machine to a predetermined state (error state). This state is canceled by a reset switch (not shown). The reset switch is provided on the panel of the power supply unit 205, for example.

  There are also errors that occur in the sub-board 20. Although this error does not result in an inoperable state, the liquid crystal display device or the like can notify that an error has occurred due to the processing of the sub-board 20 itself. The error occurs, for example, when an invalid command is received (including when the encrypted command cannot be correctly decrypted), and the error is canceled by the reset switch (from the main board 10 to the sub board 20). Reset command).

  Further, the main board 10 may perform control to shift the gaming state between the normal state, the bonus establishment state, and the bonus state (gaming state transition control function). As the game condition transition condition, one condition may be defined, or a plurality of conditions may be defined. When a plurality of conditions are established, transitioning the gaming state to another gaming state based on the fact that one of the plurality of conditions is satisfied or all of the plurality of conditions are satisfied Can do.

  The normal state is a game state corresponding to the initial state among a plurality of types of game states, and a transition from the normal state to the bonus establishment state is possible. The bonus establishment state is a gaming state that shifts when a big bonus or a regular bonus is won in the internal lottery. In the bonus establishment state, when the big bonus is won in the internal lottery in the normal state, the lottery flag corresponding to the big bonus is maintained in the winning state until the big bonus is won, and the regular bonus is won in the internal lottery in the normal state Until the regular bonus is won, the lottery flag corresponding to the regular bonus is maintained in the winning state. In the bonus state, it is determined whether or not the end condition is satisfied based on the total number of medals paid out by the bonus game, and medals exceeding a predetermined payout limit number are paid out according to the type of bonus won. The bonus state is terminated and the gaming state is returned to the normal state.

  The reel unit 203 includes three spinning cylinders 40a to 40c, and one stepping motor 155a to 155c is attached to each of the three spinning cylinders 40a to 40c. The stepping motor 155 includes a gear-shaped iron core or permanent magnet as a rotor (rotor), a plurality of windings (coils) as a stator (stator), and is rotated by switching windings through which current flows. It is. That is, a current is passed through the windings of the stator to generate a magnetic force, and the rotor is rotated by attracting the rotor. Since the rotation axis can be stopped at a specified angle, it is used to drive the rotation of the slot machine. A plurality of windings constitute one phase. As the number of phases, for example, there are two (two phases), four (four phases), and five (five phases).

  The stepping motor can change its characteristics (excitation mode changes) by changing the way of applying current to the windings of each phase. The two-phase type is as follows.

• Single-phase excitation Always allow current to flow through only one phase of the winding. Positioning accuracy is good.

・ Two-phase excitation
Current flows in two phases. An output torque approximately twice that of single-phase excitation can be obtained. The positioning accuracy is good and the stationary torque is large when stopped, so that the stop position can be held reliably.

・ One-two-phase excitation
A current is passed by alternately switching between one phase and two phases. Since the step angle can be halved in the case of one-phase excitation and two-phase excitation, smooth rotation can be obtained.

  Note that “driving” a stepping motor includes rotating the motor by the above-described excitation and exciting each phase in order to stop at a desired position and hold the position.

  In the slot machine, for example, a four-phase stepping motor having a basic step angle of 1.43 degrees is used, and one-two-phase excitation is adopted as a pulse output method.

  10CG is a command transmitter that transmits a command to be sent to the sub-board 20. This command includes a command related to winning combination information, a command related to information on the number of inserted medals and the number of credits (stored number). Specifically, the command transmission unit 10CG is realized by the CPU executing a program written in advance in a ROM mounted on the main board 10. The command transmission will be described later.

Next, the game processing in the main board 10 will be described with reference to FIG.
Generally, in a gaming machine, one game is started from the insertion of medals (insertion of credits) until the end of payout (or until the increase in the number of credits is completed). There is a rule that it is not possible to proceed to the next game until one game is finished.

  First, when a prescribed number of medals are inserted, the start switch 134 is activated, and the processing of FIG. 4 is started.

  In step S1, the start switch 134 is turned on by operating the start switch 134. Then, the process proceeds to the next step S2.

  In step S2, a lottery process is performed by the main board 10. Then, the process proceeds to the next step S3.

  In step S3, the rotation of the first reel to the third reel starts. Then, the process proceeds to next Step S4.

  In step S4, when the stop button 140 is operated, the stop button 140 is turned ON. Then, the process proceeds to next Step S5.

  In step S5, rotation stop processing is performed on the reel corresponding to the pressed stop button 140 among the first to third reels. Then, the process proceeds to next Step S6.

  In step S6, it is determined whether or not the operation of the stop button 140 corresponding to the three reels has been performed. If it is determined that all three stop buttons 140 corresponding to the three reels have been operated, the process proceeds to the next step S7.

  In step S7, it is determined whether or not the winning symbols corresponding to the lottery flag are aligned on the effective winning line while the lottery flag is established, that is, whether or not the winning is confirmed. If it is determined that the winning is confirmed, the process proceeds to the next step S8. If the winning is not confirmed, no medals are paid out even if the lottery flag is established.

  In step S8, medals corresponding to winning symbols are paid out.

  The process from the insertion of the medal to the completion of the execution of step S8 is one game. When the standby process in step S8 ends, the process returns to the beginning of the flowchart. In other words, the next game is possible (transition to the next game).

<Command transmission from main board to sub board>
The sub-board 20 receives a command from the main board 10 and performs processing such as rendering according to the command. The flow of commands is only one from the main board 10 to the sub board 20, and conversely, no command or the like is issued from the sub board 20 to the main board 10.

  The sub-board 20 generates a command (liquid crystal display device command, drawing command) for displaying a predetermined screen on the liquid crystal display device LCD, for example, in accordance with a command from the main substrate 10. For example, when performing an effect by animation or the like, a large number of commands are continuously transmitted one after another.

  In FIG. 3, 20 CR is a command receiving unit that receives a command received from the main board 10. Specifically, the command receiving unit 20CR is realized by the CPU executing a program written in advance in a ROM mounted on the sub-board 20.

  As the above-mentioned command, there is a command for performing an effect suggesting the winning contents by the software on the sub-board 20 side. For example, as shown in the following AT, a suggestion for obtaining a ball is displayed on a liquid crystal display device so as to provide (assist) the player with the convenience of operation. The suggestion is not always issued, but in specific cases.

  The gaming machine includes an effect display device including a liquid crystal display device, a speaker, a display lamp, and the like. This effect display device is controlled by the sub-board 20 to notify the player of a prize or the like, or in a so-called assist time (AT), the base itself teaches the user with some action during a certain game with some action. It is for doing. (Assist time (AT): Even if a specific small role is established, the player will not be refunded if the reels are not aligned. After the big bonus ends (or at the time of establishment) to ensure payout by the small role) Alternatively, a lottery of assist time is drawn at any other opportunity, and if this is won, the player is instructed to perform an operation with some action for aligning specific small roles during a certain game)

  FIG. 5C is a block diagram of the command transmission unit 10CG according to the present embodiment.

  Reference numeral 101 denotes a command register that accepts the command to be transmitted. The command register 101 sends the command to the transmission data register 102 immediately after receiving the command. The command register 101 temporarily stores one command.

  The command is a set of data of a predetermined bit, for example, a set of data in units of 8 bits, and is created based on a predetermined command system.

  Reference numeral 102 denotes a transmission data register (transmission FIFO) that stores a plurality of commands in the accepted order and outputs them in accordance with the accepted order.

  Reference numeral 103 denotes a transmission shift register that receives a command output from the transmission data register 102 and transmits it to the sub-board 20.

  The main board 10 transmits the generated command to the sub board 20 by setting it in the command register 101.

  The command receiving unit 20CR receives a command received from the main board 10. For example, a command received as serial data is input to a serial-parallel converter (shift register), and is output every certain data (for example, 8 bits). The output data is transferred to the CPU of the sub-board 20 as a command, and is interpreted and executed.

<Sub-board>
A peripheral substrate (local substrate) such as a liquid crystal control substrate 200 for controlling the liquid crystal display device, a speaker substrate 201, and an LED substrate 202 is connected to the sub substrate 20. Furthermore, the movable body control part 60 which controls the movable body 50 is connected.

  Moreover, the output of the operation part PAN operated by the player is connected. The operation unit PAN is, for example, a jog dial. A signal from the operation unit PAN is input to the CPU of the sub-board 20 through an I / O (not shown).

  FIG. 6 is an explanatory diagram of the connection between the sub-board 20 and its peripheral board. As shown in FIG. 3, a liquid crystal control board 200, a speaker board 201, an LED board 202, and a movable body control unit 60 are connected to the sub board 20. These should be called peripheral substrates of the sub-substrate 20.

  The plurality of peripheral boards are connected as shown in FIG. 6 (the display of the LED board 202 and the movable body controller 60 is omitted). That is, a plurality of peripheral boards are connected to a common bus (communication line, communication path), and communicate with the sub-board 20 through the bus. The signal flowing through the bus is a signal on two lines, a data line and a clock line, such as a parallel signal (for example, a signal transmitted by an 8-bit line) or a serial signal (for example, I2C (Inter-Integrated Circuit)). ). In the following description, serial communication is taken as an example. In the example of FIG. 5C, the signal output from the sub-board 20 returns to the sub-board 20, but this is an example, and the end opposite to the connection end is opened as in a general bus structure. May be.

  The liquid crystal control board 200 has a built-in VDP (Video Display Processor), and the speaker board 201 has a built-in sound controller. The VDP and sound controller will be described later.

  Data is transmitted from the sub board 20 to the peripheral board by designating an address. For example, when data is sent to the liquid crystal control board 200 as a peripheral board, an address previously associated with the liquid crystal control board 200 is designated and the data is sent to the bus. When the liquid crystal control board 200 recognizes that the data is addressed to itself by the address, the liquid crystal control board 200 takes in the data subsequent to the address into the latch. A predetermined operation is performed according to the fetched data. If the fetched data is a command for transmitting data acquired or obtainable by the liquid crystal control board 200 to the sub-board 20, the data is sent to the sub-board 20 (after receiving predetermined data, it is determined in advance. Data can always be transmitted to the sub-board 20).

  The speaker substrate 201 operates in the same manner as the liquid crystal control substrate 200.

  In the following description, the term “peripheral board” is mainly used when the operation is applied to an arbitrary transmission destination such as the liquid crystal control board 200 and the speaker board 201 without specifying the transmission destination. When it is necessary to specify to which peripheral substrate the data transmission is to be made, it is specifically specified as “liquid crystal control substrate 200”.

  When transmitting data to the peripheral board, the sub-board 20 performs processing in units of data (for example, 8-bit data) in which a plurality of 0 or 1 data is collected. The sub-board 20 transmits a command (command) for causing the sub-board 20 to perform a predetermined operation. In this specification, the data includes the command. Note that the command is a set of predetermined bits of data, for example, a set of data in units of 8 bits, and is created based on a predetermined command system.

  In the following description, the term “data” is mainly used, but the term “command” may be used to clarify that the instruction is a command to the peripheral device.

In order to send data to peripheral devices such as the liquid crystal control board 200 and the speaker board 201, the sub board 20 includes a data transmission unit 20TX.
FIG. 7 shows an internal block diagram of the data transmitter 20TX. Specifically, the data transmission unit 20TX is realized by the CPU executing a program written in advance in a ROM mounted on the sub-board 20.

  Reference numeral 2101 denotes a data register (command register) that receives data to be transmitted to the peripheral board. The data register 2101 sends the data to the transmission data register 2102 immediately after receiving the data. The data register 2101 temporarily stores one unit of data. In addition, since the content of data is well-known, description about what kind of data is transmitted is abbreviate | omitted.

  Reference numeral 2102 denotes a transmission data register that stores a plurality of data in the accepted order and outputs them in accordance with the accepted order.

  Reference numeral 2103 denotes a transmission shift register which receives data output from the transmission data register 2102 and transmits it to the peripheral board. The transmission shift register 103 converts data to be transmitted from parallel to serial.

FIG. 8 is a schematic explanatory diagram of data (command) transmission and operations of the liquid crystal control board 200 and the speaker board 201 that have received the data (command) transmission.
The sub board 20 sends image data and audio data to the liquid crystal control board 200 and the speaker board 201, respectively (reference characters P and R). In response to the image data, the liquid crystal control board 200 displays a predetermined screen (symbol Q), and on receiving the audio data, the speaker board 201 generates a predetermined sound (symbol S). Other sounds such as BGM and sound effects are generated in addition to the sound, but these are also included in the sound for convenience. Voice / voice data can be said to be acoustic / acoustic data. Unless otherwise specified, in this specification, “sound” includes other sounds such as BGM and sound effects as well as sound of normal meaning.

  Further, the sub-board 20 sends control data of the movable body 50 to the movable body control unit 60 (reference numerals T and U).

  As can be seen from FIG. 8, the command transmission by the sub-board 20 → the execution of the command by the peripheral board, the screen display, and the voice generation are presented. The sub-board 20 can control what command is sent to which peripheral board at which timing, and it cannot be specified at what timing the presentation of screen display or voice generation can be performed. For this reason, it is necessary to appropriately manage the command transmission timing for each peripheral board.

<Configuration related to screen display and sound generation>
The configuration related to screen display and sound generation in the gaming machine will be described. In the following description, for the sake of convenience, what is drawn on the memory is displayed as an image, and what is to be read out and displayed on the liquid crystal display device LCD is referred to as a screen. In general, an object such as a character represented by a bitmap is an image, and a screen in which an object is arranged on a background and becomes a single picture is a screen.

  FIG. 9 is a schematic diagram of the structure of the VDP. The VDP is an LSI provided on the liquid crystal control board, an interface I / F with the CPU, a drawing engine E1 that draws an image according to a command from the CPU, a video memory VRAM that stores the drawn image, and a video memory VRAM Is provided with a display engine E2 for reading out the image stored in the memory and sending it to the liquid crystal display device LCD. Each of these elements is connected to an internal bus BUS so that data can be read from and written to each other. The interface I / F can receive data such as commands from the CPU and can also output an interrupt signal from the display engine E2 or the like to the CPU. This VDP can draw and display 60 frames per second at an XGA size resolution (1024 × 768 pixel resolution), for example.

  When drawing and displaying at 60 frames per second (= 60 fps), the time for one frame is 16.67 ms. This is referred to as frame time. Two consecutive frames are referred to as V frames. Frame × 2 = V frame × 1. The time of the V frame is 33.33 ms, and the screen update rate (update frequency) is 30 fps. The frame and the V frame are a display unit and a processing unit. In the following description, the data in the frame and the V frame, the processing result (drawn image), and the image displayed on the liquid crystal display device LCD are displayed. It may mean. For example, when a number (symbol) is added, such as V frame 1, it indicates a specific V frame and may mean drawing data, image data, and display data corresponding to the specific V frame.

  The liquid crystal display device LCD is controlled in three stages: drawing data (including commands for the liquid crystal display device, moving image decoding information, etc.), drawing execution based on the drawing data, and display execution of the drawn image. That is, the CPU sends drawing data to the VDP, the drawing engine E1 of the VDP executes drawing, and the display engine E2 displays an image on the liquid crystal display device LDC. These three stages of processing are executed in parallel (independently). Since three stages are required until the image is displayed, at the timing when a certain image is displayed (V frame), the drawing execution draws an image to be displayed in the next V frame, and the storage of the drawing data is performed next. The image to be displayed in the V frame is saved. This is shown in FIG.

  Whether to save drawing data, execute drawing, and execute display is determined in one cycle for one V frame. In other words, drawing data storage (first processing), drawing execution (second processing), and display execution (third processing) are each performed in units of V frames (more precisely, frames included in the V frames). Processing is performed in units. For example, when there is data input during V frame update, drawing data related to data input in one of the two frames of V frame is saved, drawn, and displayed) . Therefore, the update frequency of the liquid crystal display device LCD of this gaming machine is 30 fps. This is a principle, and fps can change depending on the processing status.

  It takes a time corresponding to two V frames from saving the drawing data to executing the display. For example, in FIG. 10, the drawing data written with the code T1 is displayed with the code T3 delayed by two V frames. However, since storage of drawing data, execution of drawing, and execution of display are executed in parallel, the image on the liquid crystal display device LCD is updated in units of V frames. In the example of FIG. 10, the display is updated as V frame 1, V frame 2,.

  FIG. 11 shows an internal block diagram of the sound controller SC. This figure is a conceptual diagram, and shows only the parts necessary for explaining the operation.

  SC1 is a phrase data storage unit that stores in advance phrase data including a plurality of sound data to be reproduced in a predetermined order of reproduction.

  SC2 is a decoder that reproduces sound by decoding phrase data. The decoder returns predetermined sound data (for example, WAV) to sound, and since this process is well known, the description thereof is omitted.

  SC3 is a volume adjusting unit that adjusts the volume of the sound reproduced by the decoder SC2. The volume adjustment unit SC3 is configured by a digital or analog circuit. When the input is a digital signal, it is constituted by a digital circuit, for example, a multiplier, and the volume is adjusted by multiplying the value of the volume by the acoustic digital data. When the input is an analog signal, it is constituted by an analog circuit, for example, an amplifier, and the volume is adjusted by changing the amplification factor (variable resistor) of the amplifier. The output of the volume adjuster SC3 is sent to the speaker SP.

  FIG. 12A shows an outline of the contents stored in the phrase data storage unit SC1. When there are a plurality of effects such as effects A, B, C, D,..., A sound phrase (audio data) is stored corresponding to each. There is an upper limit on the number of sound phrases, and for example, 255 sound phrases can be stored.

  FIG. 12B shows the structure of audio data (for example, WAV) of effect A. The production A is composed of three sounds, that is, a first sound (cut-in sound), a second sound (character voice), and a third sound (developed sound).

  The cut-in sound is a sound associated with a cut-in that inserts another shot into a certain shot (scene). The character voice is the sound of the dialogue of the character displayed on the screen. The development sound is a sound that is added when the production develops to another production at the end of the production.

  The sub board 20 transmits, for example, data for reproducing the cut-in sound of effect A in FIG. 12B, data for reproducing the character voice, and data for reproducing the developed sound, to the speaker board 201, for example. In response to these three data (commands), the sound controller SC generates a predetermined sound.

<Movable body>
FIG. 13 is a schematic diagram of the movable body 50 according to the present embodiment. 4A is a top view, FIG. 2B is a front view, FIG. 4C is a cross-sectional view taken along the line BB, and FIG. 4D is a cross-sectional view taken along the line A-A. In the figure, the drive unit including the stepping motor 54, the index 56, and the index sensor 57 are shown only for the right shutter 51R, but the same is provided for the left shutter 51L (the left one). Is not shown).

  The movable body 50 includes a left shutter 51L and a right shutter 51R, an upper rail 52U and a lower rail 52L that slidably hold upper and lower ends of the shutters 51L and 51R, and an inner side of the movable body 50. A rack 53a provided in parallel with the lower rail 52L, a pinion 53b meshing with the rack 53a, a stepping motor 54 with the pinion 53b attached to its rotating shaft directly or via a reduction gear mechanism (not shown), and a right shutter The bracket 55 attached to the inside of the 51R (the bracket 55 which is an arm bracket / extrusion bracket is also an attachment base of the stepping motor 54), the index 56 attached to the inside of the right shutter 51R, and the index 56 are detected. And an index sensor 57. In the drawing, the pinion 53b to the index 56 are shown for the right shutter 51R, but the left shutter 51L has the same structure, and the description thereof is omitted.

  FIG. 5B shows a state in which the shutters 51L and 51R are fully opened on both sides, and in the example of the figure, the index sensor 57 detects the index 56 in this state. The index sensor 57 is an optical sensor such as a photo interrupter or a contact sensor such as a microswitch. The movable range of the shutters 51L and 51R is the same and can move only to the middle point. The numbers 0, 50, and 100 in FIG. The shutter 51L can move from 0 on the left side to 100 in the center, and the shutter 51R can move from 0 on the right side to 100 in the center. The index sensor 57 detects that the shutters 51L and 51R have come to the “0” position. That is, as shown in FIG. 14A, when the shutters 51L and 51R are fully opened (when the lower limit is reached), the end is at the position “0”, and as shown in FIG. 14B. When the shutters 51L and 51R are completely closed (when the upper limit is reached), the end is at the position “100”. When the shutters 51L and 51R are completely closed, the liquid crystal display device LCD is completely invisible.

  The rack 53a and the pinion 53b are mechanisms that convert the rotational force into a linear motion. The pinion 53b is a small-diameter circular gear, and the rack 53a is formed by cutting a tooth on a flat bar (toothed). When a rotational force is applied to the pinion 53b by the stepping motor 54, the shutters 51L and 51R move horizontally on the rack 53a. According to FIG. 13, since the rack 53a is fixed to the frame of the movable body 50 and the stepping motor 54 is attached to the shutters 51L and 51R by the bracket 55, the shutters 51L and 51R move.

  A stepping motor includes a gear-shaped iron core or permanent magnet as a rotor (rotor), a plurality of windings (coils) as a stator (stator), and is rotated by switching windings through which current flows. is there. That is, a current is passed through the windings of the stator to generate a magnetic force, and the rotor is rotated by attracting the rotor. Since the rotation axis can be stopped at a specified angle, it is used to drive the rotation of the reel of the slot machine. A plurality of windings constitute one phase. As the number of phases, for example, there are two (two phases), four (four phases), and five (five phases). The motor shaft rotates by passing a current through the coil of the stepping motor in a predetermined order, and the motor shaft rotates in the reverse direction when a current is passed in the reverse order.

  FIG. 15 is a block diagram of the movable body control unit.

  A position information calculation unit 61 calculates position information (position information on the program) of the shutters (movable elements) 51L and 51R based on a drive signal given to the stepping motor (drive unit) 54 by the drive signal generation unit 63. . For example, when a pulse signal for moving the shutters 51L and 51R by a unit distance in the plus direction (a signal for causing current to flow sequentially through the coils of the stepping motor 54) is given to the stepping motor 54, the current position information is incremented by +1. To do. When the pulse signal is in the minus direction, the current position information is decremented by one.

  A target position setting unit 62 sets target positions of the shutters (movable elements) 51L and 51R. The stepping motor 54 moves the shutters 51L and 51R to the target position and stops when reaching the target position.

  63 compares the target position of the target position setting unit 62 with the position information of the position information calculation unit 61, and generates a drive signal for moving the shutters (movable elements) 51L and 51R to the target position based on the comparison result. It is a drive signal generation part. For example, when the current position information is smaller than the target position, a pulse for moving the shutters 51L and 51R in the positive direction is generated. On the other hand, when the current position information is larger, a pulse for moving in the negative direction is generated.

  64 is a position where a value larger than the upper limit (for example, “200”) or a value smaller than the lower limit (for example, “−50”) is set as the first value serving as a reference for calculating the position information of the position information calculating unit 61. It is an information initial setting unit.

  When starting control of the shutters (movable elements) 51L and 51R, the target position is set to a position (“0” in the above example) from which the index signal is output from the index sensor 57, and the position information calculation unit The position information 61 is a value (for example, “200” “−50”) that is outside the upper limit (“100” in the above example) and the lower limit (“0” in the above example) as the first value serving as a reference for calculation. ). Accordingly, the shutters 51L and 51R are moved toward the position where the index signal is output. When the index signal is output, the position information of the position information calculation unit 61 is set to a predetermined initial value (“0” in the above example).

  FIG. 16 is a flowchart of the movable body effect process in FIG.

  According to the game flow chart shown in FIG. 4, the effect by the movable body 50 is performed in the range of S2 to S7 in FIG. When predetermined conditions are met during this period, the process of FIG. 16 is started.

S10: The movable body control unit 60 receives a start command related to the movable body effect from the sub-board 10.

S11: The operation content of the movable body 50 is determined. That is, the movement destinations (target positions) of the movable elements 51L and 51R are determined.

S12: A movable body drive process is performed.

S13: It is determined whether or not there is an interruption for stopping the movable body effect. When the interruption occurs (YES), the movable body effect is stopped immediately.

When the medal insertion related to the next game is performed, the movable body effect is stopped.
When the effect of the movable body is associated with one game, the initialization operation is performed with the suspension of the movable body effect, and the movable body is returned to the initial position (for example, 0).

S14: It is determined whether the operation of the movable body is finished. When the position information on the program reaches the target position (YES), the operation is terminated. Otherwise (NO), the movable body driving process S12 is repeated.

<Relationship between main processing and interrupt processing in peripheral board control>
When controlling the movable body control unit 60 in which the sub board is a peripheral board, the movable body control unit is controlled from the sub board 20 via the communication system of FIG. Send command to 60.

Specifically, the following processing is performed on the peripheral substrate.
-Set the pointer of the operation table (control data) of the control details you want to operate.
• Executes from the set pointer to the end of the table. Further, an operation status table (for example, a motor table) that changes according to the operation status is updated. If the pointer is reset during the table processing, execution is switched to the reset pointer.
-Check the table update status and reset the data table pointer.

  In performing the above processing, the role is assigned to each of the main routine (main processing) of the program and the interrupt processing. This concept is illustrated in FIG. This figure shows the control of the movable body. The same applies to other peripheral boards (there may be no feedback from the peripheral board to the sub-board). Solid lines indicate processing, and dotted lines indicate parameters. All of the processing of FIG. 17 is performed on the sub-substrate 20 and part of it is performed on the peripheral substrate.

  In many cases, the first cycle that is the processing interval of the main processing is different from the second cycle that is the processing interval of the interrupt processing. For example, the first cycle is greater than the second cycle. For example, the first cycle is 33.3 ms (30 fps), and the second cycle is 2.08 ms (480 fps).

  PP1 is a parameter from the main process to the interrupt process, and is a table setting pointer for designating the address of the operation table to be analyzed. The interrupt process analyzes the operation table according to the pointer, and continues the operation until the end of the operation table is reached or the next operation table is designated.

  MP1 is a main process for designating the table setting pointer PP1.

  IP1 is an interrupt process performed in response to the table setting pointer PP1.

PP2 is a parameter from the interrupt process to the main process, and is a motor table update state indicating the operation state on the peripheral board. This is status information for transmitting the operation state of the movable body 50 to the main process in the interrupt process. The main process confirms the status, and instructs the re-designation of the operation table and the stop of the operation as necessary. A part of the update state (related to the operation flag) can be operated on the main processing side by a control command of the operation table.
IP2 is an interrupt process for updating the motor table update state.
MP2 is a main process performed in response to the motor table update state PP2.

<Synchronization of operation between a plurality of peripheral substrates, synchronization of movable body and liquid crystal display as an example (part 1)>
There is an effect in which operations are performed among a plurality of peripheral boards. For example, the movable body 50 is moved in accordance with the change of the screen. As shown in FIG. 10, a delay of about 2 frames (66.6 ms) occurs when an image is displayed on the liquid crystal display device LCD. Therefore, in order to synchronize the operation of the liquid crystal display screen and the movable body 50, it is necessary to delay the processing according to the delay.

  FIG. 18 shows a block diagram of the gaming machine according to the present embodiment. This figure shows a configuration for synchronizing operations among a plurality of peripheral boards.

  2001 sets first control data and second control data (operation table) for controlling at least two first peripheral substrates and the second peripheral substrate (for example, the liquid crystal control substrate 200 and the movable body control unit 60). It is a control data setting unit. This corresponds to, for example, the motor operation table setting MP1 of FIG. Since the control data setting unit 2001 itself is publicly known, detailed description thereof is omitted.

  Reference numeral 2002 denotes a first analysis unit that analyzes the first control data at a predetermined first period T1 and causes the first peripheral substrate (for example, the liquid crystal control substrate 200) to perform a predetermined operation based on the analysis result. is there. Since the 1st analysis part 2002 itself is well-known, the detailed description is abbreviate | omitted.

  Reference numeral 2003 denotes a delay processing unit that includes a plurality of storage elements (registers) 2003R-1 to 2003R-3 and a delay control unit 2003C that controls these, and delays transmission of the second control data based on the first period T1. is there. The plurality of storage elements 2003R-1 to 2003R-3 constitute a first-in first-out buffer. The delay processing unit 2003 is typically a shift register or a FIFO. Note that the number of storage elements is not limited to three and is arbitrary.

  The storage element 2003R-1 may be referred to as an “entrance end storage element”, and the storage element 2003R-3 may be referred to as an “exit end storage element”.

  A second analysis unit 2004 analyzes the second control data at a predetermined second period T2, and causes the second peripheral substrate (for example, the movable body control unit 60) to perform a predetermined operation based on the analysis result. It is. This is, for example, the setting pointer confirmation IP1 of FIG. Since the second analysis unit 2004 itself is known, a detailed description thereof will be omitted.

  Reference numeral 2005 denotes an error signal receiving unit that receives a predetermined error signal. The error signal receiving unit 2005 receives a signal related to an error that needs to immediately stop the operation of at least the second peripheral substrate (for example, the movable body control unit 60). For example, opening a front door of a gaming machine during a game corresponds to an abnormal state such as an illegal act, so that an error signal is generated and the operation of the gaming machine needs to be stopped. Some of these types of errors are generated by the error processing unit 1700, but other types of errors may be used.

  Reference numeral 2006 denotes a first timer that generates a timing signal related to the first period T1. For example, the first period T1 = 33.3 ms (30 fps) or 16.7 ms (60 fps).

  Reference numeral 2007 denotes a second timer that generates a timing signal related to the second period T2. For example, the second period T2 = 2.08 ms (480 fps).

  The control data setting unit 2001 to the second timer 2007 are realized, for example, when the CPU of the sub-board 20 executes a predetermined program. Alternatively, it is realized by hardware such as a dedicated IC or a memory.

  A normal operation (operation when no error signal is received) of the apparatus of FIG. 18 (particularly the delay processing unit 2003) will be described with reference to FIG. 19 and FIG.

  19 and 20 are diagrams schematically illustrating control data input / output and movement of control data in the storage elements 2003R-1 to 2003R-3. A and B in the square indicate control data. Control data is input from the upper side of the drawing and output to the lower side. The lowermost square indicates the second analysis unit 2004, and the control data A and B shown here are analyzed and executed. (A)-(f) shows the state according to progress of time, (a) shows the past and (f) shows the future.

  FIG. 19 shows an example with one control data (only A), and FIG. 20 shows an example with two control data (A and B). Circles indicate writing of control data, and diamonds indicate analysis / execution of control data.

  In FIG. 19A, the control data A is written to the storage element 2003R-1 at time t0. The timing of writing is arbitrary, and is not necessarily synchronized with the period of the first timer 2006 and the second timer 2007. This state is held until the next period of the first timer 2006 (FIG. 19B). Note that t1-t0 <T1.

  In FIG. 19C, the control data A moves to the adjacent storage element 2003R-2 at time t2. This timing is synchronized with the cycle of the first timer 2006. That is, t2 = t1 + T1.

  In FIG. 19D, the control data A moves to the storage element 2003R-3 at the outlet end at time t3. t3 = t2 + T1. In this state, the second analysis unit 2004 can acquire and analyze the control data A (FIG. 19 (e)). The timing at which the second analysis unit 2004 acquires the control data A is synchronized with the cycle of the second timer 2007. For example, t4 = t3 + T2.

  As can be seen from the above description, the control data is delayed by 2 × T1 + α (α is the time from FIG. 19 (a) to (b) = t1−t0, and from (d) to (e). Sum of time T2). Increasing the number of storage elements increases the amount of delay.

  For convenience of explanation, the display of + α is basically omitted below, and the delay amount is simply expressed as 2 × T1 unless otherwise specified.

  In FIG. 20, two control data A and B are written, but the operation is not different from FIG. The time interval between the oblique arrows is T1. As shown in FIG. 19 (e), the timing at which the second analysis unit 2004 acquires the control data is synchronized with the cycle of the second timer 2007. However, for convenience of explanation, the timing of FIG. In the display, the first period T1 and the second period T2 are not distinguished.

  The control data A and B are delayed by a predetermined delay amount and output in the order in which they are written.

  FIG. 21 is an explanatory diagram of an operation when the error signal receiving unit 2005 receives an error signal. In the figure, E indicates error control data or error processing.

  The operation for normal control data A is the same as in FIG. 19, but the operation when an error is received is completely different. That is, the error control data output from the error signal receiving unit 2005 is immediately passed to the second analysis unit 2004, and error processing is immediately performed. This is because immediacy is required for error processing and it is not necessary to synchronize with other peripheral substrates (the liquid crystal control substrate 200).

  In order to realize this immediacy, the error control data is processed differently from normal control data. For example, the error control data is overwritten in the memory element 2003R-3 at the exit end. Or it inputs directly into the 2nd analysis part 2004 (FIG.21 (e)).

  As shown in FIG. 21, the above-described method for realizing immediacy is when the control data exists only in the storage element 2003R-3 at the outlet end and is overwritten with error control data, or the storage elements 2003R-1 to 2003R-3. It can be applied without any problem when none of the above.

  However, problems arise if it is not. This will be described with reference to FIG. In this example, two control data A and B exist, and it is assumed that the error signal receiving unit 2005 receives an error signal while the second analysis unit 2004 is processing the control data A. Since error control data is directly input to the second analysis unit 2004, error processing is immediately executed (FIG. 22 (f)). However, the control data B existing in the storage element 2003R-3 at the outlet end in the next first cycle T1 or second cycle T2 is acquired by the second analysis unit 2004, and the error processing is interrupted (FIG. 22 (g )). According to FIG. 22, the error processing is only executed for a very short time (first period T1 or second period T2). Since error processing requires not only immediacy but also state retainability of retaining an error state until reset, the above method for realizing immediacy cannot be employed as it is.

  When no error occurs, the operation of the plurality of peripheral boards can be made to coincide with each other by the configuration shown in FIG. For example, in the case where the movable body 50 is moved in accordance with the change of the screen, the movable body control data is delayed so that the movable body 50 is moved by half when the screen is changed by half, and the entire screen is changed. It is possible to accurately synchronize operations such as moving the entire movable body 50 (for example, fully opening the shutter). When an image is displayed on the liquid crystal display device LCD, a delay of about 2 frames (66.6 ms) occurs, and this delay is larger than the delay in the control of the movable body 50. Therefore, the delay processing unit 2003 controls the movable body. Try to delay. The amount of delay can be adjusted by the number of storage elements 2003R. According to FIG. 18, it is possible to synchronize presentation operations among a plurality of peripheral boards with the immediateness of error processing by the method described below.

  Therefore, the gaming machine according to the present embodiment employs the technique shown in FIG. That is, when control data exists in any one of the storage elements 2003R-1 to 2003R-3 (FIGS. 23B to 23E), error control data is stored behind (preferably immediately after) the control data. Writing is performed (FIG. 23 (f)). By doing so, error control data as shown in FIG. 22 (g) is not overwritten with normal control data, and state retention can be realized.

  In the method of FIG. 23, some time is required from the writing of the error control data to its analysis / execution, and the immediacy is somewhat impaired. In the example of FIG. 23, it takes about t24−t15 = T1 + T2 from writing to analysis / execution.

  The technique of FIG. 23 can be applied to errors that do not require strict immediacy. In other words, it can be said that the method of FIG. 23 is a suitable form for an error that is easy to process and reliable, and that does not require strict immediacy.

  The operation of the delay control unit 2003c for realizing the processes of FIGS. 19 to 21 and 23 will be described. For the following processes (1.3) to (1.5), refer also to the flowchart of FIG.

(1.1)
The set control data (second control data for the second analysis unit 2004) is written to the storage element 2003R-1 at the entrance end (FIGS. 19A, 20A, 20C, and 21A). FIG. 23 (a) (c)).

(1.2)
Based on the first period T1, the control data stored in the storage elements 2003R-1 and 2003R-2 are respectively moved to the storage elements on the outlet side (FIGS. 19A to 19D and 20A to 20A). e), FIG. 21 (a)-(c), FIG. 23 (a)-(g)). This operation is the same for error control data.

  The control data of the memory element 2003R-3 at the outlet end is sent to the second analysis unit 2004 (FIG. 19 (e), FIG. 20 (e) (f), FIG. 21 (d), FIG. 23 (e) (g)). .

(1.3)
When an error signal is received, writing of new normal control data is stopped (S20 in FIG. 24).

  The states of the storage elements 2003R-1 to 2003R-3 are examined (S21 in FIG. 24), and it is determined whether or not the control data is stored (S22 in FIG. 24).

(1.4)
If none of the storage elements 2003R-1 to 2003R-3 stores the control data (NO in S22 of FIG. 24), the error analysis data for causing the operation corresponding to the error signal to be performed is the second analysis unit. (S28 in FIG. 24, FIG. 21 (e)). When the second analysis unit 2004 is processing normal control data, the operation being analyzed may be canceled and the error control data may be immediately analyzed.

(1.5)
When any one of the storage elements 2003R-1 to 2003R-3 stores the control data (YES in S22 of FIG. 24), the storage element storing the control data is the most entry side (the last one) The tail storage element) is specified (S23 in FIG. 24, 2003R-3 in FIG. 23). The error control data is written to the storage element (S26 in FIG. 24, 2003R-2 in FIG. 23) on the entry side of the last storage element. A shift operation is performed based on the first period, and the second analysis unit 2004 performs error processing (S27 in FIG. 24).

  When the last storage element is 2003R-1, error control data cannot be written. Therefore, the shift operation is waited, the storage element 2003R-1 is waited for, and then the error control data is written therein (in S24 of FIG. 24). YES, S25).

  According to the gaming machine according to the present embodiment, error processing can be appropriately performed even when a plurality of peripheral boards are synchronized using a first-in first-out buffer. That is, both immediacy and state retention can be achieved.

For example, if there are effects scheduled to be executed in the order of effects A, B, and C, and an error occurs during the execution of effect B, an error is displayed instead of effect B that was being executed, but the buffer still remains Since the production C remains, when the execution time of the production B ends, when the error display is finished, the production C is avoided despite the fact that the production C is executed internally. be able to.
Further, in (4), error notification can be immediately performed by causing the second analysis unit to cancel the operation being analyzed and immediately analyze the error control data. This approach is particularly useful for errors that require immediateness.
Further, in (5), when the last storage element is the storage element at the entry end, the error control data is written into the storage element at the entry end after the above (2). Even if is full, it can be handled appropriately. Error processing can be performed without causing so-called buffer overflow.

<Synchronization of operations between multiple peripheral substrates, synchronization of movable body and liquid crystal display as an example (part 2)>
A description will be given of the present embodiment in which the processing content is different from the above example. In this example, a functional block diagram (FIG. 18) and a basic operation explanatory diagram (FIGS. 19 and 20) are not different, and are referred to.

  In the gaming machine according to the present embodiment, as shown in FIG. 25, error control data is stored in memory elements 2003R-1 to 2003R-3 regardless of whether or not control data exists there. Writing (overwriting) is performed (FIG. 25 (f)). By doing so, error control data as shown in FIG. 22 (g) is not overwritten with normal control data, and state retention can be realized.

  In the method of FIG. 25, the time required from the writing of the error control data to the analysis / execution thereof is a minimum T2 to a maximum T1, which is excellent in terms of immediacy. In the example of FIG. 23, it takes about t24−t15 = T1 + T2 from writing to analysis / execution, but it is shorter by T1 than this.

  The method of FIG. 25 can also be applied to errors that require immediacy. It can be said that this is a preferred form for errors that require immediacy.

  In addition, as shown in FIG. 26, if an error signal is received, error control data is directly sent to the second analysis unit 2004 and immediately executed, so that the immediacy can be further improved. According to the method of FIG. 26, the time required from writing error control data to its analysis / execution is about T2. The method of FIG. 26 can be applied to the case where the second analysis unit 2004 can cancel the operation being analyzed and immediately analyze the error control data.

  The operation of the delay control unit 2003c for realizing the processing of FIG. 25 will be described. The processes (1.1) and (1.2) described above are the same in the case of FIG. Refer also to the flowchart of FIG. 27 for the process (2.3) below.

(2.3)
When an error signal is received, writing of new normal control data is stopped (S30 in FIG. 27).

Error control data is written (overwritten) in the memory elements 2003R-1 to 2003R-3 (S31 in FIG. 27).
In the method of FIG. 26, error control data is sent to the second analysis unit 2004.

A shift operation is performed based on the first cycle, and the second analysis unit 2004 performs error processing (S32 in FIG. 27).
In the example of FIG. 25, the error control data is given three times to the second analysis unit 2004, and is given four times in the example of FIG. When the second analysis unit 2004 repeatedly receives error control data, it cancels the previous error operation and starts the error operation from the beginning, but there is no problem because the error state is retained.

  According to the gaming machine according to the present embodiment, error processing can be appropriately performed even when a plurality of peripheral boards are synchronized using a first-in first-out buffer. That is, both immediacy and state retention can be achieved.

  This embodiment is superior in terms of immediacy, and since the conditional branch is not used for the processing, the program can be simplified, and the capacity can be reduced and the processing speed can be improved.

<Synchronization of operation between a plurality of peripheral substrates, and synchronization of movable body and liquid crystal display (example 3)>
Another embodiment different from the present embodiment, which is different in processing content from the above example, will be described. Also in this example, the functional block diagram (FIG. 18), the basic operation explanatory diagram (FIGS. 19 and 20), and the operation explanatory diagram (FIG. 21) when no control data is stored are not different. Refer to these.

  In the gaming machine according to the present embodiment, as shown in FIG. 28, when an error signal is received, an error occurs with respect to the storage element 2003R-3, which is the first output area among the write areas in the buffer. Continue to write error processing data until it is released. By doing so, error control data as shown in FIG. 22 (g) is not overwritten with normal control data, and state retention can be realized.

  In the method of FIG. 28, the time required from the writing of the error control data to its analysis / execution is a minimum T2 to a maximum T1, which is excellent in terms of immediacy. In the example of FIG. 23, it takes about t24−t15 = T1 + T2 from writing to analysis / execution, but it is shorter by T1 than this.

  The method of FIG. 28 can also be applied to errors that require immediacy. It can be said that this is a preferred form for errors that require immediacy.

  Further, as shown in FIG. 21, if an error signal is received, error control data is directly sent to the second analysis unit 2004 to be immediately executed (S46 in FIG. 29), so that immediacy can be further improved. According to this method, the time required from the writing of error control data to its analysis / execution is about T2. This technique can be applied to the case where the second analysis unit 2004 can cancel the operation being analyzed and immediately analyze the error control data.

  The operation of the delay control unit 2003c for realizing the processing of FIG. 28 will be described with reference to the flowchart of FIG.

S40: When receiving an error signal, writing of new normal control data is stopped.

S41: The states of the storage elements 2003R-1 to 2003R-3 are checked.

S42: It is determined whether control data is stored.

S47: If none of the storage elements 2003R-1 to 2003R-3 stores the control data (NO in S42), error control data for performing an operation corresponding to the error signal is stored in the second analysis unit 2004. (FIG. 21E). When the second analysis unit 2004 is processing normal control data, the operation being analyzed may be canceled and the error control data may be immediately analyzed.

S43: If any of the storage elements 2003R-1 to 2003R-3 stores the control data (YES in S42), the error control data is written to the storage element 2003R-3 at the exit end.

S44: A shift operation is performed based on the first period, and the second analysis unit 2004 is caused to perform error processing.

S45: The state of the memory elements 2003R-1 to 2003R-3 is examined.

S46: It is determined whether control data is stored. If none of the storage elements 2003R-1 to 2003R-3 stores the control data (NO), the error signal is not canceled because the state as shown in FIG. 22 (g) does not occur. Cancels processing when receiving a signal.

  When any of the storage elements 2003R-1 to 2003R-3 stores the control data (YES), the processes of S43 to S45 are repeated.

  When the second analysis unit 2004 repeatedly receives error control data, it cancels the previous error operation and starts the error operation from the beginning, but there is no problem because the error state is retained. By repeatedly writing the error control data, the error state can be reliably maintained.

  According to the gaming machine according to the present embodiment, error processing can be appropriately performed even when a plurality of peripheral boards are synchronized using a first-in first-out buffer. That is, both immediacy and state retention can be achieved.

This embodiment is excellent in terms of immediacy. Further, since the error control data is written only to the storage element at the outlet end, it can be performed quickly and reliably as compared with the case of writing to all the storage elements, and the processing speed and reliability can be improved.
<Eliminating chattering without conditional branching>

  The main board 10 and the sub board 20 provided in the gaming machine receive output signals from various sensors and switches operated by the player. Then, based on output signals from sensors, switches, etc., the game processing as described above is performed. For example, the sub-board 20 receives a signal from a push button switch PHSW provided at the center together with a sensor for detecting the rotation of the operation unit (jog dial) PAN.

  The main board 10 and the sub board 20 are provided with a microcomputer (CPU) and perform processing based on digital signals. Therefore, the processing is performed by converting signals from the sensors and switches into digital signals and treating them as data. The digital signal is typically a data string of “0” and “1” respectively associated with high / low (H / L) signal levels. As a digital signal interface often used in an IC, for example, there is a TTL (Transistor Transistor Logic). In order to convert the signals from the sensors and switches into digital signals, the boards such as the main board 10 and the sub board 20 sample the signals from the sensors and switches at regular intervals, and based on the result, “0” “1” is generated.

  The signal from the sensor or switch may contain noise. In addition, in devices such as switches, chattering (on / off may be repeated irregularly within a short time) may occur due to structural reasons. These noises and chattering are not only unnecessary, but they should be removed because their presence may cause the CPU to malfunction or perform processing different from the intended processing.

  In order to eliminate noise and chattering, in conventional gaming machines, a signal string is obtained by sampling signals from the sensors and switches, and a plurality of data included in the data string are compared to match each other. The state of the signal was confirmed.

  Thus, in general, comparison processing and conditional branch instructions are used to eliminate chattering.

  The comparison processing (comparison instruction) has a heavy processing load compared with arithmetic instructions such as logical product and logical sum. From the viewpoint of reducing the processing load on the CPU, it is better not to use a comparison instruction.

  In addition, some recent CPUs have a superscalar structure, and there is a problem in that conditional branch instructions in this CPU are less efficient. A superscalar is a kind of CPU architecture, which implements the parallel computing concept of instruction level parallelism in the CPU, and a plurality of processing units provided in the CPU by simultaneously reading a plurality of instructions. Are processed in parallel using. Even if a superscalar CPU executes multiple instructions, if it jumps to an instruction of a different branch route depending on a conditional branch instruction, other instructions executed at the same time will be wasted. Line is stalled "). If the conditional branch instruction is used in this way, the processing efficiency deteriorates.

  In the present embodiment, chattering is removed without using a comparison instruction and a conditional branch instruction, and as a result, the processing load on the CPU is reduced.

  FIG. 30 is a flowchart of chattering removal processing according to the present embodiment. In this process, the comparison process and the conditional branch process (determination process) are not used.

  The processing of FIG. 30 eliminates chattering in a short time (same as the sampling period of the input signal or less than twice the sampling period). When chattering occurs, the previous input data is taken over.

  For example, as an operation monitoring of the jog dial PAN, sampling is performed about every 521 μs (1920 fps) regarding detection of the sensors JS1 and JS2 related to the rotation of the dial JD and detection of pressing of the push button switch PHSW. This period is defined by the communication protocol between the sub-board 20 and the peripheral board. In the process of FIG. 30, in order to remove chattering, the sampling result every about 521 μs is monitored twice, and if the result matches, it is taken into the process as a normal signal.

  Regarding the jog dial PAN, left and right rotations are detected based on the results obtained from the two input signals from the two sensors JS1 and JS2 shown in FIG. 5B. Are also processed, and chattering removal is performed on a total of three input signals. However, since these processes are independent for each line, in the following description, any one of these processes will be described.

  Although chattering removal processing can be performed in real time, real-time processing is not required for processing of the operation unit PAN in this case, and there is enough time to wait for the processing result. In addition, since the CPU can process data of a plurality of bits (8 bits, 16 bits, 32 bits, etc.) at a time, a plurality of times (8 times, each signal (1 bit signal)). It is more efficient to handle sampling data (16 times, 32 times, etc.) as one unit (word).

  Therefore, in this embodiment, analysis is performed collectively after a certain amount of data is accumulated. For example, the analysis timing is every 30 fps (about 33.33 ms), 32 pieces of data are held per signal (signal change is 1 bit, ON and OFF only), and stored in a 32-bit variable. Yes. The process of FIG. 30 is performed for each bit of the 32-bit variable.

  However, in order to simplify the description, a description will be added below taking a 1-bit process as an example. The CPU register is designed to simultaneously perform logical operations on each bit of one word. In the case of a plurality of bits, the following 1-bit processing is performed simultaneously.

  A description of symbols in FIG. 30 will be added.

[S1] is sampled data (1 bit).
[S2] is sampled data after [S1].
[B] is a value (output) obtained in the previous process.
[Sa] is a logical product of [S1] and [S2]. This truth table is shown in FIG.
[So] is the logical sum of [S1] and [S2]. This truth table is shown in FIG.
[SB] is the logical sum of [Sa] and [B]. This truth table is shown in FIG.
[SBo] is the logical product of [SB] and [So]. This truth table is shown in FIG.

  FIG. 35 is a block diagram of a logic circuit that performs the same processing as that of FIG. FIG. 35 shows the internal structure of the chattering removal unit. This embodiment can be realized not only by software but also by hardware such as an IC.

  Reference numerals 2100 and 2101 denote latches for sampling signals. An input of the latch 2101 is a signal from the operation unit, and this output is an input of the latch 2100. The series connection of latches as shown in the figure operates so that the signal shifts at every sampling timing. At a certain point in time, the latest data (the latest sampling data) is held in the latch 2101, and the data before one sampling is held in the latch 2100. In the example of FIG. 36, when the latch 2101 holds the data (13), the latch 2100 holds the data (12). In other words, the output of the latch 2100 is delayed by one cycle of the sampling signal (TS1 in FIG. 36) compared to the output of the latch 2101. Therefore, the output of the latch 2101 is [S2], and the output of the latch 2100 is [S1].

Reference numeral 2102 denotes an AND circuit for obtaining a logical product of [S1] and [S2].
Reference numeral 2103 denotes an OR circuit for obtaining a logical sum of [S1] and [S2].
Reference numeral 2104 denotes an OR circuit that calculates the logical sum of the output [Sa] of the AND circuit 2102 and the output [B] of the latch 2106.
An AND circuit 2105 obtains a logical product of the output [SB] of the OR circuit 2104 and the output [So] of the OR circuit 2103. The output [B] of the AND circuit 2105 is an output from which chattering has been removed.
Reference numeral 2106 denotes a latch that holds the output [B] for use in the next processing.

  FIG. 36 is a timing chart for explaining chattering removal according to the present embodiment. A sampling signal is generated every sampling interval TS1, and processing is performed in units of this. A processing result is output after a predetermined processing time TS2, and a signal from which chattering has been removed is output.

  In FIG. 36, chattering does not occur, but even if a chattering signal (a signal shorter than twice TS1) occurs, the signal is removed and does not appear on the output side. For example, if the low level is 0 and the high level is 1, it should originally be “001111...”, But if it becomes “001011.

  The chattering elimination logic according to the present embodiment (1) outputs the value when the same value is sampled twice or more consecutively (00, 11), and (2) outputs the previous value otherwise. Is to do. FIG. 37 shows a truth table of the logic.

  The output (right end) of the truth table in FIG. 34, which is the output of FIGS. 30 and 35, is the same as the output (right end) of FIG. 37, so the processing of FIG. 30 and the apparatus of FIG. ing.

  With reference to FIGS. 30 and 35, the chattering removal processing according to the present embodiment will be described.

S50: A logical product of [S1] and [S2] is obtained by AND2102, and this output is set to [Sa].

S51a: The logical sum of [Sa] and the previous value [B] is obtained by the OR circuit 2104, and this output is set to [SB].

S51b: The OR circuit 2103 obtains the logical sum of [S1] and [S2], and sets this output as [So].
Since the value used in S51a and the value used in S51b do not overlap, S51a and S51b can be executed simultaneously in a superscalar CPU. Further, since there is no conditional branch, the CPU pipeline does not stall.

S52: A logical product of [SB] and [So] is obtained by the AND circuit 2105, and this output is set to [SBo]. Output the signal with chattering removed [SBo].

S53: The latch 2106 holds [SBo] as the previous output [B].

Eventually, the above processing is equivalent to the following equation.
This time [SBo] = (([S1] AND [S2]) OR [B]) AND ([S1] OR [S2])

  According to the present embodiment, there is the following advantage compared with a general processing method using conditional branching.

(1) Since the comparison instruction is not used, the CPU pipeline does not stall.
The stall will be described with reference to FIGS. 38 and 39. FIG.
FIG. 38 is a flowchart of general chattering removal using a conditional branch. FIG. 39 is a timing chart showing the processing procedure, and processing proceeds from left to right. FIG. 39 (a) shows the processing of the present embodiment, and FIG. 39 (b) shows the processing of FIG.

  S62 in FIG. 38 is a conditional branch, which compares two sampled data. Depending on the comparison result (YES / NO), the contents of the process are different (S63 or S64). Even if a plurality of instructions S63 and S64 are read simultaneously using the superscalar, one of them is always wasted (not used). The crosses in FIG. 39 (b) mean this. Therefore, a stall occurs in the process of FIG. I can't use my superscalar.

  On the other hand, according to the present embodiment, as shown in FIG. 39 (a), the logical sum of [Sa] and [B], which is the previous value, in which there is no mutually dependent data exists. The process of [SB] and the process of obtaining the logical sum of [S1] and [S2] and setting it to [So] can be performed at the same time, and these results are not discarded, so a stall occurs. do not do. Superscalar can be utilized. Processing efficiency is improved by executing the processes in parallel.

(2) It is possible to simultaneously analyze input signals up to the number of bits (for example, 32 bits) of the CPU register. According to the present embodiment, as long as the number of bits in the register is within the range, even if the data to be processed increases, the processing load does not change and high-efficiency processing is possible.

  For example, data obtained by sampling a plurality of signals at the same time from MSB to LSB in that order is stored in register A (this becomes [S1]), and the next sampling data is similarly stored in another register B. (This is [S2]). For registers A and B, the processing of S50 and S51b in FIG. 30 is performed. Other processes also process a plurality of data simultaneously using the number of bits of the register.

  It is also possible to simultaneously process a plurality of sampling signals for one signal. Data obtained by sampling one signal a plurality of times (for example, 32 times) from MSB to LSB in that order is stored in register A (this becomes [S1]), and data sampled a plurality of times with a delay of one sampling period Are arranged in the order from the MSB to the LSB and stored in the register B (this is [S2]).

  Alternatively, [S1] is shifted by 1 bit in the MSB direction, and new sampling data is stored in the free LSB and stored in another register B (this becomes [S2]).

  For registers A and B, the processing of S50 and S51b in FIG. 30 is performed. Other processes also process a plurality of data simultaneously using the number of bits of the register.

  A plurality of latches 2106 are also prepared in accordance with a plurality of sampling times.

  In FIG. 36, 13 arrows (1),... (12), (13) indicating the sampling timing are shown (the display of (2) to (11) is omitted for easy viewing of the drawing. If this is taken as an example, sampling data (1) to (12) is [S1], and sampling data (2) to (13) is [S2]. The same applies to bit shift.

  In the processing of FIG. 38, it is necessary to perform the chattering removal unit in 1-bit units and perform comparison for each bit (since there is a conditional branch, a plurality of data cannot be processed simultaneously). S60, S65, and S66 in FIG. 38 correspond to this process. In the figure, since 8-bit data is processed, the processing is looped eight times. For this reason, processing efficiency deteriorates.

  According to the present embodiment, by configuring the chattering removal method with high-speed and low-load logic, it is possible to reduce resources necessary for calculation.

  In the above example, the old and new sample information is divided into two parts, but this is not essential. For example, if the processed data is copied and bit-shifted, it can be handled as the previous one.

<Jog dial: Check sensor signal>
The processing procedure of the output signal of the jog dial PAN (especially the detection determination of the rotation direction) will be described.

  The jog dial PAN is a substantially cylindrical device and includes a rotatable ring (dial JD) as shown in FIG. 5A, and a push button switch PHSW is provided at the center thereof. The dial JD can be turned left and right. The push button switch PHSW is provided with a light emitting element. The dial JD is rotated in a plurality of steps (for example, the number of steps = 30, the angle = 12 degrees).

  As shown in FIG. 5 (b), the jog dial PAN has two sensors [1] JS1 and [2] JS2 for detecting the rotation of the dial JD (hereinafter, JS1 and JS2 for simplicity of description). Display is omitted). Sensors [1] and [2] output two digital signals of H / L according to the rotation, but they are different from each other. An example of the output signals of the sensors [1] and [2] is shown in FIG. The figure shows the change of the signal according to the rotation of the dial JD. A notch is a step. For example, a 12-degree rotation of the dial JD is one step. The stop position of the dial JD is in units of notches. That is, the dial JD stops at the position indicated by the dotted line in FIG. 40, and does not stop at other positions. + And-indicate the direction of rotation, for example, right rotation is + and left rotation is-(this correspondence is arbitrary). The H / L relationship may be reversed (either positive logic or negative logic may be used).

  FIG. 40 is merely an example of a signal when the jog dial PAN is rotated. The signal of the jog dial PAN may be changed at a timing different from that in FIG.

  The signal of the jog dial PAN has the following properties.

(1) The edge change of each signal that occurs during one notch (one segment) is one time.
An edge is a point that changes from H to L or from L to H. Since the correspondence relationship of H / L is arbitrary, attention is focused on edge change.

(2) Each signal repeats the same content in units of 2 notches. That is, the repetition period is 2 notches.

(3) The signal waveform patterns of sensors [1] and [2] are the same, but there is a phase shift. Therefore, both the sensors [1] and [2] do not change edges simultaneously. In FIG. 40, this shift is not equal left and right. TZ1 ≠ TZ2. In other words, when the signal of sensor [2] is moved in the + direction so as to match the signal of sensor [1], the amount of movement (TZ2) is the same as the amount of movement (TZ1) when moved in the-direction. It is not. Note that TZ1 = TZ2.

  According to FIG. 40, the following phenomenon occurs in order when rotated to the + side. However, it is assumed that the stop position is in the range of TZ2. Note that the stop position may be within the range of TZ1, but in this case, the sensor [1] and the sensor [2] in the following rules are switched.

(+ Side phenomenon (1)) Edge change occurs in sensor [1].
(+ Side phenomenon (2)) Edge change occurs in sensor [2].

  According to this rule, when the phenomenon occurs in the order of sensor [1] and sensor [2], it can be recognized that dial JD has rotated one notch in the + direction.

  Similarly, when rotated to the minus side, the following phenomena occur in order.

(-Side phenomenon (1)) Edge change occurs in sensor [2].
(-Side phenomenon (2)) Edge change occurs in sensor [1].

  According to this rule, when the phenomenon occurs in the order of sensor [2] and sensor [1], it can be recognized that dial JD has rotated one notch in the negative direction.

  As a method for operating the jog dial, there is an operation for reversing the direction of rotation, for example, by moving it vigorously alternately left and right in addition to simply rotating in the same direction. An example of the signal change at this time is shown in FIG.

  FIG. 41 is a timing chart. Time elapses from left to right. The rotation direction of the dial JD is reversed at the operation reversal position in the center of the chart. In the example of the figure, the direction is changed from forward rotation (+ direction) to reverse rotation (− direction). When a reverse rotation operation is performed, the edge is always detected again from the sensor that detected the edge immediately before. Such a phenomenon occurs because the lengths (GY1 + and GY1-, GY2 + and GY2-) to the front and rear edges of the same sensor are equal.

  Thus, a phenomenon different from that during forward rotation occurs during reverse rotation.

  Even if the player does not intend, the reverse rotation phenomenon may occur. The dial JD is provided with a positioning mechanism called a notch so that the user can easily grasp the number of steps during rotation. When the rotation is stopped, the dial JD is always in one of the notches. Due to the inertia of the dial JD, during rotation, the user may not fit in the notch at the moment when the user stops the operation, and at this time, the dial JD may rotate counterclockwise for a moment. At this time, the sensor may output a signal.

  FIG. 42 shows a block diagram of an apparatus for obtaining the rotation amount (including the rotation direction) of the jog dial that outputs the signals shown in FIGS.

  Reference numeral 2201-1 denotes an edge detector that receives the sensor [1] and detects an edge thereof.

  Reference numeral 2201-2 denotes an edge detector that receives the sensor [2] and detects an edge thereof.

  The edge detector 2201-1 includes a buffer 2201-11, a bit shifter 2201-12, a buffer 2201-13, and an exclusive OR circuit 2201-14. Although not shown, the edge detector 2201-1 is the same.

  The buffer 2201-11 samples the signal of the sensor [1] (1-bit H / L signal) at regular intervals, and stores them in that order. The buffer 2201-11 is a shift register, for example. An example of the stored contents is shown in FIG. A plurality of 1-bit data is stored, and data is input from the right side LSB and shifted to the left side every sampling. The right LSB is the latest data, and the left MSB is the most recently sampled data.

  When a certain number (for example, 32) of data is written in the buffer 2201-11, all the data in the bit shifter 2201-12 is read out, shifted by 1 bit, and written in the buffer 2201-13. The bit shifter 2201-12 moves each piece of data in the buffer 2201-11 by one in the right (entrance LSB) direction.

  The buffer 2201-13 is a memory (shift register) having the same structure as the buffer 2201-11. By the operation of the bit shifter 2201-12, the data in the buffer 2201-13 becomes as shown in FIG. Since the bit shifter 2201-12 shifts by one to the right, there is no data in the left end MSB (symbol X), and the data in the right end LSB in FIG. 43 (a) is lost. There is no problem if the exclusive OR operation is not performed on the leftmost MSB, but data can be prevented from being lost if the following operation is performed.

  The right end LSB data of FIG. 43 (a) before the bit shift is stored in a memory (not shown), and the contents of the buffer 2201-11 are cleared next time (after the edge detection process is finished and the result is output). When sampling is performed again and the buffer 2201-11 becomes full, the bit shift is performed again), and the data is written to the leftmost MSB (symbol X) in FIG.

  The exclusive OR circuit 2201-14 calculates an exclusive OR for each bit of the buffers 2201-11 and 2201-13. This makes it possible to know where the edge is (when the data change occurs). That is, an edge exists at the position “1” in FIG.

  As described above, the steps necessary for edge detection are data acquisition (for example, 32 sampling), bit shift / data copy, and exclusive OR, and a plurality of (for example, 32 times) data can be processed at once. In addition, the edge detection can be performed much more efficiently than the condition determination for each sampling.

  Reference numeral 2203 denotes a logical sum circuit (which may be an exclusive logical sum as will be described later) for obtaining a logical sum of the outputs of the edge detectors 2201-1 and 201-2.

  Next, processing for determining the amount of rotation (including the rotation direction) based on the detected edge will be described. This processing is performed by the rotation detection unit 2202 based on one output of the edge detector 2201-1 or 2201-2 and the output of the OR circuit 2203.

  FIG. 44 is an explanatory diagram (timing chart) of edge detection status and rotation amount, that is, forward / reverse rotation determination. FIG. 44 (a) shows the output signal waveforms of the sensors [1] [2] and the edge detection position (“1” indicates edge detection. One square corresponds to the sampling interval). FIG. 44B shows rotation detection based on edge detection. A circle indicates that a forward or reverse rotation of one notch has occurred at that timing (one square). The amount of rotation can be obtained by accumulating ○ marks for each of the forward rotation and the reverse rotation. For example, (accumulation of circles in forward rotation) × (angle of 2 notches) = (rotation angle in the forward direction). Alternatively, (the accumulation of the forward rotation circles) itself can be used as the rotation amount. In this case, the notch is a unit of rotation. The forward rotation is, for example, right rotation and the reverse rotation is, for example, left rotation, but this correspondence is arbitrary.

  With reference to the above rule, the rotation amount is obtained based on the edge detection shown in FIG.

  That is, when it is detected that the sensors [1] and [2] alternately generate edges, it is determined that the rotation is (circle). When the edge is continuously detected by the sensor, it is determined that the rotation direction is reversed.

  If a condition determination sentence is used to check whether the sensors [1] and [2] alternately generate edges during the above determination, the CPU occupancy rate increases. Therefore, it is preferable to use a process that eliminates conditional expressions as much as possible.

  FIG. 45 is a process flowchart of the rotation detection unit 2202. FIG. 46 is an explanatory diagram (timing chart) thereof. In FIG. 46, the first square is in the initial setting state, and the dial JD is not moving. The next 6 squares advance 3 notches in the forward direction, and the next 6 squares go back 3 notches in the reverse direction.

  First, processing for forward rotation (FIG. 46 (A) and the like) will be described. It is assumed that initialization has been performed before the processing, and all of the forward rotation flag, the reverse rotation flag, and the rotation amount are zero.

  When the dial JD rotates and proceeds to the next notch, the signals of the sensors [1] and [2] change as described above.

  First, the signal of the sensor [1] changes (symbol (A1)), and the rotation detection unit 2202 detects an edge based on the output of the OR circuit 2203 (YES in S70). Note that an exclusive logic circuit can be used as the reference numeral 2203 instead of the OR circuit 2203. In principle, the signals of sensors [1] and [2] do not become 1 at the same time, so even if an exclusive logic circuit is used, it is not different from the case of an OR circuit.

  It is determined that the signal of the sensor [1] has changed based on the output of the edge detector 2201-1 (YES in S71).

  A rotation amount is obtained (S72). The rotation amount is obtained by subtracting the reverse rotation flag from the previous rotation amount, but the rotation amount does not change because the reverse rotation flag is zero.

  The example of FIG. 45 is an example in which the rotation direction corresponds to the sign of the rotation amount +/−. One rotation amount in FIG. 45 corresponds to both the left and right rotations. For this reason, in S72, the reverse rotation flag is subtracted from the rotation amount. In addition, you may make it give separate rotation amount (variable) to each of right and left. For example, as shown in FIG. 48 described later and the description thereof, two variables of a reverse rotation amount and a forward rotation amount may be used. In this case, a reverse rotation flag is added to the reverse rotation amount.

  A forward rotation flag is obtained (S73). The forward rotation flag is obtained by inverting the logic of the previous reverse rotation flag (to obtain an exclusive OR with 1). Since the reverse rotation flag is zero, the forward rotation flag is 1.

  The reverse rotation flag is set to zero (S74).

  When the signal from the sensor [1] changes first, it is determined that the rotation is forward by the above processing.

  Next, the signal of the sensor [2] changes (sign (A2)). However, since the output of the edge detector 2201-1 has not changed, the rotation detector 2202 determines that the signal of the sensor [1] has not changed (NO in S71).

  A rotation amount is obtained (S75). The rotation amount is obtained by adding a forward rotation flag to the previous rotation amount. Since the forward rotation flag is 1 in S73, the rotation amount is incremented by one.

  A reverse rotation flag is obtained (S76). The reverse rotation flag is obtained by inverting the logic of the previous forward rotation flag (to obtain an exclusive OR with 1). Since the forward rotation flag is 1, the reverse rotation flag is zero.

  The forward rotation flag is set to zero (S77).

  The above process is a determination process for one sequence of forward rotation. When the process of sign (a) ends, both the forward rotation flag and the reverse rotation flag become zero, and the initial state is restored. As a result, it becomes possible to cope with whether the next is forward rotation or reverse rotation.

  Next, processing for reverse rotation (such as (A) in FIG. 46) will be described.

  When the dial JD rotates and proceeds to the next notch, the signals of the sensors [1] and [2] change as described above.

  First, the signal of sensor [2] changes (symbol (A1)), and rotation detection unit 2202 detects an edge based on the output of OR circuit 2203 (YES in S70). Since the output of the edge detector 2201-1 has not changed, the rotation detector 2202 determines that the signal of the sensor [1] has not changed (NO in S71).

  A rotation amount is obtained (S75). The rotation amount is obtained by adding a forward rotation flag to the previous rotation amount. Since the forward rotation flag is zero, the rotation amount does not change.

  A reverse rotation flag is obtained (S76). The reverse rotation flag is obtained by inverting the logic of the previous forward rotation flag (to obtain an exclusive OR with 1). Since the forward rotation flag is zero, the reverse rotation flag is set to 1.

  The forward rotation flag is set to zero (S77).

  Next, the signal of the sensor [1] changes (symbol (A2)), and the rotation detection unit 2202 detects an edge based on the output of the OR circuit 2203 (YES in S70). And it determines with the signal of sensor [1] having changed based on the output of edge detector 2201-1 (it is YES at S71).

  A rotation amount is obtained (S72). The rotation amount is obtained by subtracting the reverse rotation flag from the previous rotation amount. However, since the reverse rotation flag is 1, the rotation amount is decreased by 1.

  A forward rotation flag is obtained (S73). The forward rotation flag is obtained by inverting the logic of the previous reverse rotation flag. Since the reverse rotation flag is 1, the forward rotation flag is zero.

  The reverse rotation flag is set to zero (S74).

  When the signal of the sensor [2] changes first, it is determined that the rotation is reverse by the above processing.

  The above process is a determination process for one sequence of reverse rotation. When the process of sign (a) is completed, both the forward rotation flag and the reverse rotation flag become zero, and the initial state is restored. As a result, it becomes possible to cope with whether the next is forward rotation or reverse rotation.

  By the way, in the above description, the processing is started by detecting the edge of one of the two sensors [1] [2] (OR circuit 2203 in FIG. 42, S70 in FIG. 45). On the other hand, as shown in FIG. 47, a method of making a determination for each of the two sensors [1] and [2] is also conceivable.

  However, the method of FIG. 47 has a problem that the processing load increases. In actual processing, the amount of rotation (the number of times of edge detection) that can be detected in a plurality of sampling periods is not so much, and considering the actual operation on the gaming machine, the jog dial is more frequently stopped when it is stopped. Considering this situation, as shown in FIG. 45, it is better to determine the stop state first and exclude it from the processing (the processing of S71 to S77 of FIG. 45 is not performed) than the processing of FIG. However, the processing load can be reduced.

  Although it does not occur in practice, consider detecting edges simultaneously at sensor [1] and sensor [2] (since sampling processing is performed, high-speed rotation is performed so that the notch interval exceeds the sampling period. Sometimes there can be simultaneous detection). In this case, in the process of FIG. 45, the process on the sensor [1] side (S72 to S74) is always performed, and the forward rotation is performed (when an OR circuit is used for reference numeral 2203). However, since simultaneous edge detection of sensor [1] and sensor [2] is not necessarily forward rotation, the possibility of erroneous processing cannot be denied according to the processing of FIG. Note that when an exclusive OR circuit is used for the reference numeral 2203, the above-mentioned problem does not occur because the processing of S72 to S74 and S75 to S77 is not performed in the simultaneous edge detection. Since parameter initialization (S102, S103) is not performed, there is a possibility that malfunctions cannot be completely prevented.

  49 and 50 show processing flowcharts for solving the above problem. These processing flowcharts show processing for a plurality of bits (32 bits) shown in FIG.

S90: The edge of each sensor is detected.
As described above, the edge detectors 2201-1 and 201-2 generate edge detection data as shown in FIG. The data shown in FIG. 41C is generated for each of the sensor [1] and the sensor [2].

S91: Find overlapping edges and exclusive edges of both sensors.
A logical product is obtained for each bit of the edge data of the sensor [1] and the edge data of the sensor [2], and this is used as overlapping edge data. The overlapping edge data indicates that the simultaneous detection has occurred.

  Similarly, an exclusive OR is obtained for each bit of the edge data of the sensor [1] and the edge data of the sensor [2], and this is used as exclusive edge data. The exclusive edge data indicates that edge detection has occurred in either sensor [1] or sensor [2]. Even if the above simultaneous detection occurs, the calculation result is zero, so if the edge data of sensor [1] and the edge data of sensor [2] are both non-detection and simultaneous detection only, the exclusive edge data is All become zero.

S92: It is determined whether the exclusive edge data is all zero.
If the exclusive edge data is all zero (YES), the sensor [1] and the sensor [2] are not detected (or detected simultaneously), so there is no need to process them, and the process ends.

  Otherwise (NO), the processing after S93 is executed. The subsequent processing is performed for a plurality of bits (32 bits) MSB (the oldest data 1 bit). Since the processing is sequentially performed from the MSB side by performing bit shift in S104 to S106, the processing after S93 is processing along the time axis as shown in FIGS.

  Since the jog dial is operated only when necessary and edges are not detected in many cases, the processing load can be reduced by performing the processing of S92 first.

  In addition, == shows an equal sign. 48 and 49, the symbol == is used to distinguish from = (substitution).

S93: It is determined whether duplicate edge data is set.
If the MSB of the overlapping edge data is set (= 1) (YES), the rotation amount is not calculated. However, if the edges overlap, there is a high possibility that the rotation direction will be misidentified, or there is a high possibility of a malfunction, so if the same condition occurs, all the parameters for rotation monitoring are initialized (S102). , S103). Since MSB = 1 indicates a negative value, in S93, it is determined whether or not overlapping edge <0 (S94 and S95 are the same).

  The situation where edge detection occurs at the same time is an unexpected event, but can occur during high-speed rotation. Under such circumstances, it is assumed that the player itself does not grasp the amount of rotation, so even if the amount of rotation is not calculated, some rotation error due to this does not seem to be a problem.

  In the drawing, whether or not overlapping edge data is set is determined by the sign of overlapping edge data being negative. In order to determine whether a certain bit is 1/0, specific data (only the relevant bit is 1 and the others are 0) is prepared in advance, and this is calculated by calculating the data to be compared. Whether the MSB is 1/0 can be more easily checked by checking a predetermined flag (sign) in a state where the MSB is put in a register. Therefore, in S93, S94, and S95, the MSB is determined to be 1/0 by determining the sign of the data. Since 1 means minus and 0 means plus, S93, S94, and S95 are YES when the data is 1.

S94: It is determined whether exclusive edge data is set.
If the MSB of the exclusive edge data is not set (= 0, NO), the rotation amount is not calculated.
This process corresponds to S70 in FIG.

S95: It is determined whether it is detected by the sensor [1].
Processing is distributed according to the MSB set / reset (1/0) of the sensor [1].
This process corresponds to S71 in FIG.

  S96 to S101 correspond to S72 to S77 in FIG. With these processes, the rotation amount is obtained for each bit. In order to process the next bit, bit shift is performed in S104 to S106.

S104: The exclusive edge data is shifted to the MSB side by 1 bit so that the next data can be processed. Zero is inserted in the LSB side.
<< = indicates a bit shift to the left side (MSB), and a number indicates a shift amount.

S105: The data of sensor [1] is shifted to the MSB side by 1 bit so that the next data can be processed. Zero is inserted in the LSB side.

S106: The overlapping edge data is shifted by 1 bit to the MSB side so that the next data can be processed. Zero is inserted in the LSB side.

S107: It is determined whether the exclusive edge data is all zero.
If the exclusive edge data is all zero (YES), the sensor [1] and the sensor [2] are not detected (or detected simultaneously) from this point onwards, so there is no need to process them. After performing (S108), the present process is terminated.

  If all of them are not zero (NO), there remains edge data to be processed, so the process returns to S93 to repeat the processing.

  According to S107, the processing can be terminated when there is no processing target (1 bit), and therefore it is not always necessary to repeat the processing by the number of bits (32 bits). As a result, the processing load can be reduced.

  According to the present embodiment, the rotation amount calculation process based on the logical sum (or exclusive OR) of the outputs of the two sensors before the calculation process of the jog dial rotation amount (forward rotation amount, reverse rotation amount). If there is no edge in any of the two sensors and there is no need for the rotation amount calculation process, the jog dial rotation amount calculation process is immediately exited. For this reason, the execution frequency of the conditional branch instruction can be lowered in the process of detecting the rotation direction and angle of the jog dial. Most of the jog dial processes with a lot of non-operation time can be terminated at the first conditional branch. Thereby, the processing load on the CPU can be reduced.

  In addition, rotation is detected by using three parameters, a forward rotation flag, a reverse rotation flag, and a rotation amount, and the rotation amount is obtained. Since there is little possibility that these three parameters become illegal values simultaneously due to noise or the like, erroneous detection due to noise can be prevented by using the three parameters.

  The monitoring of the jog dial sensor performs sampling at high speed in order to accurately recognize the rotation information, but the jog dial itself is not a device that always rotates (continuously rotates), and the signal change of each sensor is compared with the sampling interval. Overwhelmingly few. In the present embodiment, by performing the above-described processing, it is possible to suppress the control load during normal time (no rotation) as much as possible.

  In response to sensor response, conditional branching is reduced as much as possible to reduce the load.

  In addition, when each signal is individually determined, there is a problem that erroneous rotation detection is performed if the sensor signal is changed simultaneously due to the sampling interval of the sensor or signal misdetection. In the present embodiment, the exclusive OR is used to perform the process with one sensor [1] being valid, so that the above problem can be avoided without performing a special process. For example, no false detection occurs even if the edge changes simultaneously due to the influence of radio waves or the like. Further, it is possible to reduce the weight of the recovery process when the sensor is erroneously detected.

<V frame delay support>
As already described with reference to FIG. 10, when an image is displayed on the liquid crystal display device, a time corresponding to two V frames is required after the drawing data is saved until the display is executed. Cost. For this reason, it is necessary to match the operations of the effects performed while synchronizing the display of the liquid crystal display device and the sound (the liquid crystal control board 200 and the speaker board 201) (synchronization of the accessory is described above). As shown in FIG. 10, a delay of about 2 frames (66.6 ms) occurs when an image is displayed on the liquid crystal display device LCD. For this reason, in order to synchronize the screen and sound of the liquid crystal display, it is necessary to delay the processing according to the delay.

  Writing (transfer) of a sound command for generating sound is performed via a command buffer (corresponding to the transmission data register 2102 described above) as shown in FIG. A command for causing the CPU of the sub-board 20 to generate a specific sound is written in the command buffer, and the command is read from the command buffer at a predetermined timing, and the sound generator (IC) (not shown) of the speaker board 201 (or the sub-board 200) is shown. Send to. Command transfer is performed at predetermined intervals (time required for main task processing on the system side is 16.6 ms). Although the time until sound generation varies depending on the number of commands required until sound reproduction, there is a possibility that it is about 1 to 2 V frames ahead of the processing of the liquid crystal display device as described above.

  As a command buffer registration method, there are an exclusive single command registration method (D in FIG. 50) and an exclusive batch command registration method (e in FIG. 50).

  “Exclusive expression” indicates that a command prepared for writing is not recorded in the command buffer in response to an overflow of the command buffer. “Batch command registration” indicates that a plurality of commands to be registered in the sound generator (IC) are registered at once. At this time, if an overflow occurs in the command buffer during registration, data up to the point of occurrence is registered. In the case of batch registration, since the number of registered data is returned to the caller, it can be set excluding registered data at the next recording.

  A command to the sound generator (IC) registered in the command buffer is basically set unconditionally to the sound generator (IC).

  When an abnormality of the sound generator (IC) is detected and reset, all data registered in the command buffer are initialized before returning. This is because the output from the command buffer is prohibited during the initialization operation, so that the remaining data is accumulated and there is a possibility that a part of the sound is reproduced at the time of return. .

  In order to synchronize the liquid crystal display screen and sound, the sound processing is delayed according to the above-mentioned delay on the image side. As this delay method, an automatic delay type in which the delay amount is fixed, and a delay amount There are two types of designated delay types in which the variable is variable. FIG. 51 is an explanatory diagram of these operations.

  The automatic delay type in FIG. 51 delays 2V frames, and each of the commands 1 to 9 is taken out in the frame on the right by two.

  In the designated delay type of FIG. 51, since no delay is designated for commands 1 and 2, 6 and 7, and 8 and 9, those commands are extracted in the same frame, but 3, 4 and 5 are delayed. Since the designation has been made, each frame is taken out by two adjacent frames.

  In this way, data can be extracted by automatic / designated delay type reading for command setting (buffer) writing. In FIG. 51, the automatic / designated delay type sample with the shortest read timing is shown. “Delay designation” is valid only for the designated delay type (the delay amount is 2 V frame delay).

  Since the above automatic / designated delay type cannot be used together, either one is adopted. In the example of FIG. 51, a two-frame delay is taken as an example, but any number of frame delays can be set. Further, since the memory usage that changes when n frames are delayed is n × 4 bytes (only n address storage areas), the burden on the memory is small even if the number of delays increases.

  The delay to synchronize the LCD screen and sound can be determined by selecting the automatic / designated delay type and registering the command in the command buffer without being aware of the delay if the number of delay frames (n) is determined. Triggered automatically (if specified delay type, it is necessary to specify delay before registration).

  Next, processing for realizing the delay of FIG. 51 will be described.

First, automatic delay processing will be described with reference to FIGS.
FIG. 52 shows the stored contents of a command storage unit (corresponding to the data register 2101 in FIG. 7) that stores commands to be registered in the command buffer. Nine commands CMD1 to CMD9 are stored at addresses 100 to 108 (this is an example, and more commands can be stored).

  FIG. 53 shows the structure of the command buffer (corresponding to the transmission data register 2102 in FIG. 7). The command buffer is a first-in first-out buffer (FIFO), and the data written in W1 moves in order of W2 and W3, and the command in W3 is transmitted (sent to the transmission shift register 2103 in FIG. 7). Data transfer timing is V frame switching.

  FIG. 54 shows how the automatic delay commands 1 and 2 (CMD1, CMD2) in FIG. 51 are delayed.

  FIG. 54A shows a state in which CMD1 and CMD2 are written in the command buffer W1 in the 1V frame of FIG.

  FIG. 54B shows a state in which CMD1 and CMD2 have moved to W2 in the 2V frame of FIG.

  FIG. 54 (c) shows that CMD1 and CMD2 move to W3 and are transmitted in the 3V frame of FIG.

  As described above, the command is automatically transmitted with a delay of two frames. The number of delays is related to the number of command buffer stages (W1 to W3). If the number of stages is increased by 1 to 4, the delay is 3 frames, and if the number of stages is decreased by 1, the delay is 2 frames.

  Next, the specified delay type processing will be described with reference to FIGS. 55 and 56. FIG.

  In the designated delay type, instead of writing a command to the multistage buffer of FIG. 53, the address of the command storage unit is designated and read. FIG. 55 shows an example of a read table (corresponding to a command buffer) for that purpose. The table is taken out from the top (in the order of W1 to W5), and the command is read out accordingly. What is stored in the table is the address of the command storage unit. W1 is “101”, which indicates that a command having an address lower than 101 has not been read yet. Therefore, CMD1 and CMD2 are read out. Similarly, CMD3 is read by W2 “102”.

  Which data (address) of W1 to W5 in the read table is to be taken out is designated by a queue. The queue automatically moves to W2 after taking out, for example, W1 from the read table, but the timing follows the delay designation. That is, if delay designation = 0 frame, the data immediately moves to the next data in the read table, but if delay designation = 1 frame, 2 frames, the data moves to the next data in the read table after 1 frame and 2 frames respectively. .

  Data acquisition from the read table using a queue and command transmission will be described with reference to FIG.

  FIG. 56A shows a state where a queue is located at the first data W1 of the read table in order to start command transmission. Since W1 address = 101, CMD1 and CMD2 in FIG. 52 are read out as in the case of the automatic delay type. And it is transmitted immediately. This is equivalent to setting CMD1 and CMD2 in the 1V frame and transmitting CMD1 and CMD2 in the frame in the designated delay type of FIG.

  FIG. 56B shows a state in which a specified delay of 2 frames is received at the 2V frame in FIG. 51, and a queue is located at the next data W2 at the 4V frame that is the frame of the specified delay. As a result, CMD3 is read out and transmitted in the 4V frame.

  FIG. 56 (c) shows a state in which a specified delay of 2 frames is received at the 3V frame in FIG. 51, and the queue is located at the next data W3 at the 5V frame which is the frame of this specified delay. As a result, CMD4 to CMD6 are read and transmitted in the 5V frame. Since there is no designated delay for the next W4, the queue immediately moves to W4, and CMD7 is read and transmitted. In the example of FIG. 51, CMD7 is transmitted in the 5V frame.

  In FIG. 56D, since there is no designated delay for the next W5, the queue immediately moves to W5, and CMD8 and CMD9 are read and transmitted. In the example of FIG. 51, CMD8 and CMD9 are transmitted in the 6V frame.

  As described above, the command is transmitted at the designated timing in the designated delay type.

  FIG. 57 is a block diagram of a designated delay type transmission control unit.

  A command storage unit 2300 stores commands for each address as shown in FIG.

  Reference numeral 2301 denotes a read control unit that reads a command in response to a command registration request and sets a read timing in accordance with a delay designation. The reading control unit 2301 has a table as shown in FIG. 55, and designates which command is read to the command reading unit 2302 by an address. Also, the read control unit 2301 sets the timing for outputting the designation (queue) according to the delay designation.

  2302 reads a command based on an instruction from the read control unit 2301 and passes the command to the transmission unit (transmission shift register 2103 in FIG. 7). The operation of the read control unit 2301 has already been described with reference to FIG.

  According to the present embodiment, the command (audio data) is not written to the first-in first-out buffer, but the address where the command is stored is written, and control by this is realized using the queue. Since no buffer is used, the amount of delay can be arbitrarily specified, and flexible control can be realized.

<Power interruption processing>
By the way, the CPU which is the processing unit executes the power-off saving process in response to the input of a predetermined power-off notice signal when the power is turned off. This process includes a process for obtaining a checksum of data stored in a memory that does not lose data even when the power is turned off.

  The CPU sets the program execution address to a predetermined address by inputting a reset signal after turning on the power, reads the data stored in the memory that does not lose data even when the power is turned off, along with various initial settings, on the work memory normally used Initialization processing such as expanding to The two operations of the power-off saving process and the initialization process realize a backup of the state before the power is turned off and a return after the power is turned on based on the backup. In other words, when the gaming machine is turned on, it returns to the power-off state.

  FIG. 58 is a block diagram showing the relationship between the sub-board 20 and the power supply unit. The same applies to the main board 10.

  The PS is a power supply unit that receives an AC power supply (for example, AC 24 V) and generates a DC power supply.

  Processing related to the game executed on the sub-board 20 is executed by the CPU operating in accordance with a program stored in advance in the ROM. When performing the processing, the CPU stores various data in the first memory M1, reads as necessary, performs processing, and stores it again as necessary. Further, since the second memory M2 receives a battery backup from the backup power supply BAK, the stored contents are retained even during power-off. The backup power supply BAK is, for example, a rechargeable secondary battery.

  The first memory M1 is a memory (work memory) whose access speed is faster than that of the second memory M2, but data is not backed up when the power is turned off. The second memory M2 is a backupable memory (backup memory).

  In normal processing (processing other than power-off processing), the first memory M1 is basically used.

  At a predetermined timing, a predetermined one of the data in the first memory M1 is transferred to the second memory M2. Examples of this are listed below.

During the known setting process, data is stored in the first memory M1, and when the setting is confirmed, the data is transferred from the first memory M1 to the second memory M2.

When the sub board 20 receives a predetermined command from the main board 10, specific data corresponding thereto is transferred from the first memory M 1 to the second memory M 2.

Transfer predetermined data from the first memory M1 to the second memory M2 when the power is turned on.

  In addition, the second memory M2 may store a backup flag, a RAM checksum, and a flag relating to an illegal act (such as an illegal reset flag).

  When the power switch PSW is turned off from on, a power-off notice signal is output from the power supply unit PS. This signal gives an interrupt to the CPU, for example.

  Even if the power switch PSW is turned off from the on state, the power source voltage does not drop immediately, and after a while after the power switch PSW is turned off, the power source voltage becomes zero. Therefore, the CPU can perform certain processing after receiving the power-off signal and before stopping the operation due to the voltage drop.

  For example, when the power is turned on, the power-off notice signal is at the H level, but when it changes from the H level to the L level, it means that the power is cut off. When the AC input is turned off, the DC voltage is turned off, but the voltage does not immediately become zero due to components such as capacitors provided in the power supply unit and each circuit. For example, when the power supply voltage falls below a certain value (for example, when the DC24V output decreases to 18V), the power-off notice signal changes to L level (and it takes more time before DC5V is turned off).

  A voltage comparator (comparator) can be used as a circuit for generating a power-off notice signal. A battery with a desired voltage (for example, 18V) is prepared, and a power-off notice signal can be generated by comparing this voltage with the power supply voltage of DC24V. This type of circuit is well known and will not be described in detail. There is a commercially available dedicated IC for monitoring the power supply voltage, and it can be used.

  Or you may make it generate | occur | produce a power-off notice signal using the switch (or contact) linked with the power switch PSW.

  Although not shown, the gaming machine includes a power-on detection unit that detects power-on. This is, for example, a device (a switch or a contact that works in conjunction with the power switch) that detects when the power switch is on. Similarly to the power-off notice signal, it is possible to detect power-on using a voltage comparator (comparator). Alternatively, a commercially available dedicated IC for monitoring the power supply voltage may be used.

<Changing the priority of multiple processes when a power interruption occurs>
In the following description, the power interruption is referred to as “power interruption”, and the power interruption saving process is referred to as “power interruption process”.

  By the way, the recent sub-board 20 adopts a multi-process method in which one CPU executes a plurality of processes at the same time. The power interruption process when a plurality of processes are executed simultaneously is different from the power interruption process of one process, and must wait for the completion of all the processes. However, since the time for performing the power interruption process (backup) is limited as described above, the power interruption process may not be in time when waiting for the end of all the processes. In order to prioritize the power interruption process, the process being executed may be forcibly processed. However, the aborted process may become incomplete and may cause a problem. For this reason, in the sub board | substrate 20 which employ | adopts a multi-process system, it is necessary to perform the electrical disconnection process different from the conventional game machine.

  The principle of the power interruption process in the multi-process method will be described with reference to FIGS.

  For example, there are processing A, processing B,..., Processing Z in descending order of priority, and it is assumed that processing B and processing C access the backup target data (FIG. 59).

  Here, when a power interruption occurs during access to the backup target data in the processes B and C, it is necessary to immediately terminate the process and shift to a power interruption process. When process A having a higher priority than C interrupts, a delay occurs in the transition to the power interruption process.

  Therefore, the processing that does not access the backup target data when a power interruption occurs is changed to the lowest priority. For example, the priority of process A,..., Process Z other than process B and process C is lowered (FIG. 60). Lowering the priority means lowering the priority of process A,..., Process Z over the lower priority of process B and process C accessing the backup target data. However, the lowest priority (priority of processing Z) may be set easily. In addition, if the processes A,..., And the processes Z are not necessary at all after the occurrence of power interruption, the processes may be put into a dormant state (this is also included in lowering the priority). As a result, the processes B and C that access the backup target data are not interrupted by the processes A,...

  The process (process B and process C) for accessing the data to be backed up is monitored, changed to the lowest priority when the access is not being performed or when the access is completed, or the hibernation state is set. For example, the process B that has been accessed is put into a dormant state (FIG. 61). As a result, access to the backup target data does not occur again, and no delay occurs when shifting to the power interruption process.

  Then, when there is no processing being accessed (when the access of process C is completed), the process proceeds to the power interruption process.

  Note that a power interruption prohibition flag may be set in order to reliably prohibit power interruption during access. The power interruption prohibition flag is a flag that is referred to when the CPU starts power interruption processing. When this flag is set, the power interruption processing is not started (for example, after waiting for a predetermined time, and then again) Checking the flag is repeated). The power interruption prohibition flag is set by, for example, a power interruption notice signal, and is reset when there is no possibility of access to the backup target data (for example, it is reset when YES in S115 in FIG. 63). .

  FIG. 62 is a block diagram of the gaming machine for performing the above processing (only the portion related to the power interruption processing is shown). Each unit in the figure is a functional unit realized by the CPU executing a predetermined program (except for a backup target memory which is hardware such as an IC). For example, processing A,..., Processing Z does not mean a plurality of processing units (CPUs) but functionally expresses each of the multi-process processing realized by one CPU. Note that some or all of these units may be configured by hardware.

  Reference numeral 2400 denotes a memory that stores data related to games (flags related to winning determination / winning determination) and / or data related to the effects (flags related to effects, etc.). Since the contents of the memory 2400 are to be backed up, they are described as “backup target memory 2400”. There are memories (ROM, RAM) for storing other data, but the display thereof is omitted.

  Reference numeral 2401 denotes a power interruption processing unit that backs up data (such as various flags) in the backup target memory 2400 when power is interrupted. Since the processing content of the power interruption processing unit 2401 is known, the description thereof is omitted.

  2402 includes a priority changing unit 2402a that changes priorities of a plurality of processes A,..., And a process Z, and a process execution state monitoring unit that monitors execution states of the plurality of processes A,. 2402b, and after the execution of a predetermined process A, ..., process Z (process B and process C in the example of FIGS. 59 to 61) of the plurality of processes is completed, 2401 is a power interruption preprocessing unit that starts backup.

  Reference numeral 2403 denotes a power interruption processing activation unit that causes the power interruption front processing unit 2402 to start processing based on a predetermined signal (power interruption notice signal) from the power supply unit PS.

  The process execution state monitoring unit 2402b of the power interruption preprocessing unit 2402 examines the execution states of the plurality of processes A,..., Z based on the signal from the power interruption process activation unit 2403, and performs the plurality of processes. A process accessing the data to be backed up (hereinafter “first process”, processes B and C in FIGS. 59 to 61) and a process not accessing the data (hereinafter “second process”). ", Processing B and processing other than processing C).

  The priority changing unit 2402a sets the priority of the second process to be lower than the priority of the first process (the meaning of “low” has been described above).

  The process execution state monitoring unit 2402b monitors the first process to check whether or not the execution has been completed, and causes the power interruption processing unit 2410 to perform backup when the process is completed. When the first process includes a plurality of processes (process B and process C in FIGS. 59 to 61), when a part of the first process (process B) is completed, the priority of the part of the process is set. The priority is set lower than the priority of the remaining first process (process C), and when the entire execution of the first process is completed, the power interruption processing unit 2401 performs backup.

  The priority changing unit 2402a includes a priority table that holds a predetermined priority for each of a plurality of processes A,... When the priority of the second process is set lower than the priority of the first process, for example, it is set to the lowest one of the predetermined priorities (value lower than 26 of process Z = 27). . In this way, if the process Z is the first process, this can be prioritized. In FIG. 64, it is assumed that the smaller the numerical value, the higher the priority. Processing with priority = 1 is executed with the highest priority.

  FIG. 63 shows a processing flowchart of the apparatus shown in FIG. This process is activated by the power interruption process activation unit 2403.

S110: The process execution state monitoring unit 2402b recognizes a process that accesses the backup target memory 2400 (first process) and a process that does not access (second process).

  59 to 61, the first process = process B, process C, the second process = process A, process Z, and the like. The processes B and C that are accessing the backup target memory 2400 cannot be immediately terminated even if the power interruption notice signal is generated. If the process is terminated, the data (flag) to be backed up is not generated correctly.

S111: Based on the monitoring result of the process execution state monitoring unit 2402b, the priority changing unit 2402a makes the priority of the second process the lowest.

  The priority changing unit 2402a includes a priority table as shown in FIG. 64 (a) in advance. As shown in FIG. 6B, the priority of the second process (processes other than process B and process C) is set low (27 in this example). By doing so, as shown in FIG. 60, execution of processes other than process B and process C can be suppressed.

S112: The process execution status monitoring unit 2402b monitors the access status of the first process.

S113: When access to the backup target memory 2400 by any of the first processes is completed (YES), the process proceeds to S114.

S114: The priority changing unit 2402a sets the priority to the lowest for the first process for which access has been completed.

  In the example of FIG. 64C, the priority of process B is 27. As shown in FIG. 61, execution of subsequent processing for processing B can be suppressed.

S115: When all the first processes (process B, process C) are completed (YES), the power interruption process is started (S116), and if there is a remaining first process, S113 to S115 are repeated.

  In a conventional gaming machine, when a power interruption occurs, if data to be backed up is being processed, the power interruption process is delayed until the end of the process. On the other hand, if the same processing as before is performed in a multi-process environment in which multiple processes operate simultaneously, the data to be backed up will not be handled, but processing with higher priority may be interrupted. The delay time increases, and stable power interruption processing cannot be performed. On the other hand, according to the present embodiment, an increase in the delay time can be suppressed as much as possible, and a stable power interruption process can be performed.

  That is, according to the present embodiment, when the occurrence of a power interruption is detected, the process that does not access the data to be backed up is changed to a low priority or hibernation state, and the process to access the data to be backed up is also monitored. And the processing is changed to a low priority or a dormant state at a safe timing when data is not accessed. As a result, the processing related to the data to be backed up can be promptly terminated, and the data can be passed to the power interruption process without delay, and a stable power interruption process can be realized. The safe timing is a time when data to be backed up can be correctly generated and there is no problem even if the data is passed to the power interruption process. If the processing is terminated at a timing other than safe timing, there is a possibility that a problem such as inconsistency occurs in the generated data. Thereby, the time required for backup can be minimized, and stable power interruption processing can be performed.

<Process interruption reset when voltage is restored during power interruption (measures for instantaneous interruption)>
In multi-process processing, timer interruption is performed at predetermined intervals (for example, every 512 μs) in order to realize the parallel processing, and each processing (process) is started with a timer. This also applies to the power interruption saving process.

  The operation of the power interruption saving process in the multi-process process is generally as follows. A specific interrupt (NMI) is generated by a power-off notice signal (or a signal indicating a drop in power supply voltage), and a power-off flag (power-off flag) is set by processing corresponding to this. The interruption interruption process is activated by the timer interrupt, and the predetermined process as described above is performed. Then, after completing the power interruption saving process, the CPU enters a standby state (infinite loop state), where the power is completely turned off to stop the operation.

  In the power interruption saving process, for example, the power supply voltage is temporarily lowered due to noise or the like and a power interruption notice signal is generated, but the power supply voltage is restored after that (this is called instantaneous interruption) It needs to be possible. After completing the power interruption saving process, the CPU is in a standby state, and it is necessary to avoid the situation where it cannot be recovered from there.

  Note that in conventional gaming machines that are not multi-process processing, power-off saving processing is performed by interruption based on a power-off notice signal, and when power is restored, it can be restored by similar interruption processing. On the other hand, since each process is started by a timer interrupt in the multi-process process, a special measure against an instantaneous interruption is necessary.

  Further, in the multi-process process, a complicated procedure is required to return to the process immediately before the power-off save process after the power-off save process, and such a process is actually difficult.

  FIG. 65 shows a block diagram of an apparatus for returning a gaming machine to an operating state even when a so-called instantaneous interruption occurs under multi-process processing.

  The power interruption processing units 2401 and 2402 correspond to the power interruption processing unit 2401 and the power interruption preprocessing unit 2402 in FIG. In FIG. 65, 2401 and 2402 are shown as one block for easy viewing of the drawing. Although the notation of “electricity cutting pretreatment unit” is omitted, there is no problem in handling the electric power interruption processing unit 2401 and the electric interruption pretreatment unit 2402 as a unit in the processing of the apparatus of FIG. The power interruption processing activation unit 2403 is the same as that shown in FIG.

  2500 is a power interruption flag storage unit set / reset by the power interruption processing activation unit 2403. The power interruption flag is set, for example, when the power supply voltage is lowered, and is reset when the power supply voltage is restored. Alternatively, it is set when the power switch is turned off and reset when the power switch is turned on.

  An interrupt timer 2501 outputs an interrupt signal that triggers execution of a plurality of processes at a predetermined interval (for example, every 512 μs). Although there are a plurality of processes activated by the interrupt timer 2500, only the power interruption processing units 2401 and 2402 are shown in FIG.

  Reference numeral 2502 denotes a watchdog timer that outputs a reset signal when a predetermined operation is not performed.

  The watchdog timer is a device that detects abnormal computer operations (hangup, freeze, etc.). Exception handling is executed when a regular watchdog operation is not performed (timeout) due to an illegal state such as a hang-up. In exception handling, the system is often reset for the purpose of returning the hung-up system to normal operation, but there are also cases in which the system is forcibly stopped by turning off the power supply and that the system is turned on again after the power supply is turned off.

  For example, the CPU always performs a counting operation during the operation, and the watchdog operation is a process of clearing (resetting) the counter at a certain period. When the counter is not reset for some reason and reaches a predetermined value (overflow or the like), reset processing (exception processing) is performed.

  Reference numeral 2503 denotes a watchdog timer clear unit that resets the counter.

  The power interruption processing units 2401 and 2402 check the power interruption flag based on the output of the interrupt timer 2501, perform backup when the flag is set, and check the power interruption flag after completing the backup, When is set, the watchdog timer 2502 is reset, and when the power interruption flag is not set, reset is not performed.

FIG. 66 is a flowchart of the apparatus shown in FIG. This figure shows only the instantaneous interruption countermeasure processing portion.
67 and 68 are operation explanatory diagrams (timing charts) of the apparatus of FIG.

  The operation of the apparatus shown in FIG. 65 will be described below with reference to FIGS. 66 to 68.

  FIG. 67 (a) shows a case where the power supply is normally cut off without instantaneous interruption.

  When the voltage drops due to the power switch being turned off, the power interruption process starting unit 2403 sets the power interruption flag at time t1.

  The power interruption processing units 2401 and 2402 are activated by the interrupt timer 2501 at time t2, and the power interruption processing is started. This process is completed at time t3. Then, it will be in a standby state until operation stops.

  That is, the power interruption flag is checked (S121 in FIG. 66). In FIG. 67 (a), since the voltage continues to drop, the power interruption flag remains set (NO). The watchdog timer 2502 is cleared (S122). For this reason, the reset by the watchdog timer 2502 is not performed.

  While the processes of NO and S122 are repeated in S121, the voltage is sufficiently lowered at time t4 and the operation of the CPU is stopped.

  FIG. 67B shows a case where a very short interruption (for example, shorter than the interrupt timer period) has occurred.

  Although the voltage dropped at time t5 due to noise or the like, the voltage immediately recovered at time t6. The power interruption flag is set at time t5, but is reset at time t6. Since no timer interrupt has occurred between time t5 and t6, the power interruption processing units 2401 and 2402 are not activated.

  FIG. 68 shows a case where a momentary interruption that is long enough to activate the power interruption processing units 2401 and 2402 occurs. FIG. 4A shows a case where the instantaneous interruption is longer than the time required to complete the power interruption process, and FIG. 4B shows a case where the instantaneous interruption is shorter.

  In FIG. 68 (a), when the voltage drops for some reason, the power interruption processing activation unit 2403 sets the power interruption flag at time t1.

  The power interruption processing units 2401 and 2402 are activated by the interrupt timer 2501 at time t2, and the power interruption processing is started. This process is completed at time t3. Then, it will be in the standby state by NO of S121 and S122.

  When the voltage is restored for some reason, the power interruption flag set at time t1 is reset at time t7. In response, after time 8, YES in S121, an infinite loop is entered. The watchdog timer is not reset in S122.

  Therefore, a watchdog reset is performed at time t9, the CPU is restarted, and normal processing is performed.

  Similarly in FIG. 68 (b), the power interruption flag is reset at time t7 ′, and after time t8 ′, YES is obtained in S121, and an infinite loop is entered. Since the watchdog timer is not reset in S122, the watchdog is reset at time t9 ′, the CPU is restarted, and normal processing is performed.

  As described above, according to the present embodiment, the power interruption processing unit checks the power interruption flag after completing the backup, and resets the watchdog timer when the power interruption flag is set. Since the reset is not performed when the disconnection flag is not set, the reset can be automatically performed after the power is restored even when the backup is performed by an instantaneous disconnection. Therefore, hang-up and freezing of the gaming machine can be avoided, and the troublesome work of manually turning on / off the gaming machine can be eliminated.

  According to this embodiment, even when a so-called instantaneous interruption occurs under multi-process processing, the gaming machine can be returned to the operating state.

  69 and 70 are comparative examples. These do not have a watchdog timer and a watchdog timer clear section.

  In this comparative example, the process up to the power interruption process (backup) is the same, but then the standby state (infinite loop state) is entered. When the voltage is restored for some reason, the power interruption flag is reset at time t7, but is in an infinite loop state and is not reset. This causes hang-up and freeze.

<Suppression of processing when power interruption occurs>
Another embodiment will be described.
FIG. 71 shows a block diagram according to the present embodiment. This figure corresponds to FIG. 62, and the same or corresponding parts are denoted by the same reference numerals, and the description thereof is omitted.

  The process execution state monitoring unit 2042 is a process to be monitored (hereinafter, “communication process”) for communicating with an external device. In FIG. 71, processing A and processing B correspond to each other for convenience. The external devices are the liquid crystal control board 200, the speaker board 201, the LED board, the movable body control unit 60, and the like.

  In the communication process, a signal is sent from the sub-board 20 to the peripheral board (device) and controlled, and status information is received from the peripheral board. If a process to be backed up is in communication or is about to start communication when a power outage occurs, there is a risk of losing the communication content, so data backup cannot be performed normally and power outage is saved. Processing may be incomplete. This causes a wrinkle in the operation after the power is turned on again. In view of the above, by the apparatus configuration and processing procedure described below, a power interruption saving process is appropriately performed even for a process that is in communication or about to start communication so that the operation after the power is turned on again can be performed normally.

  Reference numeral 2402c denotes a time lag setting unit that sets a predetermined time lag for communication processing. The time lag is the time required for the communication process to start communication after attempting to start communication. In the example of FIG. 71, it is the time from the start of the communication protocol when the process A and the process B start communication to the time when the power interruption suppression flag is set. By setting the time lag, it is possible to perform a power interruption saving process immediately after the start of communication, and prevent communication data from being lost.

  A time-out error flag storage unit 2402d stores a time-out error flag indicating that the time for performing backup for communication processing is insufficient.

The processing performed by the CPU after receiving the power-off signal and before stopping the operation due to the voltage drop is as follows.
(Processing 1) The processing currently being executed is stopped or the end of the processing is awaited.
(Process 2) A power-off saving process is executed instead of the normal process.

  The total time of (Process 1) and (Process 2) must be shorter than “the time from when the power-off signal is received until the operation is stopped due to the voltage drop”.

  The time-out error flag is that (Process 1) is too long, so the total time of (Process 1) and (Process 2) is longer than the “time from when the power is cut off until the operation is stopped due to voltage drop”. This indicates that the backup may be incomplete. Processing related to the timeout error flag will be described later.

  Reference numerals 2600a and 2600b denote power interruption suppression flag storage units for storing a power interruption suppression flag for prohibiting (suppressing) the power interruption process since the communication process is performed. The power interruption suppression flag is set after the processes A and B start communication. There is a slight time delay from the start of the communication process to the setting of the power interruption suppression flag, which is shorter than the time lag. In other words, the time lag is set to be equal to or greater than the maximum value of the time delay.

72 is a flowchart of the apparatus shown in FIG. This figure shows only the communication processing countermeasure part.
73 to 75 are operation explanatory diagrams (timing charts) of the apparatus of FIG.

  The operation of the apparatus shown in FIG. 72 will be described below with reference to FIGS. 72 to 75.

  FIG. 73 shows a case where communication was not performed (a case where the power interruption suppression flag was not set) when the power interruption flag was set based on the output of the power interruption processing activation unit 2403.

  When the voltage drops due to the power switch being turned off, the power interruption process starting unit 2403 sets the power interruption flag at time t1.

  The time lag is set in the time lag setting unit 2402c (S130 in FIG. 72), and after a predetermined time has elapsed (NO in S131), the power interruption processing unit 2401 is activated at time t2 and the power interruption process is started ( NO in S132, S116). This process is completed at time t3. Then, it will be in a standby state until operation stops. For the power interruption process S116, refer to the above description.

  FIG. 74 shows a case in which communication is performed at the time when the power interruption flag is set based on the output of the power interruption processing activation unit 2403 (case where the power interruption suppression flag is set), and the power interruption suppression is performed. Indicates a case where the timeout error flag is set due to the time being too long.

  In FIG. 74, since the above-mentioned (Process 1) is too long, the total time of (Process 1) and (Process 2) is longer than the “time from when the power-off signal is received until the operation is stopped due to voltage drop” Longer, which can result in incomplete backups.

  When the voltage drops due to the power switch being turned off, the power interruption process starting unit 2403 sets the power interruption flag at time t1. At the same time, the power interruption preprocessing unit 2402 starts measuring time with a counter (not shown).

  The time lag is set in the time lag setting unit 2402c (S130 in FIG. 72), and after a predetermined time has elapsed (NO in S131), the power interruption flag is checked at time t2. Since the power interruption flag is set (YES in S132), instead of activating the power interruption processing unit 2401, timeout measurement (S133) and determination of occurrence of timeout (S134) are performed. Until the timeout occurs, the processes of S132, S133, and S134 are repeated.

  At time t10 when a predetermined time ΔT has elapsed, a timeout occurs (YES in S134), and a timeout error flag is set (S135). The time ΔT is set so that the total time of the above (Process 1) and (Process 2) is equal to or slightly shorter than “the time from when the power-off signal is received until the operation is stopped due to the voltage drop”. . For example, ΔT ≦ (the time from when the power-off signal is received until the operation is stopped due to the voltage drop) − (the time required for the power-off process).

  The power interruption process is started after the timeout error flag is set (S116). This process is completed at time t3. Then, it will be in a standby state until operation stops.

  In the case of FIG. 74, the power interruption process is started even during communication. Therefore, there is a risk of missing the communication content related to the communication processing. The timeout error flag warns about this. Since the power interruption process is normally performed, there is no problem in the return operation after the power is turned on again. However, it is desirable that the communication that was in the middle of the communication process is performed again from the beginning.

  FIG. 75 shows a case in which communication was performed at the time when the power interruption flag was set based on the output of the power interruption processing activation unit 2403 (a case where the power interruption suppression flag was set), and a timeout occurred. In this case, the timeout error flag is not set. Therefore, incomplete backup does not occur.

  When the voltage drops due to the power switch being turned off, the power interruption process starting unit 2403 sets the power interruption flag at time t1. At the same time, the power interruption preprocessing unit 2402 starts measuring time with a counter (not shown).

  The time lag is set in the time lag setting unit 2402c (S130 in FIG. 72), and after a predetermined time has elapsed (NO in S131), the power interruption flag is checked at time t2. Since the power interruption flag is set (YES in S132), instead of activating the power interruption processing unit 2401, timeout measurement (S133) and determination of occurrence of timeout (S134) are performed. The processes of S132, S133, and S134 are repeated.

  When the power interruption suppression flag is reset at time t20 before the predetermined time ΔT elapses (NO in S132), the power interruption process is started (S116). This process is completed at time t21. Then, it will be in a standby state until operation stops.

  In the case of FIG. 74, there is no possibility of missing the communication contents related to the communication processing. Therefore, there is no problem in the return operation after the power is turned on again.

  According to the present embodiment, since the power interruption process is performed after a predetermined time lag has elapsed since the power interruption flag was set, data related to communication is not missed. Since the power interruption process is not performed during the communication process, data related to the communication is not lost.

  Further, when the power interruption process is not in time during the communication process, it is possible to prevent the backup from causing a problem by giving priority to the power interruption process. With the timeout error flag indicating that, the influence of the communication processing can be reduced by performing some measures (reset, communication restart from the beginning, etc.) at the time of restart.

  As described above, according to the present embodiment, it is possible to appropriately perform the power-off saving process even for a process that is in communication or about to start communication, so that the operation after power-on can be normally performed. .

  Note that the above embodiment can be combined as appropriate. It is possible to combine all of the devices shown in FIGS. 62, 65, and 71, or some of them.

<Re-notification at power failure recovery using multiple pointers>
In the multi-process method used by the gaming machine according to the present embodiment and one CPU executing a plurality of processes at the same time, commands and data are exchanged between a plurality of processes (hereinafter referred to as “tasks”). ing. A “mailbox” is used for communication between the tasks. A mailbox performs communication between tasks by passing a message packet (hereinafter referred to as “message”) secured in a memory.

  Communication between tasks is performed between a user and a user (processing and processing) via an operating system (OS) kernel. The kernel is a core part of the OS, manages system resources, and exchanges hardware and software components.

  FIG. 76 shows the structure of a message. The message MES includes link information (kernel management part) QH with the next message and a message body MB. The message body MB includes a transmission source ID and a text. The transmission ID of the message body indicates the type of message, and is determined in advance, for example, command = 0 and data = 1. The body of the message body is managed by the user and includes the contents of commands and data. The body type and size vary depending on the sender.

  FIG. 77 is an explanatory diagram of a communication procedure between tasks. The flow of message transmission / reception is as follows.

(1) A transmission task (user layer) writes a predetermined message in a message buffer (memory) (not shown). In the example of FIG. 77, three messages M1, M2, and M3 are prepared and written to the message buffer. The addresses of the messages M1, M2, and M3 in the message buffer are 0x1000, 0x1004, and 0x1008, respectively. Command construction and write processing are executed by timer interruption.

(2) The message buffer address is sent to the kernel in the send task process. In the example of the figure, transmission is performed in the order of M1, M2, and M3. Only the queue header QH is transmitted here, and the message body MB is not transmitted.

(3) In the reception task process, the kernel transmits the message buffer address to the reception task (user layer). Transmission is performed in the order of M1, M2, and M3 so that the reception order is the same as the transmission order. This is controlled by the queue header QH, and the next message M2 is designated by the queue header of the message M1, and the next message M3 is designated by the queue header of the message M2, as shown in FIG.

(4) The reception task reads the message body MB from the message buffer according to the address received from the kernel, and performs analysis. For example, the message body of the message M1 is read based on the address = 0x1000. If the message transmission source ID = 0, the message body MB is analyzed as a command, and if the message transmission source ID = 1, the message body MB is determined to be data, and the parameters of the command read out earlier are used. If there is, analyze both together. In FIG. 77, for example, the message M1 is a command, and M2 and M3 are data.

  The above procedure will be described in detail based on a specific example.

  As shown in FIG. 78, eight messages M1 to M8 are written in the message buffer MBUF. In the interrupt process for performing writing, direct transmission / reception with the kernel is impossible due to the specification of the OS. For this reason, the address transmission to the kernel cannot be performed in the process (1), and (2) is separated from (1).

  In the present embodiment, the following three pointers are used to transmit a message via the message buffer MBUF.

WRITE pointer This is a pointer for writing the message buffer MBUF. It is updated when message body writing is completed by timer interruption. By updating, the above-mentioned (2) is pointed to the first message that has not been transmitted. Specifically, it indicates a head address such as 0x1000 in FIG.

SEND pointer This is a pointer for address transmission to the kernel. Updated when the sending task completes sending the address of the message buffer MBUF to the kernel. By updating, the first message that does not complete the above (3) is indicated.

READ pointer This is a pointer of the message buffer MBUF. It is updated when the message body MB is read from the message buffer MBUF based on the address received from the kernel by the reception task. By updating, the first message that does not complete the above (4) is indicated.

  FIG. 79 is a timing chart showing transmission / reception processing at normal time (when there is no power interruption). Reference numerals T101 to T106 respectively denote a processing completion point by the first timer interrupt (1) (○ 1), a completion point of the first transmission 1, a completion point of the first reception 1 (at this time, at least the message M1 from the message buffer MBUF And M2 are read, but the analysis is continuing), the processing completion time by the timer interrupt (4) (（4), the transmission 2 completion time, and the reception 2 completion time. An arrow connecting the timer interrupt, the transmission task, and the reception task indicates a process transition according to the priority order.

  FIG. 80 shows the states of the three pointers at timings T101 to T106 in FIG. 80 indicates an initial state not shown in FIG. 79. The pointer state is information about which message the pointer points to, and specifically, the address of the message buffer MBUF. In other words, the contents of the pointer are address data.

  With reference to FIG. 79 and FIG. 80, the transmission / reception processing at the normal time (when there is no power interruption) will be described.

T100: Initial state All three pointers indicate the first address. In this state, since the WRITE pointer is in the message buffer MBUF, the message M1 is not written.

T101: Timer interrupt A main command is registered in the message buffer MBUF by a timer interrupt. In this example, two messages M1 and M2 are written. At this completion, the WRITE pointer points to the next 0x1008 of M2. The remaining pointer points to 0x1000.

T102: Transmission task Passed to the queue headers QH of the messages M1 and M2 by the transmission task. Along with this, the SEND pointer moves to the same position as the WRITE pointer. As shown in FIG. 79, the priority of processing is timer interruption> transmission task> reception task, and therefore the transmission task is interrupted during the timer interruption (the reception task is the same). The reception task is started after the transmission task is completed.

T103: Reception task The reception task receives the information of the addresses of the messages M1 and M2 from the kernel, and reads the messages M1 and M2 from the message buffer MBUF based on the information. These are then analyzed. Accordingly, the READ pointer points to 0x1008 next to M2.

T104: Timer interrupt Message M3 is written by a timer interrupt. At this completion, the WRITE pointer points to the next 0x100C of M3. The remaining pointers will point to 0x1008.

T105: Transmission task Passed to the queue header QH of the message M3 by the transmission task. Along with this, the SEND pointer moves to the same position as the WRITE pointer.

T106: Reception task The reception task receives the address information of the message M3 from the kernel, and reads the message M3 from the message buffer MBUF based on this information. These are then analyzed. Accordingly, the READ pointer points to 0x100C next to M2.

  A command is transmitted from one task to another by the procedure described above.

  If power failure countermeasures are not taken into consideration, only the WRITE and READ pointers are required, and the SEND pointer is unnecessary. When the WRITE pointer and the READ pointer do not match, the queue header QH is passed to the kernel so that the READ pointer matches the WRITE pointer, and the message is read by the receiving task. However, a SEND pointer is necessary in order to prevent a command from being missed in the event of a power interruption.

  If the command disappears due to power interruption, there is a possibility that it may be disadvantageous to the player, so it is necessary to deal with power interruption processing. However, although the contents of the memory can be saved by the above-described backup, the queue header QH which is “link information with the next message” held by the kernel is lost. When the power is turned on again, the queue header QH is automatically initialized by the kernel. That is, if a power interruption occurs in a state where there are unread commands, some commands cannot be read. For example, if a power failure occurs at T102 in FIG. 79, the queue header QH of the messages M1 and M2 in the kernel is lost, so the messages M1 and M2 are skipped and read out in the receiving task after the power is turned on again. Can not be.

  In this embodiment, by using the SEND pointer, it is possible to avoid the command loss as described above.

  FIG. 81 is a block diagram of a message transmission / reception unit according to the present embodiment.

  Reference numeral 2700 denotes a transmission task which is processing on the transmission side.

  Reference numeral 2701 denotes a reception task which is processing on the reception side.

  Reference numeral 2702 denotes a kernel that performs processing related to transmission of a command from the transmission task 2700 to the reception task 2701.

  The transmission task 2700, the reception task 2701, and the kernel 2702 are functions realized by the CPU.

  Reference numeral 2703 denotes a pointer (register, memory) for storing the WRITE, SEND, and READ pointers.

  Reference numeral 2704 denotes a power interruption processing unit that backs up at least a part of data in a memory (for example, the memory 2400 in FIG. 62) when power is interrupted.

  Reference numeral 2705 denotes a return processing unit that performs a predetermined return process based on the backed up data when the power is turned on.

  Reference numeral 2706 denotes a backup (memory) that holds backup data. This corresponds to M2 in FIG.

  MBUF is a message buffer that stores messages. This stored content has already been described.

  FIG. 82 is a flowchart of the power interruption process according to the present embodiment (only the pointer backup portion is shown).

  FIG. 83 is a flowchart of the return process according to the present embodiment (only the pointer return process part is shown).

  FIG. 84 is a timing chart showing a transmission / reception process when there is a power interruption. Symbols T111 to T116 respectively indicate the time when the first timer interrupt (1) (◯ 1) is completed, the time when the first transmission 1 is completed (= immediately before power interruption), the time immediately after power interruption (after return processing), and the timer interrupt. (3) Indicates the time point when the processing according to (３3) is completed, the time point when transmission 2 is completed, and the time point when reception 2 is completed.

  FIG. 85 shows the states of the three pointers at timings T111 to T116 in FIG. 85 indicates an initial state that is not shown in FIG.

  With reference to FIGS. 81 to 85, transmission / reception processing when there is a power interruption will be described.

T110: Initial state All three pointers indicate the first address. In this state, since the WRITE pointer is in the message buffer MBUF, the message M1 is not written.

T111: Timer interrupt The transmission task 2700 writes a message in the message buffer MBUF according to the WRITE pointer and moves the WRITE pointer of the pointer 2703. In FIG. 84, the main command is registered in the message buffer MBUF by the timer interruption. In this example, two messages M1 and M2 are written. At this completion, the WRITE pointer points to the next 0x1008 of M2. The remaining pointer points to 0x1000.

T112: Transmission task The queue header QH of the messages M1 and M2 is passed to the kernel 2702 by the transmission task. Along with this, the SEND pointer moves to the same position as the WRITE pointer.
At this time or immediately after that, a power interruption occurs, and the three pointers WRITE, SEND, and READ are backed up by the power interruption process described above (S140 in FIG. 82).

T113: Return processing When the power is turned on again, the queue header QH of the message is automatically initialized by the kernel at the time of return. For this reason, if there is an unread command (M1 and M2 in the example of FIG. 84) as described above, the received task cannot read these commands unless some measure is taken. Therefore, the return processing unit 2705 performs the process of FIG.

S150: Check whether the WRITE pointer and the READ pointer match.
If they match (YES in S150), the queue header QH has not been lost in the kernel, so the process of FIG. 83 is skipped and another return process is performed.
If they do not match (NO in S150), the process of S151 is performed.

S151: Return the SEND pointer to the position of the READ pointer.
If they do not match, it is determined that there is an unread command in the message buffer MBUF, and the SEND pointer is returned to the position of the READ pointer.

S152: The commands M1 and M2 in which the queue header QH has been lost in the kernel are retransmitted from the transmission task to the reception task.
At this point, the READ pointer and the SEND pointer point to the leading 0x1000.

T114: Timer interrupt Message M3 is written by the timer interrupt. At this completion, the WRITE pointer points to the next 0x100C of M3. The remaining pointers still point to 0x1000.

T115: Transmission task The queue header QH of the messages M1, M2, and M3 is passed to the kernel by the transmission task. Along with this, the SEND pointer moves to the same position as the WRITE pointer.

T116: Reception task The reception task 2701 reads the message from the message buffer MBUF according to the READ pointer and moves the READ pointer of the pointer 2703. The reception task receives the address information of the messages M1, M2, and M3 from the kernel, and reads the messages M1, M2, and M3 from the message buffer MBUF based on the information. These are then analyzed. Accordingly, the READ pointer points to 0x100C next to M2.

  According to the present embodiment, a SEND pointer indicating a transmission request (queue header) to the kernel that mediates message transmission from the transmission task to the reception task, together with a WRITE pointer indicating command writing and a READ pointer indicating command reading. Can be used to back up these three pointers in the event of a power failure, and return the SEND pointer to the position of the READ pointer when power is restored. . Therefore, even if the queue header, which is link information with the next message, disappears due to automatic initialization of the kernel when power is restored, the buffer address of the unread command is retransmitted, so the command is not missed. .

  The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say.

2400 Memory to be backed up 2401 Power-off processing unit 2402 Power-off pre-processing unit 2402a Priority change unit 2402b Process execution state monitoring unit 2403 Power-off processing activation unit

Claims (1)

In a gaming machine comprising a control unit that performs processing related to a game, and a power supply unit that supplies power to the control unit,
A memory for storing data relating to the game;
In the event of a power interruption, a power interruption processing unit that backs up at least part of the data in the memory;
An electrical disconnection pre-processing unit that starts backup in the electrical disconnection processing unit after execution of a communication process that communicates with a predetermined device is a process related to the game,
The power interruption preprocessing unit waits from a start based on a predetermined signal from the power supply unit to a lapse of a predetermined time lag for the communication processing, and after that time, backup to the power interruption processing unit Start,
The communication process sets a power interruption suppression flag for suppressing power interruption processing by the power interruption processing unit when starting communication, and resets the power interruption suppression flag when ending communication,
The gaming machine according to claim 1, wherein the time lag is set longer than a time from the start of communication by the communication process to the setting of the power interruption suppression flag.

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