JP2017098428A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a stress caused by a wiring layer.SOLUTION: According to one embodiment, a semiconductor memory includes a substrate, and a laminate. The laminate is provided in a first direction in parallel in a flat surface parallel to the substrate, and is extended to a second direction orthogonal to the first direction. A plurality of conductors are laminated and formed through an insulation layer on the substrate. The conductor includes at least a first conductor layer applying a tensile stress to the substrate and a second conductor layer applying a compression stress to the substrate. The second conductor layer is laminated and formed on the first conductor layer, or the second conductor layer is laminated and formed on the first conductor layer.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  A semiconductor memory device is manufactured using a semiconductor wafer process. Increasing the capacity, lowering power consumption, and reducing the cost of semiconductor memory devices has been realized with the progress of two-dimensional miniaturization technology in the wafer process.

  Further microfabrication requires an enormous capital investment than ever before. In addition, the miniaturization limit of transistors has been pointed out. For this reason, development of a nonvolatile semiconductor memory device including a three-dimensional memory cell array in which a plurality of memory cells are stacked in the vertical direction is being promoted in various fields.

  In order to increase the capacity of a three-dimensional memory cell array, it is necessary to greatly increase the number of wiring layers such as word lines. For the wiring layer, a metal film or metal silicide film having a resistance lower than that of the polycrystalline silicon film is used in order to reduce the wiring resistance. Since the metal film and the metal silicide film have different Young's moduli from the semiconductor substrate of the semiconductor memory device, when the number of wiring layers is increased, a tensile stress or a compressive stress exceeding a predetermined value is generated on the wafer. When tensile stress or compressive stress is generated, the amount of warpage of the wafer is increased, and manufacturing process troubles including misalignment and wafer alignment errors occur, leading to a decrease in yield.

US Patent Application Publication No. 2015/0055413 Japanese Patent Laying-Open No. 2015-153449

  An embodiment of the present invention is to provide a semiconductor memory device that can relieve stress generated by a wiring layer.

  According to one embodiment, the semiconductor memory device includes a substrate and a stacked body. The stacked body is arranged in parallel in the first direction in a plane parallel to the substrate, extends in a second direction perpendicular to the first direction, and a plurality of stacked conductors are formed on the substrate via an insulating layer. . The conductor has at least a first conductive layer that applies tensile stress to the substrate and a second conductive layer that applies compressive stress to the substrate, and the second conductive layer is laminated on the first conductive layer. A second conductive layer is stacked on one conductive layer.

1 is a cross-sectional view showing a semiconductor memory device according to a first embodiment. 1 is a cross-sectional view showing a semiconductor memory device according to a first embodiment. 1 is a cross-sectional view showing a memory cell array according to a first embodiment. FIG. 4 (a) is a diagram illustrating a laminated structure of a substrate and a film, FIG. 4 (b) is a diagram illustrating a case where tensile stress is generated, and FIG. 4 (c) is a diagram illustrating compressive stress. It is a figure which shows a case. It is a figure which shows the relationship between the Young's modulus of silicon and various metals. It is a figure which shows the relationship between the work function of a silicon | silicone and various metals. Sectional drawing which shows the memory cell transistor of the modification concerning 1st Embodiment, Fig.7 (a) is a 1st modification, FIG.7 (b) is a 2nd modification. It is sectional drawing which shows the memory cell transistor of the 3rd modification based on 1st Embodiment. It is sectional drawing which shows the memory cell transistor of the 4th modification based on 1st Embodiment. It is sectional drawing which shows the memory cell transistor of the 5th modification based on 1st Embodiment. 6 is a cross-sectional view showing a manufacturing process of the semiconductor memory device according to the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor memory device according to the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor memory device according to the first embodiment. FIG. It is a figure which shows the relationship between the number of metal lamination | stacking which concerns on 1st Embodiment, and wafer curvature. It is sectional drawing which shows the semiconductor memory device which concerns on 2nd Embodiment. It is sectional drawing which shows the semiconductor memory device which concerns on 2nd Embodiment. It is sectional drawing which shows the memory cell array concerning 2nd Embodiment. It is sectional drawing which shows the resistance change element of the 6th modification based on 2nd Embodiment. It is sectional drawing which shows the resistance change element of the 7th modification based on 2nd Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. The same parts in the drawings are denoted by the same reference numerals, detailed description thereof will be omitted as appropriate, and different parts will be described. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as the actual ones. Even when the same portion is shown, the dimensions and ratios may be differently shown in the drawings.

(First embodiment)
First, the semiconductor memory device according to the first embodiment will be described with reference to the drawings. 1 and 2 are cross-sectional views showing a semiconductor memory device. FIG. 3 is a cross-sectional view showing the memory cell array.

  In this embodiment, a first conductive layer that applies tensile stress to a substrate and a second conductive layer that applies compressive stress to a substrate are stacked on a conductor used for a word line or the like, and the generated stress is reduced. Suppressed.

  As shown in FIGS. 1 and 2, the semiconductor memory device 100 is, for example, a NAND flash memory, and includes a memory cell array MCA having a three-dimensional structure. In the semiconductor memory device 100, a stacked body 60 in which a plurality of conductors 5 are formed through the insulating layer 4 and a conductor 6 is formed over the conductor 5 through the insulating layer 4 is provided on the substrate 1. . A memory cell array MCA is formed in the region of the stacked body 60. The conductor 5 is used as the word line wiring and the gate electrode of the memory cell transistor, and the conductor 6 is used as the selection gate wiring and the selection gate electrode of the selection transistor.

  Here, FIG. 1 shows a cross section perpendicular to the word lines of the memory cell array MCA, and FIG. 2 shows a cross section parallel to the extending direction of the word lines.

  In the description of the present embodiment, the first direction in a plane parallel to the substrate 1 is the X direction, and the second direction orthogonal to the X direction is the Y direction in the same plane. A direction perpendicular to the X direction and the Y direction and perpendicular to the substrate 1 is defined as a Z direction.

  As shown in FIG. 1, the insulating layer 2 is provided on the substrate 1. As the substrate 1, for example, a silicon substrate is used. The conductive layer 3 is provided on the insulating layer 2. The stacked body 60 is provided on the conductive layer 3. The insulating layer 14 reaches the lowermost insulating layer 4 of the stacked body 60 and penetrates the insulating layer 7, the conductor 6, and the plurality of insulating layers 4 and the conductor 5. The insulating layer 15 reaches the uppermost insulating layer 4 of the stacked body 60 and penetrates the insulating layer 7 and the conductor 6.

  The NAND strings 70 have a U-shaped structure. The NAND strings 70 reach the conductive layer 3 and penetrate the insulating layer 7 and the stacked body 60. The NAND string 70 includes a semiconductor layer 11 a, a semiconductor layer 11 b, a coupling portion 12, and a memory layer 13. The semiconductor layer 11 on the left side in the drawing shown as the semiconductor layer 11 a and the semiconductor layer 11 on the right side in the drawing shown as the semiconductor layer 11 b reach the conductive layer 3 and penetrate the insulating layer 7 and the stacked body 60. The connection part 12 connects the bottom part of the semiconductor layer 11a and the bottom part of the semiconductor layer 11b. A memory layer 13 is provided on the outer periphery of the semiconductor layer 11 a, the semiconductor layer 11 b, and the connecting portion 12.

  An insulating layer 8 and an insulating layer 9 are provided on the stacked body 60. A bit line 18 is provided in the insulating layer 9. The bit line 18 and the semiconductor layer 11 b are connected via the contact plug 16 and the contact plug 20. A source line 17 is provided on the surface of the insulating layer 8. The source line 17 and the semiconductor layer 11a are connected through a contact plug 20. A pad electrode 19 is provided on the insulating layer 8.

  As shown in FIG. 2, the memory cell array MCA has a semiconductor pillar 80 composed of a semiconductor layer 11 and a memory layer 13 at the center, and a terrace portion (step) at the end of the word line extending direction (word line drawing direction). Part). The semiconductor pillar 80 reaches the conductive layer 3 and penetrates the insulating layer 7 and the stacked body 60. A wiring 24 is provided on the surface of the insulating layer 8 in the terrace portion (step portion). The wiring 24 and the conductor 5 in the terrace portion (step portion) are connected via a contact plug 23. The pad electrode 19 and the wiring 24 are connected via a contact plug 25, a wiring 26, and a contact plug 28.

  The stacked body 60 is juxtaposed in the first direction (X direction) in a plane parallel to the substrate 1 and extends in a second direction (Y direction) orthogonal to the first direction (X direction). A conductor is laminated on the insulating layer 4 therebetween.

  Here, for the insulating layer 2, the insulating layer 4, the insulating layer 7, the insulating layer 14, and the insulating layer 15, for example, a silicon oxide film is used. The conductive layer 3 functions as a back gate, and for example, silicon or polycrystalline silicon is used. For example, polycrystalline silicon or amorphous silicon is used for the semiconductor layer 11. As the memory layer 13, for example, a laminated film in which three layers of silicon oxide film / silicon nitride film / silicon oxide film are laminated is used.

  As shown in FIG. 3, the conductor 5 of the memory cell array MCA has at least two conductive layers. For example, the conductor 5 is formed by stacking a conductive layer 31 (first conductive layer) and a conductive layer 32 (second conductive layer). The conductor 6 of the memory cell array MCA has at least two conductive layers. For example, the conductor 6 is formed by laminating a conductive layer 31 (first conductive layer) and a conductive layer 32 (second conductive layer). The conductive layer 31 applies tensile stress to the substrate 1, for example. The conductive layer 32 provided on the conductive layer 31 applies compressive stress to the substrate 1, for example.

  The conductor 5 (the conductive layer 31 and the conductive layer 32), the memory layer 13, and the semiconductor layer 11 constitute a memory cell transistor MCT. The conductor 5 (conductive layers 31 and 32) functions as a gate electrode, the memory layer 13 functions as a gate insulating film, and the semiconductor layer 11 functions as a source, a channel portion, and a drain. The memory cell transistors MCT are formed in multiple stages in a third direction (Z direction) perpendicular to the substrate 1.

  The conductor 6 (the conductive layer 31 and the conductive layer 32), the memory layer 13, and the semiconductor layer 11 constitute a selection transistor SGT. The conductor 6 (conductive layers 31 and 32) functions as a selection gate electrode, the memory layer 13 functions as a gate insulating film, and the semiconductor layer 11 functions as a source, a channel portion, and a drain.

  Since the conductor 5 (conductive layer 31 and conductive layer 32) as the gate electrode and the conductor 6 (conductive layer 31 and conductive layer 32) as the selection gate electrode are also used as wiring, a low-resistance material is used. Is preferred. In this embodiment, the conductive layer 31 and the conductive layer 32 are made of a metal or metal silicide having a resistance lower than that of polycrystalline silicon. The conductor 5 is used as the word line wiring and the gate electrode of the memory cell transistor, and the conductor 6 is used as the selection gate wiring and the selection gate electrode.

  Next, the generation of stress in the laminated film will be described with reference to FIG. FIG. 4A is a diagram showing a laminated structure of a substrate and a film. FIG. 4B is a diagram illustrating a case where tensile stress is generated in the laminated film. FIG. 4C is a diagram illustrating a case where compressive stress is generated in the laminated film.

The stress generated in the laminated film of the substrate 41 and the film 42 formed on the substrate 41 shown in FIG. If the physical properties of the substrate 41 and the film 42 are different, the laminated film is curved and a stress σ is applied to the substrate 41. Specifically, the stress σ is
σ = (ED ² ) / {6 (1-V) R × t} (1)
It is represented by Here, E is Young's modulus, V is Poisson's ratio, D is the film thickness of the substrate 41, R is the radius of curvature, and t is the film thickness of the film 42. Expression (1) is an expression that is established under the condition of t << D. P. Muraka (SILICIDES FOR VLSI APPLICATIONS, 1983, Academic Press, page 64, formula (19)).

  Here, the Young's modulus of the substrate 41 is E1, and the Young's modulus of the film 42 is E2. When E1> E2, the tensile stress (TENSILE STRESS) is applied to the substrate 41 because the lateral extension of the film 42 is small as shown in FIG. 4B. In the case of E1 <E2, as shown in FIG. 4C, the lateral extension of the film 42 is large, so that a compressive stress (COMPRESSIVE STRESS) is applied to the substrate 41.

  Next, characteristics of silicon used for the substrate 1 of the present embodiment and various metals used for the conductive layer 31 and the conductive layer 32 will be described with reference to FIGS. FIG. 5 is a diagram showing the relationship between the Young's modulus of silicon and various metals. FIG. 6 is a diagram showing the relationship between the work functions of silicon and various metals.

  As shown in FIG. 5, metals that have a small Young's modulus relative to silicon and apply tensile pressure to silicon as a substrate include vanadium (V), copper (Cu), titanium (Ti), silver (Ag), and hafnium (Hf). ), Gold (Au), aluminum (Al), and the like. Note that metal silicides made of these metals also apply a tensile pressure to silicon as a substrate.

  Metals that give compressive stress to silicon as a substrate include tantalum (Ta), cobalt (Co), iron (Fe), beryllium (Be), molybdenum (Mo), tungsten (W), osmium (Os), and the like. In addition, the metal silicide which consists of these metals similarly applies a compression pressure to the silicon as a substrate.

  As shown in FIG. 6, the metal having a work function smaller than that of silicon is, for example, hafnium (Hf). Hafnium silicide also has a lower work function than silicon.

  Metals having a larger work function than silicon are aluminum (Al), titanium (Ti), tantalum (Ta), copper (Cu), silver (Ag), vanadium (V), cobalt (Co), and molybdenum (Mo). , Tungsten (W), gold (Au), iron (Fe), osmium (Os), beryllium (Be), and the like. Note that metal silicides made of these metals also have a work function larger than that of silicon.

  Here, the conductive layer 31 and the conductive layer 32 (shown in FIG. 3) function as a gate electrode of the memory cell transistor MCT and a selection gate electrode of the selection transistor SGT. For this reason, in this embodiment, for example, the metal used for the conductive layer 31 is a first metal that applies a tensile pressure to silicon, the metal used for the conductive layer 32 is a second metal that applies compressive pressure to silicon, and the first metal and the first metal It is preferable to select a metal having substantially the same work function of the two metals. The metal used for the conductive layer 31 may be a first metal that applies compression pressure to silicon, and the metal used for the conductive layer 32 may be a second metal that applies tensile pressure to silicon. Increasing the difference between the first metal and the second metal work function is not preferable because the characteristics (for example, threshold voltage) of the conductive layer 31 and the conductive layer 32 are greatly different.

  With reference to the above-described fact and FIGS. 5 and 6, in this embodiment, for example, vanadium (V) is selected for the conductive layer 31 and cobalt (Co) is selected for the conductive layer 32. Vanadium (V) has a Young's modulus of 128 (GPa) and a work function of 4.44 (eV). Cobalt (Co) has a Young's modulus of 209 (GPa) and a work function of 4.45 (eV). Silicon (when the plane orientation is <100>) has a Young's modulus of 150 (GPa) and a work function of 4.05 (eV).

  Here, when the work function of the metal used for the conductive layer 31 and the work function of the metal used for the conductive layer 32 are different (for example, when titanium (Ti) is used for the conductor 31 and tungsten (W) is used for the conductor 32). As in the first modification shown in FIG. 7A, the conductor 5a in contact with the memory layer 13 of the memory cell transistor MCT may be changed.

  Titanium (Ti) has a Young's modulus of 110 (GPa) and a work function of 4.14 (eV). Tungsten (W) has a Young's modulus of 410 (GPa) and a work function of 4.52 (eV). Although not shown, the selection transistor SGT has the same structure. Specifically, the conductive layer 32 in contact with the memory layer 13 is replaced with a conductive layer 31a (same titanium (Ti) as the conductive layer 31). The conductive layer 32 does not contact the memory layer 13. The conductive layer 31 and the conductive layer 31 a are in contact with the memory layer 13.

  Further, as in the second modified example shown in FIG. 7B, the conductor 5b in contact with the memory layer 13 of the memory cell transistor MCT may be changed. Although not shown, the selection transistor SGT has the same structure. Specifically, the conductive layer 32 in contact with the memory layer 13 is replaced with the insulating layer 4. The conductive layer 32 does not contact the memory layer 13. The conductive layer 31 is in contact with the memory layer 13.

  A barrier film 33 may be provided between the conductor 5 and the insulating layer 4 as in the third modification shown in FIG. By providing the barrier film 33, outward diffusion of the metal used for the conductive layer 31 and the conductive layer 32 can be suppressed.

  As in the fourth modified example shown in FIG. 9, the conductor 5c in contact with the memory layer 13 of the memory cell transistor MCT may be changed. Although not shown, the selection transistor SGT has the same structure. Specifically, a barrier film 34 may be provided between the conductor 31 and the conductor 32. By providing the barrier film 34, diffusion from the conductive layer 31 to the conductive layer 32 and diffusion from the conductive layer 32 to the conductive layer 31 can be suppressed.

  As in the fifth modification shown in FIG. 10, the conductor 5 d in contact with the memory layer 13 of the memory cell transistor MCT may be changed. Although not shown, the selection transistor SGT has the same structure. Specifically, the conductor 5d has a three-layer structure of conductor 35 / conductor 32 / conductor 31. As the conductor 35, a metal or metal silicide that applies tensile stress, or a metal or metal silicide that applies compressive stress is used.

  Next, a method for manufacturing a semiconductor memory device will be described with reference to FIGS. 11 to 13 are cross-sectional views showing the manufacturing process of the semiconductor memory device.

As shown in FIG. 11, an insulating film 2 is formed on the substrate 1. A conductive layer 3 is formed on the insulating film 2. An insulating layer 50 (which becomes the connecting portion 12 portion) is selectively embedded in the surface of the conductive layer 3. For example, a silicon nitride film (Si ₃ N ₄ ) formed using a CVD (Chemical Vapor Deposition) method is used for the insulating layer 50. An insulating layer 4 is formed on the conductive layer 3 and the insulating layer 50. A conductor 5 including a conductive layer 31 and a conductive layer 32 is formed on the insulating layer 4. Specifically, the conductive layer 31 made of vanadium (V) and the conductive layer 32 made of cobalt (Co) are formed by sputtering, ALD (Atomic Layer Deposition), or MOCVD (Metal Organic Chemical Vapor Deposition). To do.

  As shown in FIG. 12, a plurality of conductors 5 are formed to be stacked via the insulating layer 4, and a stacked body 60 in which the conductor 6 is formed on the insulating layer 4 is formed. The conductor 6 is formed by a method similar to that for the conductor 5. An insulating layer 7 is formed on the stacked body 60. After the insulating layer 7 is formed, the groove 51 and the groove 52 are formed by using, for example, the RIE (Reactive Ion Etching) method using the mask material as a mask. The groove 51 is a deep groove reaching the surface of the lowermost insulating layer 4 of the stacked body 60. The groove 52 is a shallow groove reaching the surface of the uppermost insulating layer 4 of the stacked body 60. Mask material removal and RIE post processing (not shown) are performed.

  As shown in FIG. 13, the insulating layer 14 is embedded in the groove 51, and the insulating layer 15 is embedded in the groove 52. After the insulating layer 14 and the insulating layer 15 are formed, a groove 53 reaching the insulating layer 50 is formed by using the mask material as a mask and using the RIE method. After the groove 53 is formed, the insulating layer 50 is selectively removed to extend in the lateral direction, and a groove 54 connected to the groove 53 is formed.

  In addition, illustration and description are omitted for the subsequent formation including the formation of the memory layer 13 and the semiconductor layer 11.

  In the present embodiment, the laminated metal is also used for the selection gate wiring and the selection gate electrode, but the present invention is not necessarily limited thereto. A laminated metal may be used only for the word line wiring and the gate electrode of the memory cell transistor. A laminated metal may be used for the source line 17 and the bit line 18.

  Next, the characteristics of the semiconductor memory device 100 of this embodiment using a laminated metal and the semiconductor memory device of a conventional example using a single layer metal will be described with reference to FIG. FIG. 14 is a diagram illustrating the relationship between the number of metal stacks and wafer warpage.

  As shown in FIG. 14, in the conventional example 1 using only the word line wiring, the gate electrode of the memory cell transistor, the selection gate wiring, and the metal that applies compressive stress to the selection gate electrode, as the number of stacked metal layers increases (+ ) Wafer warpage in the direction increases rapidly. In Conventional Example 2 using only the metal that gives tensile stress to the word line wiring, the gate electrode of the memory cell transistor, the selection gate wiring, and the selection gate electrode, the wafer warpage in the (−) direction increases rapidly as the number of metal stacks increases. To do. For example, when the amount of warpage of the wafer exceeds a predetermined value, problems in the manufacturing process such as an increase in misalignment, occurrence of a wafer alignment error, and an increase in film thickness variation of the insulating film increase rapidly.

  On the other hand, in the semiconductor memory device 100 of this embodiment using a laminated metal, the stress generated by using a metal that applies compressive stress and a metal that applies tensile stress is greatly suppressed. Specifically, the upper limit wafer warp (in the + direction) and the lower limit wafer warp (in the − direction) are very small values as compared with the first and second examples. As a result, even if the number of metal stacks increases, the amount of wafer warpage can be significantly suppressed. Misalignment, wafer alignment error, film thickness variation of insulating film, etc. can be greatly reduced.

  As described above, in the semiconductor memory device of the present embodiment, a stacked body 60 in which a plurality of conductors 5 are formed via the insulating layer 4 and the conductor 6 is formed on the conductor 5 via the insulating layer 4. Is provided on the substrate 1. A memory cell array MCA is formed in the region of the stacked body 60. The conductor 5 and the conductor 6 are formed by laminating a conductive layer 31 and a conductive layer 32. For the conductive layer 31, a metal that applies a tensile pressure is used. For the conductive layer 32, a metal that applies a compression pressure is used.

  For this reason, the stress with respect to the board | substrate 1 can be suppressed. Since the warpage of the wafer can be greatly reduced, the yield of the semiconductor memory device 100 can be improved.

  In the present embodiment, the semiconductor memory device 100 includes the NAND string 70 having a U-shaped structure, but the present invention is not necessarily limited thereto. For example, the present invention may be applied to a semiconductor memory device having a memory cell composed of a single semiconductor pillar without providing the connecting portion 12.

(Second Embodiment)
Next, a semiconductor memory device according to a second embodiment will be described with reference to the drawings. 15 and 16 are cross-sectional views showing the semiconductor memory device. FIG. 17 is a cross-sectional view showing a memory cell array.

  In this embodiment, the first conductive layer that applies tensile stress to the substrate and the second conductive layer that applies compressive stress to the substrate are stacked on the conductor used for the word line to suppress the generated stress. doing.

  As shown in FIGS. 15 and 16, the semiconductor memory device 300 is a ReRAM (Resistive RAM) using a resistance change element as a memory, and includes a memory cell array MCA having a three-dimensional structure. In the semiconductor memory device 300, a stacked body 260 in which a plurality of conductors 210 are stacked through an insulating layer 209 is provided over the substrate 201. A memory cell array MCA is formed in the region of the stacked body 260. The conductor 209 is used as a word line wiring.

  Here, FIG. 15 shows a cross section perpendicular to the word lines of the memory cell array MCA, and FIG. 16 shows a cross section parallel to the extending direction of the word lines.

  In the description of the present embodiment, the first direction in a plane parallel to the substrate 201 is the X direction, and the second direction orthogonal to the X direction is the Y direction in the same plane. A direction perpendicular to the X direction and the Y direction and perpendicular to the substrate 201 is defined as a Z direction.

As shown in FIGS. 15 and 16, the insulating layer 202 is provided on the substrate 201. As the substrate 201, for example, a silicon substrate is used. An insulating layer 204, a conductive layer 205, and an insulating layer 206 are stacked over the conductive layer 203. A semiconductor layer 207 is provided so as to penetrate the insulating layer 204, the conductive layer 205, and the insulating layer 206. A gate insulating film 208 is provided on the outer periphery of the semiconductor layer 207. The semiconductor layer 207 is formed by stacking an N ⁺ semiconductor layer 207a, a P ⁺ semiconductor layer 207b, and an N ⁺ semiconductor layer 207c.

The conductive layer 205, the gate insulating film 208, the N ⁺ semiconductor layer 207a, the P ⁺ semiconductor layer 207b, and the N ⁺ semiconductor layer 207c constitute the selection transistor SGT. The conductive layer 205 functions as a gate electrode. The N ⁺ semiconductor layer 207a and the N ⁺ semiconductor layer 207c function as a source or a drain. The P ⁺ semiconductor layer 207b functions as a channel portion.

  The memory cell array MCA includes a semiconductor pillar 280 including a conductive layer 211 and a resistance change film 112. The semiconductor pillar 280 penetrates the stacked body 260. The resistance change film 112 is provided between the stacked body 260 and the conductive layer 211.

Here, as the insulating layer 202, the insulating layer 204, the insulating layer 206, and the insulating layer 209, for example, a silicon oxide film is used. The conductive layer 3 functions as a global bit line, and for example, silicon, polycrystalline silicon, or metal is used. The conductive layer 211 functions as a vertical bit line, and for example, polycrystalline silicon, amorphous silicon, or metal is used. Variable resistance film 112, for example, a metal oxide _{(HfO ×, Al 2 O ×} , TiO ×, NiO ×, WO ×, Ta 2 O × etc.) or a silicon oxide film is used.

  As shown in FIG. 17, the conductor 210 of the memory cell array MCA has a conductive layer made of at least two metals or metal silicides. The conductor 210 includes, for example, a conductive layer 231 (first conductive layer), a conductive layer 232 (second conductive layer), and a conductive layer 231 a made of the same material as the conductive layer 231. A conductive layer 232 is provided over the conductive layer 231. A conductive film 231a (the same material as the conductive film 231) is provided over an end portion of the conductive layer 231 (a portion in contact with the resistance change film 212).

  The conductive layer 211, the resistance change film 212, the conductive layer 231, the conductive layer 232, and the conductive film 231a function as the resistance change element RCE. The ends of the conductive layer 231 and the conductive film 231 a are in contact with the resistance change film 212.

  Here, for the conductive layer 231 and the conductive layer 231a, for example, a metal (first metal) that applies a tensile pressure to silicon is used. For the conductive layer 23, for example, a metal (first metal) that applies compressive pressure to silicon is used. Note that the metal used for the conductive layer 231 and the conductive layer 231a may be a first metal that applies compression pressure to silicon, and the metal used for the conductive layer 232 may be a second metal that applies tensile force to silicon.

  Metals that can be used for the conductive layer 231 and the conductive layer 231a, have a Young's modulus small to silicon, apply tensile pressure to silicon as a substrate, and can also be used as an ion source, include copper (Cu), titanium (Ti), silver (Ag ), Gold (Au), aluminum (Al), or the like is preferably used.

  Cobalt (Co), iron (Fe), nickel (Ni), or the like is preferably used as a metal that can be used for the conductive layer 232 to apply compressive stress to silicon as a substrate and can also be used as an ion source.

  In this embodiment, silver (Ag) is used for the metal used for the conductive layer 231 and the conductive layer 231a. Cobalt (Co) is used for the metal used for the conductive layer 232. Silver (Ag) has a Young's modulus of 83 (GPa) and a work function of 4.31 (eV). Cobalt (Co) has a Young's modulus of 209 (GPa) and a work function of 4.45 (eV). Note that an alloy made of silver (Ag) and copper (Cu) that can be used as an ion source by applying a tensile pressure to silicon as a metal used for the conductive layer 231 and the conductive layer 231a may be used.

  In the semiconductor memory device 300 of this embodiment using a laminated metal, the stress generated by using a metal that applies compressive stress and a metal that applies tensile stress is greatly suppressed. As a result, even if the number of metal stacks increases, the amount of wafer warpage can be significantly suppressed. Misalignment, wafer alignment error, film thickness variation of insulating film, etc. can be greatly reduced.

  Here, the resistance change element RCE may be changed as in the sixth modification shown in FIG. Specifically, the resistance change element RCE includes a conductive layer 211, a resistance change film 212, and a conductive layer 231. The conductive layer 232 of the conductor 210 a in contact with the resistance change film 212 is replaced with the insulating layer 209. The conductive layer 232 does not contact the resistance change film 212. The conductive layer 231 is in contact with the resistance change film 212.

  You may change the resistance change element RCE like the 7th modification shown in FIG. Specifically, the resistance change element RCE includes a conductive layer 211, a resistance change film 212, and a conductive layer 231. An air gap 240 is formed between the conductive layer 232 of the conductor 210 b and the resistance change film 212. The conductive layer 232 of the conductor 210 a in contact with the resistance change film 212 is replaced with the insulating layer 209. The conductive layer 232 of the conductor 210 a in contact with the resistance change film 212 is replaced with the insulating layer 209.

  As described above, in the semiconductor memory device of this embodiment, the stacked body 260 in which a plurality of conductors 210 are stacked with the insulating layer 209 interposed therebetween is provided on the substrate 201. A memory cell array MCA is formed in the region of the stacked body 260. The conductor 209 is used as a word line wiring. The conductor 210 includes a conductive layer 231, a conductive layer 232, and a conductive layer 231 a made of the same material as the conductive layer 231. A conductive layer 232 is provided over the conductive layer 231. A conductive film 231a (the same material as the conductive film 231) is provided over an end portion of the conductive layer 231 (a portion in contact with the resistance change film 212).

  For this reason, the stress with respect to the board | substrate 201 can be suppressed. Since the warpage of the wafer can be greatly reduced, the yield of the semiconductor memory device 300 can be improved.

  In the first embodiment, a three-dimensional NAND flash memory is presented, and in the second embodiment, a three-dimensional ReRAM is presented. However, the present invention is not necessarily limited to this. The present invention can also be applied to a three-dimensional semiconductor memory device other than a NAND flash memory and ReRAM in which a plurality of word lines and bit lines are stacked. Further, the present invention can also be applied to a semiconductor memory device in which a plurality of memory chips are stacked through TSV (Through Silicon Via).

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1,201 Substrate 2, 4, 7-9, 14, 15, 21, 22, 50, 202, 204, 206, 209 Insulating layer 3, 31, 31a, 32, 35, 203, 205, 211, 231, 231a 232 Conductive layer 5, 5a to 5d, 6, 210, 210a, 210b Conductor 11a, 11b, 207 Semiconductor layer 12 Connection portion 13 Memory layer 16, 20, 23, 25, 27 Contact plug 17 Source line 18 Bit line 19 Pad electrode 24, 26 Wiring 34 Barrier film 41 Substrate 42 Film 51-54 Groove 60, 260 Stack 70 NAND strings 80, 280 Semiconductor pillar 100, 300 Semiconductor memory device 207a, 207c N ⁺ Semiconductor layer 207b P ⁺ Semiconductor layer 208 Gate Insulating film 212 Resistance change film 250 Air gap E1 Young's modulus E2 of substrate Yan of film Rate MCT memory cell transistor R curvature radius RCE variable resistance element SGT select transistor

Claims (7)

A substrate,
A multi-layered structure in which a plurality of conductors are stacked on an insulating layer on the substrate, arranged in a first direction in a plane parallel to the substrate, and extending in a second direction perpendicular to the first direction. Body,
Comprising
The conductor includes at least a first conductive layer that applies tensile stress to the substrate and a second conductive layer that applies compressive stress to the substrate, and the second conductive layer is disposed on the first conductive layer. A semiconductor memory device, wherein the second conductive layer is stacked or formed on the first conductive layer. The stacked body passes through the stacked body in a third direction orthogonal to the first and second directions, has a memory layer and a first semiconductor layer, and the memory layer is provided between the conductor and the first semiconductor layer. The semiconductor memory device according to claim 1, further comprising a semiconductor pillar. The semiconductor memory device according to claim 2, wherein the memory layer is in contact with one of the first conductive layer and the second conductive layer. The laminated body is penetrated in a third direction orthogonal to the first and second directions, and has a resistance change film and a third conductive layer, and the resistance change film is between the conductor and the third conductive layer. The semiconductor memory device according to claim 1, further comprising a semiconductor pillar provided. The semiconductor memory device according to claim 4, wherein the variable resistance film is in contact with one of the first conductive layer and the second conductive layer. The first conductive layer includes at least one of titanium (Ti), hafnium (Hf), vanadium (V), copper (Cu), aluminum (Al), gold (Au), and silver (Ag), or Including at least one of titanium silicide, hafnium silicide, and vanadium silicide,
The second conductive layer includes at least one of tungsten (W), cobalt (Co), tantalum (Ta), molybdenum (Mo), beryllium (Be), iron (Fe), and osmium (Os), or 4. The semiconductor memory device according to claim 1, comprising at least one of tungsten silicide, cobalt silicide, tantalum silicide, and molybdenum silicide. 5. The semiconductor memory device according to claim 1, wherein the substrate is a silicon substrate.